SOCKET_M1 Lint Results

Wednesday August 21 2024 23:02:35 UTC

GitHub Revision: e0a468f9e8

Branch: os_regression

Tool: ASCENTLINT

Build Mode Flow Infos Flow Warnings Flow Errors Lint Infos Lint Warnings Lint Errors
default 0 0 0 27 0 0

Messages for Build Mode 'default'

Lint Infos

I   ONE_BIT_VEC:   prim_fifo_sync.sv:32       Declaration range '[DepthW - 1:0]' ([0:0]) of 'depth_o' has a length of one, instance 'tlul_socket_m1.u_devicefifo.reqfifo' of module 'prim_fifo_sync' (Depth=1,DepthW=1 ('prim_util_pkg::vbits(Depth + 1)'))                                                           New                            

I   ONE_BIT_VEC:   prim_fifo_sync.sv:63       Declaration range '[gen_normal_fifo.PtrW - 1:0]' ([0:0]) of 'gen_normal_fifo.fifo_wptr' has a length of one, instance 'tlul_socket_m1.u_devicefifo.reqfifo' of module 'prim_fifo_sync' (Depth=1,gen_normal_fifo.PtrW=1 ('prim_util_pkg::vbits(Depth)'))                 New                            

I   ONE_BIT_VEC:   prim_fifo_sync.sv:105      Declaration range '[Depth - 1:0]' ([0:0]) of 'gen_normal_fifo.storage' has a length of one, instance 'tlul_socket_m1.u_devicefifo.reqfifo' of module 'prim_fifo_sync' (Depth=1,Width=32'h6C)                                                                            New                            

I   ONE_BIT_VEC:   prim_fifo_sync_cnt.sv:25   Declaration range '[PtrW - 1:0]' ([0:0]) of 'wptr_o' has a length of one, instance 'tlul_socket_m1.u_devicefifo.reqfifo.gen_normal_fifo.u_fifo_cnt' of module 'prim_fifo_sync_cnt' (Depth=1,PtrW=1 ('prim_util_pkg::vbits(Depth)'))                                     New                            

I   ONE_BIT_VEC:   prim_fifo_sync_cnt.sv:26   Declaration range '[PtrW - 1:0]' ([0:0]) of 'rptr_o' has a length of one, instance 'tlul_socket_m1.u_devicefifo.reqfifo.gen_normal_fifo.u_fifo_cnt' of module 'prim_fifo_sync_cnt' (Depth=1,PtrW=1 ('prim_util_pkg::vbits(Depth)'))                                     New                            

I   ONE_BIT_VEC:   prim_fifo_sync_cnt.sv:31   Declaration range '[DepthW - 1:0]' ([0:0]) of 'depth_o' has a length of one, instance 'tlul_socket_m1.u_devicefifo.reqfifo.gen_normal_fifo.u_fifo_cnt' of module 'prim_fifo_sync_cnt' (Depth=1,DepthW=1 ('prim_util_pkg::vbits(Depth + 1)'))                            New                            

I   ONE_BIT_VEC:   tlul_fifo_sync.sv:23       Declaration range '[SpareReqW - 1:0]' ([0:0]) of 'spare_req_i' has a length of one, instance 'tlul_socket_m1.u_devicefifo' of module 'tlul_fifo_sync' (SpareReqW=1)                                                                                                     New                            

I   ONE_BIT_VEC:   tlul_fifo_sync.sv:24       Declaration range '[SpareReqW - 1:0]' ([0:0]) of 'spare_req_o' has a length of one, instance 'tlul_socket_m1.u_devicefifo' of module 'tlul_fifo_sync' (SpareReqW=1)                                                                                                     New                            

I   ONE_BIT_VEC:   tlul_fifo_sync.sv:25       Declaration range '[SpareRspW - 1:0]' ([0:0]) of 'spare_rsp_i' has a length of one, instance 'tlul_socket_m1.u_devicefifo' of module 'tlul_fifo_sync' (SpareRspW=1)                                                                                                     New                            

I   ONE_BIT_VEC:   tlul_fifo_sync.sv:26       Declaration range '[SpareRspW - 1:0]' ([0:0]) of 'spare_rsp_o' has a length of one, instance 'tlul_socket_m1.u_devicefifo' of module 'tlul_fifo_sync' (SpareRspW=1)                                                                                                     New                            

I   ONE_BIT_VEC:   tlul_pkg.sv:111            Declaration range '[top_pkg::TL_DIW - 1:0]' ([0:0]) of 'd_sink' has a length of one                                                                                                                                                                                     New                            

I   ONE_BIT_VEC:   tlul_pkg.sv:111            Declaration range '[top_pkg::TL_DIW - 1:0]' ([0:0]) of 'drsp_fifo_o' has a length of one                                                                                                                                                                                New                            

I   ONE_BIT_VEC:   tlul_pkg.sv:111            Declaration range '[top_pkg::TL_DIW - 1:0]' ([0:0]) of 'hrsp_fifo_i' has a length of one                                                                                                                                                                                New                            

I   ONE_BIT_VEC:   tlul_pkg.sv:111            Declaration range '[top_pkg::TL_DIW - 1:0]' ([0:0]) of 'tl_d2h_t' has a length of one                                                                                                                                                                                   New                            

I   ONE_BIT_VEC:   tlul_pkg.sv:111            Declaration range '[top_pkg::TL_DIW - 1:0]' ([0:0]) of 'tl_d_i' has a length of one                                                                                                                                                                                     New                            

I   ONE_BIT_VEC:   tlul_pkg.sv:111            Declaration range '[top_pkg::TL_DIW - 1:0]' ([0:0]) of 'tl_h_o' has a length of one                                                                                                                                                                                     New                            

I   EXPLICIT_BITLEN:   prim_fifo_sync_cnt.sv:51   Bit length not specified for constant '1'                 New                            

I   EXPLICIT_BITLEN:   prim_fifo_sync_cnt.sv:52   Bit length not specified for constant '1'                 New                            

I   EXPLICIT_BITLEN:   prim_util_pkg.sv:85        Bit length not specified for constant '1'                 New                            

I   MIN_NAME_LEN:   prim_arbiter_ppc.sv:28    Name 'N' is shorter than minimum length 2                 New                            

I   MIN_NAME_LEN:   prim_arbiter_ppc.sv:83    Name 'i' is shorter than minimum length 2                 New                            

I   MIN_NAME_LEN:   prim_arbiter_ppc.sv:110   Name 'i' is shorter than minimum length 2                 New                            

I   MIN_NAME_LEN:   prim_arbiter_ppc.sv:125   Name 'i' is shorter than minimum length 2                 New                            

I   MIN_NAME_LEN:   tlul_socket_m1.sv:26      Name 'M' is shorter than minimum length 2                 New                            

I   ZERO_BASED:   tlul_socket_m1.sv:104   Declaration range '[IDW - 1:IDW - STIDW]' ([7:6]) of 'gen_host_fifo[0:3].unused_tl_h_source' is not zero-based                 New                            

I   CONST_OUTPUT:   prim_fifo_sync.sv:98        Output 'err_o' is driven by constant zero by port 'gen_normal_fifo.u_fifo_cnt.err_o' in module 'prim_fifo_sync' (Width=32'h6c,Depth=32'h1)                 New                            

I   CONST_OUTPUT:   prim_fifo_sync_cnt.sv:136   Output 'err_o' is driven by constant zero in module 'prim_fifo_sync_cnt' (Depth=32'h1)                                                                     New                            

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