UART Simulation Results

Tuesday May 16 2023 07:02:31 UTC

GitHub Revision: `50278df8b`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 1341560578

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	30.610s	6.049ms	50	50	100.00
V1	csr_hw_reset	uart_csr_hw_reset	0.610s	11.575us	5	5	100.00
V1	csr_rw	uart_csr_rw	0.640s	46.977us	20	20	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.590s	3.086ms	5	5	100.00
V1	csr_aliasing	uart_csr_aliasing	0.760s	16.459us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.090s	65.218us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.640s	46.977us	20	20	100.00
		uart_csr_aliasing	0.760s	16.459us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	base_random_seq	uart_tx_rx	4.865m	117.820ms	50	50	100.00
V2	parity	uart_smoke	30.610s	6.049ms	50	50	100.00
		uart_tx_rx	4.865m	117.820ms	50	50	100.00
V2	parity_error	uart_intr	26.966m	1.078s	49	50	98.00
		uart_rx_parity_err	5.136m	217.673ms	50	50	100.00
V2	watermark	uart_tx_rx	4.865m	117.820ms	50	50	100.00
		uart_intr	26.966m	1.078s	49	50	98.00
V2	fifo_full	uart_fifo_full	5.560m	348.282ms	50	50	100.00
V2	fifo_overflow	uart_fifo_overflow	16.101m	161.308ms	50	50	100.00
V2	fifo_reset	uart_fifo_reset	6.758m	168.995ms	300	300	100.00
V2	rx_frame_err	uart_intr	26.966m	1.078s	49	50	98.00
V2	rx_break_err	uart_intr	26.966m	1.078s	49	50	98.00
V2	rx_timeout	uart_intr	26.966m	1.078s	49	50	98.00
V2	perf	uart_perf	25.392m	29.897ms	50	50	100.00
V2	sys_loopback	uart_loopback	23.810s	5.583ms	50	50	100.00
V2	line_loopback	uart_loopback	23.810s	5.583ms	50	50	100.00
V2	rx_noise_filter	uart_noise_filter	10.976m	203.451ms	50	50	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	1.179m	43.542ms	50	50	100.00
V2	tx_overide	uart_tx_ovrd	26.860s	6.884ms	50	50	100.00
V2	rx_oversample	uart_rx_oversample	34.990s	3.918ms	42	50	84.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	22.654m	188.120ms	50	50	100.00
V2	stress_all	uart_stress_all	37.674m	78.200ms	50	50	100.00
V2	stress_all_with_reset	uart_stress_all_with_rand_reset	26.797m	671.974ms	100	100	100.00
V2	alert_test	uart_alert_test	0.790s	19.149us	50	50	100.00
V2	intr_test	uart_intr_test	0.640s	44.838us	50	50	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.270s	276.923us	20	20	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.270s	276.923us	20	20	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	0.610s	11.575us	5	5	100.00
		uart_csr_rw	0.640s	46.977us	20	20	100.00
		uart_csr_aliasing	0.760s	16.459us	5	5	100.00
		uart_same_csr_outstanding	0.790s	113.378us	20	20	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	0.610s	11.575us	5	5	100.00
		uart_csr_rw	0.640s	46.977us	20	20	100.00
		uart_csr_aliasing	0.760s	16.459us	5	5	100.00
		uart_same_csr_outstanding	0.790s	113.378us	20	20	100.00
V2		TOTAL			1181	1190	99.24
V2S	tl_intg_err	uart_sec_cm	0.870s	66.153us	5	5	100.00
		uart_tl_intg_err	1.460s	81.697us	20	20	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.460s	81.697us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3		TOTAL			0	0	--
		TOTAL			1311	1320	99.32

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	19	19	17	89.47
V2S	2	2	2	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.28	99.80	98.45	100.00	--	99.76	100.00	97.65

Failure Buckets

UVM_ERROR (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: uart_reg_block.val.rx reset value: *

has 8 failures:

Test uart_rx_oversample has 8 failures.

2.uart_rx_oversample.3644022023
Line 218, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/2.uart_rx_oversample/latest/run.log

  UVM_ERROR @ 656811645 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (23012 [0x59e4] vs 46024 [0xb3c8]) Regname: uart_reg_block.val.rx reset value: 0x0
  UVM_INFO @ 665361278 ps: (uart_rx_oversample_vseq.sv:37) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_oversample_vseq] finished run 4/6
  UVM_ERROR @ 665478381 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (31719 [0x7be7] vs 63439 [0xf7cf]) Regname: uart_reg_block.val.rx reset value: 0x0
  UVM_INFO @ 882020061 ps: (uart_rx_oversample_vseq.sv:37) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_oversample_vseq] finished run 5/6
  UVM_INFO @ 1201077341 ps: (uart_rx_oversample_vseq.sv:37) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_oversample_vseq] finished run 6/6

4.uart_rx_oversample.3462403701
Line 215, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/4.uart_rx_oversample/latest/run.log

  UVM_ERROR @  24502508 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (9839 [0x266f] vs 11983 [0x2ecf]) Regname: uart_reg_block.val.rx reset value: 0x0
  UVM_INFO @  33052141 ps: (uart_rx_oversample_vseq.sv:37) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_oversample_vseq] finished run 1/3
  UVM_ERROR @  33169244 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (65023 [0xfdff] vs 56046 [0xdaee]) Regname: uart_reg_block.val.rx reset value: 0x0
  UVM_INFO @  45982865 ps: (uart_rx_oversample_vseq.sv:37) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_oversample_vseq] finished run 2/3
  UVM_INFO @ 367599928 ps: (uart_rx_oversample_vseq.sv:37) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_oversample_vseq] finished run 3/3

... and 6 more failures.

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test uart_intr has 1 failures.
  - 38.uart_intr.3420524923
    Line 242, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/38.uart_intr/latest/run.log
```
  UVM_FATAL @ 3000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 3000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 3000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```