UART Simulation Results

Saturday February 08 2025 05:05:54 UTC

GitHub Revision: `9f20940d49`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 88344288495849993302635329522992994622996067932062874150778031027723701018040

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	43.170s	5.910ms	50	50	100.00
V1	csr_hw_reset	uart_csr_hw_reset	0.900s	45.883us	5	5	100.00
V1	csr_rw	uart_csr_rw	0.930s	74.807us	20	20	100.00
V1	csr_bit_bash	uart_csr_bit_bash	3.880s	265.062us	5	5	100.00
V1	csr_aliasing	uart_csr_aliasing	1.150s	47.580us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.950s	28.341us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.930s	74.807us	20	20	100.00
		uart_csr_aliasing	1.150s	47.580us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	base_random_seq	uart_tx_rx	4.888m	104.711ms	50	50	100.00
V2	parity	uart_smoke	43.170s	5.910ms	50	50	100.00
		uart_tx_rx	4.888m	104.711ms	50	50	100.00
V2	parity_error	uart_intr	7.238m	184.434ms	48	50	96.00
		uart_rx_parity_err	9.212m	106.747ms	50	50	100.00
V2	watermark	uart_tx_rx	4.888m	104.711ms	50	50	100.00
		uart_intr	7.238m	184.434ms	48	50	96.00
V2	fifo_full	uart_fifo_full	6.811m	206.845ms	49	50	98.00
V2	fifo_overflow	uart_fifo_overflow	7.038m	124.276ms	50	50	100.00
V2	fifo_reset	uart_fifo_reset	14.085m	105.082ms	299	300	99.67
V2	rx_frame_err	uart_intr	7.238m	184.434ms	48	50	96.00
V2	rx_break_err	uart_intr	7.238m	184.434ms	48	50	96.00
V2	rx_timeout	uart_intr	7.238m	184.434ms	48	50	96.00
V2	perf	uart_perf	34.574m	31.469ms	50	50	100.00
V2	sys_loopback	uart_loopback	36.940s	9.667ms	50	50	100.00
V2	line_loopback	uart_loopback	36.940s	9.667ms	50	50	100.00
V2	rx_noise_filter	uart_noise_filter	5.317m	92.259ms	50	50	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	2.149m	50.070ms	50	50	100.00
V2	tx_overide	uart_tx_ovrd	1.276m	13.192ms	50	50	100.00
V2	rx_oversample	uart_rx_oversample	1.447m	7.378ms	50	50	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	26.989m	189.877ms	50	50	100.00
V2	stress_all	uart_stress_all	57.740m	874.938ms	50	50	100.00
V2	alert_test	uart_alert_test	0.880s	27.460us	50	50	100.00
V2	intr_test	uart_intr_test	0.870s	14.806us	50	50	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	3.570s	50.763us	20	20	100.00
V2	tl_d_illegal_access	uart_tl_errors	3.570s	50.763us	20	20	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	0.900s	45.883us	5	5	100.00
		uart_csr_rw	0.930s	74.807us	20	20	100.00
		uart_csr_aliasing	1.150s	47.580us	5	5	100.00
		uart_same_csr_outstanding	1.190s	124.916us	20	20	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	0.900s	45.883us	5	5	100.00
		uart_csr_rw	0.930s	74.807us	20	20	100.00
		uart_csr_aliasing	1.150s	47.580us	5	5	100.00
		uart_same_csr_outstanding	1.190s	124.916us	20	20	100.00
V2		TOTAL			1086	1090	99.63
V2S	tl_intg_err	uart_sec_cm	1.370s	103.025us	5	5	100.00
		uart_tl_intg_err	1.980s	138.703us	20	20	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.980s	138.703us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	40.463m	230.854ms	99	100	99.00
V3		TOTAL			99	100	99.00
		TOTAL			1315	1320	99.62

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	18	18	15	83.33
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.11	99.10	97.65	100.00	--	98.38	100.00	99.53

Failure Buckets

UVM_ERROR (uart_scoreboard.sv:442) [scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (* [*] vs * [*]) Interrupt: TxEmpty has 4 failures:

Test uart_fifo_reset has 1 failures.

2.uart_fifo_reset.9904016077043761941482384836900805560542981781595901377450666046360840995484
Line 61, in log /workspaces/repo/scratch/os_regression/uart-sim-vcs/2.uart_fifo_reset/latest/run.log

  UVM_ERROR @   1322268 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxEmpty
  UVM_INFO @ 4050570744 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 1/8
  UVM_INFO @ 4680610518 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 2/8
  UVM_INFO @ 4890085056 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 3/8
  UVM_INFO @ 5259084687 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 4/8

Test uart_fifo_full has 1 failures.

3.uart_fifo_full.93220319841622052254211050670093896830833479902223534142875167700196469574145
Line 61, in log /workspaces/repo/scratch/os_regression/uart-sim-vcs/3.uart_fifo_full/latest/run.log

  UVM_ERROR @  17742674 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxEmpty
  UVM_INFO @ 615278995 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_full_vseq] finished run 1/6
  UVM_INFO @ 20829713400 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_full_vseq] finished run 2/6
  UVM_INFO @ 128319650847 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_full_vseq] finished run 3/6
  UVM_INFO @ 128321717524 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_full_vseq] finished run 4/6

Test uart_intr has 2 failures.

26.uart_intr.50624440577584646201565022284619014901339181485963523880305141551467592080817
Line 73, in log /workspaces/repo/scratch/os_regression/uart-sim-vcs/26.uart_intr/latest/run.log

  UVM_ERROR @ 958415606 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxEmpty
  UVM_INFO @ 1050208007 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
  Testing RxOverflow
  UVM_INFO @ 6636711032 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
  Testing RxTimeout

42.uart_intr.89503954120006396038154175050564338932715986751160849882186936646050218940071
Line 82, in log /workspaces/repo/scratch/os_regression/uart-sim-vcs/42.uart_intr/latest/run.log

  UVM_ERROR @ 3200267598 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxEmpty
  UVM_INFO @ 3285327598 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
  Testing RxFrameErr
  UVM_INFO @ 3457657598 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
  Testing TxEmpty

UVM_ERROR (cip_base_vseq.sv:755) [uart_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:

Test uart_stress_all_with_rand_reset has 1 failures.

54.uart_stress_all_with_rand_reset.85669231776600185388233670303517880377586106715908115382101552720769582332677
Line 147, in log /workspaces/repo/scratch/os_regression/uart-sim-vcs/54.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 6798035914 ps: (cip_base_vseq.sv:755) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 6798035914 ps: (cip_base_vseq.sv:759) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Issuing reset for run 4/5
  UVM_INFO @ 6798056116 ps: (cip_base_vseq.sv:767) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Stress w/ reset is done for run 4/5