12e3b8572e| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | uart_smoke | 33.250s | 11.571ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | uart_csr_hw_reset | 29.290s | 4 | 5 | 80.00 | |
| V1 | csr_rw | uart_csr_rw | 29.292s | 18 | 20 | 90.00 | |
| V1 | csr_bit_bash | uart_csr_bit_bash | 2.080s | 74.407us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | uart_csr_aliasing | 29.338s | 4 | 5 | 80.00 | |
| V1 | csr_mem_rw_with_rand_reset | uart_csr_mem_rw_with_rand_reset | 29.316s | 19 | 20 | 95.00 | |
| V1 | regwen_csr_and_corresponding_lockable_csr | uart_csr_rw | 29.292s | 18 | 20 | 90.00 | |
| uart_csr_aliasing | 29.338s | 4 | 5 | 80.00 | |||
| V1 | TOTAL | 100 | 105 | 95.24 | |||
| V2 | base_random_seq | uart_tx_rx | 7.564m | 165.939ms | 50 | 50 | 100.00 |
| V2 | parity | uart_smoke | 33.250s | 11.571ms | 50 | 50 | 100.00 |
| uart_tx_rx | 7.564m | 165.939ms | 50 | 50 | 100.00 | ||
| V2 | parity_error | uart_intr | 7.074m | 146.486ms | 50 | 50 | 100.00 |
| uart_rx_parity_err | 6.215m | 118.179ms | 50 | 50 | 100.00 | ||
| V2 | watermark | uart_tx_rx | 7.564m | 165.939ms | 50 | 50 | 100.00 |
| uart_intr | 7.074m | 146.486ms | 50 | 50 | 100.00 | ||
| V2 | fifo_full | uart_fifo_full | 17.362m | 294.184ms | 50 | 50 | 100.00 |
| V2 | fifo_overflow | uart_fifo_overflow | 9.367m | 106.953ms | 50 | 50 | 100.00 |
| V2 | fifo_reset | uart_fifo_reset | 6.726m | 220.571ms | 300 | 300 | 100.00 |
| V2 | rx_frame_err | uart_intr | 7.074m | 146.486ms | 50 | 50 | 100.00 |
| V2 | rx_break_err | uart_intr | 7.074m | 146.486ms | 50 | 50 | 100.00 |
| V2 | rx_timeout | uart_intr | 7.074m | 146.486ms | 50 | 50 | 100.00 |
| V2 | perf | uart_perf | 31.215m | 37.619ms | 50 | 50 | 100.00 |
| V2 | sys_loopback | uart_loopback | 41.270s | 9.662ms | 50 | 50 | 100.00 |
| V2 | line_loopback | uart_loopback | 41.270s | 9.662ms | 50 | 50 | 100.00 |
| V2 | rx_noise_filter | uart_noise_filter | 4.721m | 152.914ms | 50 | 50 | 100.00 |
| V2 | rx_start_bit_filter | uart_rx_start_bit_filter | 1.865m | 45.142ms | 50 | 50 | 100.00 |
| V2 | tx_overide | uart_tx_ovrd | 47.280s | 11.833ms | 50 | 50 | 100.00 |
| V2 | rx_oversample | uart_rx_oversample | 1.274m | 7.144ms | 50 | 50 | 100.00 |
| V2 | long_b2b_transfer | uart_long_xfer_wo_dly | 20.166m | 115.977ms | 50 | 50 | 100.00 |
| V2 | stress_all | uart_stress_all | 32.750m | 197.705ms | 50 | 50 | 100.00 |
| V2 | alert_test | uart_alert_test | 0.860s | 22.027us | 50 | 50 | 100.00 |
| V2 | intr_test | uart_intr_test | 29.295s | 48 | 50 | 96.00 | |
| V2 | tl_d_oob_addr_access | uart_tl_errors | 29.313s | 18 | 20 | 90.00 | |
| V2 | tl_d_illegal_access | uart_tl_errors | 29.313s | 18 | 20 | 90.00 | |
| V2 | tl_d_outstanding_access | uart_csr_hw_reset | 29.290s | 4 | 5 | 80.00 | |
| uart_csr_rw | 29.292s | 18 | 20 | 90.00 | |||
| uart_csr_aliasing | 29.338s | 4 | 5 | 80.00 | |||
| uart_same_csr_outstanding | 29.333s | 18 | 20 | 90.00 | |||
| V2 | tl_d_partial_access | uart_csr_hw_reset | 29.290s | 4 | 5 | 80.00 | |
| uart_csr_rw | 29.292s | 18 | 20 | 90.00 | |||
| uart_csr_aliasing | 29.338s | 4 | 5 | 80.00 | |||
| uart_same_csr_outstanding | 29.333s | 18 | 20 | 90.00 | |||
| V2 | TOTAL | 1084 | 1090 | 99.45 | |||
| V2S | tl_intg_err | uart_sec_cm | 1.260s | 229.001us | 5 | 5 | 100.00 |
| uart_tl_intg_err | 29.306s | 18 | 20 | 90.00 | |||
| V2S | sec_cm_bus_integrity | uart_tl_intg_err | 29.306s | 18 | 20 | 90.00 | |
| V2S | TOTAL | 23 | 25 | 92.00 | |||
| V3 | stress_all_with_rand_reset | uart_stress_all_with_rand_reset | 2.498m | 9.341ms | 97 | 100 | 97.00 |
| V3 | TOTAL | 97 | 100 | 97.00 | |||
| TOTAL | 1304 | 1320 | 98.79 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 2 | 33.33 |
| V2 | 18 | 18 | 15 | 83.33 |
| V2S | 2 | 2 | 1 | 50.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 99.12 | 99.08 | 97.65 | 100.00 | -- | 98.35 | 100.00 | 99.64 |
Job returned non-zero exit code has 13 failures:
Test uart_csr_aliasing has 1 failures.
1.uart_csr_aliasing.33378951322313086275963280929724363481485502630524517283018727569540156679746
Log /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/1.uart_csr_aliasing/latest/run.log
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Oct 15 11:29 2024
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/workspaces/repo/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 255
Test uart_same_csr_outstanding has 2 failures.
1.uart_same_csr_outstanding.82271123118710830047935061570467525615931237801019556255501592684464084131172
Log /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/1.uart_same_csr_outstanding/latest/run.log
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Oct 15 11:29 2024
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/workspaces/repo/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 255
5.uart_same_csr_outstanding.105416973642845934679107894322119848550332094827757039266825564914493182164430
Log /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/5.uart_same_csr_outstanding/latest/run.log
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Oct 15 11:29 2024
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/workspaces/repo/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 255
Test uart_csr_mem_rw_with_rand_reset has 1 failures.
1.uart_csr_mem_rw_with_rand_reset.41209373031642199475345635147054109392769067935840063267438321911579465161974
Log /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/1.uart_csr_mem_rw_with_rand_reset/latest/run.log
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Oct 15 11:29 2024
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/workspaces/repo/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 255
Test uart_tl_errors has 2 failures.
2.uart_tl_errors.48412392820592314469787022390319143416542725207903130307720838933919418297320
Log /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/2.uart_tl_errors/latest/run.log
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Oct 15 11:29 2024
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/workspaces/repo/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 255
5.uart_tl_errors.80139788385723280812241667461304649434042427184839818171482102990983314269901
Log /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/5.uart_tl_errors/latest/run.log
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Oct 15 11:29 2024
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/workspaces/repo/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 255
Test uart_tl_intg_err has 2 failures.
2.uart_tl_intg_err.111959439412346312310117765459515282265597208226677589388652649215476539523703
Log /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/2.uart_tl_intg_err/latest/run.log
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Oct 15 11:29 2024
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/workspaces/repo/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 255
5.uart_tl_intg_err.62102654016224502692628651773324116074534382471908691317526852168536313013432
Log /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/5.uart_tl_intg_err/latest/run.log
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Oct 15 11:29 2024
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/workspaces/repo/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 255
... and 3 more tests.
UVM_ERROR (cip_base_vseq.sv:867) [uart_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 3 failures:
26.uart_stress_all_with_rand_reset.14729121305874781386947749428498928134005385673474382797084076970637974898079
Line 73, in log /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/26.uart_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 573276492 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_ERROR @ 573290287 ps: (cip_base_vseq.sv:771) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 573290287 ps: (cip_base_vseq.sv:775) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
Issuing reset for run 2/5
UVM_INFO @ 573324111 ps: (uart_intr_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] finished run 1/2
30.uart_stress_all_with_rand_reset.75874505698466234043284264777017654999432379496537390050695824818018562976507
Line 76, in log /workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/30.uart_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 256275620 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_ERROR @ 256283927 ps: (cip_base_vseq.sv:771) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 256283927 ps: (cip_base_vseq.sv:775) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
Issuing reset for run 2/10
UVM_INFO @ 256285721 ps: (uart_intr_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] finished run 1/1
... and 1 more failures.