UART Simulation Results

Thursday July 25 2024 23:02:35 UTC

GitHub Revision: `a47820eb4c`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 42717125255024305080795900498886328747526075712606813106869971419713539568742

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	22.980s	6.336ms	50	50	100.00
V1	csr_hw_reset	uart_csr_hw_reset	0.640s	57.028us	5	5	100.00
V1	csr_rw	uart_csr_rw	0.680s	19.542us	20	20	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.460s	3.371ms	5	5	100.00
V1	csr_aliasing	uart_csr_aliasing	0.810s	160.908us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.350s	314.525us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.680s	19.542us	20	20	100.00
		uart_csr_aliasing	0.810s	160.908us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	base_random_seq	uart_tx_rx	4.852m	150.130ms	50	50	100.00
V2	parity	uart_smoke	22.980s	6.336ms	50	50	100.00
		uart_tx_rx	4.852m	150.130ms	50	50	100.00
V2	parity_error	uart_intr	7.981m	337.976ms	49	50	98.00
		uart_rx_parity_err	4.765m	186.746ms	50	50	100.00
V2	watermark	uart_tx_rx	4.852m	150.130ms	50	50	100.00
		uart_intr	7.981m	337.976ms	49	50	98.00
V2	fifo_full	uart_fifo_full	8.934m	261.648ms	50	50	100.00
V2	fifo_overflow	uart_fifo_overflow	12.057m	102.137ms	50	50	100.00
V2	fifo_reset	uart_fifo_reset	10.046m	165.229ms	299	300	99.67
V2	rx_frame_err	uart_intr	7.981m	337.976ms	49	50	98.00
V2	rx_break_err	uart_intr	7.981m	337.976ms	49	50	98.00
V2	rx_timeout	uart_intr	7.981m	337.976ms	49	50	98.00
V2	perf	uart_perf	25.294m	31.220ms	50	50	100.00
V2	sys_loopback	uart_loopback	22.100s	9.169ms	50	50	100.00
V2	line_loopback	uart_loopback	22.100s	9.169ms	50	50	100.00
V2	rx_noise_filter	uart_noise_filter	2.617m	168.887ms	50	50	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	1.257m	46.442ms	50	50	100.00
V2	tx_overide	uart_tx_ovrd	39.520s	6.972ms	50	50	100.00
V2	rx_oversample	uart_rx_oversample	47.680s	5.348ms	50	50	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	24.619m	164.397ms	50	50	100.00
V2	stress_all	uart_stress_all	28.466m	321.423ms	50	50	100.00
V2	alert_test	uart_alert_test	0.600s	13.987us	50	50	100.00
V2	intr_test	uart_intr_test	0.630s	49.478us	50	50	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.460s	87.229us	20	20	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.460s	87.229us	20	20	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	0.640s	57.028us	5	5	100.00
		uart_csr_rw	0.680s	19.542us	20	20	100.00
		uart_csr_aliasing	0.810s	160.908us	5	5	100.00
		uart_same_csr_outstanding	0.790s	34.124us	20	20	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	0.640s	57.028us	5	5	100.00
		uart_csr_rw	0.680s	19.542us	20	20	100.00
		uart_csr_aliasing	0.810s	160.908us	5	5	100.00
		uart_same_csr_outstanding	0.790s	34.124us	20	20	100.00
V2		TOTAL			1088	1090	99.82
V2S	tl_intg_err	uart_sec_cm	0.840s	511.376us	5	5	100.00
		uart_tl_intg_err	1.360s	274.599us	20	20	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.360s	274.599us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	45.432m	116.526ms	99	100	99.00
V3		TOTAL			99	100	99.00
		TOTAL			1317	1320	99.77

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	18	18	16	88.89
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.10	99.10	97.65	100.00	--	98.38	100.00	99.48

Failure Buckets

UVM_ERROR (uart_scoreboard.sv:442) [scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (* [*] vs * [*]) Interrupt: TxEmpty has 2 failures:

Test uart_intr has 1 failures.

31.uart_intr.65001312439144660639666445395369134904878582603744096953959703800260411601510
Line 302, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/31.uart_intr/latest/run.log

  UVM_ERROR @ 22574560548 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxEmpty
  UVM_INFO @ 22670021888 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
  Testing RxBreakErr
  UVM_INFO @ 23625449699 ps: (uart_intr_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] finished run 3/4
  UVM_INFO @ 23625532171 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]

Test uart_stress_all_with_rand_reset has 1 failures.

46.uart_stress_all_with_rand_reset.74776061134238497768850208729543037602476661313668546343261801701750600331277
Line 441, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/46.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 76205867994 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxEmpty
  UVM_INFO @ 76513790763 ps: (cip_base_vseq__tl_errors.svh:201) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 46/933
  UVM_INFO @ 76777021269 ps: (cip_base_vseq__tl_errors.svh:201) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 47/933
  UVM_INFO @ 77230405431 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
  Testing RxOverflow

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test uart_fifo_reset has 1 failures.
  - 254.uart_fifo_reset.7251078140802265723822381448823334409225706404610842585982072771761531182866
    Line 254, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/254.uart_fifo_reset/latest/run.log
```
  UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```