UART Simulation Results

Tuesday May 30 2023 07:03:17 UTC

GitHub Revision: `f8b3c19a2`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 1284268927

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	27.110s	11.054ms	50	50	100.00
V1	csr_hw_reset	uart_csr_hw_reset	2.150s	1.033ms	5	5	100.00
V1	csr_rw	uart_csr_rw	0.640s	43.016us	20	20	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.580s	1.471ms	5	5	100.00
V1	csr_aliasing	uart_csr_aliasing	0.810s	85.197us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.200s	45.585us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.640s	43.016us	20	20	100.00
		uart_csr_aliasing	0.810s	85.197us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	base_random_seq	uart_tx_rx	4.714m	72.573ms	50	50	100.00
V2	parity	uart_smoke	27.110s	11.054ms	50	50	100.00
		uart_tx_rx	4.714m	72.573ms	50	50	100.00
V2	parity_error	uart_intr	41.355m	1.514s	49	50	98.00
		uart_rx_parity_err	4.481m	185.999ms	50	50	100.00
V2	watermark	uart_tx_rx	4.714m	72.573ms	50	50	100.00
		uart_intr	41.355m	1.514s	49	50	98.00
V2	fifo_full	uart_fifo_full	7.492m	255.059ms	50	50	100.00
V2	fifo_overflow	uart_fifo_overflow	8.361m	177.976ms	50	50	100.00
V2	fifo_reset	uart_fifo_reset	6.670m	176.242ms	300	300	100.00
V2	rx_frame_err	uart_intr	41.355m	1.514s	49	50	98.00
V2	rx_break_err	uart_intr	41.355m	1.514s	49	50	98.00
V2	rx_timeout	uart_intr	41.355m	1.514s	49	50	98.00
V2	perf	uart_perf	32.834m	39.903ms	50	50	100.00
V2	sys_loopback	uart_loopback	22.640s	10.373ms	50	50	100.00
V2	line_loopback	uart_loopback	22.640s	10.373ms	50	50	100.00
V2	rx_noise_filter	uart_noise_filter	6.796m	195.165ms	50	50	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	1.254m	44.707ms	50	50	100.00
V2	tx_overide	uart_tx_ovrd	29.190s	12.612ms	50	50	100.00
V2	rx_oversample	uart_rx_oversample	47.330s	4.528ms	41	50	82.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	22.519m	210.731ms	50	50	100.00
V2	stress_all	uart_stress_all	56.526m	1.756s	50	50	100.00
V2	stress_all_with_reset	uart_stress_all_with_rand_reset	25.318m	567.036ms	98	100	98.00
V2	alert_test	uart_alert_test	0.620s	50.000us	50	50	100.00
V2	intr_test	uart_intr_test	0.650s	16.127us	50	50	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.560s	53.006us	20	20	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.560s	53.006us	20	20	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	2.150s	1.033ms	5	5	100.00
		uart_csr_rw	0.640s	43.016us	20	20	100.00
		uart_csr_aliasing	0.810s	85.197us	5	5	100.00
		uart_same_csr_outstanding	0.770s	98.456us	20	20	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	2.150s	1.033ms	5	5	100.00
		uart_csr_rw	0.640s	43.016us	20	20	100.00
		uart_csr_aliasing	0.810s	85.197us	5	5	100.00
		uart_same_csr_outstanding	0.770s	98.456us	20	20	100.00
V2		TOTAL			1178	1190	98.99
V2S	tl_intg_err	uart_sec_cm	0.880s	115.760us	5	5	100.00
		uart_tl_intg_err	1.390s	90.372us	20	20	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.390s	90.372us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3		TOTAL			0	0	--
		TOTAL			1308	1320	99.09

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	19	19	16	84.21
V2S	2	2	2	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.25	99.80	98.45	100.00	--	99.76	100.00	97.51

Failure Buckets

UVM_ERROR (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: uart_reg_block.val.rx reset value: * has 9 failures:

Test uart_rx_oversample has 9 failures.

4.uart_rx_oversample.3429931595
Line 216, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/4.uart_rx_oversample/latest/run.log

  UVM_ERROR @ 349493472 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (37275 [0x919b] vs 9011 [0x2333]) Regname: uart_reg_block.val.rx reset value: 0x0
  UVM_INFO @ 357944896 ps: (uart_rx_oversample_vseq.sv:37) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_oversample_vseq] finished run 2/15
  UVM_ERROR @ 358108848 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (56415 [0xdc5f] vs 47293 [0xb8bd]) Regname: uart_reg_block.val.rx reset value: 0x0
  UVM_INFO @ 534589754 ps: (uart_rx_oversample_vseq.sv:37) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_oversample_vseq] finished run 3/15
  UVM_INFO @ 944845973 ps: (uart_rx_oversample_vseq.sv:37) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_oversample_vseq] finished run 4/15

12.uart_rx_oversample.412238733
Line 217, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/12.uart_rx_oversample/latest/run.log

  UVM_ERROR @  51739093 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (51925 [0xcad5] vs 38315 [0x95ab]) Regname: uart_reg_block.val.rx reset value: 0x0
  UVM_INFO @ 268204749 ps: (uart_rx_oversample_vseq.sv:37) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_oversample_vseq] finished run 3/18
  UVM_INFO @ 691750341 ps: (uart_rx_oversample_vseq.sv:37) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_oversample_vseq] finished run 4/18
  UVM_INFO @ 709563722 ps: (uart_rx_oversample_vseq.sv:37) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_oversample_vseq] finished run 5/18
  UVM_ERROR @ 709691725 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (29911 [0x74d7] vs 59822 [0xe9ae]) Regname: uart_reg_block.val.rx reset value: 0x0

... and 7 more failures.

UVM_ERROR (uart_intr_vseq.sv:252) [uart_intr_vseq] Check failed act_intr_state[uart_intr] == exp (* [*] vs * [*]) has 2 failures:

Test uart_stress_all_with_rand_reset has 2 failures.

49.uart_stress_all_with_rand_reset.3754809146
Line 405, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/49.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 99330404513 ps: (uart_intr_vseq.sv:252) [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] Check failed act_intr_state[uart_intr] == exp (1 [0x1] vs 0 [0x0])
  UVM_ERROR @ 99330404513 ps: (uart_intr_vseq.sv:254) [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] Check failed cfg.intr_vif.pins[uart_intr] == exp_pin (1 [0x1] vs 0 [0x0]) uart_intr name/val: RxTimeout/6, en_intr: d4
  UVM_ERROR @ 99706942598 ps: (uart_intr_vseq.sv:252) [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] Check failed act_intr_state[uart_intr] == exp (1 [0x1] vs 0 [0x0])
  UVM_ERROR @ 99706942598 ps: (uart_intr_vseq.sv:254) [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] Check failed cfg.intr_vif.pins[uart_intr] == exp_pin (1 [0x1] vs 0 [0x0]) uart_intr name/val: RxTimeout/6, en_intr: d4
  UVM_INFO @ 99717019511 ps: (cip_base_vseq__tl_errors.svh:196) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 22/41

78.uart_stress_all_with_rand_reset.3532657031
Line 417, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/78.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 132710948647 ps: (uart_intr_vseq.sv:252) [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] Check failed act_intr_state[uart_intr] == exp (1 [0x1] vs 0 [0x0])
  UVM_ERROR @ 132948221137 ps: (uart_intr_vseq.sv:252) [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] Check failed act_intr_state[uart_intr] == exp (1 [0x1] vs 0 [0x0])
  UVM_ERROR @ 133183766356 ps: (uart_intr_vseq.sv:252) [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] Check failed act_intr_state[uart_intr] == exp (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 133314584407 ps: (cip_base_vseq__tl_errors.svh:196) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 14/493
  UVM_ERROR @ 133423402480 ps: (uart_intr_vseq.sv:252) [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] Check failed act_intr_state[uart_intr] == exp (1 [0x1] vs 0 [0x0])

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test uart_intr has 1 failures.
  - 2.uart_intr.210212577
    Line 293, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/2.uart_intr/latest/run.log
```
  UVM_FATAL @ 3000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 3000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 3000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```