Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	99720	1			T2	1		T13	8		T14	8
all_values[1]	99720	1			T2	1		T13	8		T14	8
all_values[2]	99720	1			T2	1		T13	8		T14	8
all_values[3]	99720	1			T2	1		T13	8		T14	8
all_values[4]	99720	1			T2	1		T13	8		T14	8
all_values[5]	99720	1			T2	1		T13	8		T14	8
all_values[6]	99720	1			T2	1		T13	8		T14	8
all_values[7]	99720	1			T2	1		T13	8		T14	8

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

463110

1

T2

8

T13

28

T14

28

auto[1]

334650

1

T13

36

T14

36

T17

36

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

779560

1

T2

8

T13

32

T14

32

auto[1]

18200

1

T13

32

T14

32

T17

32

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	38720	1			T2	1		T13	2		T14	2
all_values[0]	auto[0]	auto[1]	1850	1			T13	3		T14	3		T17	3
all_values[0]	auto[1]	auto[0]	56500	1			T18	88		T19	96		T20	6
all_values[0]	auto[1]	auto[1]	2650	1			T13	3		T14	3		T17	3
all_values[1]	auto[0]	auto[0]	15270	1			T2	1		T13	1		T14	1
all_values[1]	auto[0]	auto[1]	1750	1			T13	1		T14	1		T17	1
all_values[1]	auto[1]	auto[0]	81300	1			T13	3		T14	3		T17	3
all_values[1]	auto[1]	auto[1]	1400	1			T13	3		T14	3		T17	3
all_values[2]	auto[0]	auto[0]	46970	1			T2	1		T13	2		T14	2
all_values[2]	auto[0]	auto[1]	1500	1			T19	4		T20	1		T46	2
all_values[2]	auto[1]	auto[0]	47750	1			T13	1		T14	1		T17	1
all_values[2]	auto[1]	auto[1]	3500	1			T13	5		T14	5		T17	5
all_values[3]	auto[0]	auto[0]	63320	1			T2	1		T13	2		T14	2
all_values[3]	auto[0]	auto[1]	500	1			T19	3		T50	3		T51	3
all_values[3]	auto[1]	auto[0]	35300	1			T13	5		T14	5		T17	5
all_values[3]	auto[1]	auto[1]	600	1			T13	1		T14	1		T17	1
all_values[4]	auto[0]	auto[0]	81220	1			T2	1		T6	1		T7	1
all_values[4]	auto[0]	auto[1]	900	1			T13	3		T14	3		T17	3
all_values[4]	auto[1]	auto[0]	16950	1			T13	2		T14	2		T17	2
all_values[4]	auto[1]	auto[1]	650	1			T13	3		T14	3		T17	3
all_values[5]	auto[0]	auto[0]	87770	1			T2	1		T13	1		T14	1
all_values[5]	auto[0]	auto[1]	250	1			T13	2		T14	2		T17	2
all_values[5]	auto[1]	auto[0]	11100	1			T13	2		T14	2		T17	2
all_values[5]	auto[1]	auto[1]	600	1			T13	3		T14	3		T17	3
all_values[6]	auto[0]	auto[0]	46820	1			T2	1		T13	2		T14	2
all_values[6]	auto[0]	auto[1]	500	1			T13	2		T14	2		T17	2
all_values[6]	auto[1]	auto[0]	51850	1			T13	4		T14	4		T17	4
all_values[6]	auto[1]	auto[1]	550	1			T19	4		T50	4		T51	4
all_values[7]	auto[0]	auto[0]	75220	1			T2	1		T13	4		T14	4
all_values[7]	auto[0]	auto[1]	550	1			T13	3		T14	3		T17	3
all_values[7]	auto[1]	auto[0]	23500	1			T13	1		T14	1		T17	1
all_values[7]	auto[1]	auto[1]	450	1			T19	2		T50	2		T51	2