ASSERT | PROPERTIES | SEQUENCES | |
Total | 323 | 0 | 10 |
Category 0 | 323 | 0 | 10 |
ASSERT | PROPERTIES | SEQUENCES | |
Total | 323 | 0 | 10 |
Severity 0 | 323 | 0 | 10 |
NUMBER | PERCENT | |
Total Number | 323 | 100.00 |
Uncovered | 4 | 1.24 |
Success | 319 | 98.76 |
Failure | 0 | 0.00 |
Incomplete | 0 | 0.00 |
Without Attempts | 0 | 0.00 |
NUMBER | PERCENT | |
Total Number | 10 | 100.00 |
Uncovered | 2 | 20.00 |
All Matches | 8 | 80.00 |
First Matches | 8 | 80.00 |
ASSERTIONS | CATEGORY | SEVERITY | ATTEMPTS | REAL SUCCESSES | FAILURES | INCOMPLETE | SRC |
tb.dut.uart_csr_assert.ctrl_rd_A | 0 | 0 | 2147483647 | 0 | 0 | 0 | |
tb.dut.uart_csr_assert.intr_enable_rd_A | 0 | 0 | 2147483647 | 0 | 0 | 0 | |
tb.dut.uart_csr_assert.ovrd_rd_A | 0 | 0 | 2147483647 | 0 | 0 | 0 | |
tb.dut.uart_csr_assert.timeout_ctrl_rd_A | 0 | 0 | 2147483647 | 0 | 0 | 0 |
COVER SEQUENCES | CATEGORY | SEVERITY | ATTEMPTS | ALL MATCHES | FIRST MATCHES | INCOMPLETE | SRC |
tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C | 0 | 0 | 2147483647 | 0 | 0 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C | 0 | 0 | 2147483647 | 0 | 0 | 0 |
COVER SEQUENCES | CATEGORY | SEVERITY | ATTEMPTS | ALL MATCHES | FIRST MATCHES | INCOMPLETE | SRC |
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C | 0 | 0 | 2147483647 | 88070 | 88070 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C | 0 | 0 | 2147483647 | 100 | 100 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C | 0 | 0 | 2147483647 | 100 | 100 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C | 0 | 0 | 2147483647 | 100 | 100 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C | 0 | 0 | 2147483647 | 100 | 100 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C | 0 | 0 | 2147483647 | 420 | 420 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C | 0 | 0 | 2147483647 | 876740 | 876740 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C | 0 | 0 | 2147483647 | 33265835 | 33265835 | 1200 |
COVER SEQUENCES | CATEGORY | SEVERITY | ATTEMPTS | ALL MATCHES | FIRST MATCHES | INCOMPLETE | SRC |
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C | 0 | 0 | 2147483647 | 88070 | 88070 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C | 0 | 0 | 2147483647 | 100 | 100 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C | 0 | 0 | 2147483647 | 100 | 100 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C | 0 | 0 | 2147483647 | 100 | 100 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C | 0 | 0 | 2147483647 | 100 | 100 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C | 0 | 0 | 2147483647 | 420 | 420 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C | 0 | 0 | 2147483647 | 876740 | 876740 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C | 0 | 0 | 2147483647 | 33265835 | 33265835 | 1200 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |