Unified Coverage Report :: Group :: uart_agent_pkg::uart_agent_cov::uart_reset_cg

Group : uart_agent_pkg::uart_agent_cov::uart_reset_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
45.71	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_uart_agent_0.1/uart_agent_cov.sv

---

Summary for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	5	8	61.54
Crosses	22	14	8	36.36

Variables for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dir	2	0	2	100.00	100	1	1	0
cp_rst_pos	11	5	6	54.55	100	1	1	0

Crosses for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
uart_reset_cg_cc	22	14	8	36.36	100	1	1	0

Summary for Variable cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_dir

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[UartTx]

3020

1

T1

3

T11

1

T12

3

auto[UartRx]

3020

1

T1

3

T11

1

T12

3

---

Summary for Variable cp_rst_pos

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	5	6	54.55

User Defined Bins for cp_rst_pos

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
values[1]	0	1	1
values[2]	0	1	1
values[3]	0	1	1
values[5]	0	1	1
values[10]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	5140	1			T1	6		T11	2		T12	6
values[4]	300	1			T19	3		T50	3		T51	3
values[6]	200	1			T19	2		T50	2		T51	2
values[7]	100	1			T19	1		T50	1		T51	1
values[8]	100	1			T19	1		T50	1		T51	1
values[9]	200	1			T19	2		T50	2		T51	2

---

Summary for Cross uart_reset_cg_cc

Samples crossed: cp_dir cp_rst_pos

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	22	14	8	36.36	14

Automatically Generated Cross Bins for uart_reset_cg_cc

Uncovered bins

cp_dir	cp_rst_pos	COUNT	AT LEAST	NUMBER	STATUS
[auto[UartTx]]	[values[1] , values[2] , values[3] , values[4] , values[5]]	--	--	5
[auto[UartTx]]	[values[8] , values[9] , values[10]]	--	--	3
[auto[UartRx]]	[values[1] , values[2] , values[3]]	--	--	3
[auto[UartRx]]	[values[5]]	0	1	1
[auto[UartRx]]	[values[7]]	0	1	1
[auto[UartRx]]	[values[10]]	0	1	1

Covered bins

cp_dir	cp_rst_pos	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[UartTx]	values[0]	2820	1			T1	3		T11	1		T12	3
auto[UartTx]	values[6]	100	1			T19	1		T50	1		T51	1
auto[UartTx]	values[7]	100	1			T19	1		T50	1		T51	1
auto[UartRx]	values[0]	2320	1			T1	3		T11	1		T12	3
auto[UartRx]	values[4]	300	1			T19	3		T50	3		T51	3
auto[UartRx]	values[6]	100	1			T19	1		T50	1		T51	1
auto[UartRx]	values[8]	100	1			T19	1		T50	1		T51	1
auto[UartRx]	values[9]	200	1			T19	2		T50	2		T51	2