Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

Group : uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
15.22	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

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Summary for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	5	7	58.33
Crosses	34	34	0	0.00

Variables for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_baud_rate	7	0	7	100.00	100	1	1	0
cp_clk_freq	5	5	0	0.00	100	1	1	0

Crosses for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
baud_rate_w_core_clk_cg_cc	34	34	0	0.00	100	1	1	0

Summary for Variable cp_baud_rate

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_baud_rate

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	3650	1			T18	1		T19	17		T20	1
auto[BaudRate115200]	2700	1			T19	7		T20	2		T42	12
auto[BaudRate230400]	1500	1			T19	3		T20	3		T42	6
auto[BaudRate128Kbps]	2450	1			T18	1		T19	6		T20	6
auto[BaudRate256Kbps]	3600	1			T19	17		T20	4		T42	12
auto[BaudRate1Mbps]	1800	1			T18	2		T19	3		T20	2
auto[BaudRate1p5Mbps]	2500	1			T18	2		T19	9		T20	1

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Summary for Variable cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	5	0	0.00

User Defined Bins for cp_clk_freq

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
freqs[24]	0	1	1
freqs[25]	0	1	1
freqs[48]	0	1	1
freqs[50]	0	1	1
freqs[100]	0	1	1

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Summary for Cross baud_rate_w_core_clk_cg_cc

Samples crossed: cp_baud_rate cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	34	34	0	0.00	34
Automatically Generated Cross Bins	34	34	0	0.00	34
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for baud_rate_w_core_clk_cg_cc

Element holes

cp_baud_rate	cp_clk_freq	COUNT	AT LEAST	NUMBER	STATUS
[auto[BaudRate9600] , auto[BaudRate115200] , auto[BaudRate230400] , auto[BaudRate128Kbps] , auto[BaudRate256Kbps] , auto[BaudRate1Mbps]]	*	--	--	30

Uncovered bins

cp_baud_rate	cp_clk_freq	COUNT	AT LEAST	NUMBER	STATUS
[auto[BaudRate1p5Mbps]]	[freqs[25] , freqs[48] , freqs[50] , freqs[100]]	--	--	4

User Defined Cross Bins for baud_rate_w_core_clk_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
unsupported	0	Excluded