Unified Coverage Report :: Group : uart_env_pkg::uart_env_cov::fifo_level_cg

Summary for Variable cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_dir

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[UartTx]

25830750

1

T18

203

T19

29886

T20

488

auto[UartRx]

25833000

1

T18

203

T19

29897

T20

487

---

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	43246600	1			T18	202		T19	58289		T20	677
all_levels[1]	327600	1			T18	2		T19	53		T20	43
all_levels[2]	210850	1			T19	5		T20	9		T46	53
all_levels[3]	210050	1			T19	2		T20	7		T46	50
all_levels[4]	208850	1			T19	1		T20	3		T46	41
all_levels[5]	208100	1			T19	1		T20	14		T46	36
all_levels[6]	232150	1			T18	1		T19	2		T20	8
all_levels[7]	167350	1			T19	1		T20	8		T46	42
all_levels[8]	194900	1			T18	5		T19	1		T20	1
all_levels[9]	166000	1			T19	2		T20	2		T46	46
all_levels[10]	162700	1			T19	3		T20	3		T46	46
all_levels[11]	170700	1			T19	2		T20	98		T46	39
all_levels[12]	167550	1			T19	1		T20	23		T46	56
all_levels[13]	164500	1			T46	39		T63	3251		T89	3251
all_levels[14]	165050	1			T19	1		T46	40		T63	3258
all_levels[15]	164750	1			T19	4		T46	38		T63	3241
all_levels[16]	164400	1			T19	2		T46	40		T63	3240
all_levels[17]	213550	1			T18	194		T19	3		T20	16
all_levels[18]	43950	1			T19	4		T20	1		T46	47
all_levels[19]	44200	1			T18	2		T19	3		T43	2
all_levels[20]	43550	1			T19	1		T20	1		T46	41
all_levels[21]	44800	1			T19	6		T20	5		T46	42
all_levels[22]	43800	1			T19	3		T46	44		T63	820
all_levels[23]	44350	1			T19	3		T46	50		T63	827
all_levels[24]	72000	1			T19	1		T20	16		T46	47
all_levels[25]	10000	1			T19	1		T46	43		T63	155
all_levels[26]	10850	1			T46	57		T63	155		T89	155
all_levels[27]	9850	1			T46	41		T63	155		T89	155
all_levels[28]	11000	1			T46	53		T63	155		T90	7
all_levels[29]	10850	1			T46	44		T63	155		T89	155
all_levels[30]	9850	1			T46	45		T63	151		T64	1
all_levels[31]	9150	1			T46	42		T63	141		T89	141
all_levels[32]	10350	1			T19	1		T46	49		T63	155
all_levels[33]	9700	1			T46	39		T63	155		T89	155
all_levels[34]	10600	1			T46	55		T63	155		T64	1
all_levels[35]	9650	1			T46	38		T63	155		T89	155
all_levels[36]	10750	1			T20	20		T46	39		T63	155
all_levels[37]	9750	1			T19	1		T46	38		T63	155
all_levels[38]	10850	1			T20	20		T46	45		T63	152
all_levels[39]	9850	1			T46	47		T63	149		T64	1
all_levels[40]	10600	1			T46	51		T63	155		T89	155
all_levels[41]	9900	1			T46	43		T63	155		T89	155
all_levels[42]	10250	1			T19	1		T46	48		T63	155
all_levels[43]	10250	1			T46	50		T63	155		T89	155
all_levels[44]	10000	1			T46	45		T63	155		T89	155
all_levels[45]	10000	1			T19	1		T46	43		T63	155
all_levels[46]	10250	1			T46	50		T63	155		T89	155
all_levels[47]	9800	1			T46	41		T63	155		T89	155
all_levels[48]	9850	1			T46	41		T63	155		T89	155
all_levels[49]	9900	1			T46	43		T63	155		T89	155
all_levels[50]	9850	1			T46	42		T63	155		T89	155
all_levels[51]	7350	1			T19	1		T46	51		T63	93
all_levels[52]	2100	1			T46	41		T63	1		T89	1
all_levels[53]	2600	1			T46	51		T63	1		T89	1
all_levels[54]	2200	1			T19	1		T46	41		T63	1
all_levels[55]	2450	1			T46	47		T63	1		T89	1
all_levels[56]	2350	1			T46	46		T63	1		T89	1
all_levels[57]	2100	1			T46	40		T63	1		T64	1
all_levels[58]	2250	1			T19	1		T46	42		T63	1
all_levels[59]	2450	1			T46	48		T63	1		T89	1
all_levels[60]	2750	1			T19	1		T46	52		T63	1
all_levels[61]	2500	1			T19	1		T46	47		T63	1
all_levels[62]	2000	1			T19	1		T46	37		T63	1
all_levels[63]	2500	1			T46	43		T49	6		T63	1
all_levels[64]	30150	1			T46	48		T49	554		T63	1
all_levels[65]	2300	1			T46	45		T63	1		T89	1
all_levels[66]	2550	1			T19	1		T46	48		T63	1
all_levels[67]	2350	1			T19	1		T46	44		T63	1
all_levels[68]	2450	1			T46	48		T63	1		T89	1
all_levels[69]	2100	1			T46	41		T63	1		T89	1
all_levels[70]	2400	1			T46	47		T63	1		T89	1
all_levels[71]	2400	1			T46	47		T63	1		T89	1
all_levels[72]	2250	1			T46	44		T63	1		T89	1
all_levels[73]	2300	1			T46	45		T63	1		T89	1
all_levels[74]	1600	1			T46	31		T63	1		T89	1
all_levels[75]	2200	1			T46	43		T63	1		T89	1
all_levels[76]	1950	1			T46	38		T63	1		T89	1
all_levels[77]	2750	1			T46	48		T63	1		T64	6
all_levels[78]	2000	1			T46	39		T63	1		T89	1
all_levels[79]	2200	1			T46	43		T63	1		T89	1
all_levels[80]	2600	1			T46	51		T63	1		T89	1
all_levels[81]	2750	1			T19	1		T46	52		T63	1
all_levels[82]	2450	1			T46	48		T63	1		T89	1
all_levels[83]	2750	1			T46	53		T63	1		T89	1
all_levels[84]	2250	1			T46	44		T63	1		T89	1
all_levels[85]	2450	1			T19	1		T46	46		T63	1
all_levels[86]	2350	1			T19	1		T46	44		T63	1
all_levels[87]	2500	1			T46	49		T63	1		T89	1
all_levels[88]	2650	1			T46	52		T63	1		T89	1
all_levels[89]	2700	1			T46	53		T63	1		T89	1
all_levels[90]	3100	1			T46	61		T63	1		T89	1
all_levels[91]	2800	1			T46	53		T63	1		T64	2
all_levels[92]	2400	1			T46	47		T63	1		T89	1
all_levels[93]	2300	1			T46	45		T63	1		T89	1
all_levels[94]	2300	1			T46	45		T63	1		T89	1
all_levels[95]	2200	1			T46	43		T63	1		T89	1
all_levels[96]	4200	1			T19	6		T46	51		T63	1
all_levels[97]	2550	1			T46	50		T63	1		T89	1
all_levels[98]	2400	1			T19	1		T46	45		T63	1
all_levels[99]	56750	1			T19	1		T46	51		T63	1082
all_levels[100]	2250	1			T46	45		T91	45		T92	45
all_levels[101]	2650	1			T46	53		T91	53		T92	53
all_levels[102]	2350	1			T46	47		T91	47		T92	47
all_levels[103]	2050	1			T46	41		T91	41		T92	41
all_levels[104]	2200	1			T46	44		T91	44		T92	44
all_levels[105]	2350	1			T46	47		T91	47		T92	47
all_levels[106]	1400	1			T46	28		T91	28		T92	28
all_levels[107]	2250	1			T46	45		T91	45		T92	45
all_levels[108]	2550	1			T46	51		T91	51		T92	51
all_levels[109]	2250	1			T46	45		T91	45		T92	45
all_levels[110]	2250	1			T46	45		T91	45		T92	45
all_levels[111]	2200	1			T46	44		T91	44		T92	44
all_levels[112]	2350	1			T46	47		T91	47		T92	47
all_levels[113]	2500	1			T46	50		T91	50		T92	50
all_levels[114]	2250	1			T46	45		T91	45		T92	45
all_levels[115]	2500	1			T46	50		T91	50		T92	50
all_levels[116]	2100	1			T46	42		T91	42		T92	42
all_levels[117]	2550	1			T46	51		T91	51		T92	51
all_levels[118]	2250	1			T46	45		T91	45		T92	45
all_levels[119]	1850	1			T46	37		T91	37		T92	37
all_levels[120]	1800	1			T46	36		T91	36		T92	36
all_levels[121]	2300	1			T19	1		T46	44		T50	1
all_levels[122]	2000	1			T46	40		T91	40		T92	40
all_levels[123]	2400	1			T46	48		T91	48		T92	48
all_levels[124]	2400	1			T46	48		T91	48		T92	48
all_levels[125]	2500	1			T46	50		T91	50		T92	50
all_levels[126]	2200	1			T46	44		T91	44		T92	44
all_levels[127]	65050	1			T46	1301		T91	1301		T92	1301
all_levels[128]	4186000	1			T19	1364		T46	80992		T50	1364

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

51653400

1

T18

396

T19

59766

T20

974

auto[1]

10350

1

T18

10

T19

17

T20

1

---

Summary for Cross fifo_level_cg_cc

Samples crossed: cp_dir cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	516	346	170	32.95	346

Automatically Generated Cross Bins for fifo_level_cg_cc

Element holes

cp_dir	cp_lvl	cp_rst	COUNT	AT LEAST	NUMBER	STATUS
[auto[UartRx]]	[all_levels[13] , all_levels[14]]	*	--	--	4
[auto[UartRx]]	[all_levels[18]]	*	--	--	2
[auto[UartRx]]	[all_levels[20] , all_levels[21]]	*	--	--	4
[auto[UartRx]]	[all_levels[24]]	*	--	--	2
[auto[UartRx]]	[all_levels[26] , all_levels[27] , all_levels[28] , all_levels[29]]	*	--	--	8
[auto[UartRx]]	[all_levels[31]]	*	--	--	2
[auto[UartRx]]	[all_levels[33]]	*	--	--	2
[auto[UartRx]]	[all_levels[35]]	*	--	--	2
[auto[UartRx]]	[all_levels[37] , all_levels[38]]	*	--	--	4
[auto[UartRx]]	[all_levels[40] , all_levels[41]]	*	--	--	4
[auto[UartRx]]	[all_levels[43] , all_levels[44] , all_levels[45] , all_levels[46] , all_levels[47]]	*	--	--	10
[auto[UartRx]]	[all_levels[49] , all_levels[50] , all_levels[51] , all_levels[52] , all_levels[53] , all_levels[54]]	*	--	--	12
[auto[UartRx]]	[all_levels[56]]	*	--	--	2
[auto[UartRx]]	[all_levels[58] , all_levels[59] , all_levels[60] , all_levels[61]]	*	--	--	8
[auto[UartRx]]	[all_levels[63] , all_levels[64] , all_levels[65] , all_levels[66] , all_levels[67] , all_levels[68] , all_levels[69] , all_levels[70] , all_levels[71] , all_levels[72] , all_levels[73] , all_levels[74] , all_levels[75] , all_levels[76] , all_levels[77] , all_levels[78] , all_levels[79] , all_levels[80] , all_levels[81] , all_levels[82] , all_levels[83] , all_levels[84] , all_levels[85] , all_levels[86] , all_levels[87] , all_levels[88] , all_levels[89] , all_levels[90] , all_levels[91] , all_levels[92] , all_levels[93] , all_levels[94] , all_levels[95] , all_levels[96] , all_levels[97] , all_levels[98] , all_levels[99] , all_levels[100] , all_levels[101] , all_levels[102] , all_levels[103] , all_levels[104] , all_levels[105] , all_levels[106] , all_levels[107] , all_levels[108] , all_levels[109] , all_levels[110] , all_levels[111] , all_levels[112] , all_levels[113] , all_levels[114] , all_levels[115] , all_levels[116] , all_levels[117] , all_levels[118] , all_levels[119] , all_levels[120] , all_levels[121] , all_levels[122] , all_levels[123] , all_levels[124] , all_levels[125] , all_levels[126] , all_levels[127] , all_levels[128]]	*	--	--	132

Uncovered bins

cp_dir	cp_lvl	cp_rst	COUNT	AT LEAST	NUMBER	STATUS
[auto[UartTx]]	[all_levels[1] , all_levels[2] , all_levels[3] , all_levels[4] , all_levels[5] , all_levels[6]]	[auto[1]]	--	--	6
[auto[UartTx]]	[all_levels[9] , all_levels[10]]	[auto[1]]	--	--	2
[auto[UartTx]]	[all_levels[12] , all_levels[13] , all_levels[14] , all_levels[15] , all_levels[16]]	[auto[1]]	--	--	5
[auto[UartTx]]	[all_levels[18] , all_levels[19] , all_levels[20] , all_levels[21] , all_levels[22] , all_levels[23] , all_levels[24] , all_levels[25] , all_levels[26] , all_levels[27]]	[auto[1]]	--	--	10
[auto[UartTx]]	[all_levels[29] , all_levels[30] , all_levels[31] , all_levels[32] , all_levels[33] , all_levels[34] , all_levels[35] , all_levels[36] , all_levels[37] , all_levels[38] , all_levels[39]]	[auto[1]]	--	--	11
[auto[UartTx]]	[all_levels[41] , all_levels[42] , all_levels[43] , all_levels[44] , all_levels[45] , all_levels[46] , all_levels[47] , all_levels[48] , all_levels[49] , all_levels[50] , all_levels[51] , all_levels[52] , all_levels[53] , all_levels[54] , all_levels[55] , all_levels[56] , all_levels[57] , all_levels[58] , all_levels[59] , all_levels[60] , all_levels[61] , all_levels[62]]	[auto[1]]	--	--	22
[auto[UartTx]]	[all_levels[64] , all_levels[65] , all_levels[66] , all_levels[67] , all_levels[68] , all_levels[69] , all_levels[70] , all_levels[71] , all_levels[72] , all_levels[73] , all_levels[74] , all_levels[75] , all_levels[76] , all_levels[77] , all_levels[78] , all_levels[79] , all_levels[80] , all_levels[81] , all_levels[82] , all_levels[83] , all_levels[84] , all_levels[85] , all_levels[86] , all_levels[87] , all_levels[88] , all_levels[89] , all_levels[90] , all_levels[91] , all_levels[92] , all_levels[93] , all_levels[94] , all_levels[95] , all_levels[96] , all_levels[97] , all_levels[98]]	[auto[1]]	--	--	35
[auto[UartTx]]	[all_levels[100] , all_levels[101] , all_levels[102] , all_levels[103] , all_levels[104] , all_levels[105] , all_levels[106] , all_levels[107] , all_levels[108] , all_levels[109] , all_levels[110] , all_levels[111] , all_levels[112] , all_levels[113] , all_levels[114] , all_levels[115] , all_levels[116] , all_levels[117] , all_levels[118] , all_levels[119] , all_levels[120] , all_levels[121] , all_levels[122] , all_levels[123] , all_levels[124] , all_levels[125] , all_levels[126] , all_levels[127] , all_levels[128]]	[auto[1]]	--	--	29
[auto[UartRx]]	[all_levels[1] , all_levels[2] , all_levels[3] , all_levels[4] , all_levels[5] , all_levels[6] , all_levels[7] , all_levels[8] , all_levels[9] , all_levels[10] , all_levels[11] , all_levels[12]]	[auto[1]]	--	--	12
[auto[UartRx]]	[all_levels[15] , all_levels[16] , all_levels[17]]	[auto[1]]	--	--	3
[auto[UartRx]]	[all_levels[22] , all_levels[23]]	[auto[1]]	--	--	2
[auto[UartRx]]	[all_levels[25]]	[auto[1]]	0	1	1
[auto[UartRx]]	[all_levels[30]]	[auto[1]]	0	1	1
[auto[UartRx]]	[all_levels[32]]	[auto[1]]	0	1	1
[auto[UartRx]]	[all_levels[34]]	[auto[1]]	0	1	1
[auto[UartRx]]	[all_levels[36]]	[auto[1]]	0	1	1
[auto[UartRx]]	[all_levels[39]]	[auto[1]]	0	1	1
[auto[UartRx]]	[all_levels[42]]	[auto[1]]	0	1	1
[auto[UartRx]]	[all_levels[48]]	[auto[1]]	0	1	1
[auto[UartRx]]	[all_levels[55]]	[auto[1]]	0	1	1
[auto[UartRx]]	[all_levels[57]]	[auto[1]]	0	1	1
[auto[UartRx]]	[all_levels[62]]	[auto[1]]	0	1	1

Covered bins

cp_dir	cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[UartTx]	all_levels[0]	auto[0]	17530850	1			T18	1		T19	28432		T20	212
auto[UartTx]	all_levels[0]	auto[1]	1500	1			T18	1		T19	3		T43	1
auto[UartTx]	all_levels[1]	auto[0]	214450	1			T18	1		T19	19		T20	26
auto[UartTx]	all_levels[2]	auto[0]	209400	1			T19	3		T20	6		T46	53
auto[UartTx]	all_levels[3]	auto[0]	209100	1			T19	2		T20	5		T46	50
auto[UartTx]	all_levels[4]	auto[0]	208400	1			T19	1		T20	3		T46	41
auto[UartTx]	all_levels[5]	auto[0]	207900	1			T19	1		T20	14		T46	36
auto[UartTx]	all_levels[6]	auto[0]	232000	1			T18	1		T19	2		T20	8
auto[UartTx]	all_levels[7]	auto[0]	166350	1			T19	1		T20	8		T46	42
auto[UartTx]	all_levels[7]	auto[1]	900	1			T49	18		T61	18		T62	18
auto[UartTx]	all_levels[8]	auto[0]	193900	1			T18	2		T19	1		T20	1
auto[UartTx]	all_levels[8]	auto[1]	900	1			T18	3		T43	3		T44	3
auto[UartTx]	all_levels[9]	auto[0]	165850	1			T19	2		T20	2		T46	46
auto[UartTx]	all_levels[10]	auto[0]	162650	1			T19	3		T20	3		T46	46
auto[UartTx]	all_levels[11]	auto[0]	170450	1			T19	1		T20	97		T46	39
auto[UartTx]	all_levels[11]	auto[1]	50	1			T20	1		T93	1		T94	1
auto[UartTx]	all_levels[12]	auto[0]	167400	1			T20	23		T46	56		T63	3256
auto[UartTx]	all_levels[13]	auto[0]	164500	1			T46	39		T63	3251		T89	3251
auto[UartTx]	all_levels[14]	auto[0]	165050	1			T19	1		T46	40		T63	3258
auto[UartTx]	all_levels[15]	auto[0]	164700	1			T19	4		T46	38		T63	3241
auto[UartTx]	all_levels[16]	auto[0]	164350	1			T19	2		T46	40		T63	3240
auto[UartTx]	all_levels[17]	auto[0]	213200	1			T18	193		T19	3		T20	16
auto[UartTx]	all_levels[17]	auto[1]	300	1			T18	1		T43	1		T44	1
auto[UartTx]	all_levels[18]	auto[0]	43950	1			T19	4		T20	1		T46	47
auto[UartTx]	all_levels[19]	auto[0]	43600	1			T19	3		T46	48		T63	816
auto[UartTx]	all_levels[20]	auto[0]	43550	1			T19	1		T20	1		T46	41
auto[UartTx]	all_levels[21]	auto[0]	44800	1			T19	6		T20	5		T46	42
auto[UartTx]	all_levels[22]	auto[0]	43700	1			T19	2		T46	44		T63	820
auto[UartTx]	all_levels[23]	auto[0]	44250	1			T19	2		T46	50		T63	827
auto[UartTx]	all_levels[24]	auto[0]	72000	1			T19	1		T20	16		T46	47
auto[UartTx]	all_levels[25]	auto[0]	9900	1			T46	43		T63	155		T89	155
auto[UartTx]	all_levels[26]	auto[0]	10850	1			T46	57		T63	155		T89	155
auto[UartTx]	all_levels[27]	auto[0]	9850	1			T46	41		T63	155		T89	155
auto[UartTx]	all_levels[28]	auto[0]	10950	1			T46	53		T63	155		T90	6
auto[UartTx]	all_levels[28]	auto[1]	50	1			T90	1		T95	1		T96	1
auto[UartTx]	all_levels[29]	auto[0]	10850	1			T46	44		T63	155		T89	155
auto[UartTx]	all_levels[30]	auto[0]	9800	1			T46	45		T63	151		T89	151
auto[UartTx]	all_levels[31]	auto[0]	9150	1			T46	42		T63	141		T89	141
auto[UartTx]	all_levels[32]	auto[0]	10300	1			T19	1		T46	49		T63	155
auto[UartTx]	all_levels[33]	auto[0]	9700	1			T46	39		T63	155		T89	155
auto[UartTx]	all_levels[34]	auto[0]	10550	1			T46	55		T63	155		T64	1
auto[UartTx]	all_levels[35]	auto[0]	9650	1			T46	38		T63	155		T89	155
auto[UartTx]	all_levels[36]	auto[0]	10700	1			T20	20		T46	39		T63	155
auto[UartTx]	all_levels[37]	auto[0]	9750	1			T19	1		T46	38		T63	155
auto[UartTx]	all_levels[38]	auto[0]	10850	1			T20	20		T46	45		T63	152
auto[UartTx]	all_levels[39]	auto[0]	9800	1			T46	47		T63	149		T89	149
auto[UartTx]	all_levels[40]	auto[0]	10550	1			T46	51		T63	155		T89	155
auto[UartTx]	all_levels[40]	auto[1]	50	1			T97	1		T98	1		T99	1
auto[UartTx]	all_levels[41]	auto[0]	9900	1			T46	43		T63	155		T89	155
auto[UartTx]	all_levels[42]	auto[0]	10150	1			T46	48		T63	155		T89	155
auto[UartTx]	all_levels[43]	auto[0]	10250	1			T46	50		T63	155		T89	155
auto[UartTx]	all_levels[44]	auto[0]	10000	1			T46	45		T63	155		T89	155
auto[UartTx]	all_levels[45]	auto[0]	10000	1			T19	1		T46	43		T63	155
auto[UartTx]	all_levels[46]	auto[0]	10250	1			T46	50		T63	155		T89	155
auto[UartTx]	all_levels[47]	auto[0]	9800	1			T46	41		T63	155		T89	155
auto[UartTx]	all_levels[48]	auto[0]	9800	1			T46	41		T63	155		T89	155
auto[UartTx]	all_levels[49]	auto[0]	9900	1			T46	43		T63	155		T89	155
auto[UartTx]	all_levels[50]	auto[0]	9850	1			T46	42		T63	155		T89	155
auto[UartTx]	all_levels[51]	auto[0]	7350	1			T19	1		T46	51		T63	93
auto[UartTx]	all_levels[52]	auto[0]	2100	1			T46	41		T63	1		T89	1
auto[UartTx]	all_levels[53]	auto[0]	2600	1			T46	51		T63	1		T89	1
auto[UartTx]	all_levels[54]	auto[0]	2200	1			T19	1		T46	41		T63	1
auto[UartTx]	all_levels[55]	auto[0]	2400	1			T46	47		T63	1		T89	1
auto[UartTx]	all_levels[56]	auto[0]	2350	1			T46	46		T63	1		T89	1
auto[UartTx]	all_levels[57]	auto[0]	2050	1			T46	40		T63	1		T89	1
auto[UartTx]	all_levels[58]	auto[0]	2250	1			T19	1		T46	42		T63	1
auto[UartTx]	all_levels[59]	auto[0]	2450	1			T46	48		T63	1		T89	1
auto[UartTx]	all_levels[60]	auto[0]	2750	1			T19	1		T46	52		T63	1
auto[UartTx]	all_levels[61]	auto[0]	2500	1			T19	1		T46	47		T63	1
auto[UartTx]	all_levels[62]	auto[0]	1900	1			T46	37		T63	1		T89	1
auto[UartTx]	all_levels[63]	auto[0]	2250	1			T46	43		T49	1		T63	1
auto[UartTx]	all_levels[63]	auto[1]	250	1			T49	5		T61	5		T62	5
auto[UartTx]	all_levels[64]	auto[0]	30150	1			T46	48		T49	554		T63	1
auto[UartTx]	all_levels[65]	auto[0]	2300	1			T46	45		T63	1		T89	1
auto[UartTx]	all_levels[66]	auto[0]	2550	1			T19	1		T46	48		T63	1
auto[UartTx]	all_levels[67]	auto[0]	2350	1			T19	1		T46	44		T63	1
auto[UartTx]	all_levels[68]	auto[0]	2450	1			T46	48		T63	1		T89	1
auto[UartTx]	all_levels[69]	auto[0]	2100	1			T46	41		T63	1		T89	1
auto[UartTx]	all_levels[70]	auto[0]	2400	1			T46	47		T63	1		T89	1
auto[UartTx]	all_levels[71]	auto[0]	2400	1			T46	47		T63	1		T89	1
auto[UartTx]	all_levels[72]	auto[0]	2250	1			T46	44		T63	1		T89	1
auto[UartTx]	all_levels[73]	auto[0]	2300	1			T46	45		T63	1		T89	1
auto[UartTx]	all_levels[74]	auto[0]	1600	1			T46	31		T63	1		T89	1
auto[UartTx]	all_levels[75]	auto[0]	2200	1			T46	43		T63	1		T89	1
auto[UartTx]	all_levels[76]	auto[0]	1950	1			T46	38		T63	1		T89	1
auto[UartTx]	all_levels[77]	auto[0]	2750	1			T46	48		T63	1		T64	6
auto[UartTx]	all_levels[78]	auto[0]	2000	1			T46	39		T63	1		T89	1
auto[UartTx]	all_levels[79]	auto[0]	2200	1			T46	43		T63	1		T89	1
auto[UartTx]	all_levels[80]	auto[0]	2600	1			T46	51		T63	1		T89	1
auto[UartTx]	all_levels[81]	auto[0]	2750	1			T19	1		T46	52		T63	1
auto[UartTx]	all_levels[82]	auto[0]	2450	1			T46	48		T63	1		T89	1
auto[UartTx]	all_levels[83]	auto[0]	2750	1			T46	53		T63	1		T89	1
auto[UartTx]	all_levels[84]	auto[0]	2250	1			T46	44		T63	1		T89	1
auto[UartTx]	all_levels[85]	auto[0]	2450	1			T19	1		T46	46		T63	1
auto[UartTx]	all_levels[86]	auto[0]	2350	1			T19	1		T46	44		T63	1
auto[UartTx]	all_levels[87]	auto[0]	2500	1			T46	49		T63	1		T89	1
auto[UartTx]	all_levels[88]	auto[0]	2650	1			T46	52		T63	1		T89	1
auto[UartTx]	all_levels[89]	auto[0]	2700	1			T46	53		T63	1		T89	1
auto[UartTx]	all_levels[90]	auto[0]	3100	1			T46	61		T63	1		T89	1
auto[UartTx]	all_levels[91]	auto[0]	2800	1			T46	53		T63	1		T64	2
auto[UartTx]	all_levels[92]	auto[0]	2400	1			T46	47		T63	1		T89	1
auto[UartTx]	all_levels[93]	auto[0]	2300	1			T46	45		T63	1		T89	1
auto[UartTx]	all_levels[94]	auto[0]	2300	1			T46	45		T63	1		T89	1
auto[UartTx]	all_levels[95]	auto[0]	2200	1			T46	43		T63	1		T89	1
auto[UartTx]	all_levels[96]	auto[0]	4200	1			T19	6		T46	51		T63	1
auto[UartTx]	all_levels[97]	auto[0]	2550	1			T46	50		T63	1		T89	1
auto[UartTx]	all_levels[98]	auto[0]	2400	1			T19	1		T46	45		T63	1
auto[UartTx]	all_levels[99]	auto[0]	56700	1			T19	1		T46	51		T63	1081
auto[UartTx]	all_levels[99]	auto[1]	50	1			T63	1		T89	1		T100	1
auto[UartTx]	all_levels[100]	auto[0]	2250	1			T46	45		T91	45		T92	45
auto[UartTx]	all_levels[101]	auto[0]	2650	1			T46	53		T91	53		T92	53
auto[UartTx]	all_levels[102]	auto[0]	2350	1			T46	47		T91	47		T92	47
auto[UartTx]	all_levels[103]	auto[0]	2050	1			T46	41		T91	41		T92	41
auto[UartTx]	all_levels[104]	auto[0]	2200	1			T46	44		T91	44		T92	44
auto[UartTx]	all_levels[105]	auto[0]	2350	1			T46	47		T91	47		T92	47
auto[UartTx]	all_levels[106]	auto[0]	1400	1			T46	28		T91	28		T92	28
auto[UartTx]	all_levels[107]	auto[0]	2250	1			T46	45		T91	45		T92	45
auto[UartTx]	all_levels[108]	auto[0]	2550	1			T46	51		T91	51		T92	51
auto[UartTx]	all_levels[109]	auto[0]	2250	1			T46	45		T91	45		T92	45
auto[UartTx]	all_levels[110]	auto[0]	2250	1			T46	45		T91	45		T92	45
auto[UartTx]	all_levels[111]	auto[0]	2200	1			T46	44		T91	44		T92	44
auto[UartTx]	all_levels[112]	auto[0]	2350	1			T46	47		T91	47		T92	47
auto[UartTx]	all_levels[113]	auto[0]	2500	1			T46	50		T91	50		T92	50
auto[UartTx]	all_levels[114]	auto[0]	2250	1			T46	45		T91	45		T92	45
auto[UartTx]	all_levels[115]	auto[0]	2500	1			T46	50		T91	50		T92	50
auto[UartTx]	all_levels[116]	auto[0]	2100	1			T46	42		T91	42		T92	42
auto[UartTx]	all_levels[117]	auto[0]	2550	1			T46	51		T91	51		T92	51
auto[UartTx]	all_levels[118]	auto[0]	2250	1			T46	45		T91	45		T92	45
auto[UartTx]	all_levels[119]	auto[0]	1850	1			T46	37		T91	37		T92	37
auto[UartTx]	all_levels[120]	auto[0]	1800	1			T46	36		T91	36		T92	36
auto[UartTx]	all_levels[121]	auto[0]	2300	1			T19	1		T46	44		T50	1
auto[UartTx]	all_levels[122]	auto[0]	2000	1			T46	40		T91	40		T92	40
auto[UartTx]	all_levels[123]	auto[0]	2400	1			T46	48		T91	48		T92	48
auto[UartTx]	all_levels[124]	auto[0]	2400	1			T46	48		T91	48		T92	48
auto[UartTx]	all_levels[125]	auto[0]	2500	1			T46	50		T91	50		T92	50
auto[UartTx]	all_levels[126]	auto[0]	2200	1			T46	44		T91	44		T92	44
auto[UartTx]	all_levels[127]	auto[0]	65050	1			T46	1301		T91	1301		T92	1301
auto[UartTx]	all_levels[128]	auto[0]	4186000	1			T19	1364		T46	80992		T50	1364
auto[UartRx]	all_levels[0]	auto[0]	25708250	1			T18	196		T19	29840		T20	465
auto[UartRx]	all_levels[0]	auto[1]	6000	1			T18	4		T19	14		T42	14
auto[UartRx]	all_levels[1]	auto[0]	113150	1			T18	1		T19	34		T20	17
auto[UartRx]	all_levels[2]	auto[0]	1450	1			T19	2		T20	3		T50	2
auto[UartRx]	all_levels[3]	auto[0]	950	1			T20	2		T101	5		T64	2
auto[UartRx]	all_levels[4]	auto[0]	450	1			T64	3		T97	3		T102	3
auto[UartRx]	all_levels[5]	auto[0]	200	1			T101	1		T97	3		T98	3
auto[UartRx]	all_levels[6]	auto[0]	150	1			T97	3		T98	3		T99	3
auto[UartRx]	all_levels[7]	auto[0]	100	1			T102	2		T103	2		T104	2
auto[UartRx]	all_levels[8]	auto[0]	100	1			T97	1		T102	1		T103	1
auto[UartRx]	all_levels[9]	auto[0]	150	1			T97	2		T102	1		T103	1
auto[UartRx]	all_levels[10]	auto[0]	50	1			T97	1		T98	1		T99	1
auto[UartRx]	all_levels[11]	auto[0]	200	1			T19	1		T50	1		T51	1
auto[UartRx]	all_levels[12]	auto[0]	150	1			T19	1		T50	1		T51	1
auto[UartRx]	all_levels[15]	auto[0]	50	1			T97	1		T98	1		T99	1
auto[UartRx]	all_levels[16]	auto[0]	50	1			T64	1		T105	1		T106	1
auto[UartRx]	all_levels[17]	auto[0]	50	1			T64	1		T105	1		T106	1
auto[UartRx]	all_levels[19]	auto[0]	300	1			T18	1		T43	1		T44	1
auto[UartRx]	all_levels[19]	auto[1]	300	1			T18	1		T43	1		T44	1
auto[UartRx]	all_levels[22]	auto[0]	100	1			T19	1		T50	1		T51	1
auto[UartRx]	all_levels[23]	auto[0]	100	1			T19	1		T50	1		T51	1
auto[UartRx]	all_levels[25]	auto[0]	100	1			T19	1		T50	1		T51	1
auto[UartRx]	all_levels[30]	auto[0]	50	1			T64	1		T105	1		T106	1
auto[UartRx]	all_levels[32]	auto[0]	50	1			T64	1		T105	1		T106	1
auto[UartRx]	all_levels[34]	auto[0]	50	1			T97	1		T98	1		T99	1
auto[UartRx]	all_levels[36]	auto[0]	50	1			T97	1		T98	1		T99	1
auto[UartRx]	all_levels[39]	auto[0]	50	1			T64	1		T105	1		T106	1
auto[UartRx]	all_levels[42]	auto[0]	100	1			T19	1		T50	1		T51	1
auto[UartRx]	all_levels[48]	auto[0]	50	1			T97	1		T98	1		T99	1
auto[UartRx]	all_levels[55]	auto[0]	50	1			T97	1		T98	1		T99	1
auto[UartRx]	all_levels[57]	auto[0]	50	1			T64	1		T105	1		T106	1
auto[UartRx]	all_levels[62]	auto[0]	100	1			T19	1		T50	1		T51	1