Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	99720	1			T2	1		T13	8		T14	8
all_pins[1]	99720	1			T2	1		T13	8		T14	8
all_pins[2]	99720	1			T2	1		T13	8		T14	8
all_pins[3]	99720	1			T2	1		T13	8		T14	8
all_pins[4]	99720	1			T2	1		T13	8		T14	8
all_pins[5]	99720	1			T2	1		T13	8		T14	8
all_pins[6]	99720	1			T2	1		T13	8		T14	8
all_pins[7]	99720	1			T2	1		T13	8		T14	8

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	786660	1			T2	8		T13	46		T14	46
values[0x1]	11100	1			T13	18		T14	18		T17	18
transitions[0x0=>0x1]	9100	1			T13	11		T14	11		T17	11
transitions[0x1=>0x0]	9100	1			T13	11		T14	11		T17	11

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	96970	1			T2	1		T13	5		T14	5
all_pins[0]	values[0x1]	2750	1			T13	3		T14	3		T17	3
all_pins[0]	transitions[0x0=>0x1]	2500	1			T13	3		T14	3		T17	3
all_pins[0]	transitions[0x1=>0x0]	1150	1			T13	3		T14	3		T17	3
all_pins[1]	values[0x0]	98320	1			T2	1		T13	5		T14	5
all_pins[1]	values[0x1]	1400	1			T13	3		T14	3		T17	3
all_pins[1]	transitions[0x0=>0x1]	800	1			T19	3		T50	3		T51	3
all_pins[1]	transitions[0x1=>0x0]	2900	1			T13	2		T14	2		T17	2
all_pins[2]	values[0x0]	96220	1			T2	1		T13	3		T14	3
all_pins[2]	values[0x1]	3500	1			T13	5		T14	5		T17	5
all_pins[2]	transitions[0x0=>0x1]	3250	1			T13	4		T14	4		T17	4
all_pins[2]	transitions[0x1=>0x0]	350	1			T49	4		T101	3		T61	4
all_pins[3]	values[0x0]	99120	1			T2	1		T13	7		T14	7
all_pins[3]	values[0x1]	600	1			T13	1		T14	1		T17	1
all_pins[3]	transitions[0x0=>0x1]	500	1			T19	2		T49	4		T50	2
all_pins[3]	transitions[0x1=>0x0]	550	1			T13	2		T14	2		T17	2
all_pins[4]	values[0x0]	99070	1			T2	1		T13	5		T14	5
all_pins[4]	values[0x1]	650	1			T13	3		T14	3		T17	3
all_pins[4]	transitions[0x0=>0x1]	400	1			T13	1		T14	1		T17	1
all_pins[4]	transitions[0x1=>0x0]	450	1			T13	1		T14	1		T17	1
all_pins[5]	values[0x0]	99020	1			T2	1		T13	5		T14	5
all_pins[5]	values[0x1]	700	1			T13	3		T14	3		T17	3
all_pins[5]	transitions[0x0=>0x1]	400	1			T13	3		T14	3		T17	3
all_pins[5]	transitions[0x1=>0x0]	750	1			T19	1		T20	1		T50	1
all_pins[6]	values[0x0]	98670	1			T2	1		T13	8		T14	8
all_pins[6]	values[0x1]	1050	1			T19	4		T20	1		T50	4
all_pins[6]	transitions[0x0=>0x1]	950	1			T19	3		T20	1		T50	3
all_pins[6]	transitions[0x1=>0x0]	350	1			T19	1		T50	1		T51	1
all_pins[7]	values[0x0]	99270	1			T2	1		T13	8		T14	8
all_pins[7]	values[0x1]	450	1			T19	2		T50	2		T51	2
all_pins[7]	transitions[0x0=>0x1]	300	1			T19	1		T50	1		T51	1
all_pins[7]	transitions[0x1=>0x0]	2600	1			T13	3		T14	3		T17	3