Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.39	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	1	47	97.92

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	1	47	97.92	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	1600	1			T13	7		T14	7		T17	7
all_values[1]	1600	1			T13	7		T14	7		T17	7
all_values[2]	1600	1			T13	7		T14	7		T17	7
all_values[3]	1600	1			T13	7		T14	7		T17	7
all_values[4]	1600	1			T13	7		T14	7		T17	7
all_values[5]	1600	1			T13	7		T14	7		T17	7
all_values[6]	1600	1			T13	7		T14	7		T17	7
all_values[7]	1600	1			T13	7		T14	7		T17	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

6750

1

T13

32

T14

32

T17

32

auto[1]

6050

1

T13

24

T14

24

T17

24

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4350

1

T13

22

T14

22

T17

22

auto[1]

8450

1

T13

34

T14

34

T17

34

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7000

1

T13

33

T14

33

T17

33

auto[1]

5800

1

T13

23

T14

23

T17

23

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	1	47	97.92	1
Automatically Generated Cross Bins	48	1	47	97.92	1
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Uncovered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	250	1			T13	1		T14	1		T17	1
all_values[0]	auto[0]	auto[0]	auto[1]	250	1			T13	2		T14	2		T17	2
all_values[0]	auto[0]	auto[1]	auto[0]	450	1			T19	3		T50	3		T51	3
all_values[0]	auto[0]	auto[1]	auto[1]	50	1			T101	1		T107	1		T108	1
all_values[0]	auto[1]	auto[0]	auto[1]	200	1			T13	2		T14	2		T17	2
all_values[0]	auto[1]	auto[1]	auto[1]	400	1			T13	2		T14	2		T17	2
all_values[1]	auto[0]	auto[0]	auto[0]	250	1			T13	2		T14	2		T17	2
all_values[1]	auto[0]	auto[0]	auto[1]	200	1			T19	2		T50	2		T51	2
all_values[1]	auto[0]	auto[1]	auto[0]	100	1			T13	1		T14	1		T17	1
all_values[1]	auto[0]	auto[1]	auto[1]	150	1			T13	1		T14	1		T17	1
all_values[1]	auto[1]	auto[0]	auto[1]	450	1			T13	1		T14	1		T17	1
all_values[1]	auto[1]	auto[1]	auto[1]	450	1			T13	2		T14	2		T17	2
all_values[2]	auto[0]	auto[0]	auto[0]	450	1			T13	1		T14	1		T17	1
all_values[2]	auto[0]	auto[0]	auto[1]	50	1			T101	1		T107	1		T108	1
all_values[2]	auto[0]	auto[1]	auto[0]	250	1			T19	1		T50	1		T51	1
all_values[2]	auto[0]	auto[1]	auto[1]	500	1			T13	4		T14	4		T17	4
all_values[2]	auto[1]	auto[0]	auto[1]	200	1			T13	1		T14	1		T17	1
all_values[2]	auto[1]	auto[1]	auto[1]	150	1			T13	1		T14	1		T17	1
all_values[3]	auto[0]	auto[0]	auto[0]	250	1			T13	3		T14	3		T17	3
all_values[3]	auto[0]	auto[0]	auto[1]	250	1			T19	1		T50	1		T51	1
all_values[3]	auto[0]	auto[1]	auto[0]	400	1			T13	3		T14	3		T17	3
all_values[3]	auto[0]	auto[1]	auto[1]	300	1			T19	2		T50	2		T51	2
all_values[3]	auto[1]	auto[0]	auto[1]	300	1			T19	2		T50	2		T51	2
all_values[3]	auto[1]	auto[1]	auto[1]	100	1			T13	1		T14	1		T17	1
all_values[4]	auto[0]	auto[0]	auto[0]	200	1			T13	1		T14	1		T17	1
all_values[4]	auto[0]	auto[0]	auto[1]	200	1			T13	1		T14	1		T17	1
all_values[4]	auto[0]	auto[1]	auto[0]	200	1			T101	4		T107	4		T108	4
all_values[4]	auto[0]	auto[1]	auto[1]	50	1			T13	1		T14	1		T17	1
all_values[4]	auto[1]	auto[0]	auto[1]	450	1			T13	1		T14	1		T17	1
all_values[4]	auto[1]	auto[1]	auto[1]	500	1			T13	3		T14	3		T17	3
all_values[5]	auto[0]	auto[0]	auto[0]	500	1			T13	2		T14	2		T17	2
all_values[5]	auto[0]	auto[1]	auto[0]	100	1			T101	2		T107	2		T108	2
all_values[5]	auto[0]	auto[1]	auto[1]	150	1			T13	1		T14	1		T17	1
all_values[5]	auto[1]	auto[0]	auto[1]	400	1			T13	3		T14	3		T17	3
all_values[5]	auto[1]	auto[1]	auto[1]	450	1			T13	1		T14	1		T17	1
all_values[6]	auto[0]	auto[0]	auto[0]	150	1			T13	3		T14	3		T17	3
all_values[6]	auto[0]	auto[0]	auto[1]	150	1			T101	3		T107	3		T108	3
all_values[6]	auto[0]	auto[1]	auto[0]	250	1			T13	2		T14	2		T17	2
all_values[6]	auto[0]	auto[1]	auto[1]	100	1			T19	1		T50	1		T51	1
all_values[6]	auto[1]	auto[0]	auto[1]	450	1			T13	2		T14	2		T17	2
all_values[6]	auto[1]	auto[1]	auto[1]	500	1			T19	3		T50	3		T51	3
all_values[7]	auto[0]	auto[0]	auto[0]	500	1			T13	2		T14	2		T17	2
all_values[7]	auto[0]	auto[0]	auto[1]	100	1			T13	1		T14	1		T17	1
all_values[7]	auto[0]	auto[1]	auto[0]	50	1			T13	1		T14	1		T17	1
all_values[7]	auto[0]	auto[1]	auto[1]	150	1			T19	1		T50	1		T51	1
all_values[7]	auto[1]	auto[0]	auto[1]	550	1			T13	3		T14	3		T17	3
all_values[7]	auto[1]	auto[1]	auto[1]	250	1			T19	2		T50	2		T51	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal