| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 92.89 | 99.79 | 98.22 | 100.00 | 99.52 | 98.20 | 61.62 |
| T1251 | /workspace/coverage/default/44.uart_alert_test.57552881178229913936685400126141013537922124930066447559639587172527126966231 | Nov 22 01:45:26 PM PST 23 | Nov 22 01:45:27 PM PST 23 | 16368684 ps | ||
| T1252 | /workspace/coverage/default/39.uart_tx_rx.25471902358356301437619251670069398140462769156106537006103948645837673837971 | Nov 22 01:45:04 PM PST 23 | Nov 22 01:46:08 PM PST 23 | 57391945390 ps | ||
| T1253 | /workspace/coverage/default/32.uart_rx_oversample.191358865463706490286067776290673816452802542810051512554863633327458335070 | Nov 22 01:44:44 PM PST 23 | Nov 22 01:45:06 PM PST 23 | 4370280281 ps | ||
| T1254 | /workspace/coverage/default/9.uart_fifo_full.43788496854139338885941420867062168900107984544268895146318781527115626696914 | Nov 22 01:43:55 PM PST 23 | Nov 22 01:45:00 PM PST 23 | 61777160308 ps | ||
| T1255 | /workspace/coverage/default/64.uart_fifo_reset.80832995571771748593791819029368585709393407608894186595736947710159017209501 | Nov 22 01:46:15 PM PST 23 | Nov 22 01:48:10 PM PST 23 | 123972198458 ps | ||
| T1256 | /workspace/coverage/default/208.uart_fifo_reset.10948138693547725705272507187729990368090982564318741295547389937137399666615 | Nov 22 01:46:19 PM PST 23 | Nov 22 01:48:14 PM PST 23 | 123972198458 ps | ||
| T1257 | /workspace/coverage/default/48.uart_perf.60726984759752000919084854513884666874074582234589053226895330045980393603887 | Nov 22 01:46:01 PM PST 23 | Nov 22 01:53:53 PM PST 23 | 14098773881 ps | ||
| T1258 | /workspace/coverage/default/25.uart_long_xfer_wo_dly.65604440310466837548799471639665485769613862347543326018915219858977747253227 | Nov 22 01:44:41 PM PST 23 | Nov 22 01:50:38 PM PST 23 | 93387746707 ps | ||
| T1259 | /workspace/coverage/default/25.uart_loopback.9117893846578164555393654257451009057713808869953581864780696558632757033691 | Nov 22 01:44:41 PM PST 23 | Nov 22 01:44:58 PM PST 23 | 14572448663 ps | ||
| T1260 | /workspace/coverage/default/40.uart_fifo_full.26730455971523155199385993422827037265658994825214670303358364848230159918846 | Nov 22 01:45:28 PM PST 23 | Nov 22 01:46:31 PM PST 23 | 61777160308 ps | ||
| T1261 | /workspace/coverage/default/51.uart_stress_all_with_rand_reset.46905886211817266953030335844478819369984682501632856811358595466963204017887 | Nov 22 01:45:28 PM PST 23 | Nov 22 01:53:19 PM PST 23 | 87476847566 ps | ||
| T1262 | /workspace/coverage/default/30.uart_alert_test.85375651964464094311215071156100469471335282789020772516320348236053821019089 | Nov 22 01:45:09 PM PST 23 | Nov 22 01:45:11 PM PST 23 | 16368684 ps | ||
| T1263 | /workspace/coverage/default/162.uart_fifo_reset.67573203709301459275352231888320269208589049742758146820294893942118475613628 | Nov 22 01:46:05 PM PST 23 | Nov 22 01:48:05 PM PST 23 | 123972198458 ps | ||
| T1264 | /workspace/coverage/default/18.uart_tx_ovrd.21817778392205557421746258415674318514307911691553880742995528360463988389159 | Nov 22 01:44:14 PM PST 23 | Nov 22 01:44:19 PM PST 23 | 485186362 ps | ||
| T1265 | /workspace/coverage/default/3.uart_long_xfer_wo_dly.42100906253307957765373255310204604053482096387514110317614508800524905042451 | Nov 22 01:43:53 PM PST 23 | Nov 22 01:49:50 PM PST 23 | 93387746707 ps | ||
| T1266 | /workspace/coverage/default/22.uart_alert_test.105780611925910070511844779828217931026564445539135126066396337093465863999373 | Nov 22 01:44:47 PM PST 23 | Nov 22 01:44:51 PM PST 23 | 16368684 ps | ||
| T1267 | /workspace/coverage/default/13.uart_stress_all.46442730756777521165895447542261585374423749010844975115891052022576567871600 | Nov 22 01:44:04 PM PST 23 | Nov 22 01:45:06 PM PST 23 | 43402307308 ps | ||
| T1268 | /workspace/coverage/default/38.uart_alert_test.57194347701881261728386354298854940079620553371443345763114577509348342207923 | Nov 22 01:44:54 PM PST 23 | Nov 22 01:44:56 PM PST 23 | 16368684 ps | ||
| T1269 | /workspace/coverage/default/28.uart_fifo_reset.19501799026808705877779858965114303240931796071022036878037190138592368036380 | Nov 22 01:44:42 PM PST 23 | Nov 22 01:46:37 PM PST 23 | 123972198458 ps | ||
| T1270 | /workspace/coverage/default/291.uart_fifo_reset.50128418721697312175834330764243000557367113425131746033389033829606593818791 | Nov 22 01:46:10 PM PST 23 | Nov 22 01:48:08 PM PST 23 | 123972198458 ps | ||
| T1271 | /workspace/coverage/default/47.uart_fifo_overflow.88805695259207700525767758825461792492392487933158551685161172045701255192445 | Nov 22 01:45:30 PM PST 23 | Nov 22 01:46:26 PM PST 23 | 58551936110 ps | ||
| T1272 | /workspace/coverage/default/30.uart_fifo_full.21724268583265374873698474376379507955968672626919969374573751956488633504839 | Nov 22 01:44:48 PM PST 23 | Nov 22 01:45:52 PM PST 23 | 61777160308 ps | ||
| T1273 | /workspace/coverage/default/27.uart_smoke.55896797023812200518632872339347588453645584913961724462462792554046226796853 | Nov 22 01:44:45 PM PST 23 | Nov 22 01:45:05 PM PST 23 | 5759626309 ps | ||
| T1274 | /workspace/coverage/default/150.uart_fifo_reset.60999558779334125854913274325185157970392860046336534570263502638284746963984 | Nov 22 01:46:06 PM PST 23 | Nov 22 01:48:06 PM PST 23 | 123972198458 ps | ||
| T1275 | /workspace/coverage/default/83.uart_stress_all_with_rand_reset.48382907137157603671224775245594231248196581296446011956701767958135854816684 | Nov 22 01:45:28 PM PST 23 | Nov 22 01:52:57 PM PST 23 | 87476847566 ps | ||
| T1276 | /workspace/coverage/cover_reg_top/5.uart_csr_rw.73755809887784039028718339843510364195605148460361467780583009516644391487747 | Nov 22 12:42:18 PM PST 23 | Nov 22 12:42:21 PM PST 23 | 21815069 ps | ||
| T1277 | /workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.26658619237432138552954394021495684928305755302461295042382231467868986935650 | Nov 22 12:42:27 PM PST 23 | Nov 22 12:42:31 PM PST 23 | 45029169 ps | ||
| T1278 | /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.113784941176451142110072737815198918041397323072322043906363907573316998828813 | Nov 22 12:42:33 PM PST 23 | Nov 22 12:42:39 PM PST 23 | 38332794 ps | ||
| T1279 | /workspace/coverage/cover_reg_top/1.uart_tl_errors.101730779632345618957370984675853729874242552548024068002481216980288262472071 | Nov 22 12:42:11 PM PST 23 | Nov 22 12:42:18 PM PST 23 | 152867592 ps | ||
| T1280 | /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.74613328917405631031038538909575092870811828902800226609961537270678921678836 | Nov 22 12:42:28 PM PST 23 | Nov 22 12:42:32 PM PST 23 | 38332794 ps | ||
| T1281 | /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.1393244602911630519579332638100539956251316234964323253990806387411353950810 | Nov 22 12:42:25 PM PST 23 | Nov 22 12:42:28 PM PST 23 | 38332794 ps | ||
| T1282 | /workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.1218970766201533836185943340348557106371589948142878440677952169449011454255 | Nov 22 12:42:12 PM PST 23 | Nov 22 12:42:18 PM PST 23 | 45029169 ps | ||
| T1283 | /workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.16411607283378856413390392863276713139302427744574074526835545063803323026939 | Nov 22 12:42:24 PM PST 23 | Nov 22 12:42:27 PM PST 23 | 45029169 ps | ||
| T1284 | /workspace/coverage/cover_reg_top/29.uart_intr_test.88568057809693824718399662530141094936187717588046494311611187515147159096346 | Nov 22 12:42:53 PM PST 23 | Nov 22 12:42:55 PM PST 23 | 22779347 ps | ||
| T1285 | /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.24338638723853031874534138649075475104268563026033914111759491658177652179841 | Nov 22 12:42:10 PM PST 23 | Nov 22 12:42:16 PM PST 23 | 38332794 ps | ||
| T1286 | /workspace/coverage/cover_reg_top/5.uart_tl_errors.87634847591438182315234059269686406804678657298036057999310752562730560789538 | Nov 22 12:42:18 PM PST 23 | Nov 22 12:42:23 PM PST 23 | 152867592 ps | ||
| T1287 | /workspace/coverage/cover_reg_top/32.uart_intr_test.114768852763182744744058099190830831948283022539092689169405371770192484707637 | Nov 22 12:42:53 PM PST 23 | Nov 22 12:42:55 PM PST 23 | 22779347 ps | ||
| T1288 | /workspace/coverage/cover_reg_top/21.uart_intr_test.23674786477610102083855078143697894599406285076999922110249447980686758130784 | Nov 22 12:42:40 PM PST 23 | Nov 22 12:42:44 PM PST 23 | 22779347 ps | ||
| T1289 | /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.81323426531628891116973979733230404663208595552693391058567784636381939260492 | Nov 22 12:42:16 PM PST 23 | Nov 22 12:42:21 PM PST 23 | 136349867 ps | ||
| T1290 | /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.61631760107628264596228076583544498247642666003734649866700760720466202357589 | Nov 22 12:42:20 PM PST 23 | Nov 22 12:42:23 PM PST 23 | 38332794 ps | ||
| T1291 | /workspace/coverage/cover_reg_top/12.uart_intr_test.48511004427374882187769634168666398387372438616493221374110336563605162077158 | Nov 22 12:42:26 PM PST 23 | Nov 22 12:42:28 PM PST 23 | 22779347 ps | ||
| T1292 | /workspace/coverage/cover_reg_top/8.uart_tl_errors.3399927240136426830443658391255325846526825206452526148490683651858446952621 | Nov 22 12:42:28 PM PST 23 | Nov 22 12:42:34 PM PST 23 | 152867592 ps | ||
| T1293 | /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.493072419533636812268940890951451308293697634889112230878435715628613797648 | Nov 22 12:42:52 PM PST 23 | Nov 22 12:42:54 PM PST 23 | 38332794 ps | ||
| T1294 | /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.40924233066444564894043292146604663674316083897715307213177461204218651763317 | Nov 22 12:42:21 PM PST 23 | Nov 22 12:42:25 PM PST 23 | 136349867 ps | ||
| T1295 | /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.1578942945651288238478214132587170078157611366533650098592629058150277185765 | Nov 22 12:42:10 PM PST 23 | Nov 22 12:42:16 PM PST 23 | 42368476 ps | ||
| T1296 | /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.96470951906610082371030420218611732560007404641873215130099771536632975771559 | Nov 22 12:42:19 PM PST 23 | Nov 22 12:42:22 PM PST 23 | 45029169 ps | ||
| T1297 | /workspace/coverage/cover_reg_top/7.uart_tl_errors.79824811270297543535672829742638819667467122107336250349874256065227491686921 | Nov 22 12:42:08 PM PST 23 | Nov 22 12:42:15 PM PST 23 | 152867592 ps | ||
| T1298 | /workspace/coverage/cover_reg_top/2.uart_tl_intg_err.63373462465403761341201899361986938110445859494334703258409215669050763398215 | Nov 22 12:42:09 PM PST 23 | Nov 22 12:42:15 PM PST 23 | 136349867 ps | ||
| T1299 | /workspace/coverage/cover_reg_top/15.uart_csr_rw.50670590584137602618429862330235407660470366266795665038039299827366740832447 | Nov 22 12:42:24 PM PST 23 | Nov 22 12:42:27 PM PST 23 | 21815069 ps | ||
| T1300 | /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.85688754062418045550334359162303206244027583659882477564252845774816643549627 | Nov 22 12:42:40 PM PST 23 | Nov 22 12:42:45 PM PST 23 | 38332794 ps | ||
| T1301 | /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.24804397791408697003638540504965910994953121283379428415433105739953309398729 | Nov 22 12:42:22 PM PST 23 | Nov 22 12:42:25 PM PST 23 | 136349867 ps | ||
| T1302 | /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.34411534952994530884722814393448451576772675826661565073166361494118848849818 | Nov 22 12:42:42 PM PST 23 | Nov 22 12:42:45 PM PST 23 | 38332794 ps | ||
| T1303 | /workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.17301984501843285301303205878876452782291002545588236498203307470548521623345 | Nov 22 12:42:07 PM PST 23 | Nov 22 12:42:13 PM PST 23 | 38332794 ps | ||
| T1304 | /workspace/coverage/cover_reg_top/31.uart_intr_test.5804430809372354457632900431818536090235975316744241034089124316252853951102 | Nov 22 12:42:57 PM PST 23 | Nov 22 12:42:58 PM PST 23 | 22779347 ps | ||
| T1305 | /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.54537455128776763799489186299852768580654185089804445952955491089676847802202 | Nov 22 12:42:15 PM PST 23 | Nov 22 12:42:21 PM PST 23 | 306241365 ps | ||
| T1306 | /workspace/coverage/cover_reg_top/36.uart_intr_test.108054810770159999226181416513015649660037877042468172019266414121806075603044 | Nov 22 12:43:10 PM PST 23 | Nov 22 12:43:15 PM PST 23 | 22779347 ps | ||
| T1307 | /workspace/coverage/cover_reg_top/16.uart_intr_test.69944430431183874363145903200138159710093473574259011681740076802809822033137 | Nov 22 12:42:22 PM PST 23 | Nov 22 12:42:25 PM PST 23 | 22779347 ps | ||
| T1308 | /workspace/coverage/cover_reg_top/9.uart_intr_test.74901284929032059923928679258106426889938886480783624414080225908703542797813 | Nov 22 12:42:14 PM PST 23 | Nov 22 12:42:19 PM PST 23 | 22779347 ps | ||
| T1309 | /workspace/coverage/cover_reg_top/43.uart_intr_test.54143080185020221476735684122413470520939149191461322878341464641443310749617 | Nov 22 12:42:59 PM PST 23 | Nov 22 12:43:02 PM PST 23 | 22779347 ps | ||
| T1310 | /workspace/coverage/cover_reg_top/5.uart_tl_intg_err.1141926661353384252393506157142508611441543137261496202084395026917154387324 | Nov 22 12:42:14 PM PST 23 | Nov 22 12:42:20 PM PST 23 | 136349867 ps | ||
| T1311 | /workspace/coverage/cover_reg_top/26.uart_intr_test.61297456548752942094505635418644778087872690927838477072367304997274694642790 | Nov 22 12:43:00 PM PST 23 | Nov 22 12:43:04 PM PST 23 | 22779347 ps | ||
| T1312 | /workspace/coverage/cover_reg_top/25.uart_intr_test.30717375447266362324460735833788325258975286673081255490687438813215885650805 | Nov 22 12:43:16 PM PST 23 | Nov 22 12:43:23 PM PST 23 | 22779347 ps | ||
| T1313 | /workspace/coverage/cover_reg_top/13.uart_csr_rw.10559248432517770035899955591208676022626316339980143356738584386030280797070 | Nov 22 12:42:32 PM PST 23 | Nov 22 12:42:38 PM PST 23 | 21815069 ps | ||
| T1314 | /workspace/coverage/cover_reg_top/1.uart_intr_test.20790950011131858559352952146531931810695018678038016640051392146175389019960 | Nov 22 12:42:29 PM PST 23 | Nov 22 12:42:33 PM PST 23 | 22779347 ps | ||
| T1315 | /workspace/coverage/cover_reg_top/41.uart_intr_test.30666270031182385680270480822076510297633005999919575305621510387323708997497 | Nov 22 12:42:53 PM PST 23 | Nov 22 12:42:55 PM PST 23 | 22779347 ps | ||
| T1316 | /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.94879681881096564104752554612812585287213291473687340743405008986954596251604 | Nov 22 12:42:25 PM PST 23 | Nov 22 12:42:29 PM PST 23 | 136349867 ps | ||
| T1317 | /workspace/coverage/cover_reg_top/7.uart_tl_intg_err.80989707302854593178632948005077577137188580870080383946439626503892862024930 | Nov 22 12:42:24 PM PST 23 | Nov 22 12:42:28 PM PST 23 | 136349867 ps | ||
| T1318 | /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.34343521458368861668415273806918400965227920985623892594465457737221153395876 | Nov 22 12:42:39 PM PST 23 | Nov 22 12:42:44 PM PST 23 | 136349867 ps | ||
| T1319 | /workspace/coverage/cover_reg_top/0.uart_csr_aliasing.13401928189030869627720821097863024710138190803891110997164549863198315729951 | Nov 22 12:42:02 PM PST 23 | Nov 22 12:42:12 PM PST 23 | 42368476 ps | ||
| T1320 | /workspace/coverage/cover_reg_top/39.uart_intr_test.32804848616645873160980114353075811733133899020140289643715739953204368516878 | Nov 22 12:43:04 PM PST 23 | Nov 22 12:43:13 PM PST 23 | 22779347 ps |
| Test location | /workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.83225690253876153188344331177120157311291548063650422819725575072853191685074 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 22529349 ps |
| CPU time | 0.58 seconds |
| Started | Nov 22 12:42:17 PM PST 23 |
| Finished | Nov 22 12:42:20 PM PST 23 |
| Peak memory | 195688 kb |
| Host | smart-c339a539-88fd-4cdb-b2f9-f00642993120 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83225690253876153188344331177120157311291548063650422819725575072853191685074 -assert nopo stproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover _reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_hw_reset.83225690253876153188344331177120157311291548063650422819725575072853191685074 |
| Directory | /workspace/1.uart_csr_hw_reset/latest |
| Test location | /workspace/coverage/default/22.uart_stress_all_with_rand_reset.12068223242158307336368898242429389000295743575520080392934488794305121863907 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 87476847566 ps |
| CPU time | 469.02 seconds |
| Started | Nov 22 01:44:47 PM PST 23 |
| Finished | Nov 22 01:52:39 PM PST 23 |
| Peak memory | 226248 kb |
| Host | smart-c9139afa-aae6-481f-9504-abfb30b42945 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12068223242158307336368898 242429389000295743575520080392934488794305121863907 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_stress_all_with_rand_reset.1206822324215 8307336368898242429389000295743575520080392934488794305121863907 |
| Directory | /workspace/22.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/41.uart_long_xfer_wo_dly.74548228264030771282695475318789157045541177924322825649301490318231638010304 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 93387746707 ps |
| CPU time | 355.47 seconds |
| Started | Nov 22 01:45:26 PM PST 23 |
| Finished | Nov 22 01:51:23 PM PST 23 |
| Peak memory | 200116 kb |
| Host | smart-7b1c86e7-542a-45da-96eb-9294b7c43d73 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=74548228264030771282695475318789157045541177924322825649301490318231638010304 -assert nopostproc +UVM_TES TNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 41.uart_long_xfer_wo_dly.74548228264030771282695475318789157045541177924322825649301490318231638010304 |
| Directory | /workspace/41.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/cover_reg_top/19.uart_tl_errors.34310721939993928172282152705760068119558471235653895095015868583811538967281 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 152867592 ps |
| CPU time | 2.1 seconds |
| Started | Nov 22 12:42:34 PM PST 23 |
| Finished | Nov 22 12:42:41 PM PST 23 |
| Peak memory | 199852 kb |
| Host | smart-5cf8fbd7-c122-42e6-8d8e-dec681a50c0f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34310721939993928172282152705760068119558471235653895095015868583811538967281 -assert nopostproc +U VM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 19.uart_tl_errors.34310721939993928172282152705760068119558471235653895095015868583811538967281 |
| Directory | /workspace/19.uart_tl_errors/latest |
| Test location | /workspace/coverage/default/17.uart_intr.109585496503483505108424484900619742146902284761803587628125290565521072768150 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 787145125175 ps |
| CPU time | 785.43 seconds |
| Started | Nov 22 01:44:24 PM PST 23 |
| Finished | Nov 22 01:57:35 PM PST 23 |
| Peak memory | 199996 kb |
| Host | smart-5fd7a39d-898e-470c-a753-89c4d9c91f65 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109585496503483505108424484900619742146902284761803587628125290565521072768150 -assert nopos tproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 17.uart_intr.109585496503483505108424484900619742146902284761803587628125290565521072768150 |
| Directory | /workspace/17.uart_intr/latest |
| Test location | /workspace/coverage/cover_reg_top/10.uart_intr_test.26545955776207634053124796642362364153440439321513518908074711612177879955840 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 22779347 ps |
| CPU time | 0.58 seconds |
| Started | Nov 22 12:42:25 PM PST 23 |
| Finished | Nov 22 12:42:28 PM PST 23 |
| Peak memory | 194556 kb |
| Host | smart-97cc6cd5-98f2-4aa2-a8ec-4315083cf601 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26545955776207634053124796642362364153440439321513518908074711612177879955840 -assert nopostproc +U VM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 10.uart_intr_test.26545955776207634053124796642362364153440439321513518908074711612177879955840 |
| Directory | /workspace/10.uart_intr_test/latest |
| Test location | /workspace/coverage/default/43.uart_fifo_full.60836615829624654948105347079430678152299311111916257094943625116198621307032 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 61777160308 ps |
| CPU time | 60.58 seconds |
| Started | Nov 22 01:45:30 PM PST 23 |
| Finished | Nov 22 01:46:32 PM PST 23 |
| Peak memory | 200044 kb |
| Host | smart-e11eff9e-0bf8-4dde-bb62-13ed73c52e86 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=60836615829624654948105347079430678152299311111916257094943625116198621307032 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 43.uart_fifo_full.60836615829624654948105347079430678152299311111916257094943625116198621307032 |
| Directory | /workspace/43.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/21.uart_noise_filter.100837350227979074753031233514209515375598516646327282121953526753859776039006 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 94501577082 ps |
| CPU time | 97.12 seconds |
| Started | Nov 22 01:44:39 PM PST 23 |
| Finished | Nov 22 01:46:17 PM PST 23 |
| Peak memory | 200256 kb |
| Host | smart-523cae72-ef67-4e72-86cc-0cd84ceec1bf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=100837350227979074753031233514209515375598516646327282121953526753859776039006 -assert nopostproc +UVM_TESTNAME=uart_bas e_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 21.uart_noise_filter.100837350227979074753031233514209515375598516646327282121953526753859776039006 |
| Directory | /workspace/21.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/41.uart_tx_rx.111586726189372961077375614277507449298983173807381122846549932157440478374929 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 57391945390 ps |
| CPU time | 63.76 seconds |
| Started | Nov 22 01:45:30 PM PST 23 |
| Finished | Nov 22 01:46:35 PM PST 23 |
| Peak memory | 200072 kb |
| Host | smart-631cd47b-cb7e-42bf-84ee-ddb956f73691 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=111586726189372961077375614277507449298983173807381122846549932157440478374929 -assert nopostproc +UVM_TESTNAME=uart_bas e_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 41.uart_tx_rx.111586726189372961077375614277507449298983173807381122846549932157440478374929 |
| Directory | /workspace/41.uart_tx_rx/latest |
| Test location | /workspace/coverage/cover_reg_top/1.uart_tl_intg_err.83333969254984941889865038192565926457655883906618277202208216068269665191493 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 136349867 ps |
| CPU time | 1.38 seconds |
| Started | Nov 22 12:42:06 PM PST 23 |
| Finished | Nov 22 12:42:14 PM PST 23 |
| Peak memory | 199444 kb |
| Host | smart-7c883f35-31f0-45d3-918f-69a23ecabec1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83333969254984941889865038192565926457655883906618277202208216068269665191493 -assert n opostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co ver_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_intg_err.83333969254984941889865038192565926457655883906618277202208216068269665191493 |
| Directory | /workspace/1.uart_tl_intg_err/latest |
| Test location | /workspace/coverage/default/7.uart_perf.61723513001897600969587129756663222259601948949250812067195591319303790354735 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 14098773881 ps |
| CPU time | 468.7 seconds |
| Started | Nov 22 01:44:19 PM PST 23 |
| Finished | Nov 22 01:52:10 PM PST 23 |
| Peak memory | 200180 kb |
| Host | smart-75ed108e-eba5-43bd-b520-32cc4b41a8ca |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=61723513001897600969587129756663222259601948949250812067195591319303790354735 -assert nopostproc +UVM_TES TNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 7.uart_perf.61723513001897600969587129756663222259601948949250812067195591319303790354735 |
| Directory | /workspace/7.uart_perf/latest |
| Test location | /workspace/coverage/default/117.uart_fifo_reset.66841740454439023408120691117592526163298307230043012699013349624288460010620 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 113.03 seconds |
| Started | Nov 22 01:45:51 PM PST 23 |
| Finished | Nov 22 01:47:46 PM PST 23 |
| Peak memory | 198924 kb |
| Host | smart-54b99c14-42da-4a47-9047-0a7427d668c1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=66841740454439023408120691117592526163298307230043012699013349624288460010620 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 117.uart_fifo_reset.66841740454439023408120691117592526163298307230043012699013349624288460010620 |
| Directory | /workspace/117.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/10.uart_stress_all.52731175912390233287830215970479185033035283811863628359378014850893646804022 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 43402307308 ps |
| CPU time | 55.91 seconds |
| Started | Nov 22 01:43:52 PM PST 23 |
| Finished | Nov 22 01:44:51 PM PST 23 |
| Peak memory | 200068 kb |
| Host | smart-b1ffa3bd-21c9-432b-8f46-cafcf3a9e3d1 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52731175912390233287830215970479185033035283811863628359378014850893646804022 -assert nopos tproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 10.uart_stress_all.52731175912390233287830215970479185033035283811863628359378014850893646804022 |
| Directory | /workspace/10.uart_stress_all/latest |
| Test location | /workspace/coverage/default/18.uart_rx_parity_err.52288781604610056370233101402396145727902600932352535442690354567581717842508 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 36616611594 ps |
| CPU time | 37.87 seconds |
| Started | Nov 22 01:44:38 PM PST 23 |
| Finished | Nov 22 01:45:18 PM PST 23 |
| Peak memory | 200120 kb |
| Host | smart-7d5e86df-b620-4e5c-a0f6-0a024fc27e96 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=52288781604610056370233101402396145727902600932352535442690354567581717842508 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 18.uart_rx_parity_err.52288781604610056370233101402396145727902600932352535442690354567581717842508 |
| Directory | /workspace/18.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/14.uart_fifo_overflow.85289169511612585670596719993220388768204172434836785522181402659244251016093 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 58551936110 ps |
| CPU time | 54.92 seconds |
| Started | Nov 22 01:44:08 PM PST 23 |
| Finished | Nov 22 01:45:07 PM PST 23 |
| Peak memory | 199892 kb |
| Host | smart-47254214-abc0-479e-bb9a-8530b4eb4840 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=85289169511612585670596719993220388768204172434836785522181402659244251016093 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 14.uart_fifo_overflow.85289169511612585670596719993220388768204172434836785522181402659244251016093 |
| Directory | /workspace/14.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/0.uart_sec_cm.58145506112402162695245147700996480908134754316614304802560498597354845217120 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 100582296 ps |
| CPU time | 0.84 seconds |
| Started | Nov 22 01:44:01 PM PST 23 |
| Finished | Nov 22 01:44:06 PM PST 23 |
| Peak memory | 218412 kb |
| Host | smart-391369c1-38ea-43d4-9829-9b22e8d9142b |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58145506112402162695245147700996480908134754316614304802560498597354845217120 -assert nopostpro c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 0.uart_sec_cm.58145506112402162695245147700996480908134754316614304802560498597354845217120 |
| Directory | /workspace/0.uart_sec_cm/latest |
| Test location | /workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.65090082454745294836281914248613636434033983140604986148026366767580378225265 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 45029169 ps |
| CPU time | 0.82 seconds |
| Started | Nov 22 12:42:28 PM PST 23 |
| Finished | Nov 22 12:42:32 PM PST 23 |
| Peak memory | 197096 kb |
| Host | smart-7096dd28-0e98-47b8-a657-dd783cded0f9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65090082454745294836281914248613636434033983140604986148026366767580378225265 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_same_csr_outstanding.65090082454745294836281914248613636434033983140604986148026366767580378225265 |
| Directory | /workspace/11.uart_same_csr_outstanding/latest |
| Test location | /workspace/coverage/default/10.uart_tx_ovrd.6605189952804976281037179346799299154499103576590267933965813137629110532609 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 485186362 ps |
| CPU time | 1.28 seconds |
| Started | Nov 22 01:44:05 PM PST 23 |
| Finished | Nov 22 01:44:12 PM PST 23 |
| Peak memory | 197876 kb |
| Host | smart-58abe638-ead4-4968-b6eb-42880d53d68b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=6605189952804976281037179346799299154499103576590267933965813137629110532609 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 10.uart_tx_ovrd.6605189952804976281037179346799299154499103576590267933965813137629110532609 |
| Directory | /workspace/10.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/0.uart_alert_test.95176887150200485380950022785161017652728573567125106947168290602485461070722 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 16368684 ps |
| CPU time | 0.53 seconds |
| Started | Nov 22 01:44:03 PM PST 23 |
| Finished | Nov 22 01:44:08 PM PST 23 |
| Peak memory | 194396 kb |
| Host | smart-e27ac4b5-25a1-475a-b899-cb05b241c883 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95176887150200485380950022785161017652728573567125106947168290602485461070722 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 0.uart_alert_test.95176887150200485380950022785161017652728573567125106947168290602485461070722 |
| Directory | /workspace/0.uart_alert_test/latest |
| Test location | /workspace/coverage/default/10.uart_rx_start_bit_filter.91158932436347780151072296739847579882721042366726568519773507203210128389946 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 4267638245 ps |
| CPU time | 4.72 seconds |
| Started | Nov 22 01:44:27 PM PST 23 |
| Finished | Nov 22 01:44:38 PM PST 23 |
| Peak memory | 195976 kb |
| Host | smart-c1d42e45-7b5e-452f-b110-f1652dd70e50 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=91158932436347780151072296739847579882721042366726568519773507203210128389946 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 10.uart_rx_start_bit_filter.91158932436347780151072296739847579882721042366726568519773507203210128389946 |
| Directory | /workspace/10.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/1.uart_smoke.83283671801866538521322368091886339731452877853588892947723330848341121319299 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 5759626309 ps |
| CPU time | 17.6 seconds |
| Started | Nov 22 01:43:58 PM PST 23 |
| Finished | Nov 22 01:44:19 PM PST 23 |
| Peak memory | 199420 kb |
| Host | smart-fe739d4c-e9a4-4f22-bc17-55fe24059356 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=83283671801866538521322368091886339731452877853588892947723330848341121319299 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 1.uart_smoke.83283671801866538521322368091886339731452877853588892947723330848341121319299 |
| Directory | /workspace/1.uart_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.11699223376888989785291518658246141367865482046207769547542060476884260240418 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 306241365 ps |
| CPU time | 2.56 seconds |
| Started | Nov 22 12:42:29 PM PST 23 |
| Finished | Nov 22 12:42:35 PM PST 23 |
| Peak memory | 198220 kb |
| Host | smart-3037733b-3866-4910-824f-712428b7a086 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11699223376888989785291518658246141367865482046207769547542060476884260240418 -assert nopo stproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover _reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_bit_bash.11699223376888989785291518658246141367865482046207769547542060476884260240418 |
| Directory | /workspace/1.uart_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.27932284356896399956031566710690354242627683315779060161485148052522045950456 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 42368476 ps |
| CPU time | 0.86 seconds |
| Started | Nov 22 12:42:08 PM PST 23 |
| Finished | Nov 22 12:42:14 PM PST 23 |
| Peak memory | 196548 kb |
| Host | smart-8efb1087-84bf-4e17-bf16-5ab4cf45474d |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27932284356896399956031566710690354242627683315779060161485148052522045950456 -assert nopo stproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover _reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_aliasing.27932284356896399956031566710690354242627683315779060161485148052522045950456 |
| Directory | /workspace/1.uart_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/0.uart_csr_aliasing.13401928189030869627720821097863024710138190803891110997164549863198315729951 |
| Short name | T1319 |
| Test name | |
| Test status | |
| Simulation time | 42368476 ps |
| CPU time | 0.77 seconds |
| Started | Nov 22 12:42:02 PM PST 23 |
| Finished | Nov 22 12:42:12 PM PST 23 |
| Peak memory | 196620 kb |
| Host | smart-a3d99633-f8e3-4517-aeab-96ccd4369590 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13401928189030869627720821097863024710138190803891110997164549863198315729951 -assert nopo stproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover _reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_aliasing.13401928189030869627720821097863024710138190803891110997164549863198315729951 |
| Directory | /workspace/0.uart_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.106109311818881175606998211728325048593013178198641287320392739376085430613838 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 306241365 ps |
| CPU time | 2.55 seconds |
| Started | Nov 22 12:42:15 PM PST 23 |
| Finished | Nov 22 12:42:21 PM PST 23 |
| Peak memory | 198228 kb |
| Host | smart-fd83dfba-33c6-454a-8d96-828fd183b47d |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106109311818881175606998211728325048593013178198641287320392739376085430613838 -assert nop ostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove r_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_bit_bash.106109311818881175606998211728325048593013178198641287320392739376085430613838 |
| Directory | /workspace/0.uart_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.82867731723286148375809828080962869497449453211000622577379661982825474398381 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 22529349 ps |
| CPU time | 0.61 seconds |
| Started | Nov 22 12:42:03 PM PST 23 |
| Finished | Nov 22 12:42:12 PM PST 23 |
| Peak memory | 195776 kb |
| Host | smart-97adeaa1-0b48-487f-a73f-04aa8528509c |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82867731723286148375809828080962869497449453211000622577379661982825474398381 -assert nopo stproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover _reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_hw_reset.82867731723286148375809828080962869497449453211000622577379661982825474398381 |
| Directory | /workspace/0.uart_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.61631760107628264596228076583544498247642666003734649866700760720466202357589 |
| Short name | T1290 |
| Test name | |
| Test status | |
| Simulation time | 38332794 ps |
| CPU time | 0.8 seconds |
| Started | Nov 22 12:42:20 PM PST 23 |
| Finished | Nov 22 12:42:23 PM PST 23 |
| Peak memory | 200168 kb |
| Host | smart-e1a38142-6594-4916-a96e-9abe33299bdf |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6163176010762826459622807658354449824764266 6003734649866700760720466202357589 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_mem_rw_with_rand_reset.6163176010762826459622807 6583544498247642666003734649866700760720466202357589 |
| Directory | /workspace/0.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/0.uart_csr_rw.31663682031534988395538208804812991051345697279475666582210685748074580295251 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 21815069 ps |
| CPU time | 0.59 seconds |
| Started | Nov 22 12:42:21 PM PST 23 |
| Finished | Nov 22 12:42:24 PM PST 23 |
| Peak memory | 195684 kb |
| Host | smart-b8addcc6-596c-4177-8b1d-0661bca7eb64 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31663682031534988395538208804812991051345697279475666582210685748074580295251 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t op.vdb -cm_log /dev/null -cm_name 0.uart_csr_rw.31663682031534988395538208804812991051345697279475666582210685748074580295251 |
| Directory | /workspace/0.uart_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/0.uart_intr_test.80015621307954308308074867827233423746811963647538778447345579557933502586726 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 22779347 ps |
| CPU time | 0.57 seconds |
| Started | Nov 22 12:42:10 PM PST 23 |
| Finished | Nov 22 12:42:14 PM PST 23 |
| Peak memory | 194684 kb |
| Host | smart-cc8be5e5-8410-4167-806c-24de58b2843d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80015621307954308308074867827233423746811963647538778447345579557933502586726 -assert nopostproc +U VM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 0.uart_intr_test.80015621307954308308074867827233423746811963647538778447345579557933502586726 |
| Directory | /workspace/0.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.106827961724767252438258139037490052520316108881137720670017488348627680381178 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 45029169 ps |
| CPU time | 0.75 seconds |
| Started | Nov 22 12:42:19 PM PST 23 |
| Finished | Nov 22 12:42:22 PM PST 23 |
| Peak memory | 197312 kb |
| Host | smart-a54db967-ed54-4a04-a9da-f217e149db30 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106827961724767252438258139037490052520316108881137720670017488348627680381178 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_same_csr_outstanding.10682796172476725243825813903749005252031610888113772067001748834 8627680381178 |
| Directory | /workspace/0.uart_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/0.uart_tl_errors.103345613462401902819021107640182156604807952285331117569455718461037427815543 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 152867592 ps |
| CPU time | 2.08 seconds |
| Started | Nov 22 12:42:11 PM PST 23 |
| Finished | Nov 22 12:42:19 PM PST 23 |
| Peak memory | 200220 kb |
| Host | smart-dbf72870-1492-4862-85eb-bb7894419c36 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103345613462401902819021107640182156604807952285331117569455718461037427815543 -assert nopostproc + UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 0.uart_tl_errors.103345613462401902819021107640182156604807952285331117569455718461037427815543 |
| Directory | /workspace/0.uart_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/0.uart_tl_intg_err.20389562156499107222775883791164939695189480246730620044457742169012336923634 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 136349867 ps |
| CPU time | 1.37 seconds |
| Started | Nov 22 12:42:09 PM PST 23 |
| Finished | Nov 22 12:42:14 PM PST 23 |
| Peak memory | 199412 kb |
| Host | smart-c359ce7f-accc-47d6-a732-0f573cd4edca |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20389562156499107222775883791164939695189480246730620044457742169012336923634 -assert n opostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co ver_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_intg_err.20389562156499107222775883791164939695189480246730620044457742169012336923634 |
| Directory | /workspace/0.uart_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.89079364191190748766615003445185907300243234396993922450164611642565880692754 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 38332794 ps |
| CPU time | 0.85 seconds |
| Started | Nov 22 12:42:00 PM PST 23 |
| Finished | Nov 22 12:42:11 PM PST 23 |
| Peak memory | 200092 kb |
| Host | smart-87bb96ad-116c-4b58-ad50-15d5131cc731 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8907936419119074876661500344518590730024323 4396993922450164611642565880692754 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_mem_rw_with_rand_reset.8907936419119074876661500 3445185907300243234396993922450164611642565880692754 |
| Directory | /workspace/1.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/1.uart_csr_rw.40994785396524398800260823671375963524953800323908585006461601101049224464640 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 21815069 ps |
| CPU time | 0.62 seconds |
| Started | Nov 22 12:42:26 PM PST 23 |
| Finished | Nov 22 12:42:28 PM PST 23 |
| Peak memory | 195688 kb |
| Host | smart-1ed40654-91d7-46fc-a91c-1564f23005a0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40994785396524398800260823671375963524953800323908585006461601101049224464640 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t op.vdb -cm_log /dev/null -cm_name 1.uart_csr_rw.40994785396524398800260823671375963524953800323908585006461601101049224464640 |
| Directory | /workspace/1.uart_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/1.uart_intr_test.20790950011131858559352952146531931810695018678038016640051392146175389019960 |
| Short name | T1314 |
| Test name | |
| Test status | |
| Simulation time | 22779347 ps |
| CPU time | 0.58 seconds |
| Started | Nov 22 12:42:29 PM PST 23 |
| Finished | Nov 22 12:42:33 PM PST 23 |
| Peak memory | 194660 kb |
| Host | smart-13f97fde-d712-4e33-bfc3-a06409521a65 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20790950011131858559352952146531931810695018678038016640051392146175389019960 -assert nopostproc +U VM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 1.uart_intr_test.20790950011131858559352952146531931810695018678038016640051392146175389019960 |
| Directory | /workspace/1.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.89274206560511870410191229160245140621270356189993231694085427344187489500689 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 45029169 ps |
| CPU time | 0.78 seconds |
| Started | Nov 22 12:42:08 PM PST 23 |
| Finished | Nov 22 12:42:14 PM PST 23 |
| Peak memory | 197252 kb |
| Host | smart-f5cf6586-6ab7-4294-835f-93fec3aca2fd |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89274206560511870410191229160245140621270356189993231694085427344187489500689 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_same_csr_outstanding.89274206560511870410191229160245140621270356189993231694085427344187489500689 |
| Directory | /workspace/1.uart_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/1.uart_tl_errors.101730779632345618957370984675853729874242552548024068002481216980288262472071 |
| Short name | T1279 |
| Test name | |
| Test status | |
| Simulation time | 152867592 ps |
| CPU time | 2.04 seconds |
| Started | Nov 22 12:42:11 PM PST 23 |
| Finished | Nov 22 12:42:18 PM PST 23 |
| Peak memory | 200220 kb |
| Host | smart-eef64afb-d457-4445-ac2d-a45e1986f9f5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101730779632345618957370984675853729874242552548024068002481216980288262472071 -assert nopostproc + UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 1.uart_tl_errors.101730779632345618957370984675853729874242552548024068002481216980288262472071 |
| Directory | /workspace/1.uart_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.57172947784896769294680421984500784916150471918596134364345271961856951725946 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 38332794 ps |
| CPU time | 0.77 seconds |
| Started | Nov 22 12:42:19 PM PST 23 |
| Finished | Nov 22 12:42:22 PM PST 23 |
| Peak memory | 200132 kb |
| Host | smart-882f0d3c-35a0-4aec-b057-15a927d95efd |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5717294778489676929468042198450078491615047 1918596134364345271961856951725946 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_csr_mem_rw_with_rand_reset.571729477848967692946804 21984500784916150471918596134364345271961856951725946 |
| Directory | /workspace/10.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/10.uart_csr_rw.105836741617307507653761557439051852517986332729509095613229610496957282925120 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 21815069 ps |
| CPU time | 0.62 seconds |
| Started | Nov 22 12:42:31 PM PST 23 |
| Finished | Nov 22 12:42:37 PM PST 23 |
| Peak memory | 195700 kb |
| Host | smart-3e2d495c-f557-419c-9f25-b4bb57d59f2b |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105836741617307507653761557439051852517986332729509095613229610496957282925120 -assert nopostpro c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_ top.vdb -cm_log /dev/null -cm_name 10.uart_csr_rw.105836741617307507653761557439051852517986332729509095613229610496957282925120 |
| Directory | /workspace/10.uart_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.90916069516188103463474845718221548440209032512734911052512116028108887210696 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 45029169 ps |
| CPU time | 0.74 seconds |
| Started | Nov 22 12:42:29 PM PST 23 |
| Finished | Nov 22 12:42:33 PM PST 23 |
| Peak memory | 197340 kb |
| Host | smart-843f4e77-648f-49b6-9179-9d48f7041f9e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90916069516188103463474845718221548440209032512734911052512116028108887210696 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_same_csr_outstanding.90916069516188103463474845718221548440209032512734911052512116028108887210696 |
| Directory | /workspace/10.uart_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/10.uart_tl_errors.109044742715188229633129247862835171585591376061732477026722614857834207421786 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 152867592 ps |
| CPU time | 2.11 seconds |
| Started | Nov 22 12:42:19 PM PST 23 |
| Finished | Nov 22 12:42:24 PM PST 23 |
| Peak memory | 200232 kb |
| Host | smart-ded625f2-aab4-49d3-8dae-b1f47865b53f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109044742715188229633129247862835171585591376061732477026722614857834207421786 -assert nopostproc + UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 10.uart_tl_errors.109044742715188229633129247862835171585591376061732477026722614857834207421786 |
| Directory | /workspace/10.uart_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.94879681881096564104752554612812585287213291473687340743405008986954596251604 |
| Short name | T1316 |
| Test name | |
| Test status | |
| Simulation time | 136349867 ps |
| CPU time | 1.37 seconds |
| Started | Nov 22 12:42:25 PM PST 23 |
| Finished | Nov 22 12:42:29 PM PST 23 |
| Peak memory | 199388 kb |
| Host | smart-20bb0791-a0e2-42e4-8bdb-44586e2e6ac1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94879681881096564104752554612812585287213291473687340743405008986954596251604 -assert n opostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co ver_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_intg_err.94879681881096564104752554612812585287213291473687340743405008986954596251604 |
| Directory | /workspace/10.uart_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.113784941176451142110072737815198918041397323072322043906363907573316998828813 |
| Short name | T1278 |
| Test name | |
| Test status | |
| Simulation time | 38332794 ps |
| CPU time | 0.77 seconds |
| Started | Nov 22 12:42:33 PM PST 23 |
| Finished | Nov 22 12:42:39 PM PST 23 |
| Peak memory | 200176 kb |
| Host | smart-535ef6a8-0517-4014-83a9-8ecabb1f897a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137849411764511421100727378151989180413973 23072322043906363907573316998828813 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_csr_mem_rw_with_rand_reset.11378494117645114211007 2737815198918041397323072322043906363907573316998828813 |
| Directory | /workspace/11.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/11.uart_csr_rw.75294431676890353618286615631686466526100061136896527628320753448158909936313 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 21815069 ps |
| CPU time | 0.6 seconds |
| Started | Nov 22 12:42:31 PM PST 23 |
| Finished | Nov 22 12:42:37 PM PST 23 |
| Peak memory | 195700 kb |
| Host | smart-c6a6737f-229f-48f7-a81a-66088f201c41 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75294431676890353618286615631686466526100061136896527628320753448158909936313 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t op.vdb -cm_log /dev/null -cm_name 11.uart_csr_rw.75294431676890353618286615631686466526100061136896527628320753448158909936313 |
| Directory | /workspace/11.uart_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/11.uart_intr_test.4504999029674342214134411618742114029025981693478962193140293517677172700441 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 22779347 ps |
| CPU time | 0.58 seconds |
| Started | Nov 22 12:42:21 PM PST 23 |
| Finished | Nov 22 12:42:24 PM PST 23 |
| Peak memory | 194704 kb |
| Host | smart-2d63fc44-760b-412c-976d-fdc3653c0fa7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4504999029674342214134411618742114029025981693478962193140293517677172700441 -assert nopostproc +UV M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v db -cm_log /dev/null -cm_name 11.uart_intr_test.4504999029674342214134411618742114029025981693478962193140293517677172700441 |
| Directory | /workspace/11.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/11.uart_tl_errors.39107969093137838642464988449300278600923062102077668906706749446103251928740 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 152867592 ps |
| CPU time | 2.14 seconds |
| Started | Nov 22 12:42:13 PM PST 23 |
| Finished | Nov 22 12:42:20 PM PST 23 |
| Peak memory | 200276 kb |
| Host | smart-a350ff14-5f03-48fe-94e9-74063516f45e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39107969093137838642464988449300278600923062102077668906706749446103251928740 -assert nopostproc +U VM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 11.uart_tl_errors.39107969093137838642464988449300278600923062102077668906706749446103251928740 |
| Directory | /workspace/11.uart_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.34343521458368861668415273806918400965227920985623892594465457737221153395876 |
| Short name | T1318 |
| Test name | |
| Test status | |
| Simulation time | 136349867 ps |
| CPU time | 1.31 seconds |
| Started | Nov 22 12:42:39 PM PST 23 |
| Finished | Nov 22 12:42:44 PM PST 23 |
| Peak memory | 199480 kb |
| Host | smart-07954efe-82ac-4b16-a79b-121ec0cc1bc1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34343521458368861668415273806918400965227920985623892594465457737221153395876 -assert n opostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co ver_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_intg_err.34343521458368861668415273806918400965227920985623892594465457737221153395876 |
| Directory | /workspace/11.uart_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.38866729396596375755694213057227250794422262883421728428952971316246042887939 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 38332794 ps |
| CPU time | 0.79 seconds |
| Started | Nov 22 12:42:25 PM PST 23 |
| Finished | Nov 22 12:42:28 PM PST 23 |
| Peak memory | 200032 kb |
| Host | smart-a4bdd85a-a224-4291-b205-39896e21cf70 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886672939659637575569421305722725079442226 2883421728428952971316246042887939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_csr_mem_rw_with_rand_reset.388667293965963757556942 13057227250794422262883421728428952971316246042887939 |
| Directory | /workspace/12.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/12.uart_csr_rw.44300486868450442111400637204767331403391565673903479263369725198546979661764 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 21815069 ps |
| CPU time | 0.62 seconds |
| Started | Nov 22 12:42:15 PM PST 23 |
| Finished | Nov 22 12:42:19 PM PST 23 |
| Peak memory | 195672 kb |
| Host | smart-a8a57578-1b5c-4172-958e-c60caf5eef5c |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44300486868450442111400637204767331403391565673903479263369725198546979661764 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t op.vdb -cm_log /dev/null -cm_name 12.uart_csr_rw.44300486868450442111400637204767331403391565673903479263369725198546979661764 |
| Directory | /workspace/12.uart_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/12.uart_intr_test.48511004427374882187769634168666398387372438616493221374110336563605162077158 |
| Short name | T1291 |
| Test name | |
| Test status | |
| Simulation time | 22779347 ps |
| CPU time | 0.58 seconds |
| Started | Nov 22 12:42:26 PM PST 23 |
| Finished | Nov 22 12:42:28 PM PST 23 |
| Peak memory | 194556 kb |
| Host | smart-7d21f194-eb08-440e-97ac-87ad17f6221b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48511004427374882187769634168666398387372438616493221374110336563605162077158 -assert nopostproc +U VM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 12.uart_intr_test.48511004427374882187769634168666398387372438616493221374110336563605162077158 |
| Directory | /workspace/12.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.12267509719701455693509746355026811491577757096696079010341339655691250742758 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 45029169 ps |
| CPU time | 0.75 seconds |
| Started | Nov 22 12:42:38 PM PST 23 |
| Finished | Nov 22 12:42:41 PM PST 23 |
| Peak memory | 197320 kb |
| Host | smart-89fa0c79-f03e-41f5-9bd9-f1ffe2428c14 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12267509719701455693509746355026811491577757096696079010341339655691250742758 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_same_csr_outstanding.12267509719701455693509746355026811491577757096696079010341339655691250742758 |
| Directory | /workspace/12.uart_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/12.uart_tl_errors.55049453985373395974340599047326174581741153098568882451946735373296805408849 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 152867592 ps |
| CPU time | 2.13 seconds |
| Started | Nov 22 12:42:21 PM PST 23 |
| Finished | Nov 22 12:42:25 PM PST 23 |
| Peak memory | 200264 kb |
| Host | smart-ce1dcd80-4df6-4bf2-b79a-3599c31bf07a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55049453985373395974340599047326174581741153098568882451946735373296805408849 -assert nopostproc +U VM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 12.uart_tl_errors.55049453985373395974340599047326174581741153098568882451946735373296805408849 |
| Directory | /workspace/12.uart_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/12.uart_tl_intg_err.35108602208403561209841773467659916536128936318442172375653464619126686684175 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 136349867 ps |
| CPU time | 1.31 seconds |
| Started | Nov 22 12:42:26 PM PST 23 |
| Finished | Nov 22 12:42:29 PM PST 23 |
| Peak memory | 199388 kb |
| Host | smart-402d2ce1-ab23-46d3-b7e5-80beead94d91 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35108602208403561209841773467659916536128936318442172375653464619126686684175 -assert n opostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co ver_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_intg_err.35108602208403561209841773467659916536128936318442172375653464619126686684175 |
| Directory | /workspace/12.uart_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.22062335651549382382454046505041051005256589686524119636644697363812024661839 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 38332794 ps |
| CPU time | 0.8 seconds |
| Started | Nov 22 12:42:33 PM PST 23 |
| Finished | Nov 22 12:42:39 PM PST 23 |
| Peak memory | 200172 kb |
| Host | smart-d74497ac-2517-40ca-b4a1-ca67b94300a4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206233565154938238245404650504105100525658 9686524119636644697363812024661839 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_csr_mem_rw_with_rand_reset.220623356515493823824540 46505041051005256589686524119636644697363812024661839 |
| Directory | /workspace/13.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/13.uart_csr_rw.10559248432517770035899955591208676022626316339980143356738584386030280797070 |
| Short name | T1313 |
| Test name | |
| Test status | |
| Simulation time | 21815069 ps |
| CPU time | 0.63 seconds |
| Started | Nov 22 12:42:32 PM PST 23 |
| Finished | Nov 22 12:42:38 PM PST 23 |
| Peak memory | 195740 kb |
| Host | smart-af3e9864-0e94-448b-ac75-33ebed1d519f |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10559248432517770035899955591208676022626316339980143356738584386030280797070 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t op.vdb -cm_log /dev/null -cm_name 13.uart_csr_rw.10559248432517770035899955591208676022626316339980143356738584386030280797070 |
| Directory | /workspace/13.uart_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/13.uart_intr_test.97620797322217935512608452264401278207395675175157829719768637228644761741636 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 22779347 ps |
| CPU time | 0.58 seconds |
| Started | Nov 22 12:42:20 PM PST 23 |
| Finished | Nov 22 12:42:23 PM PST 23 |
| Peak memory | 194620 kb |
| Host | smart-0ee97e6f-43ab-4c14-bd16-e508c06dc4ce |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97620797322217935512608452264401278207395675175157829719768637228644761741636 -assert nopostproc +U VM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 13.uart_intr_test.97620797322217935512608452264401278207395675175157829719768637228644761741636 |
| Directory | /workspace/13.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.4300535649465257815698659888761613053843859722089088387566696210185936449132 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 45029169 ps |
| CPU time | 0.83 seconds |
| Started | Nov 22 12:42:21 PM PST 23 |
| Finished | Nov 22 12:42:24 PM PST 23 |
| Peak memory | 197160 kb |
| Host | smart-e673029c-1963-4d84-b20f-4954a17f4b18 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4300535649465257815698659888761613053843859722089088387566696210185936449132 - assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_same_csr_outstanding.4300535649465257815698659888761613053843859722089088387566696210185936449132 |
| Directory | /workspace/13.uart_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/13.uart_tl_errors.102519812224026547214238616439111542550904382095241402946288249788749515727353 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 152867592 ps |
| CPU time | 2 seconds |
| Started | Nov 22 12:42:33 PM PST 23 |
| Finished | Nov 22 12:42:40 PM PST 23 |
| Peak memory | 200224 kb |
| Host | smart-23e30b5d-42a8-462f-81e7-112f4a3b8f5d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102519812224026547214238616439111542550904382095241402946288249788749515727353 -assert nopostproc + UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 13.uart_tl_errors.102519812224026547214238616439111542550904382095241402946288249788749515727353 |
| Directory | /workspace/13.uart_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.24804397791408697003638540504965910994953121283379428415433105739953309398729 |
| Short name | T1301 |
| Test name | |
| Test status | |
| Simulation time | 136349867 ps |
| CPU time | 1.33 seconds |
| Started | Nov 22 12:42:22 PM PST 23 |
| Finished | Nov 22 12:42:25 PM PST 23 |
| Peak memory | 199492 kb |
| Host | smart-ed6d5a1d-92c4-4d27-ba37-e451587c0de5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24804397791408697003638540504965910994953121283379428415433105739953309398729 -assert n opostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co ver_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_intg_err.24804397791408697003638540504965910994953121283379428415433105739953309398729 |
| Directory | /workspace/13.uart_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.60845409925747846524504597470460511704219701378263658987128885968285882951439 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 38332794 ps |
| CPU time | 0.86 seconds |
| Started | Nov 22 12:42:28 PM PST 23 |
| Finished | Nov 22 12:42:32 PM PST 23 |
| Peak memory | 199908 kb |
| Host | smart-69572caf-6c16-45a1-b5d9-577ee6ec3123 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6084540992574784652450459747046051170421970 1378263658987128885968285882951439 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_csr_mem_rw_with_rand_reset.608454099257478465245045 97470460511704219701378263658987128885968285882951439 |
| Directory | /workspace/14.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/14.uart_csr_rw.46470089199129279601648906521588130556678737885975741520871642093055992135095 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 21815069 ps |
| CPU time | 0.63 seconds |
| Started | Nov 22 12:42:21 PM PST 23 |
| Finished | Nov 22 12:42:24 PM PST 23 |
| Peak memory | 195756 kb |
| Host | smart-86ae3ff8-b556-4502-bb23-405f6dc298e2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46470089199129279601648906521588130556678737885975741520871642093055992135095 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t op.vdb -cm_log /dev/null -cm_name 14.uart_csr_rw.46470089199129279601648906521588130556678737885975741520871642093055992135095 |
| Directory | /workspace/14.uart_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/14.uart_intr_test.85619691123615990945955991587460825809564862665801760546229148510106195168583 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 22779347 ps |
| CPU time | 0.58 seconds |
| Started | Nov 22 12:42:16 PM PST 23 |
| Finished | Nov 22 12:42:20 PM PST 23 |
| Peak memory | 194628 kb |
| Host | smart-9bd8b8c5-1755-4bdc-9232-6915645e4be5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85619691123615990945955991587460825809564862665801760546229148510106195168583 -assert nopostproc +U VM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 14.uart_intr_test.85619691123615990945955991587460825809564862665801760546229148510106195168583 |
| Directory | /workspace/14.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.77389310009084167569147197770981948841806591962117202989337030313280699673339 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 45029169 ps |
| CPU time | 0.79 seconds |
| Started | Nov 22 12:42:37 PM PST 23 |
| Finished | Nov 22 12:42:40 PM PST 23 |
| Peak memory | 197340 kb |
| Host | smart-fc010ad4-73f7-4291-9959-f7e160b05053 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77389310009084167569147197770981948841806591962117202989337030313280699673339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_same_csr_outstanding.77389310009084167569147197770981948841806591962117202989337030313280699673339 |
| Directory | /workspace/14.uart_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/14.uart_tl_errors.67491051619468470509926703080239059118788134509507048388747673749773293235922 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 152867592 ps |
| CPU time | 2.01 seconds |
| Started | Nov 22 12:42:39 PM PST 23 |
| Finished | Nov 22 12:42:45 PM PST 23 |
| Peak memory | 200272 kb |
| Host | smart-3f9253b4-4f2f-4db7-a46d-a31a9eb60363 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67491051619468470509926703080239059118788134509507048388747673749773293235922 -assert nopostproc +U VM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 14.uart_tl_errors.67491051619468470509926703080239059118788134509507048388747673749773293235922 |
| Directory | /workspace/14.uart_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/14.uart_tl_intg_err.67815733940663393018631866860688846086526153628565762559929959293536001872868 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 136349867 ps |
| CPU time | 1.29 seconds |
| Started | Nov 22 12:42:42 PM PST 23 |
| Finished | Nov 22 12:42:45 PM PST 23 |
| Peak memory | 199456 kb |
| Host | smart-5176e0cd-0df2-4296-a565-ae9c54132a31 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67815733940663393018631866860688846086526153628565762559929959293536001872868 -assert n opostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co ver_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_intg_err.67815733940663393018631866860688846086526153628565762559929959293536001872868 |
| Directory | /workspace/14.uart_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.97864290399140974034436492806662242221894493681377227576996280144991241749336 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 38332794 ps |
| CPU time | 0.84 seconds |
| Started | Nov 22 12:42:54 PM PST 23 |
| Finished | Nov 22 12:42:56 PM PST 23 |
| Peak memory | 200036 kb |
| Host | smart-d64b9020-1565-4c73-80d3-6f51ce8ed400 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9786429039914097403443649280666224222189449 3681377227576996280144991241749336 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_csr_mem_rw_with_rand_reset.978642903991409740344364 92806662242221894493681377227576996280144991241749336 |
| Directory | /workspace/15.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/15.uart_csr_rw.50670590584137602618429862330235407660470366266795665038039299827366740832447 |
| Short name | T1299 |
| Test name | |
| Test status | |
| Simulation time | 21815069 ps |
| CPU time | 0.65 seconds |
| Started | Nov 22 12:42:24 PM PST 23 |
| Finished | Nov 22 12:42:27 PM PST 23 |
| Peak memory | 195792 kb |
| Host | smart-41ec52dd-71aa-48c9-b800-19d41eeaaf6f |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50670590584137602618429862330235407660470366266795665038039299827366740832447 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t op.vdb -cm_log /dev/null -cm_name 15.uart_csr_rw.50670590584137602618429862330235407660470366266795665038039299827366740832447 |
| Directory | /workspace/15.uart_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/15.uart_intr_test.13328511822170216174460701853912440163073453989483608893096904264973154603818 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 22779347 ps |
| CPU time | 0.62 seconds |
| Started | Nov 22 12:42:24 PM PST 23 |
| Finished | Nov 22 12:42:27 PM PST 23 |
| Peak memory | 194560 kb |
| Host | smart-b41ce90d-580a-4dcc-b845-06bfbfe3b880 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13328511822170216174460701853912440163073453989483608893096904264973154603818 -assert nopostproc +U VM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 15.uart_intr_test.13328511822170216174460701853912440163073453989483608893096904264973154603818 |
| Directory | /workspace/15.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.16411607283378856413390392863276713139302427744574074526835545063803323026939 |
| Short name | T1283 |
| Test name | |
| Test status | |
| Simulation time | 45029169 ps |
| CPU time | 0.79 seconds |
| Started | Nov 22 12:42:24 PM PST 23 |
| Finished | Nov 22 12:42:27 PM PST 23 |
| Peak memory | 197360 kb |
| Host | smart-c2b4017d-c552-4b1e-9a0e-30b3464357f0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16411607283378856413390392863276713139302427744574074526835545063803323026939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_same_csr_outstanding.16411607283378856413390392863276713139302427744574074526835545063803323026939 |
| Directory | /workspace/15.uart_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/15.uart_tl_errors.50223775446449382909034315298658878298553841360567756374672217402931928035282 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 152867592 ps |
| CPU time | 2.11 seconds |
| Started | Nov 22 12:42:28 PM PST 23 |
| Finished | Nov 22 12:42:33 PM PST 23 |
| Peak memory | 200244 kb |
| Host | smart-419303b0-2ffd-42ff-aff5-0957f47e9951 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50223775446449382909034315298658878298553841360567756374672217402931928035282 -assert nopostproc +U VM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 15.uart_tl_errors.50223775446449382909034315298658878298553841360567756374672217402931928035282 |
| Directory | /workspace/15.uart_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.96382120293051469315581558392835605927605320683188016510891198900139708194016 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 136349867 ps |
| CPU time | 1.32 seconds |
| Started | Nov 22 12:42:25 PM PST 23 |
| Finished | Nov 22 12:42:29 PM PST 23 |
| Peak memory | 199472 kb |
| Host | smart-80834e32-c273-43cb-8ee6-274b7b7820c0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96382120293051469315581558392835605927605320683188016510891198900139708194016 -assert n opostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co ver_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_intg_err.96382120293051469315581558392835605927605320683188016510891198900139708194016 |
| Directory | /workspace/15.uart_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.493072419533636812268940890951451308293697634889112230878435715628613797648 |
| Short name | T1293 |
| Test name | |
| Test status | |
| Simulation time | 38332794 ps |
| CPU time | 0.79 seconds |
| Started | Nov 22 12:42:52 PM PST 23 |
| Finished | Nov 22 12:42:54 PM PST 23 |
| Peak memory | 200036 kb |
| Host | smart-021604da-89c9-445f-bb84-5fe54a0f655c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4930724195336368122689408909514513082936976 34889112230878435715628613797648 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_csr_mem_rw_with_rand_reset.49307241953363681226894089 0951451308293697634889112230878435715628613797648 |
| Directory | /workspace/16.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/16.uart_csr_rw.89081160399731922255260782872260479893272126736119256149033578040163336512269 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 21815069 ps |
| CPU time | 0.62 seconds |
| Started | Nov 22 12:42:24 PM PST 23 |
| Finished | Nov 22 12:42:27 PM PST 23 |
| Peak memory | 195792 kb |
| Host | smart-4529179d-68e1-4f4d-baab-4a0be0503211 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89081160399731922255260782872260479893272126736119256149033578040163336512269 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t op.vdb -cm_log /dev/null -cm_name 16.uart_csr_rw.89081160399731922255260782872260479893272126736119256149033578040163336512269 |
| Directory | /workspace/16.uart_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/16.uart_intr_test.69944430431183874363145903200138159710093473574259011681740076802809822033137 |
| Short name | T1307 |
| Test name | |
| Test status | |
| Simulation time | 22779347 ps |
| CPU time | 0.59 seconds |
| Started | Nov 22 12:42:22 PM PST 23 |
| Finished | Nov 22 12:42:25 PM PST 23 |
| Peak memory | 194648 kb |
| Host | smart-b4c7c172-f5e4-4328-b948-192b1658861b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69944430431183874363145903200138159710093473574259011681740076802809822033137 -assert nopostproc +U VM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 16.uart_intr_test.69944430431183874363145903200138159710093473574259011681740076802809822033137 |
| Directory | /workspace/16.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.80438571004662603259053717380573491482231584440927893412591957879519085851825 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 45029169 ps |
| CPU time | 0.75 seconds |
| Started | Nov 22 12:42:39 PM PST 23 |
| Finished | Nov 22 12:42:44 PM PST 23 |
| Peak memory | 197288 kb |
| Host | smart-02af9b90-1bd5-49db-b3aa-36dcaa7629e8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80438571004662603259053717380573491482231584440927893412591957879519085851825 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_same_csr_outstanding.80438571004662603259053717380573491482231584440927893412591957879519085851825 |
| Directory | /workspace/16.uart_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/16.uart_tl_errors.106933684536279191740922808134573151626953625585658608752751991697822863169309 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 152867592 ps |
| CPU time | 2.07 seconds |
| Started | Nov 22 12:42:22 PM PST 23 |
| Finished | Nov 22 12:42:27 PM PST 23 |
| Peak memory | 200260 kb |
| Host | smart-92b6d22b-4d55-47b5-9b68-29d227e09bce |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106933684536279191740922808134573151626953625585658608752751991697822863169309 -assert nopostproc + UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 16.uart_tl_errors.106933684536279191740922808134573151626953625585658608752751991697822863169309 |
| Directory | /workspace/16.uart_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.110491341789859869602424130606185849334442853365061149111411389021740175925999 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 136349867 ps |
| CPU time | 1.41 seconds |
| Started | Nov 22 12:42:21 PM PST 23 |
| Finished | Nov 22 12:42:25 PM PST 23 |
| Peak memory | 199452 kb |
| Host | smart-c2896051-9c55-4984-acb4-a7e7a60484bf |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110491341789859869602424130606185849334442853365061149111411389021740175925999 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/c over_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_intg_err.110491341789859869602424130606185849334442853365061149111411389021740175925999 |
| Directory | /workspace/16.uart_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.34411534952994530884722814393448451576772675826661565073166361494118848849818 |
| Short name | T1302 |
| Test name | |
| Test status | |
| Simulation time | 38332794 ps |
| CPU time | 0.8 seconds |
| Started | Nov 22 12:42:42 PM PST 23 |
| Finished | Nov 22 12:42:45 PM PST 23 |
| Peak memory | 200160 kb |
| Host | smart-71f256c0-cb48-4e20-a149-d0d77e832ff5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441153495299453088472281439344845157677267 5826661565073166361494118848849818 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_csr_mem_rw_with_rand_reset.344115349529945308847228 14393448451576772675826661565073166361494118848849818 |
| Directory | /workspace/17.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/17.uart_csr_rw.88422434393030747997511957681444457089326450592228804047874073717700447583046 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 21815069 ps |
| CPU time | 0.61 seconds |
| Started | Nov 22 12:42:55 PM PST 23 |
| Finished | Nov 22 12:42:57 PM PST 23 |
| Peak memory | 195716 kb |
| Host | smart-a415a0c0-5123-4a56-afcc-bf24b727e55b |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88422434393030747997511957681444457089326450592228804047874073717700447583046 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t op.vdb -cm_log /dev/null -cm_name 17.uart_csr_rw.88422434393030747997511957681444457089326450592228804047874073717700447583046 |
| Directory | /workspace/17.uart_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/17.uart_intr_test.18675565291788985562410660464143960612202545450818529940428654645112246470219 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 22779347 ps |
| CPU time | 0.58 seconds |
| Started | Nov 22 12:42:32 PM PST 23 |
| Finished | Nov 22 12:42:38 PM PST 23 |
| Peak memory | 194656 kb |
| Host | smart-33dd9168-587d-4b7d-bc5e-821b7203d9f6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18675565291788985562410660464143960612202545450818529940428654645112246470219 -assert nopostproc +U VM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 17.uart_intr_test.18675565291788985562410660464143960612202545450818529940428654645112246470219 |
| Directory | /workspace/17.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.113201083000295730899106071736401823533593985542435284201211832389837687481516 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 45029169 ps |
| CPU time | 0.73 seconds |
| Started | Nov 22 12:42:30 PM PST 23 |
| Finished | Nov 22 12:42:37 PM PST 23 |
| Peak memory | 197340 kb |
| Host | smart-a459ad0c-e43e-4f42-b49f-65cbef096a8a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113201083000295730899106071736401823533593985542435284201211832389837687481516 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_same_csr_outstanding.1132010830002957308991060717364018235335939855424352842012118323 89837687481516 |
| Directory | /workspace/17.uart_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/17.uart_tl_errors.74484068961810700684056590314738141125301443837677032140475333499168471979195 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 152867592 ps |
| CPU time | 2.12 seconds |
| Started | Nov 22 12:42:20 PM PST 23 |
| Finished | Nov 22 12:42:24 PM PST 23 |
| Peak memory | 200276 kb |
| Host | smart-04ff8011-6860-4bd3-85b2-c68096208e24 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74484068961810700684056590314738141125301443837677032140475333499168471979195 -assert nopostproc +U VM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 17.uart_tl_errors.74484068961810700684056590314738141125301443837677032140475333499168471979195 |
| Directory | /workspace/17.uart_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.106955031762368143796369224814887551504514514481723969152887673976099689601070 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 136349867 ps |
| CPU time | 1.35 seconds |
| Started | Nov 22 12:42:29 PM PST 23 |
| Finished | Nov 22 12:42:34 PM PST 23 |
| Peak memory | 199432 kb |
| Host | smart-88acca29-304f-4d26-aebd-ec0642fdd2e2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106955031762368143796369224814887551504514514481723969152887673976099689601070 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/c over_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_intg_err.106955031762368143796369224814887551504514514481723969152887673976099689601070 |
| Directory | /workspace/17.uart_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.32998567842596732259565867918043866375935013019465798813452894196553482533335 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 38332794 ps |
| CPU time | 0.82 seconds |
| Started | Nov 22 12:42:28 PM PST 23 |
| Finished | Nov 22 12:42:32 PM PST 23 |
| Peak memory | 200176 kb |
| Host | smart-12b36568-ecfd-482f-996a-df4fba514d62 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299856784259673225956586791804386637593501 3019465798813452894196553482533335 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_csr_mem_rw_with_rand_reset.329985678425967322595658 67918043866375935013019465798813452894196553482533335 |
| Directory | /workspace/18.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/18.uart_csr_rw.30457580070081384288800890684557080546407010569411503731891514075171596532593 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 21815069 ps |
| CPU time | 0.64 seconds |
| Started | Nov 22 12:42:27 PM PST 23 |
| Finished | Nov 22 12:42:31 PM PST 23 |
| Peak memory | 195760 kb |
| Host | smart-bd62523a-ed06-46f8-8925-c2c8ecd454b0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30457580070081384288800890684557080546407010569411503731891514075171596532593 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t op.vdb -cm_log /dev/null -cm_name 18.uart_csr_rw.30457580070081384288800890684557080546407010569411503731891514075171596532593 |
| Directory | /workspace/18.uart_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/18.uart_intr_test.110134855968888928036851874041454073192108395410551463018633874332497487585408 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 22779347 ps |
| CPU time | 0.56 seconds |
| Started | Nov 22 12:42:36 PM PST 23 |
| Finished | Nov 22 12:42:40 PM PST 23 |
| Peak memory | 194640 kb |
| Host | smart-081fd479-4560-4db5-b470-5bd39ddb478f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110134855968888928036851874041454073192108395410551463018633874332497487585408 -assert nopostproc + UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 18.uart_intr_test.110134855968888928036851874041454073192108395410551463018633874332497487585408 |
| Directory | /workspace/18.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.29000910707758167020419202467617267888731760266548626752256014741492115071710 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 45029169 ps |
| CPU time | 0.75 seconds |
| Started | Nov 22 12:42:36 PM PST 23 |
| Finished | Nov 22 12:42:40 PM PST 23 |
| Peak memory | 197344 kb |
| Host | smart-7114bca7-f5f3-454e-a1db-c886c1b948ed |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29000910707758167020419202467617267888731760266548626752256014741492115071710 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_same_csr_outstanding.29000910707758167020419202467617267888731760266548626752256014741492115071710 |
| Directory | /workspace/18.uart_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/18.uart_tl_errors.51477324887537573206337963931255210520855840889798394037574133387380588135509 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 152867592 ps |
| CPU time | 2 seconds |
| Started | Nov 22 12:42:34 PM PST 23 |
| Finished | Nov 22 12:42:41 PM PST 23 |
| Peak memory | 199896 kb |
| Host | smart-d7d60fa2-5715-497b-95dd-1bab803e6468 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51477324887537573206337963931255210520855840889798394037574133387380588135509 -assert nopostproc +U VM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 18.uart_tl_errors.51477324887537573206337963931255210520855840889798394037574133387380588135509 |
| Directory | /workspace/18.uart_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.35701639806698078417712567426945791833853554715066135367527905656981959679288 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 136349867 ps |
| CPU time | 1.37 seconds |
| Started | Nov 22 12:42:23 PM PST 23 |
| Finished | Nov 22 12:42:27 PM PST 23 |
| Peak memory | 199496 kb |
| Host | smart-7c4e0d04-4029-4882-ad56-4e38c57f8dee |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35701639806698078417712567426945791833853554715066135367527905656981959679288 -assert n opostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co ver_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_intg_err.35701639806698078417712567426945791833853554715066135367527905656981959679288 |
| Directory | /workspace/18.uart_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.85688754062418045550334359162303206244027583659882477564252845774816643549627 |
| Short name | T1300 |
| Test name | |
| Test status | |
| Simulation time | 38332794 ps |
| CPU time | 0.82 seconds |
| Started | Nov 22 12:42:40 PM PST 23 |
| Finished | Nov 22 12:42:45 PM PST 23 |
| Peak memory | 200164 kb |
| Host | smart-c460ee15-b9d0-4c4a-b56f-7bf7b94f817b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8568875406241804555033435916230320624402758 3659882477564252845774816643549627 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_csr_mem_rw_with_rand_reset.856887540624180455503343 59162303206244027583659882477564252845774816643549627 |
| Directory | /workspace/19.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/19.uart_csr_rw.9698328485427329087582849410412764953961686808806811328920399018874378398406 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 21815069 ps |
| CPU time | 0.59 seconds |
| Started | Nov 22 12:42:28 PM PST 23 |
| Finished | Nov 22 12:42:32 PM PST 23 |
| Peak memory | 195736 kb |
| Host | smart-dcab2d8b-eb3e-4bcb-a8fd-28034fc45e4a |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9698328485427329087582849410412764953961686808806811328920399018874378398406 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 19.uart_csr_rw.9698328485427329087582849410412764953961686808806811328920399018874378398406 |
| Directory | /workspace/19.uart_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/19.uart_intr_test.96956357683323282383165573474083060280375298570350620537719956511741922272548 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 22779347 ps |
| CPU time | 0.63 seconds |
| Started | Nov 22 12:42:24 PM PST 23 |
| Finished | Nov 22 12:42:27 PM PST 23 |
| Peak memory | 194664 kb |
| Host | smart-9c97d4ab-5e56-419e-aebc-f68ec733a010 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96956357683323282383165573474083060280375298570350620537719956511741922272548 -assert nopostproc +U VM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 19.uart_intr_test.96956357683323282383165573474083060280375298570350620537719956511741922272548 |
| Directory | /workspace/19.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.89306793137493292540284745700851164145436733299719187182358686758072572192714 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 45029169 ps |
| CPU time | 0.74 seconds |
| Started | Nov 22 12:42:32 PM PST 23 |
| Finished | Nov 22 12:42:38 PM PST 23 |
| Peak memory | 197316 kb |
| Host | smart-34e57026-f2db-4735-a84b-83ddb4759a28 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89306793137493292540284745700851164145436733299719187182358686758072572192714 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_same_csr_outstanding.89306793137493292540284745700851164145436733299719187182358686758072572192714 |
| Directory | /workspace/19.uart_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/19.uart_tl_intg_err.16222972424683658785859346750446613496033810276382668228806391801178624830361 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 136349867 ps |
| CPU time | 1.32 seconds |
| Started | Nov 22 12:42:34 PM PST 23 |
| Finished | Nov 22 12:42:41 PM PST 23 |
| Peak memory | 199492 kb |
| Host | smart-c660a7c0-b380-4456-a7d2-aa87a50a455b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16222972424683658785859346750446613496033810276382668228806391801178624830361 -assert n opostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co ver_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_intg_err.16222972424683658785859346750446613496033810276382668228806391801178624830361 |
| Directory | /workspace/19.uart_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/2.uart_csr_aliasing.71284512662826001864345830121275547009100649601076965424423129595055893659052 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 42368476 ps |
| CPU time | 0.8 seconds |
| Started | Nov 22 12:42:06 PM PST 23 |
| Finished | Nov 22 12:42:13 PM PST 23 |
| Peak memory | 196640 kb |
| Host | smart-eee624f2-7962-4e9e-9d4e-b679895a2c37 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71284512662826001864345830121275547009100649601076965424423129595055893659052 -assert nopo stproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover _reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_aliasing.71284512662826001864345830121275547009100649601076965424423129595055893659052 |
| Directory | /workspace/2.uart_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.77920854315113071527171923003761642134610397242225569625644643842657802495428 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 306241365 ps |
| CPU time | 2.52 seconds |
| Started | Nov 22 12:42:08 PM PST 23 |
| Finished | Nov 22 12:42:15 PM PST 23 |
| Peak memory | 198240 kb |
| Host | smart-a56181b2-a1b5-433f-a12d-9357acf402c9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77920854315113071527171923003761642134610397242225569625644643842657802495428 -assert nopo stproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover _reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_bit_bash.77920854315113071527171923003761642134610397242225569625644643842657802495428 |
| Directory | /workspace/2.uart_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.37304378338869938462223418972145060549298936188077912904611025312969821430758 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 22529349 ps |
| CPU time | 0.6 seconds |
| Started | Nov 22 12:42:12 PM PST 23 |
| Finished | Nov 22 12:42:18 PM PST 23 |
| Peak memory | 195744 kb |
| Host | smart-d7008b2c-c2a2-48af-9c46-c837e327dbe4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37304378338869938462223418972145060549298936188077912904611025312969821430758 -assert nopo stproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover _reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_hw_reset.37304378338869938462223418972145060549298936188077912904611025312969821430758 |
| Directory | /workspace/2.uart_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.1393244602911630519579332638100539956251316234964323253990806387411353950810 |
| Short name | T1281 |
| Test name | |
| Test status | |
| Simulation time | 38332794 ps |
| CPU time | 0.82 seconds |
| Started | Nov 22 12:42:25 PM PST 23 |
| Finished | Nov 22 12:42:28 PM PST 23 |
| Peak memory | 200144 kb |
| Host | smart-42922f0b-3d2f-41be-9ff1-b9066184d245 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393244602911630519579332638100539956251316 234964323253990806387411353950810 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_mem_rw_with_rand_reset.13932446029116305195793326 38100539956251316234964323253990806387411353950810 |
| Directory | /workspace/2.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/2.uart_csr_rw.86768203662120058761442136699499805382223790337438730934227807078181955532560 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 21815069 ps |
| CPU time | 0.6 seconds |
| Started | Nov 22 12:42:14 PM PST 23 |
| Finished | Nov 22 12:42:19 PM PST 23 |
| Peak memory | 195736 kb |
| Host | smart-5d4b847c-08e2-4c7d-8b86-7a354cc8cb1b |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86768203662120058761442136699499805382223790337438730934227807078181955532560 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t op.vdb -cm_log /dev/null -cm_name 2.uart_csr_rw.86768203662120058761442136699499805382223790337438730934227807078181955532560 |
| Directory | /workspace/2.uart_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/2.uart_intr_test.71525922722448652065741894497057802824080409659812153931032404953417643869325 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 22779347 ps |
| CPU time | 0.57 seconds |
| Started | Nov 22 12:42:21 PM PST 23 |
| Finished | Nov 22 12:42:24 PM PST 23 |
| Peak memory | 194684 kb |
| Host | smart-98eb46ea-b360-4a56-ac78-64bef915b8e0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71525922722448652065741894497057802824080409659812153931032404953417643869325 -assert nopostproc +U VM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 2.uart_intr_test.71525922722448652065741894497057802824080409659812153931032404953417643869325 |
| Directory | /workspace/2.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.58627807796567477890187752250441096488202650576807844892374364030826742178297 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 45029169 ps |
| CPU time | 0.81 seconds |
| Started | Nov 22 12:42:13 PM PST 23 |
| Finished | Nov 22 12:42:19 PM PST 23 |
| Peak memory | 197312 kb |
| Host | smart-3573ddc7-8fe5-49ad-8404-f8a71ca7116c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58627807796567477890187752250441096488202650576807844892374364030826742178297 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_same_csr_outstanding.58627807796567477890187752250441096488202650576807844892374364030826742178297 |
| Directory | /workspace/2.uart_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/2.uart_tl_errors.64016023553601983709967637639457534055926776053251309773864439229291740847155 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 152867592 ps |
| CPU time | 2.01 seconds |
| Started | Nov 22 12:42:10 PM PST 23 |
| Finished | Nov 22 12:42:18 PM PST 23 |
| Peak memory | 200220 kb |
| Host | smart-30d7bd4d-9e71-415e-b374-79ec8e551de7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64016023553601983709967637639457534055926776053251309773864439229291740847155 -assert nopostproc +U VM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 2.uart_tl_errors.64016023553601983709967637639457534055926776053251309773864439229291740847155 |
| Directory | /workspace/2.uart_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/2.uart_tl_intg_err.63373462465403761341201899361986938110445859494334703258409215669050763398215 |
| Short name | T1298 |
| Test name | |
| Test status | |
| Simulation time | 136349867 ps |
| CPU time | 1.28 seconds |
| Started | Nov 22 12:42:09 PM PST 23 |
| Finished | Nov 22 12:42:15 PM PST 23 |
| Peak memory | 199488 kb |
| Host | smart-f0f55c0c-2025-4d9b-be2f-d71b48726207 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63373462465403761341201899361986938110445859494334703258409215669050763398215 -assert n opostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co ver_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_intg_err.63373462465403761341201899361986938110445859494334703258409215669050763398215 |
| Directory | /workspace/2.uart_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/20.uart_intr_test.115353835445014175223945886168334383962767417101638251721524981328593412346904 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 22779347 ps |
| CPU time | 0.58 seconds |
| Started | Nov 22 12:42:40 PM PST 23 |
| Finished | Nov 22 12:42:44 PM PST 23 |
| Peak memory | 194548 kb |
| Host | smart-126847a1-5be4-4660-86e0-9e68f7f0c2db |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115353835445014175223945886168334383962767417101638251721524981328593412346904 -assert nopostproc + UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 20.uart_intr_test.115353835445014175223945886168334383962767417101638251721524981328593412346904 |
| Directory | /workspace/20.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/21.uart_intr_test.23674786477610102083855078143697894599406285076999922110249447980686758130784 |
| Short name | T1288 |
| Test name | |
| Test status | |
| Simulation time | 22779347 ps |
| CPU time | 0.58 seconds |
| Started | Nov 22 12:42:40 PM PST 23 |
| Finished | Nov 22 12:42:44 PM PST 23 |
| Peak memory | 194540 kb |
| Host | smart-62d37998-54dd-4a28-adfd-c3157a56a591 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23674786477610102083855078143697894599406285076999922110249447980686758130784 -assert nopostproc +U VM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 21.uart_intr_test.23674786477610102083855078143697894599406285076999922110249447980686758130784 |
| Directory | /workspace/21.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/22.uart_intr_test.56486173411984629432250383073664960875234122716842125897643003452500046444214 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 22779347 ps |
| CPU time | 0.59 seconds |
| Started | Nov 22 12:42:40 PM PST 23 |
| Finished | Nov 22 12:42:44 PM PST 23 |
| Peak memory | 194680 kb |
| Host | smart-a62a2ec9-2919-4a3b-ba5a-5bba125c6060 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56486173411984629432250383073664960875234122716842125897643003452500046444214 -assert nopostproc +U VM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 22.uart_intr_test.56486173411984629432250383073664960875234122716842125897643003452500046444214 |
| Directory | /workspace/22.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/23.uart_intr_test.107989666860944867148777551710253069084068865565812480919365387325960825307095 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 22779347 ps |
| CPU time | 0.59 seconds |
| Started | Nov 22 12:43:13 PM PST 23 |
| Finished | Nov 22 12:43:21 PM PST 23 |
| Peak memory | 194640 kb |
| Host | smart-ff2ca5fd-9c4c-4ec3-805e-85820850981f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107989666860944867148777551710253069084068865565812480919365387325960825307095 -assert nopostproc + UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 23.uart_intr_test.107989666860944867148777551710253069084068865565812480919365387325960825307095 |
| Directory | /workspace/23.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/24.uart_intr_test.83004824092925558728100031339278654053634941959725489710474544273116305847070 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 22779347 ps |
| CPU time | 0.58 seconds |
| Started | Nov 22 12:42:49 PM PST 23 |
| Finished | Nov 22 12:42:52 PM PST 23 |
| Peak memory | 194628 kb |
| Host | smart-c76ce8c9-2fca-473e-9184-8171f075de9a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83004824092925558728100031339278654053634941959725489710474544273116305847070 -assert nopostproc +U VM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 24.uart_intr_test.83004824092925558728100031339278654053634941959725489710474544273116305847070 |
| Directory | /workspace/24.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/25.uart_intr_test.30717375447266362324460735833788325258975286673081255490687438813215885650805 |
| Short name | T1312 |
| Test name | |
| Test status | |
| Simulation time | 22779347 ps |
| CPU time | 0.58 seconds |
| Started | Nov 22 12:43:16 PM PST 23 |
| Finished | Nov 22 12:43:23 PM PST 23 |
| Peak memory | 194660 kb |
| Host | smart-5b534089-b94c-4a44-8198-a677ad74e612 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30717375447266362324460735833788325258975286673081255490687438813215885650805 -assert nopostproc +U VM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 25.uart_intr_test.30717375447266362324460735833788325258975286673081255490687438813215885650805 |
| Directory | /workspace/25.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/26.uart_intr_test.61297456548752942094505635418644778087872690927838477072367304997274694642790 |
| Short name | T1311 |
| Test name | |
| Test status | |
| Simulation time | 22779347 ps |
| CPU time | 0.55 seconds |
| Started | Nov 22 12:43:00 PM PST 23 |
| Finished | Nov 22 12:43:04 PM PST 23 |
| Peak memory | 194660 kb |
| Host | smart-cba67f66-c5dd-4638-8639-5070875b6d81 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61297456548752942094505635418644778087872690927838477072367304997274694642790 -assert nopostproc +U VM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 26.uart_intr_test.61297456548752942094505635418644778087872690927838477072367304997274694642790 |
| Directory | /workspace/26.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/27.uart_intr_test.108333285852956633729985413518007917043579547906628903501032006823470449330760 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 22779347 ps |
| CPU time | 0.58 seconds |
| Started | Nov 22 12:43:07 PM PST 23 |
| Finished | Nov 22 12:43:14 PM PST 23 |
| Peak memory | 194664 kb |
| Host | smart-6c3af5d1-1418-4c2f-b4e5-0f19048bde77 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108333285852956633729985413518007917043579547906628903501032006823470449330760 -assert nopostproc + UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 27.uart_intr_test.108333285852956633729985413518007917043579547906628903501032006823470449330760 |
| Directory | /workspace/27.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/28.uart_intr_test.48247493455462324604172725817853222749090252531625818311007445950949648234615 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 22779347 ps |
| CPU time | 0.57 seconds |
| Started | Nov 22 12:43:07 PM PST 23 |
| Finished | Nov 22 12:43:14 PM PST 23 |
| Peak memory | 194680 kb |
| Host | smart-b5e0aa94-48a5-4f9e-8d38-ee037b7b3992 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48247493455462324604172725817853222749090252531625818311007445950949648234615 -assert nopostproc +U VM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 28.uart_intr_test.48247493455462324604172725817853222749090252531625818311007445950949648234615 |
| Directory | /workspace/28.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/29.uart_intr_test.88568057809693824718399662530141094936187717588046494311611187515147159096346 |
| Short name | T1284 |
| Test name | |
| Test status | |
| Simulation time | 22779347 ps |
| CPU time | 0.58 seconds |
| Started | Nov 22 12:42:53 PM PST 23 |
| Finished | Nov 22 12:42:55 PM PST 23 |
| Peak memory | 194708 kb |
| Host | smart-127367e8-f130-455f-a13b-769c72c0c53b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88568057809693824718399662530141094936187717588046494311611187515147159096346 -assert nopostproc +U VM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 29.uart_intr_test.88568057809693824718399662530141094936187717588046494311611187515147159096346 |
| Directory | /workspace/29.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.69385184666248871159410936114961167941072251243972245206169366909460962777124 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 42368476 ps |
| CPU time | 0.77 seconds |
| Started | Nov 22 12:42:04 PM PST 23 |
| Finished | Nov 22 12:42:13 PM PST 23 |
| Peak memory | 196640 kb |
| Host | smart-38213bb0-4cb4-4409-a64c-4abe31196a73 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69385184666248871159410936114961167941072251243972245206169366909460962777124 -assert nopo stproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover _reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_aliasing.69385184666248871159410936114961167941072251243972245206169366909460962777124 |
| Directory | /workspace/3.uart_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.54537455128776763799489186299852768580654185089804445952955491089676847802202 |
| Short name | T1305 |
| Test name | |
| Test status | |
| Simulation time | 306241365 ps |
| CPU time | 2.53 seconds |
| Started | Nov 22 12:42:15 PM PST 23 |
| Finished | Nov 22 12:42:21 PM PST 23 |
| Peak memory | 198196 kb |
| Host | smart-4054e42e-1a1a-4730-b6d2-b4bb652a06bb |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54537455128776763799489186299852768580654185089804445952955491089676847802202 -assert nopo stproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover _reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_bit_bash.54537455128776763799489186299852768580654185089804445952955491089676847802202 |
| Directory | /workspace/3.uart_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.109168577332229851122924902070817832999930459950438419919146488480508662577513 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 22529349 ps |
| CPU time | 0.61 seconds |
| Started | Nov 22 12:42:12 PM PST 23 |
| Finished | Nov 22 12:42:18 PM PST 23 |
| Peak memory | 195764 kb |
| Host | smart-eb0e99bf-c474-4bf1-89b3-3d32b9131946 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109168577332229851122924902070817832999930459950438419919146488480508662577513 -assert nop ostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove r_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_hw_reset.109168577332229851122924902070817832999930459950438419919146488480508662577513 |
| Directory | /workspace/3.uart_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.66789333829097139564706647525920547382761053942105811077811157421287232302839 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 38332794 ps |
| CPU time | 0.8 seconds |
| Started | Nov 22 12:42:31 PM PST 23 |
| Finished | Nov 22 12:42:37 PM PST 23 |
| Peak memory | 200112 kb |
| Host | smart-d61ce78e-a56f-40b2-8480-da20edf21b80 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6678933382909713956470664752592054738276105 3942105811077811157421287232302839 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_mem_rw_with_rand_reset.6678933382909713956470664 7525920547382761053942105811077811157421287232302839 |
| Directory | /workspace/3.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/3.uart_csr_rw.23208221543614031845832613155004960542689065125336045950673684969027386842226 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 21815069 ps |
| CPU time | 0.65 seconds |
| Started | Nov 22 12:42:08 PM PST 23 |
| Finished | Nov 22 12:42:13 PM PST 23 |
| Peak memory | 195676 kb |
| Host | smart-ae3675d9-a62c-4f1d-9255-b289d47fddea |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23208221543614031845832613155004960542689065125336045950673684969027386842226 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t op.vdb -cm_log /dev/null -cm_name 3.uart_csr_rw.23208221543614031845832613155004960542689065125336045950673684969027386842226 |
| Directory | /workspace/3.uart_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/3.uart_intr_test.31625766162622650402893664916825058216759760078749086260287958174397821072604 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 22779347 ps |
| CPU time | 0.56 seconds |
| Started | Nov 22 12:42:17 PM PST 23 |
| Finished | Nov 22 12:42:20 PM PST 23 |
| Peak memory | 194580 kb |
| Host | smart-7346b899-f8f3-4fb8-b989-492644ccd140 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31625766162622650402893664916825058216759760078749086260287958174397821072604 -assert nopostproc +U VM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 3.uart_intr_test.31625766162622650402893664916825058216759760078749086260287958174397821072604 |
| Directory | /workspace/3.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.89125926594491884585562023563661771186434530839479246027800288024918576682267 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 45029169 ps |
| CPU time | 0.76 seconds |
| Started | Nov 22 12:42:14 PM PST 23 |
| Finished | Nov 22 12:42:19 PM PST 23 |
| Peak memory | 197312 kb |
| Host | smart-016965da-3889-4976-a4ca-d9181a29b80b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89125926594491884585562023563661771186434530839479246027800288024918576682267 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_same_csr_outstanding.89125926594491884585562023563661771186434530839479246027800288024918576682267 |
| Directory | /workspace/3.uart_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/3.uart_tl_errors.27535722280756303196858349993669594422146702520716487981494803320713364651596 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 152867592 ps |
| CPU time | 2.09 seconds |
| Started | Nov 22 12:42:17 PM PST 23 |
| Finished | Nov 22 12:42:22 PM PST 23 |
| Peak memory | 200252 kb |
| Host | smart-9cf1a4e7-7030-4004-a0a6-0c207fc33d8e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27535722280756303196858349993669594422146702520716487981494803320713364651596 -assert nopostproc +U VM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 3.uart_tl_errors.27535722280756303196858349993669594422146702520716487981494803320713364651596 |
| Directory | /workspace/3.uart_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/3.uart_tl_intg_err.50240170932551309187875966651477181298496320378911625317177605746065714108116 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 136349867 ps |
| CPU time | 1.33 seconds |
| Started | Nov 22 12:42:20 PM PST 23 |
| Finished | Nov 22 12:42:23 PM PST 23 |
| Peak memory | 199452 kb |
| Host | smart-7a77a55b-0470-4c7a-ab8f-8c95a32a34ae |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50240170932551309187875966651477181298496320378911625317177605746065714108116 -assert n opostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co ver_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_intg_err.50240170932551309187875966651477181298496320378911625317177605746065714108116 |
| Directory | /workspace/3.uart_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/30.uart_intr_test.7028470108618877348116246667452765105033659253601289496650266389450209366580 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 22779347 ps |
| CPU time | 0.56 seconds |
| Started | Nov 22 12:43:01 PM PST 23 |
| Finished | Nov 22 12:43:05 PM PST 23 |
| Peak memory | 194648 kb |
| Host | smart-ed2a36c2-175f-404d-ac46-6ef85e181da3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7028470108618877348116246667452765105033659253601289496650266389450209366580 -assert nopostproc +UV M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v db -cm_log /dev/null -cm_name 30.uart_intr_test.7028470108618877348116246667452765105033659253601289496650266389450209366580 |
| Directory | /workspace/30.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/31.uart_intr_test.5804430809372354457632900431818536090235975316744241034089124316252853951102 |
| Short name | T1304 |
| Test name | |
| Test status | |
| Simulation time | 22779347 ps |
| CPU time | 0.58 seconds |
| Started | Nov 22 12:42:57 PM PST 23 |
| Finished | Nov 22 12:42:58 PM PST 23 |
| Peak memory | 194704 kb |
| Host | smart-ccbef62f-0c3c-4789-b84a-c1dfcecbba7b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5804430809372354457632900431818536090235975316744241034089124316252853951102 -assert nopostproc +UV M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v db -cm_log /dev/null -cm_name 31.uart_intr_test.5804430809372354457632900431818536090235975316744241034089124316252853951102 |
| Directory | /workspace/31.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/32.uart_intr_test.114768852763182744744058099190830831948283022539092689169405371770192484707637 |
| Short name | T1287 |
| Test name | |
| Test status | |
| Simulation time | 22779347 ps |
| CPU time | 0.59 seconds |
| Started | Nov 22 12:42:53 PM PST 23 |
| Finished | Nov 22 12:42:55 PM PST 23 |
| Peak memory | 194656 kb |
| Host | smart-5e41858a-4748-4c31-96d2-6508d8238dc8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114768852763182744744058099190830831948283022539092689169405371770192484707637 -assert nopostproc + UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 32.uart_intr_test.114768852763182744744058099190830831948283022539092689169405371770192484707637 |
| Directory | /workspace/32.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/33.uart_intr_test.47109262439537551952816306259145585001314196872122536173695970502895243664388 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 22779347 ps |
| CPU time | 0.56 seconds |
| Started | Nov 22 12:42:49 PM PST 23 |
| Finished | Nov 22 12:42:52 PM PST 23 |
| Peak memory | 194708 kb |
| Host | smart-0de41657-022b-4a71-bb30-7a989f0eef2f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47109262439537551952816306259145585001314196872122536173695970502895243664388 -assert nopostproc +U VM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 33.uart_intr_test.47109262439537551952816306259145585001314196872122536173695970502895243664388 |
| Directory | /workspace/33.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/34.uart_intr_test.64706249829450622467734309370417646853027564199937270999931195122705642685083 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 22779347 ps |
| CPU time | 0.57 seconds |
| Started | Nov 22 12:43:01 PM PST 23 |
| Finished | Nov 22 12:43:05 PM PST 23 |
| Peak memory | 194676 kb |
| Host | smart-4ff4169e-ea68-44a5-b7cf-11e5ee6c23bd |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64706249829450622467734309370417646853027564199937270999931195122705642685083 -assert nopostproc +U VM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 34.uart_intr_test.64706249829450622467734309370417646853027564199937270999931195122705642685083 |
| Directory | /workspace/34.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/35.uart_intr_test.635006699765886580001250598122307128336771014418870108770871805705012938252 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 22779347 ps |
| CPU time | 0.63 seconds |
| Started | Nov 22 12:43:11 PM PST 23 |
| Finished | Nov 22 12:43:17 PM PST 23 |
| Peak memory | 194648 kb |
| Host | smart-ed8d653d-31f0-45db-99ac-7c90b6202412 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635006699765886580001250598122307128336771014418870108770871805705012938252 -assert nopostproc +UVM _TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd b -cm_log /dev/null -cm_name 35.uart_intr_test.635006699765886580001250598122307128336771014418870108770871805705012938252 |
| Directory | /workspace/35.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/36.uart_intr_test.108054810770159999226181416513015649660037877042468172019266414121806075603044 |
| Short name | T1306 |
| Test name | |
| Test status | |
| Simulation time | 22779347 ps |
| CPU time | 0.58 seconds |
| Started | Nov 22 12:43:10 PM PST 23 |
| Finished | Nov 22 12:43:15 PM PST 23 |
| Peak memory | 194652 kb |
| Host | smart-0dc59a5c-4084-4688-a499-5425f0ac825a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108054810770159999226181416513015649660037877042468172019266414121806075603044 -assert nopostproc + UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 36.uart_intr_test.108054810770159999226181416513015649660037877042468172019266414121806075603044 |
| Directory | /workspace/36.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/37.uart_intr_test.92098742724303509341915378160158274901342386199931356347930612803005224974770 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 22779347 ps |
| CPU time | 0.57 seconds |
| Started | Nov 22 12:42:51 PM PST 23 |
| Finished | Nov 22 12:42:52 PM PST 23 |
| Peak memory | 194664 kb |
| Host | smart-31e4b1b5-4416-42b1-9cea-628aeb3ccdee |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92098742724303509341915378160158274901342386199931356347930612803005224974770 -assert nopostproc +U VM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 37.uart_intr_test.92098742724303509341915378160158274901342386199931356347930612803005224974770 |
| Directory | /workspace/37.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/38.uart_intr_test.12147744920927515911103445212503912122630484295570496280455822455368353940465 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 22779347 ps |
| CPU time | 0.58 seconds |
| Started | Nov 22 12:43:00 PM PST 23 |
| Finished | Nov 22 12:43:04 PM PST 23 |
| Peak memory | 194660 kb |
| Host | smart-0049e697-a217-4739-9728-3eed0590e7cd |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12147744920927515911103445212503912122630484295570496280455822455368353940465 -assert nopostproc +U VM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 38.uart_intr_test.12147744920927515911103445212503912122630484295570496280455822455368353940465 |
| Directory | /workspace/38.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/39.uart_intr_test.32804848616645873160980114353075811733133899020140289643715739953204368516878 |
| Short name | T1320 |
| Test name | |
| Test status | |
| Simulation time | 22779347 ps |
| CPU time | 0.58 seconds |
| Started | Nov 22 12:43:04 PM PST 23 |
| Finished | Nov 22 12:43:13 PM PST 23 |
| Peak memory | 194684 kb |
| Host | smart-d816d429-e485-4786-ba45-2664efacb3af |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32804848616645873160980114353075811733133899020140289643715739953204368516878 -assert nopostproc +U VM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 39.uart_intr_test.32804848616645873160980114353075811733133899020140289643715739953204368516878 |
| Directory | /workspace/39.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.1578942945651288238478214132587170078157611366533650098592629058150277185765 |
| Short name | T1295 |
| Test name | |
| Test status | |
| Simulation time | 42368476 ps |
| CPU time | 0.8 seconds |
| Started | Nov 22 12:42:10 PM PST 23 |
| Finished | Nov 22 12:42:16 PM PST 23 |
| Peak memory | 196636 kb |
| Host | smart-af3054ba-2216-4608-920c-7cea4590eaf8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578942945651288238478214132587170078157611366533650098592629058150277185765 -assert nopos tproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_ reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_aliasing.1578942945651288238478214132587170078157611366533650098592629058150277185765 |
| Directory | /workspace/4.uart_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.25353147227665185692518603509481952628610748715530111515956963734525164903936 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 306241365 ps |
| CPU time | 2.6 seconds |
| Started | Nov 22 12:42:11 PM PST 23 |
| Finished | Nov 22 12:42:19 PM PST 23 |
| Peak memory | 198156 kb |
| Host | smart-b5e7e6e3-a2b5-40df-8758-f16e3e4f7b8e |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25353147227665185692518603509481952628610748715530111515956963734525164903936 -assert nopo stproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover _reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_bit_bash.25353147227665185692518603509481952628610748715530111515956963734525164903936 |
| Directory | /workspace/4.uart_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.19462938704584101026384547551019717304819044070275578665873260534320599693571 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 22529349 ps |
| CPU time | 0.57 seconds |
| Started | Nov 22 12:42:09 PM PST 23 |
| Finished | Nov 22 12:42:14 PM PST 23 |
| Peak memory | 195752 kb |
| Host | smart-90afbff3-9725-4cf1-be70-8a8b37d3eff4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19462938704584101026384547551019717304819044070275578665873260534320599693571 -assert nopo stproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover _reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_hw_reset.19462938704584101026384547551019717304819044070275578665873260534320599693571 |
| Directory | /workspace/4.uart_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.24338638723853031874534138649075475104268563026033914111759491658177652179841 |
| Short name | T1285 |
| Test name | |
| Test status | |
| Simulation time | 38332794 ps |
| CPU time | 0.8 seconds |
| Started | Nov 22 12:42:10 PM PST 23 |
| Finished | Nov 22 12:42:16 PM PST 23 |
| Peak memory | 200172 kb |
| Host | smart-a2437546-91d0-48e7-a21e-7fdd253eb9f5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433863872385303187453413864907547510426856 3026033914111759491658177652179841 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_mem_rw_with_rand_reset.2433863872385303187453413 8649075475104268563026033914111759491658177652179841 |
| Directory | /workspace/4.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/4.uart_csr_rw.44433299047518971467595147047694558862256481261803412005374449165621704084188 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 21815069 ps |
| CPU time | 0.6 seconds |
| Started | Nov 22 12:42:17 PM PST 23 |
| Finished | Nov 22 12:42:21 PM PST 23 |
| Peak memory | 195756 kb |
| Host | smart-45a0dfd6-cb0e-4692-b4de-8934c00e21e4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44433299047518971467595147047694558862256481261803412005374449165621704084188 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t op.vdb -cm_log /dev/null -cm_name 4.uart_csr_rw.44433299047518971467595147047694558862256481261803412005374449165621704084188 |
| Directory | /workspace/4.uart_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/4.uart_intr_test.48364628983504010008778438753794498400841691032933201578496651891429125379994 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 22779347 ps |
| CPU time | 0.57 seconds |
| Started | Nov 22 12:42:11 PM PST 23 |
| Finished | Nov 22 12:42:17 PM PST 23 |
| Peak memory | 194604 kb |
| Host | smart-0f76d0c7-97b0-4c58-a773-1e012ab580bb |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48364628983504010008778438753794498400841691032933201578496651891429125379994 -assert nopostproc +U VM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 4.uart_intr_test.48364628983504010008778438753794498400841691032933201578496651891429125379994 |
| Directory | /workspace/4.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.1218970766201533836185943340348557106371589948142878440677952169449011454255 |
| Short name | T1282 |
| Test name | |
| Test status | |
| Simulation time | 45029169 ps |
| CPU time | 0.75 seconds |
| Started | Nov 22 12:42:12 PM PST 23 |
| Finished | Nov 22 12:42:18 PM PST 23 |
| Peak memory | 197320 kb |
| Host | smart-ab28f8b1-38d1-4270-ac00-14931f1692e8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218970766201533836185943340348557106371589948142878440677952169449011454255 - assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_same_csr_outstanding.1218970766201533836185943340348557106371589948142878440677952169449011454255 |
| Directory | /workspace/4.uart_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/4.uart_tl_errors.94646516747481594970811638888947281015724847561247374580251836813206715558598 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 152867592 ps |
| CPU time | 2.05 seconds |
| Started | Nov 22 12:42:12 PM PST 23 |
| Finished | Nov 22 12:42:20 PM PST 23 |
| Peak memory | 200268 kb |
| Host | smart-c686f1cd-50c9-4db7-bd2b-89b96ddb833b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94646516747481594970811638888947281015724847561247374580251836813206715558598 -assert nopostproc +U VM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 4.uart_tl_errors.94646516747481594970811638888947281015724847561247374580251836813206715558598 |
| Directory | /workspace/4.uart_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.81323426531628891116973979733230404663208595552693391058567784636381939260492 |
| Short name | T1289 |
| Test name | |
| Test status | |
| Simulation time | 136349867 ps |
| CPU time | 1.28 seconds |
| Started | Nov 22 12:42:16 PM PST 23 |
| Finished | Nov 22 12:42:21 PM PST 23 |
| Peak memory | 199404 kb |
| Host | smart-03459f2c-f473-493d-9ff9-2f9943d29c82 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81323426531628891116973979733230404663208595552693391058567784636381939260492 -assert n opostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co ver_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_intg_err.81323426531628891116973979733230404663208595552693391058567784636381939260492 |
| Directory | /workspace/4.uart_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/40.uart_intr_test.71644536498614664185786453241987057718320357104329422369323585880025179452524 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 22779347 ps |
| CPU time | 0.62 seconds |
| Started | Nov 22 12:43:21 PM PST 23 |
| Finished | Nov 22 12:43:25 PM PST 23 |
| Peak memory | 194664 kb |
| Host | smart-dbe4d5b5-e47f-4888-ae23-713111ac666a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71644536498614664185786453241987057718320357104329422369323585880025179452524 -assert nopostproc +U VM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 40.uart_intr_test.71644536498614664185786453241987057718320357104329422369323585880025179452524 |
| Directory | /workspace/40.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/41.uart_intr_test.30666270031182385680270480822076510297633005999919575305621510387323708997497 |
| Short name | T1315 |
| Test name | |
| Test status | |
| Simulation time | 22779347 ps |
| CPU time | 0.59 seconds |
| Started | Nov 22 12:42:53 PM PST 23 |
| Finished | Nov 22 12:42:55 PM PST 23 |
| Peak memory | 194660 kb |
| Host | smart-27c4e333-e309-43fd-ad62-0732340e05c4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30666270031182385680270480822076510297633005999919575305621510387323708997497 -assert nopostproc +U VM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 41.uart_intr_test.30666270031182385680270480822076510297633005999919575305621510387323708997497 |
| Directory | /workspace/41.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/42.uart_intr_test.29404631995624008785020162377224177408921372174974985613726133573129503370205 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 22779347 ps |
| CPU time | 0.58 seconds |
| Started | Nov 22 12:43:10 PM PST 23 |
| Finished | Nov 22 12:43:15 PM PST 23 |
| Peak memory | 194660 kb |
| Host | smart-445cb147-9d96-4dd6-aac3-49c6353400ce |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29404631995624008785020162377224177408921372174974985613726133573129503370205 -assert nopostproc +U VM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 42.uart_intr_test.29404631995624008785020162377224177408921372174974985613726133573129503370205 |
| Directory | /workspace/42.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/43.uart_intr_test.54143080185020221476735684122413470520939149191461322878341464641443310749617 |
| Short name | T1309 |
| Test name | |
| Test status | |
| Simulation time | 22779347 ps |
| CPU time | 0.57 seconds |
| Started | Nov 22 12:42:59 PM PST 23 |
| Finished | Nov 22 12:43:02 PM PST 23 |
| Peak memory | 194628 kb |
| Host | smart-076213e2-b9b3-4d5d-ab0e-62676d776800 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54143080185020221476735684122413470520939149191461322878341464641443310749617 -assert nopostproc +U VM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 43.uart_intr_test.54143080185020221476735684122413470520939149191461322878341464641443310749617 |
| Directory | /workspace/43.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/44.uart_intr_test.24879499152529417210903144153318255241525267554422972410569359098603216439907 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 22779347 ps |
| CPU time | 0.59 seconds |
| Started | Nov 22 12:42:57 PM PST 23 |
| Finished | Nov 22 12:42:58 PM PST 23 |
| Peak memory | 194660 kb |
| Host | smart-f161ed5f-1882-4ef9-82aa-2a8804eb8857 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24879499152529417210903144153318255241525267554422972410569359098603216439907 -assert nopostproc +U VM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 44.uart_intr_test.24879499152529417210903144153318255241525267554422972410569359098603216439907 |
| Directory | /workspace/44.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/45.uart_intr_test.31545417032512556466905797430285876076235404728760292543980667014681146530873 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 22779347 ps |
| CPU time | 0.63 seconds |
| Started | Nov 22 12:43:09 PM PST 23 |
| Finished | Nov 22 12:43:15 PM PST 23 |
| Peak memory | 194676 kb |
| Host | smart-7c058c4b-c79c-4e17-a37b-4164d8054b4a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31545417032512556466905797430285876076235404728760292543980667014681146530873 -assert nopostproc +U VM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 45.uart_intr_test.31545417032512556466905797430285876076235404728760292543980667014681146530873 |
| Directory | /workspace/45.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/46.uart_intr_test.78416313121734751438581367261122597072505596067874064732436182936687877873099 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 22779347 ps |
| CPU time | 0.56 seconds |
| Started | Nov 22 12:43:07 PM PST 23 |
| Finished | Nov 22 12:43:14 PM PST 23 |
| Peak memory | 194660 kb |
| Host | smart-6fadc0e8-c909-4729-a9b7-cc337faed9a0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78416313121734751438581367261122597072505596067874064732436182936687877873099 -assert nopostproc +U VM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 46.uart_intr_test.78416313121734751438581367261122597072505596067874064732436182936687877873099 |
| Directory | /workspace/46.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/47.uart_intr_test.105586274750536706048700785560823182538205175195721944218912532526995352864033 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 22779347 ps |
| CPU time | 0.57 seconds |
| Started | Nov 22 12:42:54 PM PST 23 |
| Finished | Nov 22 12:42:56 PM PST 23 |
| Peak memory | 194624 kb |
| Host | smart-ec5c555f-717d-4cf5-b898-be449210137c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105586274750536706048700785560823182538205175195721944218912532526995352864033 -assert nopostproc + UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 47.uart_intr_test.105586274750536706048700785560823182538205175195721944218912532526995352864033 |
| Directory | /workspace/47.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/48.uart_intr_test.12575939479945300753996012812963545289433133364820333781533205571286303303097 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 22779347 ps |
| CPU time | 0.57 seconds |
| Started | Nov 22 12:43:24 PM PST 23 |
| Finished | Nov 22 12:43:29 PM PST 23 |
| Peak memory | 194600 kb |
| Host | smart-842bf8a5-d978-47cc-9afb-e5e38f151e65 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12575939479945300753996012812963545289433133364820333781533205571286303303097 -assert nopostproc +U VM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 48.uart_intr_test.12575939479945300753996012812963545289433133364820333781533205571286303303097 |
| Directory | /workspace/48.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/49.uart_intr_test.46068791932167059916734005491569598584449397779287645498360505087464736343388 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 22779347 ps |
| CPU time | 0.59 seconds |
| Started | Nov 22 12:43:08 PM PST 23 |
| Finished | Nov 22 12:43:14 PM PST 23 |
| Peak memory | 194636 kb |
| Host | smart-8aada30b-730c-416e-9f98-20dab8d61104 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46068791932167059916734005491569598584449397779287645498360505087464736343388 -assert nopostproc +U VM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 49.uart_intr_test.46068791932167059916734005491569598584449397779287645498360505087464736343388 |
| Directory | /workspace/49.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.15842128103830742155182701472911772993089655847164319597753135231801169823800 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 38332794 ps |
| CPU time | 0.79 seconds |
| Started | Nov 22 12:42:38 PM PST 23 |
| Finished | Nov 22 12:42:41 PM PST 23 |
| Peak memory | 200096 kb |
| Host | smart-7b5c3b79-cef1-4763-9475-77ee075c10b9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584212810383074215518270147291177299308965 5847164319597753135231801169823800 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_csr_mem_rw_with_rand_reset.1584212810383074215518270 1472911772993089655847164319597753135231801169823800 |
| Directory | /workspace/5.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/5.uart_csr_rw.73755809887784039028718339843510364195605148460361467780583009516644391487747 |
| Short name | T1276 |
| Test name | |
| Test status | |
| Simulation time | 21815069 ps |
| CPU time | 0.63 seconds |
| Started | Nov 22 12:42:18 PM PST 23 |
| Finished | Nov 22 12:42:21 PM PST 23 |
| Peak memory | 195768 kb |
| Host | smart-44eac2ee-6c2f-47aa-8076-4425a5536f1a |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73755809887784039028718339843510364195605148460361467780583009516644391487747 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t op.vdb -cm_log /dev/null -cm_name 5.uart_csr_rw.73755809887784039028718339843510364195605148460361467780583009516644391487747 |
| Directory | /workspace/5.uart_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/5.uart_intr_test.79163632744105836727695728951164021567746675797411854569158927003630556965132 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 22779347 ps |
| CPU time | 0.68 seconds |
| Started | Nov 22 12:42:28 PM PST 23 |
| Finished | Nov 22 12:42:32 PM PST 23 |
| Peak memory | 194528 kb |
| Host | smart-ccc18b35-cea0-4686-b298-7e29f79bd55a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79163632744105836727695728951164021567746675797411854569158927003630556965132 -assert nopostproc +U VM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 5.uart_intr_test.79163632744105836727695728951164021567746675797411854569158927003630556965132 |
| Directory | /workspace/5.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.14787751774261393750102543611346531053638792024251768502001855083648740689840 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 45029169 ps |
| CPU time | 0.79 seconds |
| Started | Nov 22 12:42:24 PM PST 23 |
| Finished | Nov 22 12:42:27 PM PST 23 |
| Peak memory | 197340 kb |
| Host | smart-73c7621c-5e22-4d04-831c-6733a93fb790 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14787751774261393750102543611346531053638792024251768502001855083648740689840 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_same_csr_outstanding.14787751774261393750102543611346531053638792024251768502001855083648740689840 |
| Directory | /workspace/5.uart_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/5.uart_tl_errors.87634847591438182315234059269686406804678657298036057999310752562730560789538 |
| Short name | T1286 |
| Test name | |
| Test status | |
| Simulation time | 152867592 ps |
| CPU time | 2.01 seconds |
| Started | Nov 22 12:42:18 PM PST 23 |
| Finished | Nov 22 12:42:23 PM PST 23 |
| Peak memory | 200216 kb |
| Host | smart-bae7f85e-d179-4434-9ed1-e6c925878d8b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87634847591438182315234059269686406804678657298036057999310752562730560789538 -assert nopostproc +U VM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 5.uart_tl_errors.87634847591438182315234059269686406804678657298036057999310752562730560789538 |
| Directory | /workspace/5.uart_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/5.uart_tl_intg_err.1141926661353384252393506157142508611441543137261496202084395026917154387324 |
| Short name | T1310 |
| Test name | |
| Test status | |
| Simulation time | 136349867 ps |
| CPU time | 1.29 seconds |
| Started | Nov 22 12:42:14 PM PST 23 |
| Finished | Nov 22 12:42:20 PM PST 23 |
| Peak memory | 199488 kb |
| Host | smart-89ce082e-6b93-48f1-85bc-1f66709e8c50 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141926661353384252393506157142508611441543137261496202084395026917154387324 -assert no postproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov er_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_intg_err.1141926661353384252393506157142508611441543137261496202084395026917154387324 |
| Directory | /workspace/5.uart_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.74613328917405631031038538909575092870811828902800226609961537270678921678836 |
| Short name | T1280 |
| Test name | |
| Test status | |
| Simulation time | 38332794 ps |
| CPU time | 0.86 seconds |
| Started | Nov 22 12:42:28 PM PST 23 |
| Finished | Nov 22 12:42:32 PM PST 23 |
| Peak memory | 200016 kb |
| Host | smart-5092b3cb-f692-479e-8e04-e9f157a47d54 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7461332891740563103103853890957509287081182 8902800226609961537270678921678836 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_csr_mem_rw_with_rand_reset.7461332891740563103103853 8909575092870811828902800226609961537270678921678836 |
| Directory | /workspace/6.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/6.uart_csr_rw.818559030682088338991892449000650092137372245054833148939449069989377710163 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 21815069 ps |
| CPU time | 0.59 seconds |
| Started | Nov 22 12:42:17 PM PST 23 |
| Finished | Nov 22 12:42:21 PM PST 23 |
| Peak memory | 195688 kb |
| Host | smart-7ccd9c6b-3893-4913-984f-ab0623469aef |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818559030682088338991892449000650092137372245054833148939449069989377710163 -assert nopostproc + UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 6.uart_csr_rw.818559030682088338991892449000650092137372245054833148939449069989377710163 |
| Directory | /workspace/6.uart_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/6.uart_intr_test.82042591720651462705036413907087343139938635936159902934876100277238476033430 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 22779347 ps |
| CPU time | 0.55 seconds |
| Started | Nov 22 12:42:16 PM PST 23 |
| Finished | Nov 22 12:42:20 PM PST 23 |
| Peak memory | 194684 kb |
| Host | smart-8d0bcd4b-1f1a-4ce0-9978-0d651d26aa49 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82042591720651462705036413907087343139938635936159902934876100277238476033430 -assert nopostproc +U VM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 6.uart_intr_test.82042591720651462705036413907087343139938635936159902934876100277238476033430 |
| Directory | /workspace/6.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.99766258338743747057737765615563140793052447684329431569547998696297733218874 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 45029169 ps |
| CPU time | 0.77 seconds |
| Started | Nov 22 12:42:29 PM PST 23 |
| Finished | Nov 22 12:42:33 PM PST 23 |
| Peak memory | 197308 kb |
| Host | smart-d1bd5152-1829-4edd-bb0c-e312161e83ed |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99766258338743747057737765615563140793052447684329431569547998696297733218874 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_same_csr_outstanding.99766258338743747057737765615563140793052447684329431569547998696297733218874 |
| Directory | /workspace/6.uart_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/6.uart_tl_errors.27940768373173968986396041128458417182245641019820970367215206360426503479516 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 152867592 ps |
| CPU time | 1.98 seconds |
| Started | Nov 22 12:42:30 PM PST 23 |
| Finished | Nov 22 12:42:35 PM PST 23 |
| Peak memory | 200232 kb |
| Host | smart-01b20fa7-bc01-46db-8ab0-928bd2f04b4d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27940768373173968986396041128458417182245641019820970367215206360426503479516 -assert nopostproc +U VM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 6.uart_tl_errors.27940768373173968986396041128458417182245641019820970367215206360426503479516 |
| Directory | /workspace/6.uart_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.98379709960397847605031945712028092323318123079742209602919891593005408258371 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 136349867 ps |
| CPU time | 1.26 seconds |
| Started | Nov 22 12:42:35 PM PST 23 |
| Finished | Nov 22 12:42:40 PM PST 23 |
| Peak memory | 199488 kb |
| Host | smart-0c79f3bc-11f6-468d-9df8-4042cea69fca |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98379709960397847605031945712028092323318123079742209602919891593005408258371 -assert n opostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co ver_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_intg_err.98379709960397847605031945712028092323318123079742209602919891593005408258371 |
| Directory | /workspace/6.uart_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.4530756219456333796359606710627828005118476362583131608217071637968679688333 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 38332794 ps |
| CPU time | 0.8 seconds |
| Started | Nov 22 12:42:21 PM PST 23 |
| Finished | Nov 22 12:42:24 PM PST 23 |
| Peak memory | 200144 kb |
| Host | smart-69194a73-ef0f-4c56-9b04-1b74c3ce6b40 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4530756219456333796359606710627828005118476 362583131608217071637968679688333 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_csr_mem_rw_with_rand_reset.45307562194563337963596067 10627828005118476362583131608217071637968679688333 |
| Directory | /workspace/7.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/7.uart_csr_rw.62172336214460678160977543954019716272035035762200619780537753766202072426001 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 21815069 ps |
| CPU time | 0.61 seconds |
| Started | Nov 22 12:42:38 PM PST 23 |
| Finished | Nov 22 12:42:46 PM PST 23 |
| Peak memory | 195684 kb |
| Host | smart-ae627cba-f271-48c9-8fa1-3f0f4e83a9ac |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62172336214460678160977543954019716272035035762200619780537753766202072426001 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t op.vdb -cm_log /dev/null -cm_name 7.uart_csr_rw.62172336214460678160977543954019716272035035762200619780537753766202072426001 |
| Directory | /workspace/7.uart_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/7.uart_intr_test.25075259635757127361286970537462913392379336465037405637360520631141731493718 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 22779347 ps |
| CPU time | 0.56 seconds |
| Started | Nov 22 12:42:18 PM PST 23 |
| Finished | Nov 22 12:42:22 PM PST 23 |
| Peak memory | 194620 kb |
| Host | smart-f9d928b2-e48c-4b77-831c-27581606fd0c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25075259635757127361286970537462913392379336465037405637360520631141731493718 -assert nopostproc +U VM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 7.uart_intr_test.25075259635757127361286970537462913392379336465037405637360520631141731493718 |
| Directory | /workspace/7.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.74436473552732270270198948219922220064579561937170704013991855681968716247514 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 45029169 ps |
| CPU time | 0.77 seconds |
| Started | Nov 22 12:42:19 PM PST 23 |
| Finished | Nov 22 12:42:22 PM PST 23 |
| Peak memory | 197100 kb |
| Host | smart-076cc40f-b1eb-47c6-b203-7fcbf80dc3ca |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74436473552732270270198948219922220064579561937170704013991855681968716247514 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_same_csr_outstanding.74436473552732270270198948219922220064579561937170704013991855681968716247514 |
| Directory | /workspace/7.uart_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/7.uart_tl_errors.79824811270297543535672829742638819667467122107336250349874256065227491686921 |
| Short name | T1297 |
| Test name | |
| Test status | |
| Simulation time | 152867592 ps |
| CPU time | 2.1 seconds |
| Started | Nov 22 12:42:08 PM PST 23 |
| Finished | Nov 22 12:42:15 PM PST 23 |
| Peak memory | 200176 kb |
| Host | smart-0941d34e-6178-4764-ac94-a353674590d4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79824811270297543535672829742638819667467122107336250349874256065227491686921 -assert nopostproc +U VM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 7.uart_tl_errors.79824811270297543535672829742638819667467122107336250349874256065227491686921 |
| Directory | /workspace/7.uart_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/7.uart_tl_intg_err.80989707302854593178632948005077577137188580870080383946439626503892862024930 |
| Short name | T1317 |
| Test name | |
| Test status | |
| Simulation time | 136349867 ps |
| CPU time | 1.36 seconds |
| Started | Nov 22 12:42:24 PM PST 23 |
| Finished | Nov 22 12:42:28 PM PST 23 |
| Peak memory | 199384 kb |
| Host | smart-5af93b2b-54b8-45c2-8d53-db7705defd7e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80989707302854593178632948005077577137188580870080383946439626503892862024930 -assert n opostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co ver_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_intg_err.80989707302854593178632948005077577137188580870080383946439626503892862024930 |
| Directory | /workspace/7.uart_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.17301984501843285301303205878876452782291002545588236498203307470548521623345 |
| Short name | T1303 |
| Test name | |
| Test status | |
| Simulation time | 38332794 ps |
| CPU time | 0.86 seconds |
| Started | Nov 22 12:42:07 PM PST 23 |
| Finished | Nov 22 12:42:13 PM PST 23 |
| Peak memory | 200176 kb |
| Host | smart-84b973a3-9421-47f7-be5c-0b3b596d9fbc |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730198450184328530130320587887645278229100 2545588236498203307470548521623345 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_csr_mem_rw_with_rand_reset.1730198450184328530130320 5878876452782291002545588236498203307470548521623345 |
| Directory | /workspace/8.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/8.uart_csr_rw.16755766743410629748711248884548376721277560504763116671606100590885340707793 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 21815069 ps |
| CPU time | 0.59 seconds |
| Started | Nov 22 12:42:16 PM PST 23 |
| Finished | Nov 22 12:42:20 PM PST 23 |
| Peak memory | 195668 kb |
| Host | smart-b3fdbef1-dc92-4c0a-843e-259e5b9eef99 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16755766743410629748711248884548376721277560504763116671606100590885340707793 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t op.vdb -cm_log /dev/null -cm_name 8.uart_csr_rw.16755766743410629748711248884548376721277560504763116671606100590885340707793 |
| Directory | /workspace/8.uart_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/8.uart_intr_test.41785016841503475068524041937711509103783577399770627463382652312146031875126 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 22779347 ps |
| CPU time | 0.62 seconds |
| Started | Nov 22 12:42:20 PM PST 23 |
| Finished | Nov 22 12:42:23 PM PST 23 |
| Peak memory | 194648 kb |
| Host | smart-91b842d8-d56c-4eb6-bae6-fb891651850d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41785016841503475068524041937711509103783577399770627463382652312146031875126 -assert nopostproc +U VM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 8.uart_intr_test.41785016841503475068524041937711509103783577399770627463382652312146031875126 |
| Directory | /workspace/8.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.26658619237432138552954394021495684928305755302461295042382231467868986935650 |
| Short name | T1277 |
| Test name | |
| Test status | |
| Simulation time | 45029169 ps |
| CPU time | 0.75 seconds |
| Started | Nov 22 12:42:27 PM PST 23 |
| Finished | Nov 22 12:42:31 PM PST 23 |
| Peak memory | 197316 kb |
| Host | smart-dc0b0719-8522-415d-9826-de3b6875e62a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26658619237432138552954394021495684928305755302461295042382231467868986935650 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_same_csr_outstanding.26658619237432138552954394021495684928305755302461295042382231467868986935650 |
| Directory | /workspace/8.uart_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/8.uart_tl_errors.3399927240136426830443658391255325846526825206452526148490683651858446952621 |
| Short name | T1292 |
| Test name | |
| Test status | |
| Simulation time | 152867592 ps |
| CPU time | 2.02 seconds |
| Started | Nov 22 12:42:28 PM PST 23 |
| Finished | Nov 22 12:42:34 PM PST 23 |
| Peak memory | 200300 kb |
| Host | smart-2eca69d0-b05f-443f-b429-e5b36b08cdfc |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399927240136426830443658391255325846526825206452526148490683651858446952621 -assert nopostproc +UV M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v db -cm_log /dev/null -cm_name 8.uart_tl_errors.3399927240136426830443658391255325846526825206452526148490683651858446952621 |
| Directory | /workspace/8.uart_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.40924233066444564894043292146604663674316083897715307213177461204218651763317 |
| Short name | T1294 |
| Test name | |
| Test status | |
| Simulation time | 136349867 ps |
| CPU time | 1.37 seconds |
| Started | Nov 22 12:42:21 PM PST 23 |
| Finished | Nov 22 12:42:25 PM PST 23 |
| Peak memory | 199496 kb |
| Host | smart-bb340e4e-7888-4596-bbff-daa3f319b074 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40924233066444564894043292146604663674316083897715307213177461204218651763317 -assert n opostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co ver_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_intg_err.40924233066444564894043292146604663674316083897715307213177461204218651763317 |
| Directory | /workspace/8.uart_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.37913840170326707015434711749448790618247822590100055234151678014128959095525 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 38332794 ps |
| CPU time | 0.86 seconds |
| Started | Nov 22 12:42:29 PM PST 23 |
| Finished | Nov 22 12:42:33 PM PST 23 |
| Peak memory | 200144 kb |
| Host | smart-1b6ed04b-c33a-49fc-aaaa-2a58e13e6512 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791384017032670701543471174944879061824782 2590100055234151678014128959095525 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_csr_mem_rw_with_rand_reset.3791384017032670701543471 1749448790618247822590100055234151678014128959095525 |
| Directory | /workspace/9.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/9.uart_csr_rw.25061695834351088303798787771640160679213360252716447933548574294977293126014 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 21815069 ps |
| CPU time | 0.67 seconds |
| Started | Nov 22 12:42:21 PM PST 23 |
| Finished | Nov 22 12:42:24 PM PST 23 |
| Peak memory | 195660 kb |
| Host | smart-36d8af08-dd0c-420d-a40b-75bba81170b3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25061695834351088303798787771640160679213360252716447933548574294977293126014 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t op.vdb -cm_log /dev/null -cm_name 9.uart_csr_rw.25061695834351088303798787771640160679213360252716447933548574294977293126014 |
| Directory | /workspace/9.uart_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/9.uart_intr_test.74901284929032059923928679258106426889938886480783624414080225908703542797813 |
| Short name | T1308 |
| Test name | |
| Test status | |
| Simulation time | 22779347 ps |
| CPU time | 0.56 seconds |
| Started | Nov 22 12:42:14 PM PST 23 |
| Finished | Nov 22 12:42:19 PM PST 23 |
| Peak memory | 194644 kb |
| Host | smart-73e520c3-2769-434b-946e-818e768bee3e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74901284929032059923928679258106426889938886480783624414080225908703542797813 -assert nopostproc +U VM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 9.uart_intr_test.74901284929032059923928679258106426889938886480783624414080225908703542797813 |
| Directory | /workspace/9.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.96470951906610082371030420218611732560007404641873215130099771536632975771559 |
| Short name | T1296 |
| Test name | |
| Test status | |
| Simulation time | 45029169 ps |
| CPU time | 0.77 seconds |
| Started | Nov 22 12:42:19 PM PST 23 |
| Finished | Nov 22 12:42:22 PM PST 23 |
| Peak memory | 197132 kb |
| Host | smart-2ba30b6f-8548-4210-8603-e053393fdee2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96470951906610082371030420218611732560007404641873215130099771536632975771559 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_same_csr_outstanding.96470951906610082371030420218611732560007404641873215130099771536632975771559 |
| Directory | /workspace/9.uart_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/9.uart_tl_errors.101549862522004837360327241187240103281974448459175701367997050948311979368189 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 152867592 ps |
| CPU time | 2.03 seconds |
| Started | Nov 22 12:42:25 PM PST 23 |
| Finished | Nov 22 12:42:29 PM PST 23 |
| Peak memory | 200172 kb |
| Host | smart-aca3d22e-1ceb-4351-bde2-89c1e4077cf7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101549862522004837360327241187240103281974448459175701367997050948311979368189 -assert nopostproc + UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 9.uart_tl_errors.101549862522004837360327241187240103281974448459175701367997050948311979368189 |
| Directory | /workspace/9.uart_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.111793465792639810566880524015154547115735576201679141301743454671016868796420 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 136349867 ps |
| CPU time | 1.27 seconds |
| Started | Nov 22 12:42:17 PM PST 23 |
| Finished | Nov 22 12:42:21 PM PST 23 |
| Peak memory | 199392 kb |
| Host | smart-07cbd297-db90-49b6-b7f7-4ccf7df7d67f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111793465792639810566880524015154547115735576201679141301743454671016868796420 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/c over_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_intg_err.111793465792639810566880524015154547115735576201679141301743454671016868796420 |
| Directory | /workspace/9.uart_tl_intg_err/latest |
| Test location | /workspace/coverage/default/0.uart_fifo_full.99689240722348214896728975324254371238175725512159524930882508202406493263759 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 61777160308 ps |
| CPU time | 61.74 seconds |
| Started | Nov 22 01:44:08 PM PST 23 |
| Finished | Nov 22 01:45:14 PM PST 23 |
| Peak memory | 200116 kb |
| Host | smart-d35331bb-becf-4464-9de4-85ed20a51275 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=99689240722348214896728975324254371238175725512159524930882508202406493263759 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 0.uart_fifo_full.99689240722348214896728975324254371238175725512159524930882508202406493263759 |
| Directory | /workspace/0.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/0.uart_fifo_overflow.64355793402018192818335571264237201565708103338630811983208782677692442825257 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 58551936110 ps |
| CPU time | 54.72 seconds |
| Started | Nov 22 01:44:02 PM PST 23 |
| Finished | Nov 22 01:45:01 PM PST 23 |
| Peak memory | 199824 kb |
| Host | smart-14eeb60f-b6ae-4216-979f-660ed2e31f58 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=64355793402018192818335571264237201565708103338630811983208782677692442825257 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 0.uart_fifo_overflow.64355793402018192818335571264237201565708103338630811983208782677692442825257 |
| Directory | /workspace/0.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/0.uart_fifo_reset.69407234899778899660859941829571540738967332002425017128560594164018446309066 |
| Short name | T1227 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 112.11 seconds |
| Started | Nov 22 01:44:00 PM PST 23 |
| Finished | Nov 22 01:45:56 PM PST 23 |
| Peak memory | 198884 kb |
| Host | smart-8a46eb80-cb40-4c0d-b5b2-08ae5094d3d4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=69407234899778899660859941829571540738967332002425017128560594164018446309066 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 0.uart_fifo_reset.69407234899778899660859941829571540738967332002425017128560594164018446309066 |
| Directory | /workspace/0.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/0.uart_intr.73117428264386335062081238782274324102974725263298920011366800957573997758103 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 787145125175 ps |
| CPU time | 785.68 seconds |
| Started | Nov 22 01:44:02 PM PST 23 |
| Finished | Nov 22 01:57:12 PM PST 23 |
| Peak memory | 200120 kb |
| Host | smart-135459c4-7a77-43d5-80cc-d7a923f53c8a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73117428264386335062081238782274324102974725263298920011366800957573997758103 -assert nopost proc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 0.uart_intr.73117428264386335062081238782274324102974725263298920011366800957573997758103 |
| Directory | /workspace/0.uart_intr/latest |
| Test location | /workspace/coverage/default/0.uart_long_xfer_wo_dly.11070736528831444404231063393994109390315285703501868479860699612746168211720 |
| Short name | T755 |
| Test name | |
| Test status | |
| Simulation time | 93387746707 ps |
| CPU time | 354.23 seconds |
| Started | Nov 22 01:44:06 PM PST 23 |
| Finished | Nov 22 01:50:06 PM PST 23 |
| Peak memory | 200116 kb |
| Host | smart-a09bad70-8bbb-4ca2-8946-e394cc4d76c0 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=11070736528831444404231063393994109390315285703501868479860699612746168211720 -assert nopostproc +UVM_TES TNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 0.uart_long_xfer_wo_dly.11070736528831444404231063393994109390315285703501868479860699612746168211720 |
| Directory | /workspace/0.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/0.uart_loopback.15475566623182532423785753809728849067932731276672614619499810214560804041122 |
| Short name | T673 |
| Test name | |
| Test status | |
| Simulation time | 14572448663 ps |
| CPU time | 15.98 seconds |
| Started | Nov 22 01:44:07 PM PST 23 |
| Finished | Nov 22 01:44:28 PM PST 23 |
| Peak memory | 199960 kb |
| Host | smart-af998ab8-43f9-40c4-902d-d920c4408232 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=15475566623182532423785753809728849067932731276672614619499810214560804041122 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 0.uart_loopback.15475566623182532423785753809728849067932731276672614619499810214560804041122 |
| Directory | /workspace/0.uart_loopback/latest |
| Test location | /workspace/coverage/default/0.uart_noise_filter.54603794891981235159806334641617748430317681162096301724576642237221512110038 |
| Short name | T795 |
| Test name | |
| Test status | |
| Simulation time | 94501577082 ps |
| CPU time | 96.8 seconds |
| Started | Nov 22 01:44:00 PM PST 23 |
| Finished | Nov 22 01:45:40 PM PST 23 |
| Peak memory | 200264 kb |
| Host | smart-c7476a70-e942-46ba-a638-35067f59142d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=54603794891981235159806334641617748430317681162096301724576642237221512110038 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_noise_filter.54603794891981235159806334641617748430317681162096301724576642237221512110038 |
| Directory | /workspace/0.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/0.uart_perf.770265610183493330746264871116479133628456852224758384011024796863686883697 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 14098773881 ps |
| CPU time | 463.74 seconds |
| Started | Nov 22 01:43:58 PM PST 23 |
| Finished | Nov 22 01:51:46 PM PST 23 |
| Peak memory | 200084 kb |
| Host | smart-9c98872d-6b20-4d3f-a932-bf13408a9e04 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=770265610183493330746264871116479133628456852224758384011024796863686883697 -assert nopostproc +UVM_TESTN AME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.uart_perf.770265610183493330746264871116479133628456852224758384011024796863686883697 |
| Directory | /workspace/0.uart_perf/latest |
| Test location | /workspace/coverage/default/0.uart_rx_oversample.19141218240357095966534226858294434375732195620777527561059195380955762749498 |
| Short name | T1047 |
| Test name | |
| Test status | |
| Simulation time | 4370280281 ps |
| CPU time | 19.9 seconds |
| Started | Nov 22 01:43:53 PM PST 23 |
| Finished | Nov 22 01:44:16 PM PST 23 |
| Peak memory | 198948 kb |
| Host | smart-04586546-86f7-4d0d-87a4-9d268d1e2e92 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=19141218240357095966534226858294434375732195620777527561059195380955762749498 -assert nopostproc +UVM_TES TNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 0.uart_rx_oversample.19141218240357095966534226858294434375732195620777527561059195380955762749498 |
| Directory | /workspace/0.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/0.uart_rx_parity_err.35873628211942710583364796824313955391248785411040178998910938094154444708615 |
| Short name | T960 |
| Test name | |
| Test status | |
| Simulation time | 36616611594 ps |
| CPU time | 37.81 seconds |
| Started | Nov 22 01:44:03 PM PST 23 |
| Finished | Nov 22 01:44:45 PM PST 23 |
| Peak memory | 200056 kb |
| Host | smart-00b5c9f8-8509-4302-803b-5649106e00d1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=35873628211942710583364796824313955391248785411040178998910938094154444708615 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 0.uart_rx_parity_err.35873628211942710583364796824313955391248785411040178998910938094154444708615 |
| Directory | /workspace/0.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/0.uart_rx_start_bit_filter.32681711387234377704268219200753041577002886885261237638894609739742550043837 |
| Short name | T804 |
| Test name | |
| Test status | |
| Simulation time | 4267638245 ps |
| CPU time | 4.78 seconds |
| Started | Nov 22 01:44:02 PM PST 23 |
| Finished | Nov 22 01:44:11 PM PST 23 |
| Peak memory | 195832 kb |
| Host | smart-f24c8d36-484c-4918-ac22-f7a1d56c2d5f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=32681711387234377704268219200753041577002886885261237638894609739742550043837 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 0.uart_rx_start_bit_filter.32681711387234377704268219200753041577002886885261237638894609739742550043837 |
| Directory | /workspace/0.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/0.uart_smoke.85653875712160463976016222127645905271739412827619644975234404532630340576682 |
| Short name | T930 |
| Test name | |
| Test status | |
| Simulation time | 5759626309 ps |
| CPU time | 18.17 seconds |
| Started | Nov 22 01:43:56 PM PST 23 |
| Finished | Nov 22 01:44:18 PM PST 23 |
| Peak memory | 199596 kb |
| Host | smart-b84861e6-1132-40c3-b2c4-4f6c3d5e5903 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=85653875712160463976016222127645905271739412827619644975234404532630340576682 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 0.uart_smoke.85653875712160463976016222127645905271739412827619644975234404532630340576682 |
| Directory | /workspace/0.uart_smoke/latest |
| Test location | /workspace/coverage/default/0.uart_stress_all.40997633430022035324665620189648376569402354584950197180065583775596858298907 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 43402307308 ps |
| CPU time | 56.81 seconds |
| Started | Nov 22 01:44:06 PM PST 23 |
| Finished | Nov 22 01:45:08 PM PST 23 |
| Peak memory | 200064 kb |
| Host | smart-77dc6707-bbe4-4f01-a622-7e8f975cd5b2 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40997633430022035324665620189648376569402354584950197180065583775596858298907 -assert nopos tproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.uart_stress_all.40997633430022035324665620189648376569402354584950197180065583775596858298907 |
| Directory | /workspace/0.uart_stress_all/latest |
| Test location | /workspace/coverage/default/0.uart_stress_all_with_rand_reset.40372352569008071605823377829152582621954444476239733460071085500522386235756 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 87476847566 ps |
| CPU time | 441.16 seconds |
| Started | Nov 22 01:44:01 PM PST 23 |
| Finished | Nov 22 01:51:26 PM PST 23 |
| Peak memory | 226004 kb |
| Host | smart-978c2c84-3a1a-41a6-b365-d8930e1a3e40 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40372352569008071605823377 829152582621954444476239733460071085500522386235756 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_stress_all_with_rand_reset.40372352569008 071605823377829152582621954444476239733460071085500522386235756 |
| Directory | /workspace/0.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/0.uart_tx_ovrd.65703379221885475191947526745733170889614200120259251664393186235719000778073 |
| Short name | T1079 |
| Test name | |
| Test status | |
| Simulation time | 485186362 ps |
| CPU time | 1.27 seconds |
| Started | Nov 22 01:43:57 PM PST 23 |
| Finished | Nov 22 01:44:02 PM PST 23 |
| Peak memory | 197904 kb |
| Host | smart-6c1291fe-c19c-4fbc-ab67-01f81a04d48f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=65703379221885475191947526745733170889614200120259251664393186235719000778073 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 0.uart_tx_ovrd.65703379221885475191947526745733170889614200120259251664393186235719000778073 |
| Directory | /workspace/0.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/0.uart_tx_rx.84146197977514420982239860092006992057001050023953588938861493928382764821026 |
| Short name | T1143 |
| Test name | |
| Test status | |
| Simulation time | 57391945390 ps |
| CPU time | 64.57 seconds |
| Started | Nov 22 01:43:53 PM PST 23 |
| Finished | Nov 22 01:45:01 PM PST 23 |
| Peak memory | 200108 kb |
| Host | smart-0d27fa0b-226b-4b51-9304-25645706b7f0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=84146197977514420982239860092006992057001050023953588938861493928382764821026 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 0.uart_tx_rx.84146197977514420982239860092006992057001050023953588938861493928382764821026 |
| Directory | /workspace/0.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/1.uart_alert_test.13833713920385788263902281950515630438047074139385737003851521926621537811999 |
| Short name | T680 |
| Test name | |
| Test status | |
| Simulation time | 16368684 ps |
| CPU time | 0.55 seconds |
| Started | Nov 22 01:44:01 PM PST 23 |
| Finished | Nov 22 01:44:06 PM PST 23 |
| Peak memory | 194608 kb |
| Host | smart-5fd75f10-a3ed-427a-a267-7a2dc7c4888b |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13833713920385788263902281950515630438047074139385737003851521926621537811999 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 1.uart_alert_test.13833713920385788263902281950515630438047074139385737003851521926621537811999 |
| Directory | /workspace/1.uart_alert_test/latest |
| Test location | /workspace/coverage/default/1.uart_fifo_full.17320525544481768302205334420992907650410337194322835920851498388514467566799 |
| Short name | T1232 |
| Test name | |
| Test status | |
| Simulation time | 61777160308 ps |
| CPU time | 61.16 seconds |
| Started | Nov 22 01:44:00 PM PST 23 |
| Finished | Nov 22 01:45:05 PM PST 23 |
| Peak memory | 200112 kb |
| Host | smart-7526aade-c0a0-4369-9f0e-d42f4954b011 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=17320525544481768302205334420992907650410337194322835920851498388514467566799 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 1.uart_fifo_full.17320525544481768302205334420992907650410337194322835920851498388514467566799 |
| Directory | /workspace/1.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/1.uart_fifo_overflow.60048164453511523765147626488252275101218836002957205781971794645644129285752 |
| Short name | T1119 |
| Test name | |
| Test status | |
| Simulation time | 58551936110 ps |
| CPU time | 54.12 seconds |
| Started | Nov 22 01:44:08 PM PST 23 |
| Finished | Nov 22 01:45:07 PM PST 23 |
| Peak memory | 199616 kb |
| Host | smart-96e9b1a6-5c5c-4e85-a117-82e3fa3af689 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=60048164453511523765147626488252275101218836002957205781971794645644129285752 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 1.uart_fifo_overflow.60048164453511523765147626488252275101218836002957205781971794645644129285752 |
| Directory | /workspace/1.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/1.uart_fifo_reset.93886249143767914872103979909486898829528554836865762633780193630841279014847 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 113.8 seconds |
| Started | Nov 22 01:44:07 PM PST 23 |
| Finished | Nov 22 01:46:06 PM PST 23 |
| Peak memory | 198924 kb |
| Host | smart-55058446-ba6b-40f3-a41d-cf2b2044f120 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=93886249143767914872103979909486898829528554836865762633780193630841279014847 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 1.uart_fifo_reset.93886249143767914872103979909486898829528554836865762633780193630841279014847 |
| Directory | /workspace/1.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/1.uart_intr.13841245657160013601364065472088227033098913318598210184199540987980797492876 |
| Short name | T1162 |
| Test name | |
| Test status | |
| Simulation time | 787145125175 ps |
| CPU time | 783 seconds |
| Started | Nov 22 01:44:06 PM PST 23 |
| Finished | Nov 22 01:57:14 PM PST 23 |
| Peak memory | 200000 kb |
| Host | smart-9371738a-aaf5-42e3-8cd6-a75c5ae15e8b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13841245657160013601364065472088227033098913318598210184199540987980797492876 -assert nopost proc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 1.uart_intr.13841245657160013601364065472088227033098913318598210184199540987980797492876 |
| Directory | /workspace/1.uart_intr/latest |
| Test location | /workspace/coverage/default/1.uart_long_xfer_wo_dly.101527861621883300324282075174879963446901225404897648912723738068968918994220 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 93387746707 ps |
| CPU time | 351.57 seconds |
| Started | Nov 22 01:43:41 PM PST 23 |
| Finished | Nov 22 01:49:34 PM PST 23 |
| Peak memory | 200116 kb |
| Host | smart-0e1ce845-efaf-4fad-aa2f-a13cbc315dba |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=101527861621883300324282075174879963446901225404897648912723738068968918994220 -assert nopostproc +UVM_TE STNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 1.uart_long_xfer_wo_dly.101527861621883300324282075174879963446901225404897648912723738068968918994220 |
| Directory | /workspace/1.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/1.uart_loopback.84812064765394092394263319074339137723164448804380966464480815101715802592146 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 14572448663 ps |
| CPU time | 16.05 seconds |
| Started | Nov 22 01:44:14 PM PST 23 |
| Finished | Nov 22 01:44:34 PM PST 23 |
| Peak memory | 199864 kb |
| Host | smart-3fd8c0ab-dd35-4211-8594-29c0586c78ff |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=84812064765394092394263319074339137723164448804380966464480815101715802592146 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 1.uart_loopback.84812064765394092394263319074339137723164448804380966464480815101715802592146 |
| Directory | /workspace/1.uart_loopback/latest |
| Test location | /workspace/coverage/default/1.uart_noise_filter.97797560583124158594434196532497270231448960925272069940092871410312287619133 |
| Short name | T1066 |
| Test name | |
| Test status | |
| Simulation time | 94501577082 ps |
| CPU time | 96.51 seconds |
| Started | Nov 22 01:44:13 PM PST 23 |
| Finished | Nov 22 01:45:53 PM PST 23 |
| Peak memory | 200088 kb |
| Host | smart-c17784bb-0841-4842-b64b-c602b01e5cf2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=97797560583124158594434196532497270231448960925272069940092871410312287619133 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_noise_filter.97797560583124158594434196532497270231448960925272069940092871410312287619133 |
| Directory | /workspace/1.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/1.uart_perf.105405724933231244423820248665292536405982044639137141858059463492598488522173 |
| Short name | T781 |
| Test name | |
| Test status | |
| Simulation time | 14098773881 ps |
| CPU time | 464.77 seconds |
| Started | Nov 22 01:43:54 PM PST 23 |
| Finished | Nov 22 01:51:42 PM PST 23 |
| Peak memory | 200056 kb |
| Host | smart-bb0f1ee4-fd4c-4f8c-b260-1e03ee530e21 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=105405724933231244423820248665292536405982044639137141858059463492598488522173 -assert nopostproc +UVM_TE STNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 1.uart_perf.105405724933231244423820248665292536405982044639137141858059463492598488522173 |
| Directory | /workspace/1.uart_perf/latest |
| Test location | /workspace/coverage/default/1.uart_rx_oversample.45701860456476888536954245168028031407334460893158863383972120362196281826013 |
| Short name | T1182 |
| Test name | |
| Test status | |
| Simulation time | 4370280281 ps |
| CPU time | 19.99 seconds |
| Started | Nov 22 01:43:59 PM PST 23 |
| Finished | Nov 22 01:44:22 PM PST 23 |
| Peak memory | 198952 kb |
| Host | smart-3200492a-61cd-4cd9-9701-3d9b9807b3b8 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=45701860456476888536954245168028031407334460893158863383972120362196281826013 -assert nopostproc +UVM_TES TNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 1.uart_rx_oversample.45701860456476888536954245168028031407334460893158863383972120362196281826013 |
| Directory | /workspace/1.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/1.uart_rx_parity_err.49701260600999911179584060044760313884436864086864904305320451586236774644103 |
| Short name | T1202 |
| Test name | |
| Test status | |
| Simulation time | 36616611594 ps |
| CPU time | 38.31 seconds |
| Started | Nov 22 01:44:25 PM PST 23 |
| Finished | Nov 22 01:45:08 PM PST 23 |
| Peak memory | 199920 kb |
| Host | smart-fe2cd149-b7b6-4c05-b644-e734d8bfe8e6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=49701260600999911179584060044760313884436864086864904305320451586236774644103 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 1.uart_rx_parity_err.49701260600999911179584060044760313884436864086864904305320451586236774644103 |
| Directory | /workspace/1.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/1.uart_rx_start_bit_filter.88701015047078324508675335457317678212602851217558895676014186664105065196091 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 4267638245 ps |
| CPU time | 4.71 seconds |
| Started | Nov 22 01:44:07 PM PST 23 |
| Finished | Nov 22 01:44:17 PM PST 23 |
| Peak memory | 195920 kb |
| Host | smart-0d79aaa4-f69b-4d55-aca0-333577217835 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=88701015047078324508675335457317678212602851217558895676014186664105065196091 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 1.uart_rx_start_bit_filter.88701015047078324508675335457317678212602851217558895676014186664105065196091 |
| Directory | /workspace/1.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/1.uart_sec_cm.38789574233919604061651934219182087742100309257764096346965726885820578100770 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 100582296 ps |
| CPU time | 0.84 seconds |
| Started | Nov 22 01:43:47 PM PST 23 |
| Finished | Nov 22 01:43:49 PM PST 23 |
| Peak memory | 218368 kb |
| Host | smart-56aa9021-5fb6-4638-9a2e-ab15491440c1 |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38789574233919604061651934219182087742100309257764096346965726885820578100770 -assert nopostpro c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 1.uart_sec_cm.38789574233919604061651934219182087742100309257764096346965726885820578100770 |
| Directory | /workspace/1.uart_sec_cm/latest |
| Test location | /workspace/coverage/default/1.uart_stress_all.50161491045092673201530047426885191765859833865004042745070916767552735946190 |
| Short name | T1155 |
| Test name | |
| Test status | |
| Simulation time | 43402307308 ps |
| CPU time | 56.65 seconds |
| Started | Nov 22 01:43:58 PM PST 23 |
| Finished | Nov 22 01:44:59 PM PST 23 |
| Peak memory | 200108 kb |
| Host | smart-7cd2a0dd-910e-4960-96d6-02f9e82a03c4 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50161491045092673201530047426885191765859833865004042745070916767552735946190 -assert nopos tproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 1.uart_stress_all.50161491045092673201530047426885191765859833865004042745070916767552735946190 |
| Directory | /workspace/1.uart_stress_all/latest |
| Test location | /workspace/coverage/default/1.uart_stress_all_with_rand_reset.66580527098090611493168798570764826745637462137492196660671727567513569989191 |
| Short name | T995 |
| Test name | |
| Test status | |
| Simulation time | 87476847566 ps |
| CPU time | 471.07 seconds |
| Started | Nov 22 01:43:48 PM PST 23 |
| Finished | Nov 22 01:51:42 PM PST 23 |
| Peak memory | 226128 kb |
| Host | smart-ca1781f7-00c1-4b1a-9394-b4a9ee5b5f5a |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66580527098090611493168798 570764826745637462137492196660671727567513569989191 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_stress_all_with_rand_reset.66580527098090 611493168798570764826745637462137492196660671727567513569989191 |
| Directory | /workspace/1.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/1.uart_tx_ovrd.9345059603217776328278209627913585421915132192029589892556358790557281735200 |
| Short name | T1105 |
| Test name | |
| Test status | |
| Simulation time | 485186362 ps |
| CPU time | 1.22 seconds |
| Started | Nov 22 01:44:07 PM PST 23 |
| Finished | Nov 22 01:44:13 PM PST 23 |
| Peak memory | 197972 kb |
| Host | smart-2e25f0a5-f030-44e6-9fa0-0248097efda5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=9345059603217776328278209627913585421915132192029589892556358790557281735200 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 1.uart_tx_ovrd.9345059603217776328278209627913585421915132192029589892556358790557281735200 |
| Directory | /workspace/1.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/1.uart_tx_rx.22249176927442570364868142676877690790434957210115386200125471781160154189996 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 57391945390 ps |
| CPU time | 63.15 seconds |
| Started | Nov 22 01:44:08 PM PST 23 |
| Finished | Nov 22 01:45:16 PM PST 23 |
| Peak memory | 200096 kb |
| Host | smart-b20cdac5-584d-479b-b97e-2f243322f89d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=22249176927442570364868142676877690790434957210115386200125471781160154189996 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 1.uart_tx_rx.22249176927442570364868142676877690790434957210115386200125471781160154189996 |
| Directory | /workspace/1.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/10.uart_alert_test.16110826062940087035373030706242960196148550734538797526851710862813592726135 |
| Short name | T1153 |
| Test name | |
| Test status | |
| Simulation time | 16368684 ps |
| CPU time | 0.56 seconds |
| Started | Nov 22 01:44:04 PM PST 23 |
| Finished | Nov 22 01:44:09 PM PST 23 |
| Peak memory | 194620 kb |
| Host | smart-77850ade-0a54-4af0-a1fa-f15576845ef6 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16110826062940087035373030706242960196148550734538797526851710862813592726135 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 10.uart_alert_test.16110826062940087035373030706242960196148550734538797526851710862813592726135 |
| Directory | /workspace/10.uart_alert_test/latest |
| Test location | /workspace/coverage/default/10.uart_fifo_full.85515137698493709469898717812165114843798741187228116389362260389422843578139 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 61777160308 ps |
| CPU time | 60.97 seconds |
| Started | Nov 22 01:44:10 PM PST 23 |
| Finished | Nov 22 01:45:15 PM PST 23 |
| Peak memory | 200100 kb |
| Host | smart-24e51441-2aa7-48fb-8aaa-c8c2b26f6caa |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=85515137698493709469898717812165114843798741187228116389362260389422843578139 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 10.uart_fifo_full.85515137698493709469898717812165114843798741187228116389362260389422843578139 |
| Directory | /workspace/10.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/10.uart_fifo_overflow.53496921991257931117893398130497594149203086122289286090067841303698582918114 |
| Short name | T1118 |
| Test name | |
| Test status | |
| Simulation time | 58551936110 ps |
| CPU time | 54.57 seconds |
| Started | Nov 22 01:43:57 PM PST 23 |
| Finished | Nov 22 01:44:56 PM PST 23 |
| Peak memory | 199616 kb |
| Host | smart-ef7d4bae-de1a-4c48-a65e-ae059fd01650 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=53496921991257931117893398130497594149203086122289286090067841303698582918114 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 10.uart_fifo_overflow.53496921991257931117893398130497594149203086122289286090067841303698582918114 |
| Directory | /workspace/10.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/10.uart_fifo_reset.115363085688498185378048026107644718633428798369284913482594901762007577681507 |
| Short name | T1113 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 114.13 seconds |
| Started | Nov 22 01:44:07 PM PST 23 |
| Finished | Nov 22 01:46:06 PM PST 23 |
| Peak memory | 198816 kb |
| Host | smart-b9c980fc-f26b-407c-a946-bf0dd904631b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=115363085688498185378048026107644718633428798369284913482594901762007577681507 -assert nopostproc +UVM_TESTNAME=uart_bas e_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_reset.115363085688498185378048026107644718633428798369284913482594901762007577681507 |
| Directory | /workspace/10.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/10.uart_intr.99118614832990962357892524293599383460693533573117122329251084664892344323761 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 787145125175 ps |
| CPU time | 787.66 seconds |
| Started | Nov 22 01:43:56 PM PST 23 |
| Finished | Nov 22 01:57:07 PM PST 23 |
| Peak memory | 200040 kb |
| Host | smart-9e4653f8-c81d-4efe-aadd-ec836bdd10df |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99118614832990962357892524293599383460693533573117122329251084664892344323761 -assert nopost proc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 10.uart_intr.99118614832990962357892524293599383460693533573117122329251084664892344323761 |
| Directory | /workspace/10.uart_intr/latest |
| Test location | /workspace/coverage/default/10.uart_long_xfer_wo_dly.62102032552620659627999103254824122694233188257192077285447512299271799261458 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 93387746707 ps |
| CPU time | 350.34 seconds |
| Started | Nov 22 01:43:59 PM PST 23 |
| Finished | Nov 22 01:49:53 PM PST 23 |
| Peak memory | 200020 kb |
| Host | smart-07dfd0b7-e526-45d6-93bd-ae2b38d4510c |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=62102032552620659627999103254824122694233188257192077285447512299271799261458 -assert nopostproc +UVM_TES TNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 10.uart_long_xfer_wo_dly.62102032552620659627999103254824122694233188257192077285447512299271799261458 |
| Directory | /workspace/10.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/10.uart_loopback.68451671259415289751887107404500543719770697131086428988780229463964548998858 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 14572448663 ps |
| CPU time | 16.05 seconds |
| Started | Nov 22 01:44:24 PM PST 23 |
| Finished | Nov 22 01:44:46 PM PST 23 |
| Peak memory | 199956 kb |
| Host | smart-d78a8910-2fe3-4230-b807-cc884c772419 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=68451671259415289751887107404500543719770697131086428988780229463964548998858 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 10.uart_loopback.68451671259415289751887107404500543719770697131086428988780229463964548998858 |
| Directory | /workspace/10.uart_loopback/latest |
| Test location | /workspace/coverage/default/10.uart_noise_filter.55370186834257250516912877424628297604370424334438718153854471281261060643346 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 94501577082 ps |
| CPU time | 96.72 seconds |
| Started | Nov 22 01:44:02 PM PST 23 |
| Finished | Nov 22 01:45:43 PM PST 23 |
| Peak memory | 200180 kb |
| Host | smart-58029251-7f80-4da0-bf77-2a23d375dff0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=55370186834257250516912877424628297604370424334438718153854471281261060643346 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_noise_filter.55370186834257250516912877424628297604370424334438718153854471281261060643346 |
| Directory | /workspace/10.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/10.uart_perf.48873482181788304735331747029323086473380121353757003207430436214173250045867 |
| Short name | T1073 |
| Test name | |
| Test status | |
| Simulation time | 14098773881 ps |
| CPU time | 462.67 seconds |
| Started | Nov 22 01:44:10 PM PST 23 |
| Finished | Nov 22 01:51:56 PM PST 23 |
| Peak memory | 200000 kb |
| Host | smart-b0b9ce63-397c-40ac-b1b5-5f817b6895df |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=48873482181788304735331747029323086473380121353757003207430436214173250045867 -assert nopostproc +UVM_TES TNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 10.uart_perf.48873482181788304735331747029323086473380121353757003207430436214173250045867 |
| Directory | /workspace/10.uart_perf/latest |
| Test location | /workspace/coverage/default/10.uart_rx_oversample.41198485270008856139401321869122711132848790690909868153614079509481203446122 |
| Short name | T855 |
| Test name | |
| Test status | |
| Simulation time | 4370280281 ps |
| CPU time | 20.42 seconds |
| Started | Nov 22 01:44:10 PM PST 23 |
| Finished | Nov 22 01:44:34 PM PST 23 |
| Peak memory | 198980 kb |
| Host | smart-35b2676f-1cfc-4ad9-b8e8-1c56c3d8097e |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=41198485270008856139401321869122711132848790690909868153614079509481203446122 -assert nopostproc +UVM_TES TNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 10.uart_rx_oversample.41198485270008856139401321869122711132848790690909868153614079509481203446122 |
| Directory | /workspace/10.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/10.uart_rx_parity_err.108833783326945394819002388130901491893392096840578232547766626043438550482381 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 36616611594 ps |
| CPU time | 37.95 seconds |
| Started | Nov 22 01:44:13 PM PST 23 |
| Finished | Nov 22 01:44:55 PM PST 23 |
| Peak memory | 200112 kb |
| Host | smart-2a1488d1-1d40-4b70-ae13-f8a01d9046a8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=108833783326945394819002388130901491893392096840578232547766626043438550482381 -assert nopostproc +UVM_TESTNAME=uart_bas e_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 10.uart_rx_parity_err.108833783326945394819002388130901491893392096840578232547766626043438550482381 |
| Directory | /workspace/10.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/10.uart_smoke.66324771803887278241609034182965640645813063656715776903343887994103488983067 |
| Short name | T846 |
| Test name | |
| Test status | |
| Simulation time | 5759626309 ps |
| CPU time | 18.34 seconds |
| Started | Nov 22 01:44:05 PM PST 23 |
| Finished | Nov 22 01:44:29 PM PST 23 |
| Peak memory | 199540 kb |
| Host | smart-51bb61ac-1959-438c-a2ac-a08c7ce3a605 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=66324771803887278241609034182965640645813063656715776903343887994103488983067 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 10.uart_smoke.66324771803887278241609034182965640645813063656715776903343887994103488983067 |
| Directory | /workspace/10.uart_smoke/latest |
| Test location | /workspace/coverage/default/10.uart_stress_all_with_rand_reset.7332191632703675579165422996562705556043185817127842131108410302746523561113 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 87476847566 ps |
| CPU time | 463.64 seconds |
| Started | Nov 22 01:44:27 PM PST 23 |
| Finished | Nov 22 01:52:14 PM PST 23 |
| Peak memory | 226116 kb |
| Host | smart-9183baaf-4aeb-4b82-9f89-d7f047136542 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73321916327036755791654229 96562705556043185817127842131108410302746523561113 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_stress_all_with_rand_reset.73321916327036 75579165422996562705556043185817127842131108410302746523561113 |
| Directory | /workspace/10.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/10.uart_tx_rx.78086054227663054759020197622519817864202283801670573074634638155113886393600 |
| Short name | T985 |
| Test name | |
| Test status | |
| Simulation time | 57391945390 ps |
| CPU time | 63.01 seconds |
| Started | Nov 22 01:43:59 PM PST 23 |
| Finished | Nov 22 01:45:05 PM PST 23 |
| Peak memory | 200080 kb |
| Host | smart-76761356-7f8e-43b5-906b-f55848dae6c9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=78086054227663054759020197622519817864202283801670573074634638155113886393600 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 10.uart_tx_rx.78086054227663054759020197622519817864202283801670573074634638155113886393600 |
| Directory | /workspace/10.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/100.uart_fifo_reset.78774692646438910850898731555116231095985552647953924077809344799685612828871 |
| Short name | T1197 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 113.93 seconds |
| Started | Nov 22 01:46:08 PM PST 23 |
| Finished | Nov 22 01:48:07 PM PST 23 |
| Peak memory | 198836 kb |
| Host | smart-f2d72c80-3f5c-42b9-86b1-19a0db264f74 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=78774692646438910850898731555116231095985552647953924077809344799685612828871 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 100.uart_fifo_reset.78774692646438910850898731555116231095985552647953924077809344799685612828871 |
| Directory | /workspace/100.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/101.uart_fifo_reset.11394723600603897328529554177630066199199255382257403930455349139295859064355 |
| Short name | T705 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 113.37 seconds |
| Started | Nov 22 01:46:06 PM PST 23 |
| Finished | Nov 22 01:48:06 PM PST 23 |
| Peak memory | 198872 kb |
| Host | smart-fadc9d20-0995-4919-87fa-d0543af5035d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=11394723600603897328529554177630066199199255382257403930455349139295859064355 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 101.uart_fifo_reset.11394723600603897328529554177630066199199255382257403930455349139295859064355 |
| Directory | /workspace/101.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/102.uart_fifo_reset.3272097324582697235672213870756367254284234436750428640890582010919032307467 |
| Short name | T1069 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 112.97 seconds |
| Started | Nov 22 01:46:23 PM PST 23 |
| Finished | Nov 22 01:48:17 PM PST 23 |
| Peak memory | 198920 kb |
| Host | smart-f4a9833b-6bbc-4e96-a3a1-c660130c8b93 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3272097324582697235672213870756367254284234436750428640890582010919032307467 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 102.uart_fifo_reset.3272097324582697235672213870756367254284234436750428640890582010919032307467 |
| Directory | /workspace/102.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/103.uart_fifo_reset.26657950753528828292904808301354765965826841710503364137851191060045525267060 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 114.38 seconds |
| Started | Nov 22 01:46:22 PM PST 23 |
| Finished | Nov 22 01:48:17 PM PST 23 |
| Peak memory | 198816 kb |
| Host | smart-4f0b7413-8565-4fe6-a56e-399d49a01310 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=26657950753528828292904808301354765965826841710503364137851191060045525267060 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 103.uart_fifo_reset.26657950753528828292904808301354765965826841710503364137851191060045525267060 |
| Directory | /workspace/103.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/104.uart_fifo_reset.95570588801177754125186217477604419186047757308179087620564801949385269441257 |
| Short name | T1146 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 114.02 seconds |
| Started | Nov 22 01:46:09 PM PST 23 |
| Finished | Nov 22 01:48:08 PM PST 23 |
| Peak memory | 198836 kb |
| Host | smart-b1219fe2-9c48-4955-a8ff-cbf0ab33c654 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=95570588801177754125186217477604419186047757308179087620564801949385269441257 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 104.uart_fifo_reset.95570588801177754125186217477604419186047757308179087620564801949385269441257 |
| Directory | /workspace/104.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/105.uart_fifo_reset.43043319977310127325250406943066563138117336103940565645529477283266689088018 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 113.68 seconds |
| Started | Nov 22 01:46:03 PM PST 23 |
| Finished | Nov 22 01:48:03 PM PST 23 |
| Peak memory | 198816 kb |
| Host | smart-56ea5c41-b189-40d3-9103-d4c2104dfe50 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=43043319977310127325250406943066563138117336103940565645529477283266689088018 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 105.uart_fifo_reset.43043319977310127325250406943066563138117336103940565645529477283266689088018 |
| Directory | /workspace/105.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/106.uart_fifo_reset.115005710031580221016029658842612381564919558259583296965828345205340800243271 |
| Short name | T791 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 112.69 seconds |
| Started | Nov 22 01:45:51 PM PST 23 |
| Finished | Nov 22 01:47:45 PM PST 23 |
| Peak memory | 198904 kb |
| Host | smart-1a654692-3caf-45a2-82f2-14c75b1d2de5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=115005710031580221016029658842612381564919558259583296965828345205340800243271 -assert nopostproc +UVM_TESTNAME=uart_bas e_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.uart_fifo_reset.115005710031580221016029658842612381564919558259583296965828345205340800243271 |
| Directory | /workspace/106.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/107.uart_fifo_reset.73329983780892505369065426478042472464451130369971859570910607867731610590124 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 113.35 seconds |
| Started | Nov 22 01:45:59 PM PST 23 |
| Finished | Nov 22 01:48:01 PM PST 23 |
| Peak memory | 198808 kb |
| Host | smart-3feca041-df3c-4e19-bdb7-aa05d4004e1b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=73329983780892505369065426478042472464451130369971859570910607867731610590124 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 107.uart_fifo_reset.73329983780892505369065426478042472464451130369971859570910607867731610590124 |
| Directory | /workspace/107.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/108.uart_fifo_reset.105152024392571612935592978554835177489814382492152318999264962262558129935564 |
| Short name | T738 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 112.89 seconds |
| Started | Nov 22 01:45:50 PM PST 23 |
| Finished | Nov 22 01:47:45 PM PST 23 |
| Peak memory | 198904 kb |
| Host | smart-0cd0b8e9-2398-4b26-b0e6-d55ea1e196bc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=105152024392571612935592978554835177489814382492152318999264962262558129935564 -assert nopostproc +UVM_TESTNAME=uart_bas e_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.uart_fifo_reset.105152024392571612935592978554835177489814382492152318999264962262558129935564 |
| Directory | /workspace/108.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/109.uart_fifo_reset.115204241435052407653726873988765922305216447006958301630619015559417015713466 |
| Short name | T667 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 113.05 seconds |
| Started | Nov 22 01:45:50 PM PST 23 |
| Finished | Nov 22 01:47:45 PM PST 23 |
| Peak memory | 198904 kb |
| Host | smart-7ad21eeb-32a9-416f-a9f3-04979e0347f4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=115204241435052407653726873988765922305216447006958301630619015559417015713466 -assert nopostproc +UVM_TESTNAME=uart_bas e_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.uart_fifo_reset.115204241435052407653726873988765922305216447006958301630619015559417015713466 |
| Directory | /workspace/109.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/11.uart_alert_test.828112564017639852404785590825502131355974788984052787508090304589424823963 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 16368684 ps |
| CPU time | 0.52 seconds |
| Started | Nov 22 01:44:28 PM PST 23 |
| Finished | Nov 22 01:44:36 PM PST 23 |
| Peak memory | 194636 kb |
| Host | smart-ecce6479-e532-44bd-83ed-5556b464bc42 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828112564017639852404785590825502131355974788984052787508090304589424823963 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_alert_test.828112564017639852404785590825502131355974788984052787508090304589424823963 |
| Directory | /workspace/11.uart_alert_test/latest |
| Test location | /workspace/coverage/default/11.uart_fifo_full.100628079168485710531690661585423795087268331963353457456491419647502907343123 |
| Short name | T675 |
| Test name | |
| Test status | |
| Simulation time | 61777160308 ps |
| CPU time | 60.02 seconds |
| Started | Nov 22 01:44:08 PM PST 23 |
| Finished | Nov 22 01:45:12 PM PST 23 |
| Peak memory | 199780 kb |
| Host | smart-f0a99032-7dec-4fbc-945a-805d4024576c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=100628079168485710531690661585423795087268331963353457456491419647502907343123 -assert nopostproc +UVM_TESTNAME=uart_bas e_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 11.uart_fifo_full.100628079168485710531690661585423795087268331963353457456491419647502907343123 |
| Directory | /workspace/11.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/11.uart_fifo_overflow.107808438699593306771942674556631227415513600303566207628605886912122139364022 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 58551936110 ps |
| CPU time | 55.44 seconds |
| Started | Nov 22 01:44:08 PM PST 23 |
| Finished | Nov 22 01:45:08 PM PST 23 |
| Peak memory | 199880 kb |
| Host | smart-b1eb7510-5ac1-40e9-abad-cf3fbaceb32c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=107808438699593306771942674556631227415513600303566207628605886912122139364022 -assert nopostproc +UVM_TESTNAME=uart_bas e_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 11.uart_fifo_overflow.107808438699593306771942674556631227415513600303566207628605886912122139364022 |
| Directory | /workspace/11.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/11.uart_fifo_reset.90418047659365152523630829751997504540671374035688547749662019735073519560445 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 112.97 seconds |
| Started | Nov 22 01:44:13 PM PST 23 |
| Finished | Nov 22 01:46:10 PM PST 23 |
| Peak memory | 198588 kb |
| Host | smart-a235414e-08c5-49c8-a2c1-6270c3d3e41b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=90418047659365152523630829751997504540671374035688547749662019735073519560445 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 11.uart_fifo_reset.90418047659365152523630829751997504540671374035688547749662019735073519560445 |
| Directory | /workspace/11.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/11.uart_intr.73207846406327374664623786068418397265076458514664265302632222440558507983021 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 787145125175 ps |
| CPU time | 787.28 seconds |
| Started | Nov 22 01:44:01 PM PST 23 |
| Finished | Nov 22 01:57:12 PM PST 23 |
| Peak memory | 200040 kb |
| Host | smart-70c0d614-2259-4af7-9d60-b57d80cc9363 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73207846406327374664623786068418397265076458514664265302632222440558507983021 -assert nopost proc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 11.uart_intr.73207846406327374664623786068418397265076458514664265302632222440558507983021 |
| Directory | /workspace/11.uart_intr/latest |
| Test location | /workspace/coverage/default/11.uart_long_xfer_wo_dly.62047907688190333167076467141906222633157521615260810301581968272345942323332 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 93387746707 ps |
| CPU time | 348.16 seconds |
| Started | Nov 22 01:44:14 PM PST 23 |
| Finished | Nov 22 01:50:06 PM PST 23 |
| Peak memory | 199956 kb |
| Host | smart-7bec2673-85f3-43fe-9803-62e97d52bbe2 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=62047907688190333167076467141906222633157521615260810301581968272345942323332 -assert nopostproc +UVM_TES TNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 11.uart_long_xfer_wo_dly.62047907688190333167076467141906222633157521615260810301581968272345942323332 |
| Directory | /workspace/11.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/11.uart_loopback.98016678528301650529445038689322237920279184170506797750017684412510586323156 |
| Short name | T924 |
| Test name | |
| Test status | |
| Simulation time | 14572448663 ps |
| CPU time | 16.2 seconds |
| Started | Nov 22 01:44:09 PM PST 23 |
| Finished | Nov 22 01:44:29 PM PST 23 |
| Peak memory | 199884 kb |
| Host | smart-0c70c689-679f-40b7-a3c1-46581f7cff4e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=98016678528301650529445038689322237920279184170506797750017684412510586323156 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 11.uart_loopback.98016678528301650529445038689322237920279184170506797750017684412510586323156 |
| Directory | /workspace/11.uart_loopback/latest |
| Test location | /workspace/coverage/default/11.uart_noise_filter.30507069542787419280241691908980619560340729119268377404451010913777566365296 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 94501577082 ps |
| CPU time | 96.44 seconds |
| Started | Nov 22 01:44:05 PM PST 23 |
| Finished | Nov 22 01:45:47 PM PST 23 |
| Peak memory | 200080 kb |
| Host | smart-2d52ddc9-99f6-44a4-b1bb-dfe4a88941c4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=30507069542787419280241691908980619560340729119268377404451010913777566365296 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_noise_filter.30507069542787419280241691908980619560340729119268377404451010913777566365296 |
| Directory | /workspace/11.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/11.uart_perf.78849509352804400059996452190262473144389688816513777753896281194322893242321 |
| Short name | T943 |
| Test name | |
| Test status | |
| Simulation time | 14098773881 ps |
| CPU time | 459.09 seconds |
| Started | Nov 22 01:44:25 PM PST 23 |
| Finished | Nov 22 01:52:09 PM PST 23 |
| Peak memory | 199680 kb |
| Host | smart-8989e9bc-7331-45f4-adf7-c07455297e26 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=78849509352804400059996452190262473144389688816513777753896281194322893242321 -assert nopostproc +UVM_TES TNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 11.uart_perf.78849509352804400059996452190262473144389688816513777753896281194322893242321 |
| Directory | /workspace/11.uart_perf/latest |
| Test location | /workspace/coverage/default/11.uart_rx_oversample.40370312454104708114759658999603259663402659252296209935439152244517545216599 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 4370280281 ps |
| CPU time | 20.25 seconds |
| Started | Nov 22 01:43:47 PM PST 23 |
| Finished | Nov 22 01:44:15 PM PST 23 |
| Peak memory | 198924 kb |
| Host | smart-109b5d47-66d6-43b3-8a61-40b7ceb256c6 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=40370312454104708114759658999603259663402659252296209935439152244517545216599 -assert nopostproc +UVM_TES TNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 11.uart_rx_oversample.40370312454104708114759658999603259663402659252296209935439152244517545216599 |
| Directory | /workspace/11.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/11.uart_rx_parity_err.4829071636675779866561386976134081421601839516249083370742090882925994669034 |
| Short name | T1161 |
| Test name | |
| Test status | |
| Simulation time | 36616611594 ps |
| CPU time | 37.83 seconds |
| Started | Nov 22 01:44:28 PM PST 23 |
| Finished | Nov 22 01:45:14 PM PST 23 |
| Peak memory | 200068 kb |
| Host | smart-64e6bd3b-24a6-49d3-9557-ddcf9a82d1e7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4829071636675779866561386976134081421601839516249083370742090882925994669034 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_parity_err.4829071636675779866561386976134081421601839516249083370742090882925994669034 |
| Directory | /workspace/11.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/11.uart_rx_start_bit_filter.38695534140877685907591586639237033928115232196057353911883271161166657945476 |
| Short name | T688 |
| Test name | |
| Test status | |
| Simulation time | 4267638245 ps |
| CPU time | 4.68 seconds |
| Started | Nov 22 01:44:05 PM PST 23 |
| Finished | Nov 22 01:44:15 PM PST 23 |
| Peak memory | 195696 kb |
| Host | smart-f1a50a29-2442-4afe-aa23-88a68029ddd4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=38695534140877685907591586639237033928115232196057353911883271161166657945476 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 11.uart_rx_start_bit_filter.38695534140877685907591586639237033928115232196057353911883271161166657945476 |
| Directory | /workspace/11.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/11.uart_smoke.44129006332114170475983688133455485839739742078036991875005202856604320941558 |
| Short name | T1152 |
| Test name | |
| Test status | |
| Simulation time | 5759626309 ps |
| CPU time | 18.4 seconds |
| Started | Nov 22 01:44:28 PM PST 23 |
| Finished | Nov 22 01:44:55 PM PST 23 |
| Peak memory | 199644 kb |
| Host | smart-f60afb76-fcf8-4d80-97d5-82fa2edc3a69 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=44129006332114170475983688133455485839739742078036991875005202856604320941558 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 11.uart_smoke.44129006332114170475983688133455485839739742078036991875005202856604320941558 |
| Directory | /workspace/11.uart_smoke/latest |
| Test location | /workspace/coverage/default/11.uart_stress_all.7729313945155434114805684379993046762264707220911266291026640200432917578173 |
| Short name | T1000 |
| Test name | |
| Test status | |
| Simulation time | 43402307308 ps |
| CPU time | 57.11 seconds |
| Started | Nov 22 01:44:06 PM PST 23 |
| Finished | Nov 22 01:45:08 PM PST 23 |
| Peak memory | 200100 kb |
| Host | smart-e87a9a2b-3524-4001-b745-0ed763be3c7d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7729313945155434114805684379993046762264707220911266291026640200432917578173 -assert nopost proc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 11.uart_stress_all.7729313945155434114805684379993046762264707220911266291026640200432917578173 |
| Directory | /workspace/11.uart_stress_all/latest |
| Test location | /workspace/coverage/default/11.uart_stress_all_with_rand_reset.101867518744762585273833396977743311372412633166140403900221979950008387685623 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 87476847566 ps |
| CPU time | 476.33 seconds |
| Started | Nov 22 01:44:04 PM PST 23 |
| Finished | Nov 22 01:52:05 PM PST 23 |
| Peak memory | 226208 kb |
| Host | smart-5c43820c-a3c3-426a-8b74-12a2d1b07bfa |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10186751874476258527383339 6977743311372412633166140403900221979950008387685623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_stress_all_with_rand_reset.101867518744 762585273833396977743311372412633166140403900221979950008387685623 |
| Directory | /workspace/11.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/11.uart_tx_ovrd.6309388353418502158010191568786105048421875811878315096157735926017618999996 |
| Short name | T728 |
| Test name | |
| Test status | |
| Simulation time | 485186362 ps |
| CPU time | 1.25 seconds |
| Started | Nov 22 01:44:09 PM PST 23 |
| Finished | Nov 22 01:44:15 PM PST 23 |
| Peak memory | 197928 kb |
| Host | smart-79462695-fd0e-4497-af88-c7a12a6593be |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=6309388353418502158010191568786105048421875811878315096157735926017618999996 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 11.uart_tx_ovrd.6309388353418502158010191568786105048421875811878315096157735926017618999996 |
| Directory | /workspace/11.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/11.uart_tx_rx.19119167869726736522431768083798260646173187690737956077723743461581715083905 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 57391945390 ps |
| CPU time | 63.46 seconds |
| Started | Nov 22 01:44:09 PM PST 23 |
| Finished | Nov 22 01:45:17 PM PST 23 |
| Peak memory | 200140 kb |
| Host | smart-8f94e3fe-f095-4ea9-b32a-8e99b758cc91 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=19119167869726736522431768083798260646173187690737956077723743461581715083905 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 11.uart_tx_rx.19119167869726736522431768083798260646173187690737956077723743461581715083905 |
| Directory | /workspace/11.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/110.uart_fifo_reset.69683896944873889944357181269535239368968832303394527974970773809939546868747 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 112.71 seconds |
| Started | Nov 22 01:45:59 PM PST 23 |
| Finished | Nov 22 01:48:00 PM PST 23 |
| Peak memory | 198936 kb |
| Host | smart-e01d1de0-e17a-4ebb-bf57-3ca10583f827 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=69683896944873889944357181269535239368968832303394527974970773809939546868747 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 110.uart_fifo_reset.69683896944873889944357181269535239368968832303394527974970773809939546868747 |
| Directory | /workspace/110.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/111.uart_fifo_reset.19986600131652497241772910998369068260749716831985735389652809409903648466656 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 112.43 seconds |
| Started | Nov 22 01:45:52 PM PST 23 |
| Finished | Nov 22 01:47:46 PM PST 23 |
| Peak memory | 198760 kb |
| Host | smart-fd0bb88f-23ef-422d-83f2-31bb75ae18eb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=19986600131652497241772910998369068260749716831985735389652809409903648466656 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 111.uart_fifo_reset.19986600131652497241772910998369068260749716831985735389652809409903648466656 |
| Directory | /workspace/111.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/112.uart_fifo_reset.26243760033392624797238583023625468090092470089394061869323159867628602659922 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 113.7 seconds |
| Started | Nov 22 01:45:44 PM PST 23 |
| Finished | Nov 22 01:47:39 PM PST 23 |
| Peak memory | 198804 kb |
| Host | smart-b92e7ad1-702a-4006-9c7d-3cdf243bf6f8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=26243760033392624797238583023625468090092470089394061869323159867628602659922 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 112.uart_fifo_reset.26243760033392624797238583023625468090092470089394061869323159867628602659922 |
| Directory | /workspace/112.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/113.uart_fifo_reset.67675590007844504883752941033987022139797222382566768896514895192234106673538 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 112.85 seconds |
| Started | Nov 22 01:45:40 PM PST 23 |
| Finished | Nov 22 01:47:35 PM PST 23 |
| Peak memory | 198924 kb |
| Host | smart-a87dd629-0f1a-4627-8ad3-6cae87a08d49 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=67675590007844504883752941033987022139797222382566768896514895192234106673538 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 113.uart_fifo_reset.67675590007844504883752941033987022139797222382566768896514895192234106673538 |
| Directory | /workspace/113.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/114.uart_fifo_reset.114520812101268229455578630571113832924108497330004213389153091295494421614626 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 112.17 seconds |
| Started | Nov 22 01:45:48 PM PST 23 |
| Finished | Nov 22 01:47:42 PM PST 23 |
| Peak memory | 198936 kb |
| Host | smart-da8f3057-7270-424d-9641-76e90f56277f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=114520812101268229455578630571113832924108497330004213389153091295494421614626 -assert nopostproc +UVM_TESTNAME=uart_bas e_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.uart_fifo_reset.114520812101268229455578630571113832924108497330004213389153091295494421614626 |
| Directory | /workspace/114.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/115.uart_fifo_reset.31387927584069039033902259253402333207449986358676441224901957420463423651419 |
| Short name | T760 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 112.72 seconds |
| Started | Nov 22 01:45:53 PM PST 23 |
| Finished | Nov 22 01:47:49 PM PST 23 |
| Peak memory | 198904 kb |
| Host | smart-37ab6cdf-944b-4605-96af-85f9cbfebd23 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=31387927584069039033902259253402333207449986358676441224901957420463423651419 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 115.uart_fifo_reset.31387927584069039033902259253402333207449986358676441224901957420463423651419 |
| Directory | /workspace/115.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/116.uart_fifo_reset.7972770864248477022739655748848847959452078889257883880198755021949557430493 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 113.06 seconds |
| Started | Nov 22 01:45:40 PM PST 23 |
| Finished | Nov 22 01:47:35 PM PST 23 |
| Peak memory | 198836 kb |
| Host | smart-4190e53d-f807-4d97-a010-010eb914da41 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=7972770864248477022739655748848847959452078889257883880198755021949557430493 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 116.uart_fifo_reset.7972770864248477022739655748848847959452078889257883880198755021949557430493 |
| Directory | /workspace/116.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/118.uart_fifo_reset.37999594991119758230104014965528510754379577554890244754556922145193979116474 |
| Short name | T770 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 113.36 seconds |
| Started | Nov 22 01:45:57 PM PST 23 |
| Finished | Nov 22 01:47:58 PM PST 23 |
| Peak memory | 198852 kb |
| Host | smart-af76ccfa-066e-48f4-bbeb-6091bc37d1b1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=37999594991119758230104014965528510754379577554890244754556922145193979116474 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 118.uart_fifo_reset.37999594991119758230104014965528510754379577554890244754556922145193979116474 |
| Directory | /workspace/118.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/119.uart_fifo_reset.55641935659670312446164589745177222468864643353055066436220526902890316899296 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 112.89 seconds |
| Started | Nov 22 01:45:57 PM PST 23 |
| Finished | Nov 22 01:47:57 PM PST 23 |
| Peak memory | 198848 kb |
| Host | smart-75d7f6ab-7981-483d-b325-d7aeaefad1f2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=55641935659670312446164589745177222468864643353055066436220526902890316899296 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 119.uart_fifo_reset.55641935659670312446164589745177222468864643353055066436220526902890316899296 |
| Directory | /workspace/119.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/12.uart_alert_test.16503360173295684042548599026933358833682605342245165061713708147997092718263 |
| Short name | T1109 |
| Test name | |
| Test status | |
| Simulation time | 16368684 ps |
| CPU time | 0.62 seconds |
| Started | Nov 22 01:44:09 PM PST 23 |
| Finished | Nov 22 01:44:14 PM PST 23 |
| Peak memory | 194604 kb |
| Host | smart-a0dfac9b-1c71-4ca8-ab8e-20ef7facda42 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16503360173295684042548599026933358833682605342245165061713708147997092718263 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 12.uart_alert_test.16503360173295684042548599026933358833682605342245165061713708147997092718263 |
| Directory | /workspace/12.uart_alert_test/latest |
| Test location | /workspace/coverage/default/12.uart_fifo_full.4104267607732115469706058508944114880246186565744795427882553922578975985652 |
| Short name | T967 |
| Test name | |
| Test status | |
| Simulation time | 61777160308 ps |
| CPU time | 60.77 seconds |
| Started | Nov 22 01:43:58 PM PST 23 |
| Finished | Nov 22 01:45:02 PM PST 23 |
| Peak memory | 200104 kb |
| Host | smart-7e66d66b-42ee-4660-b7ef-55912e113702 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4104267607732115469706058508944114880246186565744795427882553922578975985652 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 12.uart_fifo_full.4104267607732115469706058508944114880246186565744795427882553922578975985652 |
| Directory | /workspace/12.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/12.uart_fifo_overflow.71015902720354636165729442722803628041910363429032012938635564901729281660671 |
| Short name | T1164 |
| Test name | |
| Test status | |
| Simulation time | 58551936110 ps |
| CPU time | 55.41 seconds |
| Started | Nov 22 01:44:25 PM PST 23 |
| Finished | Nov 22 01:45:25 PM PST 23 |
| Peak memory | 199284 kb |
| Host | smart-93667749-6ea9-4bab-b4e8-764ba3f91e7d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=71015902720354636165729442722803628041910363429032012938635564901729281660671 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 12.uart_fifo_overflow.71015902720354636165729442722803628041910363429032012938635564901729281660671 |
| Directory | /workspace/12.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/12.uart_fifo_reset.73551783221812699345259066213895186150717846065555568780169810974444517968394 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 114.27 seconds |
| Started | Nov 22 01:44:26 PM PST 23 |
| Finished | Nov 22 01:46:24 PM PST 23 |
| Peak memory | 198936 kb |
| Host | smart-4d0996ec-b076-41b5-ad55-50ca1e96120f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=73551783221812699345259066213895186150717846065555568780169810974444517968394 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 12.uart_fifo_reset.73551783221812699345259066213895186150717846065555568780169810974444517968394 |
| Directory | /workspace/12.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/12.uart_intr.106046619595293471530008343213488835158012352069288920878484831379515587000630 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 787145125175 ps |
| CPU time | 783.65 seconds |
| Started | Nov 22 01:44:07 PM PST 23 |
| Finished | Nov 22 01:57:16 PM PST 23 |
| Peak memory | 200188 kb |
| Host | smart-d7caefb1-28d4-41b7-8ade-64687b90537b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106046619595293471530008343213488835158012352069288920878484831379515587000630 -assert nopos tproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 12.uart_intr.106046619595293471530008343213488835158012352069288920878484831379515587000630 |
| Directory | /workspace/12.uart_intr/latest |
| Test location | /workspace/coverage/default/12.uart_long_xfer_wo_dly.101441180256394180915905595894952735368306307158045589476115553757495895900228 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 93387746707 ps |
| CPU time | 342.04 seconds |
| Started | Nov 22 01:44:13 PM PST 23 |
| Finished | Nov 22 01:49:59 PM PST 23 |
| Peak memory | 199948 kb |
| Host | smart-73298383-ee64-4f45-9b0b-0e5da9b01519 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=101441180256394180915905595894952735368306307158045589476115553757495895900228 -assert nopostproc +UVM_TE STNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 12.uart_long_xfer_wo_dly.101441180256394180915905595894952735368306307158045589476115553757495895900228 |
| Directory | /workspace/12.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/12.uart_loopback.109911563761602639683170699349116888356947318644597769545807706474271413791034 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 14572448663 ps |
| CPU time | 16.1 seconds |
| Started | Nov 22 01:43:55 PM PST 23 |
| Finished | Nov 22 01:44:14 PM PST 23 |
| Peak memory | 200008 kb |
| Host | smart-0e2d4b8d-cf13-456c-b579-7b3e8e904376 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=109911563761602639683170699349116888356947318644597769545807706474271413791034 -assert nopostproc +UVM_TESTNAME=uart_bas e_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 12.uart_loopback.109911563761602639683170699349116888356947318644597769545807706474271413791034 |
| Directory | /workspace/12.uart_loopback/latest |
| Test location | /workspace/coverage/default/12.uart_noise_filter.28404354377351741001216352562593884174785439864418538327850702093745258424182 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 94501577082 ps |
| CPU time | 96.91 seconds |
| Started | Nov 22 01:44:04 PM PST 23 |
| Finished | Nov 22 01:45:46 PM PST 23 |
| Peak memory | 200304 kb |
| Host | smart-42c06723-c6a9-42e6-8ebe-09e2c9400934 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=28404354377351741001216352562593884174785439864418538327850702093745258424182 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_noise_filter.28404354377351741001216352562593884174785439864418538327850702093745258424182 |
| Directory | /workspace/12.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/12.uart_perf.64787187488918523895054657802406903235375424018953474842053870174840181407588 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 14098773881 ps |
| CPU time | 463.31 seconds |
| Started | Nov 22 01:44:05 PM PST 23 |
| Finished | Nov 22 01:51:53 PM PST 23 |
| Peak memory | 200188 kb |
| Host | smart-0b916e3e-ff3f-4e4e-9cd2-658cb7d26cbe |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=64787187488918523895054657802406903235375424018953474842053870174840181407588 -assert nopostproc +UVM_TES TNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 12.uart_perf.64787187488918523895054657802406903235375424018953474842053870174840181407588 |
| Directory | /workspace/12.uart_perf/latest |
| Test location | /workspace/coverage/default/12.uart_rx_oversample.97279929719032765676124214386503376518238594385916363476785123275523123900460 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 4370280281 ps |
| CPU time | 19.62 seconds |
| Started | Nov 22 01:44:25 PM PST 23 |
| Finished | Nov 22 01:44:49 PM PST 23 |
| Peak memory | 198596 kb |
| Host | smart-0a461304-fc4d-4482-bf40-f25554cf477e |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=97279929719032765676124214386503376518238594385916363476785123275523123900460 -assert nopostproc +UVM_TES TNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 12.uart_rx_oversample.97279929719032765676124214386503376518238594385916363476785123275523123900460 |
| Directory | /workspace/12.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/12.uart_rx_parity_err.36919957243943548839813266452429796944798317453702087659228543651642612826166 |
| Short name | T809 |
| Test name | |
| Test status | |
| Simulation time | 36616611594 ps |
| CPU time | 37.51 seconds |
| Started | Nov 22 01:44:15 PM PST 23 |
| Finished | Nov 22 01:45:03 PM PST 23 |
| Peak memory | 199936 kb |
| Host | smart-8d3878cb-f7fb-4142-b6a2-f36d3b40cd44 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=36919957243943548839813266452429796944798317453702087659228543651642612826166 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 12.uart_rx_parity_err.36919957243943548839813266452429796944798317453702087659228543651642612826166 |
| Directory | /workspace/12.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/12.uart_rx_start_bit_filter.89457011799436701498077021489670355621156315728404765743609858125077277236776 |
| Short name | T1097 |
| Test name | |
| Test status | |
| Simulation time | 4267638245 ps |
| CPU time | 4.74 seconds |
| Started | Nov 22 01:44:12 PM PST 23 |
| Finished | Nov 22 01:44:20 PM PST 23 |
| Peak memory | 196048 kb |
| Host | smart-595d03d3-5f15-4816-a3e4-ec03f62ed14f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=89457011799436701498077021489670355621156315728404765743609858125077277236776 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 12.uart_rx_start_bit_filter.89457011799436701498077021489670355621156315728404765743609858125077277236776 |
| Directory | /workspace/12.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/12.uart_smoke.71586672094913891940179527960915109299017935338595124242798416812765056362631 |
| Short name | T925 |
| Test name | |
| Test status | |
| Simulation time | 5759626309 ps |
| CPU time | 18.17 seconds |
| Started | Nov 22 01:44:22 PM PST 23 |
| Finished | Nov 22 01:44:48 PM PST 23 |
| Peak memory | 199504 kb |
| Host | smart-f525c7f5-d551-4374-b06f-378153ebc739 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=71586672094913891940179527960915109299017935338595124242798416812765056362631 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 12.uart_smoke.71586672094913891940179527960915109299017935338595124242798416812765056362631 |
| Directory | /workspace/12.uart_smoke/latest |
| Test location | /workspace/coverage/default/12.uart_stress_all.66911743305440637767603907690617821431712488936879090125607521458935141525824 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 43402307308 ps |
| CPU time | 56.81 seconds |
| Started | Nov 22 01:44:01 PM PST 23 |
| Finished | Nov 22 01:45:02 PM PST 23 |
| Peak memory | 200164 kb |
| Host | smart-d53ad63a-b412-4b94-a024-cb850ae802a7 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66911743305440637767603907690617821431712488936879090125607521458935141525824 -assert nopos tproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 12.uart_stress_all.66911743305440637767603907690617821431712488936879090125607521458935141525824 |
| Directory | /workspace/12.uart_stress_all/latest |
| Test location | /workspace/coverage/default/12.uart_stress_all_with_rand_reset.54833362668563637424488521689797894255289178117118984449335998450661943363414 |
| Short name | T1044 |
| Test name | |
| Test status | |
| Simulation time | 87476847566 ps |
| CPU time | 449.79 seconds |
| Started | Nov 22 01:44:13 PM PST 23 |
| Finished | Nov 22 01:51:46 PM PST 23 |
| Peak memory | 226100 kb |
| Host | smart-588a4603-ea63-44d5-8cfd-7fa9b06703fa |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54833362668563637424488521 689797894255289178117118984449335998450661943363414 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_stress_all_with_rand_reset.5483336266856 3637424488521689797894255289178117118984449335998450661943363414 |
| Directory | /workspace/12.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/12.uart_tx_ovrd.69467866603171601943465518507357188465664672104227296915573227033592905193426 |
| Short name | T1067 |
| Test name | |
| Test status | |
| Simulation time | 485186362 ps |
| CPU time | 1.3 seconds |
| Started | Nov 22 01:44:03 PM PST 23 |
| Finished | Nov 22 01:44:09 PM PST 23 |
| Peak memory | 197916 kb |
| Host | smart-0a7a0e78-63b8-4a1d-a3ec-008b2c4cbd1e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=69467866603171601943465518507357188465664672104227296915573227033592905193426 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 12.uart_tx_ovrd.69467866603171601943465518507357188465664672104227296915573227033592905193426 |
| Directory | /workspace/12.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/12.uart_tx_rx.34687443470624957755358157073800109205400648071256327523063694650132234785640 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 57391945390 ps |
| CPU time | 64.67 seconds |
| Started | Nov 22 01:44:28 PM PST 23 |
| Finished | Nov 22 01:45:41 PM PST 23 |
| Peak memory | 200084 kb |
| Host | smart-591e0684-98be-4ed7-858d-e5be5618667b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=34687443470624957755358157073800109205400648071256327523063694650132234785640 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 12.uart_tx_rx.34687443470624957755358157073800109205400648071256327523063694650132234785640 |
| Directory | /workspace/12.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/120.uart_fifo_reset.56684965670061003978907516183016799815296992847716758886949710534754878836489 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 113.48 seconds |
| Started | Nov 22 01:45:56 PM PST 23 |
| Finished | Nov 22 01:47:57 PM PST 23 |
| Peak memory | 198852 kb |
| Host | smart-1eb1f736-a3cd-4f77-97ec-be597cbd03f9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=56684965670061003978907516183016799815296992847716758886949710534754878836489 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 120.uart_fifo_reset.56684965670061003978907516183016799815296992847716758886949710534754878836489 |
| Directory | /workspace/120.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/121.uart_fifo_reset.86602218624848998340247390119747237060534159506889904936820082224263545197139 |
| Short name | T919 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 113.33 seconds |
| Started | Nov 22 01:45:42 PM PST 23 |
| Finished | Nov 22 01:47:37 PM PST 23 |
| Peak memory | 198840 kb |
| Host | smart-1d7264f3-6395-4a9e-86c4-5952bab4ef4d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=86602218624848998340247390119747237060534159506889904936820082224263545197139 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 121.uart_fifo_reset.86602218624848998340247390119747237060534159506889904936820082224263545197139 |
| Directory | /workspace/121.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/122.uart_fifo_reset.90527477321666467874971522648442834219732289527244544997205984987279997449594 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 113.53 seconds |
| Started | Nov 22 01:45:58 PM PST 23 |
| Finished | Nov 22 01:48:00 PM PST 23 |
| Peak memory | 198900 kb |
| Host | smart-57e3e253-6514-4ace-92ce-a43468265d8c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=90527477321666467874971522648442834219732289527244544997205984987279997449594 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 122.uart_fifo_reset.90527477321666467874971522648442834219732289527244544997205984987279997449594 |
| Directory | /workspace/122.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/123.uart_fifo_reset.111592108446063484827763644418805321088189053810720395139549282552010888258690 |
| Short name | T1018 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 112.88 seconds |
| Started | Nov 22 01:45:57 PM PST 23 |
| Finished | Nov 22 01:47:57 PM PST 23 |
| Peak memory | 198932 kb |
| Host | smart-5c8fa306-eaeb-4e60-94c3-eee898be60ab |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=111592108446063484827763644418805321088189053810720395139549282552010888258690 -assert nopostproc +UVM_TESTNAME=uart_bas e_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.uart_fifo_reset.111592108446063484827763644418805321088189053810720395139549282552010888258690 |
| Directory | /workspace/123.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/124.uart_fifo_reset.26450645812563995781281902317311636498779314311492048532226087599394169663983 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 112.32 seconds |
| Started | Nov 22 01:45:43 PM PST 23 |
| Finished | Nov 22 01:47:37 PM PST 23 |
| Peak memory | 198908 kb |
| Host | smart-4af35e12-3852-4060-8a7c-657725a3c272 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=26450645812563995781281902317311636498779314311492048532226087599394169663983 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 124.uart_fifo_reset.26450645812563995781281902317311636498779314311492048532226087599394169663983 |
| Directory | /workspace/124.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/125.uart_fifo_reset.67638161287443437406301527981385638886336204472840115247617306399308554360639 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 112.21 seconds |
| Started | Nov 22 01:45:59 PM PST 23 |
| Finished | Nov 22 01:47:59 PM PST 23 |
| Peak memory | 198884 kb |
| Host | smart-529b767e-eda7-4f00-bef1-59eec9a22d10 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=67638161287443437406301527981385638886336204472840115247617306399308554360639 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 125.uart_fifo_reset.67638161287443437406301527981385638886336204472840115247617306399308554360639 |
| Directory | /workspace/125.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/126.uart_fifo_reset.34352852888592785726976724484913083282054547420529927521427871851484693728766 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 113.69 seconds |
| Started | Nov 22 01:45:43 PM PST 23 |
| Finished | Nov 22 01:47:38 PM PST 23 |
| Peak memory | 198960 kb |
| Host | smart-fa0531e4-b83c-449e-8ee5-64d04c43b272 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=34352852888592785726976724484913083282054547420529927521427871851484693728766 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 126.uart_fifo_reset.34352852888592785726976724484913083282054547420529927521427871851484693728766 |
| Directory | /workspace/126.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/127.uart_fifo_reset.48877733582477391357640059237187816665144897259156269847689824386648552973781 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 113.53 seconds |
| Started | Nov 22 01:45:53 PM PST 23 |
| Finished | Nov 22 01:47:50 PM PST 23 |
| Peak memory | 198908 kb |
| Host | smart-68bddafa-8604-4cac-a03b-a73dacaba9e4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=48877733582477391357640059237187816665144897259156269847689824386648552973781 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 127.uart_fifo_reset.48877733582477391357640059237187816665144897259156269847689824386648552973781 |
| Directory | /workspace/127.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/128.uart_fifo_reset.62554954324803404977011365728986355892942845615956382318930088091158666292897 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 112.94 seconds |
| Started | Nov 22 01:45:54 PM PST 23 |
| Finished | Nov 22 01:47:51 PM PST 23 |
| Peak memory | 198908 kb |
| Host | smart-a75582a0-89d5-4ea0-b1ba-e4306d89646a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=62554954324803404977011365728986355892942845615956382318930088091158666292897 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 128.uart_fifo_reset.62554954324803404977011365728986355892942845615956382318930088091158666292897 |
| Directory | /workspace/128.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/129.uart_fifo_reset.93311596430833962462471738947374234649213096942580098400338499096837097448839 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 112.38 seconds |
| Started | Nov 22 01:45:44 PM PST 23 |
| Finished | Nov 22 01:47:38 PM PST 23 |
| Peak memory | 198900 kb |
| Host | smart-85d40579-8958-4d12-b83d-219fba02a4aa |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=93311596430833962462471738947374234649213096942580098400338499096837097448839 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 129.uart_fifo_reset.93311596430833962462471738947374234649213096942580098400338499096837097448839 |
| Directory | /workspace/129.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/13.uart_alert_test.75115777976407996740095696303098096778300232596405292449941237245131734642511 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 16368684 ps |
| CPU time | 0.53 seconds |
| Started | Nov 22 01:44:13 PM PST 23 |
| Finished | Nov 22 01:44:17 PM PST 23 |
| Peak memory | 194484 kb |
| Host | smart-25928456-a673-442c-ad32-cb58dcd9647b |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75115777976407996740095696303098096778300232596405292449941237245131734642511 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 13.uart_alert_test.75115777976407996740095696303098096778300232596405292449941237245131734642511 |
| Directory | /workspace/13.uart_alert_test/latest |
| Test location | /workspace/coverage/default/13.uart_fifo_full.111232414652000278768952210012338630749333768832457932263590121249376943158545 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 61777160308 ps |
| CPU time | 60.17 seconds |
| Started | Nov 22 01:44:04 PM PST 23 |
| Finished | Nov 22 01:45:09 PM PST 23 |
| Peak memory | 200096 kb |
| Host | smart-b4ad81ed-d0a6-4c2d-a5e7-54fe61b7b0c9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=111232414652000278768952210012338630749333768832457932263590121249376943158545 -assert nopostproc +UVM_TESTNAME=uart_bas e_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 13.uart_fifo_full.111232414652000278768952210012338630749333768832457932263590121249376943158545 |
| Directory | /workspace/13.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/13.uart_fifo_overflow.61234233065916698867434683106752443042910297526235715312197768532884458308671 |
| Short name | T1001 |
| Test name | |
| Test status | |
| Simulation time | 58551936110 ps |
| CPU time | 54.52 seconds |
| Started | Nov 22 01:44:07 PM PST 23 |
| Finished | Nov 22 01:45:06 PM PST 23 |
| Peak memory | 199920 kb |
| Host | smart-48fa1f93-76ad-4a22-8692-002c4357913d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=61234233065916698867434683106752443042910297526235715312197768532884458308671 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 13.uart_fifo_overflow.61234233065916698867434683106752443042910297526235715312197768532884458308671 |
| Directory | /workspace/13.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/13.uart_fifo_reset.98273811823843182486427258806864746640251925603022011891977551176264315367871 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 112.87 seconds |
| Started | Nov 22 01:44:05 PM PST 23 |
| Finished | Nov 22 01:46:04 PM PST 23 |
| Peak memory | 198884 kb |
| Host | smart-5ebaecb8-0423-49b3-b5fc-665161f90cb9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=98273811823843182486427258806864746640251925603022011891977551176264315367871 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 13.uart_fifo_reset.98273811823843182486427258806864746640251925603022011891977551176264315367871 |
| Directory | /workspace/13.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/13.uart_intr.94580631351357000872000221240938729881178970718581777959139806647627758939827 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 787145125175 ps |
| CPU time | 788.82 seconds |
| Started | Nov 22 01:43:59 PM PST 23 |
| Finished | Nov 22 01:57:11 PM PST 23 |
| Peak memory | 200132 kb |
| Host | smart-0e5ce9ff-2d28-414b-9a98-5ae22038a866 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94580631351357000872000221240938729881178970718581777959139806647627758939827 -assert nopost proc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 13.uart_intr.94580631351357000872000221240938729881178970718581777959139806647627758939827 |
| Directory | /workspace/13.uart_intr/latest |
| Test location | /workspace/coverage/default/13.uart_long_xfer_wo_dly.22631781243994994119497542858278723795504079140783100066960797516480106377267 |
| Short name | T875 |
| Test name | |
| Test status | |
| Simulation time | 93387746707 ps |
| CPU time | 340.45 seconds |
| Started | Nov 22 01:44:00 PM PST 23 |
| Finished | Nov 22 01:49:44 PM PST 23 |
| Peak memory | 199956 kb |
| Host | smart-046ff226-9aff-497e-8f0a-8603a94032b0 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=22631781243994994119497542858278723795504079140783100066960797516480106377267 -assert nopostproc +UVM_TES TNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 13.uart_long_xfer_wo_dly.22631781243994994119497542858278723795504079140783100066960797516480106377267 |
| Directory | /workspace/13.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/13.uart_loopback.109958671430382869116460635866235037907896991354543664466863819418658708210360 |
| Short name | T926 |
| Test name | |
| Test status | |
| Simulation time | 14572448663 ps |
| CPU time | 16.41 seconds |
| Started | Nov 22 01:44:07 PM PST 23 |
| Finished | Nov 22 01:44:28 PM PST 23 |
| Peak memory | 200052 kb |
| Host | smart-ddea8f6b-1e47-42f7-aa5b-71d7304d796c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=109958671430382869116460635866235037907896991354543664466863819418658708210360 -assert nopostproc +UVM_TESTNAME=uart_bas e_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 13.uart_loopback.109958671430382869116460635866235037907896991354543664466863819418658708210360 |
| Directory | /workspace/13.uart_loopback/latest |
| Test location | /workspace/coverage/default/13.uart_noise_filter.2540059454226647966830278185446263702205416341355613608653426680089220569036 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 94501577082 ps |
| CPU time | 98.86 seconds |
| Started | Nov 22 01:43:58 PM PST 23 |
| Finished | Nov 22 01:45:41 PM PST 23 |
| Peak memory | 200208 kb |
| Host | smart-8846d6b9-f987-43b0-9205-e50b4ac1df37 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2540059454226647966830278185446263702205416341355613608653426680089220569036 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_noise_filter.2540059454226647966830278185446263702205416341355613608653426680089220569036 |
| Directory | /workspace/13.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/13.uart_perf.32495291134359933819119031237174412118703843403985737612810410869754629230575 |
| Short name | T834 |
| Test name | |
| Test status | |
| Simulation time | 14098773881 ps |
| CPU time | 469.49 seconds |
| Started | Nov 22 01:44:29 PM PST 23 |
| Finished | Nov 22 01:52:26 PM PST 23 |
| Peak memory | 200164 kb |
| Host | smart-1e32d828-60cf-4a10-a5e3-73de3171c6f3 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=32495291134359933819119031237174412118703843403985737612810410869754629230575 -assert nopostproc +UVM_TES TNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 13.uart_perf.32495291134359933819119031237174412118703843403985737612810410869754629230575 |
| Directory | /workspace/13.uart_perf/latest |
| Test location | /workspace/coverage/default/13.uart_rx_oversample.6347461946804562637592626673973533882352486387966337747498262405865573497726 |
| Short name | T893 |
| Test name | |
| Test status | |
| Simulation time | 4370280281 ps |
| CPU time | 20.39 seconds |
| Started | Nov 22 01:44:03 PM PST 23 |
| Finished | Nov 22 01:44:28 PM PST 23 |
| Peak memory | 198968 kb |
| Host | smart-c501a869-2236-40f7-83f3-0a78c095d175 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=6347461946804562637592626673973533882352486387966337747498262405865573497726 -assert nopostproc +UVM_TEST NAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 13.uart_rx_oversample.6347461946804562637592626673973533882352486387966337747498262405865573497726 |
| Directory | /workspace/13.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/13.uart_rx_parity_err.86723474645229964600126444783521499774823846564125934638739393424646505778046 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 36616611594 ps |
| CPU time | 37.61 seconds |
| Started | Nov 22 01:44:06 PM PST 23 |
| Finished | Nov 22 01:44:48 PM PST 23 |
| Peak memory | 200112 kb |
| Host | smart-15d0937c-21f5-4cb0-b305-7f3bf62ac6a1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=86723474645229964600126444783521499774823846564125934638739393424646505778046 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 13.uart_rx_parity_err.86723474645229964600126444783521499774823846564125934638739393424646505778046 |
| Directory | /workspace/13.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/13.uart_rx_start_bit_filter.41367293534676727134954401252660545322575913002272530543040662985959543249029 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 4267638245 ps |
| CPU time | 4.92 seconds |
| Started | Nov 22 01:44:12 PM PST 23 |
| Finished | Nov 22 01:44:21 PM PST 23 |
| Peak memory | 195988 kb |
| Host | smart-86429b38-4aa3-4971-bc0b-63311a85f64b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=41367293534676727134954401252660545322575913002272530543040662985959543249029 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 13.uart_rx_start_bit_filter.41367293534676727134954401252660545322575913002272530543040662985959543249029 |
| Directory | /workspace/13.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/13.uart_smoke.77636680236216928453780923232583157619694581283137585990525145123933962625596 |
| Short name | T979 |
| Test name | |
| Test status | |
| Simulation time | 5759626309 ps |
| CPU time | 18.55 seconds |
| Started | Nov 22 01:43:59 PM PST 23 |
| Finished | Nov 22 01:44:21 PM PST 23 |
| Peak memory | 199656 kb |
| Host | smart-12032d27-decd-4822-aeff-b5e44a2dbb4a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=77636680236216928453780923232583157619694581283137585990525145123933962625596 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 13.uart_smoke.77636680236216928453780923232583157619694581283137585990525145123933962625596 |
| Directory | /workspace/13.uart_smoke/latest |
| Test location | /workspace/coverage/default/13.uart_stress_all.46442730756777521165895447542261585374423749010844975115891052022576567871600 |
| Short name | T1267 |
| Test name | |
| Test status | |
| Simulation time | 43402307308 ps |
| CPU time | 57.12 seconds |
| Started | Nov 22 01:44:04 PM PST 23 |
| Finished | Nov 22 01:45:06 PM PST 23 |
| Peak memory | 200124 kb |
| Host | smart-11d5920d-a50d-44a8-b81b-beacd4f5532f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46442730756777521165895447542261585374423749010844975115891052022576567871600 -assert nopos tproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 13.uart_stress_all.46442730756777521165895447542261585374423749010844975115891052022576567871600 |
| Directory | /workspace/13.uart_stress_all/latest |
| Test location | /workspace/coverage/default/13.uart_stress_all_with_rand_reset.87338515968677708748195086657058510105562067524755019683526234911035843491570 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 87476847566 ps |
| CPU time | 470.02 seconds |
| Started | Nov 22 01:44:14 PM PST 23 |
| Finished | Nov 22 01:52:08 PM PST 23 |
| Peak memory | 226228 kb |
| Host | smart-fb5806f9-40a3-48a1-b16b-4c82ea430ac0 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87338515968677708748195086 657058510105562067524755019683526234911035843491570 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_stress_all_with_rand_reset.8733851596867 7708748195086657058510105562067524755019683526234911035843491570 |
| Directory | /workspace/13.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/13.uart_tx_ovrd.82466996700282137761438459778079006886982854665796158984002220438076706277390 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 485186362 ps |
| CPU time | 1.26 seconds |
| Started | Nov 22 01:44:23 PM PST 23 |
| Finished | Nov 22 01:44:31 PM PST 23 |
| Peak memory | 197892 kb |
| Host | smart-cdad3368-a46c-4a68-b5fa-11c638b3e066 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=82466996700282137761438459778079006886982854665796158984002220438076706277390 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 13.uart_tx_ovrd.82466996700282137761438459778079006886982854665796158984002220438076706277390 |
| Directory | /workspace/13.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/13.uart_tx_rx.54334376007662903412915845232931317177784428502204514220040447210066484050042 |
| Short name | T1124 |
| Test name | |
| Test status | |
| Simulation time | 57391945390 ps |
| CPU time | 64.61 seconds |
| Started | Nov 22 01:44:06 PM PST 23 |
| Finished | Nov 22 01:45:16 PM PST 23 |
| Peak memory | 200160 kb |
| Host | smart-e0fdb600-5488-4313-a789-fff01b325ce6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=54334376007662903412915845232931317177784428502204514220040447210066484050042 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 13.uart_tx_rx.54334376007662903412915845232931317177784428502204514220040447210066484050042 |
| Directory | /workspace/13.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/130.uart_fifo_reset.107449253782719479837968018177729603814336895773926010285546283539890583469707 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 112.82 seconds |
| Started | Nov 22 01:45:43 PM PST 23 |
| Finished | Nov 22 01:47:38 PM PST 23 |
| Peak memory | 198960 kb |
| Host | smart-a50b3957-c9c9-4b7a-9bdf-296f1aeb939e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=107449253782719479837968018177729603814336895773926010285546283539890583469707 -assert nopostproc +UVM_TESTNAME=uart_bas e_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.uart_fifo_reset.107449253782719479837968018177729603814336895773926010285546283539890583469707 |
| Directory | /workspace/130.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/131.uart_fifo_reset.73325519506698814581511581331100734985205343937445823087877600122242337755208 |
| Short name | T740 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 113.29 seconds |
| Started | Nov 22 01:45:41 PM PST 23 |
| Finished | Nov 22 01:47:36 PM PST 23 |
| Peak memory | 198936 kb |
| Host | smart-8ac40757-6915-4882-b467-43ad90fd139c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=73325519506698814581511581331100734985205343937445823087877600122242337755208 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 131.uart_fifo_reset.73325519506698814581511581331100734985205343937445823087877600122242337755208 |
| Directory | /workspace/131.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/132.uart_fifo_reset.102786378398829528609278244527297869668416701956245171125334731394650037087297 |
| Short name | T815 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 112.97 seconds |
| Started | Nov 22 01:45:55 PM PST 23 |
| Finished | Nov 22 01:47:51 PM PST 23 |
| Peak memory | 198892 kb |
| Host | smart-bb42b339-7c50-47d9-a9c3-6ed6f0343217 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=102786378398829528609278244527297869668416701956245171125334731394650037087297 -assert nopostproc +UVM_TESTNAME=uart_bas e_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.uart_fifo_reset.102786378398829528609278244527297869668416701956245171125334731394650037087297 |
| Directory | /workspace/132.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/133.uart_fifo_reset.49207878933948773883066081151510215401495649555694869507872140889612714464680 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 113.15 seconds |
| Started | Nov 22 01:45:54 PM PST 23 |
| Finished | Nov 22 01:47:51 PM PST 23 |
| Peak memory | 198892 kb |
| Host | smart-12ea3f10-7c1e-44ab-bdc9-173ef2b8466e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=49207878933948773883066081151510215401495649555694869507872140889612714464680 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 133.uart_fifo_reset.49207878933948773883066081151510215401495649555694869507872140889612714464680 |
| Directory | /workspace/133.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/134.uart_fifo_reset.7171954265712581213569486261390437240103979748156480982644101569215391658061 |
| Short name | T1206 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 112.6 seconds |
| Started | Nov 22 01:45:48 PM PST 23 |
| Finished | Nov 22 01:47:42 PM PST 23 |
| Peak memory | 198984 kb |
| Host | smart-f3c7732a-1d78-4c02-aea3-13c45fcad0e2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=7171954265712581213569486261390437240103979748156480982644101569215391658061 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 134.uart_fifo_reset.7171954265712581213569486261390437240103979748156480982644101569215391658061 |
| Directory | /workspace/134.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/135.uart_fifo_reset.26733682700239527283525784926048283938600472537316586662385076359233899241589 |
| Short name | T1117 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 113.15 seconds |
| Started | Nov 22 01:45:57 PM PST 23 |
| Finished | Nov 22 01:47:59 PM PST 23 |
| Peak memory | 198900 kb |
| Host | smart-7dff43fe-f73a-462b-8619-810a4f90e1ad |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=26733682700239527283525784926048283938600472537316586662385076359233899241589 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 135.uart_fifo_reset.26733682700239527283525784926048283938600472537316586662385076359233899241589 |
| Directory | /workspace/135.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/136.uart_fifo_reset.15315787274377676780617446065819158466107531869592100101564809959381261738199 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 113.54 seconds |
| Started | Nov 22 01:45:56 PM PST 23 |
| Finished | Nov 22 01:47:56 PM PST 23 |
| Peak memory | 198860 kb |
| Host | smart-ba5641ed-9f09-416c-98e7-7a80b3b31ff1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=15315787274377676780617446065819158466107531869592100101564809959381261738199 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 136.uart_fifo_reset.15315787274377676780617446065819158466107531869592100101564809959381261738199 |
| Directory | /workspace/136.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/137.uart_fifo_reset.52459171524259169749190733992598579397750692534407275907635260776349084016672 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 112.48 seconds |
| Started | Nov 22 01:45:43 PM PST 23 |
| Finished | Nov 22 01:47:37 PM PST 23 |
| Peak memory | 198900 kb |
| Host | smart-fc78cc24-294b-4afd-86b4-e6db4734f649 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=52459171524259169749190733992598579397750692534407275907635260776349084016672 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 137.uart_fifo_reset.52459171524259169749190733992598579397750692534407275907635260776349084016672 |
| Directory | /workspace/137.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/138.uart_fifo_reset.72121349959884063709302566070283598763329985824965689263479680557845441517672 |
| Short name | T970 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 112.47 seconds |
| Started | Nov 22 01:45:50 PM PST 23 |
| Finished | Nov 22 01:47:44 PM PST 23 |
| Peak memory | 198908 kb |
| Host | smart-6bab866f-4eb6-45cd-93bb-826d2ed121c5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=72121349959884063709302566070283598763329985824965689263479680557845441517672 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 138.uart_fifo_reset.72121349959884063709302566070283598763329985824965689263479680557845441517672 |
| Directory | /workspace/138.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/139.uart_fifo_reset.48588365325312969947313841567599222048696035187998745390024923059059352525771 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 112.75 seconds |
| Started | Nov 22 01:46:06 PM PST 23 |
| Finished | Nov 22 01:48:06 PM PST 23 |
| Peak memory | 198868 kb |
| Host | smart-c3b23a6d-8261-431b-bea2-4abb0900c6ab |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=48588365325312969947313841567599222048696035187998745390024923059059352525771 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 139.uart_fifo_reset.48588365325312969947313841567599222048696035187998745390024923059059352525771 |
| Directory | /workspace/139.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/14.uart_alert_test.12875072194954100427964274920722727953969630049762016902405154908650423947638 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 16368684 ps |
| CPU time | 0.53 seconds |
| Started | Nov 22 01:44:23 PM PST 23 |
| Finished | Nov 22 01:44:30 PM PST 23 |
| Peak memory | 194608 kb |
| Host | smart-9af08870-cf6f-4206-a396-7302d87a0137 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12875072194954100427964274920722727953969630049762016902405154908650423947638 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 14.uart_alert_test.12875072194954100427964274920722727953969630049762016902405154908650423947638 |
| Directory | /workspace/14.uart_alert_test/latest |
| Test location | /workspace/coverage/default/14.uart_fifo_full.47091474627815057947300011893208823129337407995064138298230976132638949319821 |
| Short name | T742 |
| Test name | |
| Test status | |
| Simulation time | 61777160308 ps |
| CPU time | 60.94 seconds |
| Started | Nov 22 01:44:06 PM PST 23 |
| Finished | Nov 22 01:45:12 PM PST 23 |
| Peak memory | 200080 kb |
| Host | smart-67366b3d-0e30-4de2-8310-3c2b421d040d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=47091474627815057947300011893208823129337407995064138298230976132638949319821 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 14.uart_fifo_full.47091474627815057947300011893208823129337407995064138298230976132638949319821 |
| Directory | /workspace/14.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/14.uart_fifo_reset.41442433410847499495931817380680597225215129907629261133835286989561590765014 |
| Short name | T1247 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 113.49 seconds |
| Started | Nov 22 01:44:16 PM PST 23 |
| Finished | Nov 22 01:46:14 PM PST 23 |
| Peak memory | 198892 kb |
| Host | smart-506805d0-1660-450d-be3b-e337621260af |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=41442433410847499495931817380680597225215129907629261133835286989561590765014 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 14.uart_fifo_reset.41442433410847499495931817380680597225215129907629261133835286989561590765014 |
| Directory | /workspace/14.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/14.uart_intr.107463575149739088593756988859262654804024432949958536938785275704987881006923 |
| Short name | T931 |
| Test name | |
| Test status | |
| Simulation time | 787145125175 ps |
| CPU time | 784.07 seconds |
| Started | Nov 22 01:44:16 PM PST 23 |
| Finished | Nov 22 01:57:25 PM PST 23 |
| Peak memory | 200080 kb |
| Host | smart-ab114133-63d7-42c6-b314-9925d323a7ce |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107463575149739088593756988859262654804024432949958536938785275704987881006923 -assert nopos tproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 14.uart_intr.107463575149739088593756988859262654804024432949958536938785275704987881006923 |
| Directory | /workspace/14.uart_intr/latest |
| Test location | /workspace/coverage/default/14.uart_long_xfer_wo_dly.22321570364587431747623665050918198013146995978690923398235072535953015103791 |
| Short name | T1165 |
| Test name | |
| Test status | |
| Simulation time | 93387746707 ps |
| CPU time | 356.8 seconds |
| Started | Nov 22 01:44:36 PM PST 23 |
| Finished | Nov 22 01:50:36 PM PST 23 |
| Peak memory | 200108 kb |
| Host | smart-485608f4-00f6-46e7-8560-1539b2deab0b |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=22321570364587431747623665050918198013146995978690923398235072535953015103791 -assert nopostproc +UVM_TES TNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 14.uart_long_xfer_wo_dly.22321570364587431747623665050918198013146995978690923398235072535953015103791 |
| Directory | /workspace/14.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/14.uart_loopback.40157296135430656852638543525075817576597779599251330460986541586038602255323 |
| Short name | T933 |
| Test name | |
| Test status | |
| Simulation time | 14572448663 ps |
| CPU time | 16.59 seconds |
| Started | Nov 22 01:44:04 PM PST 23 |
| Finished | Nov 22 01:44:25 PM PST 23 |
| Peak memory | 200048 kb |
| Host | smart-8c2e30fd-43a4-444c-8360-bd09225f8b4b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=40157296135430656852638543525075817576597779599251330460986541586038602255323 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 14.uart_loopback.40157296135430656852638543525075817576597779599251330460986541586038602255323 |
| Directory | /workspace/14.uart_loopback/latest |
| Test location | /workspace/coverage/default/14.uart_noise_filter.49590582944836769548890845256964996406406370263738027398380694426032274209894 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 94501577082 ps |
| CPU time | 97.61 seconds |
| Started | Nov 22 01:44:14 PM PST 23 |
| Finished | Nov 22 01:45:55 PM PST 23 |
| Peak memory | 200248 kb |
| Host | smart-2201295c-d846-4a2a-8f8f-4d5a0b047711 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=49590582944836769548890845256964996406406370263738027398380694426032274209894 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_noise_filter.49590582944836769548890845256964996406406370263738027398380694426032274209894 |
| Directory | /workspace/14.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/14.uart_perf.80477223906014534979797663811230702902660170897234586907315374121649914552852 |
| Short name | T817 |
| Test name | |
| Test status | |
| Simulation time | 14098773881 ps |
| CPU time | 475.79 seconds |
| Started | Nov 22 01:44:20 PM PST 23 |
| Finished | Nov 22 01:52:23 PM PST 23 |
| Peak memory | 200136 kb |
| Host | smart-7152a948-5bfa-44e8-9601-06c999224593 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=80477223906014534979797663811230702902660170897234586907315374121649914552852 -assert nopostproc +UVM_TES TNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 14.uart_perf.80477223906014534979797663811230702902660170897234586907315374121649914552852 |
| Directory | /workspace/14.uart_perf/latest |
| Test location | /workspace/coverage/default/14.uart_rx_oversample.80171310942071018239199503970722083052327164945059353171633588186438231200208 |
| Short name | T778 |
| Test name | |
| Test status | |
| Simulation time | 4370280281 ps |
| CPU time | 20.15 seconds |
| Started | Nov 22 01:44:09 PM PST 23 |
| Finished | Nov 22 01:44:34 PM PST 23 |
| Peak memory | 198944 kb |
| Host | smart-d43bcefd-256e-41e5-9382-c2be834b41d1 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=80171310942071018239199503970722083052327164945059353171633588186438231200208 -assert nopostproc +UVM_TES TNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 14.uart_rx_oversample.80171310942071018239199503970722083052327164945059353171633588186438231200208 |
| Directory | /workspace/14.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/14.uart_rx_parity_err.41942671039634154358623901224017994030365873114083325896627622066524205723663 |
| Short name | T1141 |
| Test name | |
| Test status | |
| Simulation time | 36616611594 ps |
| CPU time | 38 seconds |
| Started | Nov 22 01:44:13 PM PST 23 |
| Finished | Nov 22 01:44:55 PM PST 23 |
| Peak memory | 200124 kb |
| Host | smart-0e7c6323-5e0c-45e4-b355-c6fee1288319 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=41942671039634154358623901224017994030365873114083325896627622066524205723663 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 14.uart_rx_parity_err.41942671039634154358623901224017994030365873114083325896627622066524205723663 |
| Directory | /workspace/14.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/14.uart_rx_start_bit_filter.11860524584109528686600600544749776669540224570793348039222036191418800048611 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 4267638245 ps |
| CPU time | 4.74 seconds |
| Started | Nov 22 01:44:07 PM PST 23 |
| Finished | Nov 22 01:44:17 PM PST 23 |
| Peak memory | 195904 kb |
| Host | smart-245257df-a357-4977-8570-b1df5da03c0c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=11860524584109528686600600544749776669540224570793348039222036191418800048611 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 14.uart_rx_start_bit_filter.11860524584109528686600600544749776669540224570793348039222036191418800048611 |
| Directory | /workspace/14.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/14.uart_smoke.43328859359295274467505050294770471596605143618439790293731158602452506493483 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 5759626309 ps |
| CPU time | 19.48 seconds |
| Started | Nov 22 01:44:11 PM PST 23 |
| Finished | Nov 22 01:44:33 PM PST 23 |
| Peak memory | 199636 kb |
| Host | smart-62989695-b12b-4783-a2db-34bab4dcf9d1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=43328859359295274467505050294770471596605143618439790293731158602452506493483 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 14.uart_smoke.43328859359295274467505050294770471596605143618439790293731158602452506493483 |
| Directory | /workspace/14.uart_smoke/latest |
| Test location | /workspace/coverage/default/14.uart_stress_all.90269700925329570251794964733132540159561553529853741842755091696128369763491 |
| Short name | T922 |
| Test name | |
| Test status | |
| Simulation time | 43402307308 ps |
| CPU time | 57.3 seconds |
| Started | Nov 22 01:44:19 PM PST 23 |
| Finished | Nov 22 01:45:19 PM PST 23 |
| Peak memory | 199888 kb |
| Host | smart-17f57f8b-f6bd-4c05-8257-a5cf44fa5b6b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90269700925329570251794964733132540159561553529853741842755091696128369763491 -assert nopos tproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 14.uart_stress_all.90269700925329570251794964733132540159561553529853741842755091696128369763491 |
| Directory | /workspace/14.uart_stress_all/latest |
| Test location | /workspace/coverage/default/14.uart_stress_all_with_rand_reset.78371716428848382214091364707450432115296812915994431388386899075686261748236 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 87476847566 ps |
| CPU time | 459.35 seconds |
| Started | Nov 22 01:44:23 PM PST 23 |
| Finished | Nov 22 01:52:09 PM PST 23 |
| Peak memory | 226260 kb |
| Host | smart-88144a0a-1f6d-4137-9dde-fcb791c206b7 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78371716428848382214091364 707450432115296812915994431388386899075686261748236 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_stress_all_with_rand_reset.7837171642884 8382214091364707450432115296812915994431388386899075686261748236 |
| Directory | /workspace/14.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/14.uart_tx_ovrd.36818764701291683024533113264035656794264432776595324230416178948089427798913 |
| Short name | T796 |
| Test name | |
| Test status | |
| Simulation time | 485186362 ps |
| CPU time | 1.27 seconds |
| Started | Nov 22 01:44:10 PM PST 23 |
| Finished | Nov 22 01:44:15 PM PST 23 |
| Peak memory | 197908 kb |
| Host | smart-ad962a4f-bb69-49d3-bbf8-6d2381e222f7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=36818764701291683024533113264035656794264432776595324230416178948089427798913 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 14.uart_tx_ovrd.36818764701291683024533113264035656794264432776595324230416178948089427798913 |
| Directory | /workspace/14.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/14.uart_tx_rx.44613117564664505238606992216371239523297905887812361046911028730598920700600 |
| Short name | T1008 |
| Test name | |
| Test status | |
| Simulation time | 57391945390 ps |
| CPU time | 63.53 seconds |
| Started | Nov 22 01:44:13 PM PST 23 |
| Finished | Nov 22 01:45:20 PM PST 23 |
| Peak memory | 199912 kb |
| Host | smart-67c48017-4420-4de8-a61d-703654fe5865 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=44613117564664505238606992216371239523297905887812361046911028730598920700600 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 14.uart_tx_rx.44613117564664505238606992216371239523297905887812361046911028730598920700600 |
| Directory | /workspace/14.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/140.uart_fifo_reset.3716656583264354771645718954498969300283611477777004164451565364887670442721 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 113.86 seconds |
| Started | Nov 22 01:45:53 PM PST 23 |
| Finished | Nov 22 01:47:50 PM PST 23 |
| Peak memory | 198756 kb |
| Host | smart-b39886fe-46ce-4fad-8023-e373d9e79c98 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3716656583264354771645718954498969300283611477777004164451565364887670442721 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 140.uart_fifo_reset.3716656583264354771645718954498969300283611477777004164451565364887670442721 |
| Directory | /workspace/140.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/141.uart_fifo_reset.21694079656968631445270463068446129164109131396240208558041641793443208623106 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 113.5 seconds |
| Started | Nov 22 01:46:04 PM PST 23 |
| Finished | Nov 22 01:48:05 PM PST 23 |
| Peak memory | 198760 kb |
| Host | smart-a7a78df5-4fa9-4f15-b2d9-3e7c12f65bc0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=21694079656968631445270463068446129164109131396240208558041641793443208623106 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 141.uart_fifo_reset.21694079656968631445270463068446129164109131396240208558041641793443208623106 |
| Directory | /workspace/141.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/142.uart_fifo_reset.6036818554177964356493013064969752187678793722421383966335791105938846947809 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 112.79 seconds |
| Started | Nov 22 01:46:05 PM PST 23 |
| Finished | Nov 22 01:48:05 PM PST 23 |
| Peak memory | 198856 kb |
| Host | smart-b9813eec-0505-4eb5-bd27-ddef99afffb4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=6036818554177964356493013064969752187678793722421383966335791105938846947809 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 142.uart_fifo_reset.6036818554177964356493013064969752187678793722421383966335791105938846947809 |
| Directory | /workspace/142.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/143.uart_fifo_reset.3511587434514982466732588432266314276562517614323866194878849420989057833786 |
| Short name | T1167 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 113.4 seconds |
| Started | Nov 22 01:46:07 PM PST 23 |
| Finished | Nov 22 01:48:07 PM PST 23 |
| Peak memory | 198920 kb |
| Host | smart-c29b6d87-973c-4e29-b5f7-f816660e27bc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3511587434514982466732588432266314276562517614323866194878849420989057833786 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 143.uart_fifo_reset.3511587434514982466732588432266314276562517614323866194878849420989057833786 |
| Directory | /workspace/143.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/144.uart_fifo_reset.111220664472763661525225790205502103511389406518684936230532870482093162016488 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 112.98 seconds |
| Started | Nov 22 01:46:02 PM PST 23 |
| Finished | Nov 22 01:48:01 PM PST 23 |
| Peak memory | 198884 kb |
| Host | smart-abb2b65b-1e35-48f2-ad0a-621ae645680a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=111220664472763661525225790205502103511389406518684936230532870482093162016488 -assert nopostproc +UVM_TESTNAME=uart_bas e_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.uart_fifo_reset.111220664472763661525225790205502103511389406518684936230532870482093162016488 |
| Directory | /workspace/144.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/145.uart_fifo_reset.82845104221315099421804465720873313769626968831049422254325953802743567386449 |
| Short name | T1057 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 113.87 seconds |
| Started | Nov 22 01:45:51 PM PST 23 |
| Finished | Nov 22 01:47:46 PM PST 23 |
| Peak memory | 198964 kb |
| Host | smart-3e81aa5b-9b38-455d-83e8-71b1878d0c02 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=82845104221315099421804465720873313769626968831049422254325953802743567386449 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 145.uart_fifo_reset.82845104221315099421804465720873313769626968831049422254325953802743567386449 |
| Directory | /workspace/145.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/146.uart_fifo_reset.5605356405696778378228142135798120352329020911022644267701419996826079679880 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 113.45 seconds |
| Started | Nov 22 01:46:09 PM PST 23 |
| Finished | Nov 22 01:48:08 PM PST 23 |
| Peak memory | 198760 kb |
| Host | smart-96b868c1-6c24-4717-840f-5f7cef2617af |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=5605356405696778378228142135798120352329020911022644267701419996826079679880 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 146.uart_fifo_reset.5605356405696778378228142135798120352329020911022644267701419996826079679880 |
| Directory | /workspace/146.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/147.uart_fifo_reset.74531297410413414702581460515348168698069027027259895974371806238740607019742 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 113.11 seconds |
| Started | Nov 22 01:45:43 PM PST 23 |
| Finished | Nov 22 01:47:38 PM PST 23 |
| Peak memory | 198900 kb |
| Host | smart-d5b8f7e8-df49-4362-af0f-0f920d309468 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=74531297410413414702581460515348168698069027027259895974371806238740607019742 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 147.uart_fifo_reset.74531297410413414702581460515348168698069027027259895974371806238740607019742 |
| Directory | /workspace/147.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/148.uart_fifo_reset.78630860618134268855615201363589405580036277632639744235697309114944944150258 |
| Short name | T1104 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 113.71 seconds |
| Started | Nov 22 01:45:46 PM PST 23 |
| Finished | Nov 22 01:47:41 PM PST 23 |
| Peak memory | 198900 kb |
| Host | smart-d033c58f-a239-46cc-ae82-acc171d263b3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=78630860618134268855615201363589405580036277632639744235697309114944944150258 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 148.uart_fifo_reset.78630860618134268855615201363589405580036277632639744235697309114944944150258 |
| Directory | /workspace/148.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/149.uart_fifo_reset.70915622344052791475785218077369347086649762893296729287459500341343743999973 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 113.13 seconds |
| Started | Nov 22 01:45:48 PM PST 23 |
| Finished | Nov 22 01:47:43 PM PST 23 |
| Peak memory | 198756 kb |
| Host | smart-b2128700-78ec-415d-9061-bf03d6687582 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=70915622344052791475785218077369347086649762893296729287459500341343743999973 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 149.uart_fifo_reset.70915622344052791475785218077369347086649762893296729287459500341343743999973 |
| Directory | /workspace/149.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/15.uart_alert_test.51183049672785576321994093864174233673689206407310407704786092783729941645549 |
| Short name | T1065 |
| Test name | |
| Test status | |
| Simulation time | 16368684 ps |
| CPU time | 0.53 seconds |
| Started | Nov 22 01:44:29 PM PST 23 |
| Finished | Nov 22 01:44:37 PM PST 23 |
| Peak memory | 194576 kb |
| Host | smart-9e0329d9-b856-4b46-ac72-56a43d43076b |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51183049672785576321994093864174233673689206407310407704786092783729941645549 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 15.uart_alert_test.51183049672785576321994093864174233673689206407310407704786092783729941645549 |
| Directory | /workspace/15.uart_alert_test/latest |
| Test location | /workspace/coverage/default/15.uart_fifo_full.29950165360341547154985881825528281583338073575986237939219906479014474730258 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 61777160308 ps |
| CPU time | 61.08 seconds |
| Started | Nov 22 01:44:27 PM PST 23 |
| Finished | Nov 22 01:45:32 PM PST 23 |
| Peak memory | 200104 kb |
| Host | smart-b875012a-87d5-4255-aa27-272f86a0b8f1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=29950165360341547154985881825528281583338073575986237939219906479014474730258 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 15.uart_fifo_full.29950165360341547154985881825528281583338073575986237939219906479014474730258 |
| Directory | /workspace/15.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/15.uart_fifo_overflow.86762354243658748047500416287457752180689054734280787365753851436461162832896 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 58551936110 ps |
| CPU time | 55.15 seconds |
| Started | Nov 22 01:44:07 PM PST 23 |
| Finished | Nov 22 01:45:07 PM PST 23 |
| Peak memory | 199852 kb |
| Host | smart-b8c07b1e-c097-4e36-9e46-bc9b5bf06b0d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=86762354243658748047500416287457752180689054734280787365753851436461162832896 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 15.uart_fifo_overflow.86762354243658748047500416287457752180689054734280787365753851436461162832896 |
| Directory | /workspace/15.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/15.uart_fifo_reset.92387835564703351645615589199345207895441541198090866379062332635114434111529 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 113.2 seconds |
| Started | Nov 22 01:44:39 PM PST 23 |
| Finished | Nov 22 01:46:34 PM PST 23 |
| Peak memory | 198912 kb |
| Host | smart-b2f0b4eb-52c6-4fd4-a087-04c4e78ab601 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=92387835564703351645615589199345207895441541198090866379062332635114434111529 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 15.uart_fifo_reset.92387835564703351645615589199345207895441541198090866379062332635114434111529 |
| Directory | /workspace/15.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/15.uart_intr.97248042538774893348378382847952316369329834570513132283734130474677472234984 |
| Short name | T1036 |
| Test name | |
| Test status | |
| Simulation time | 787145125175 ps |
| CPU time | 784.32 seconds |
| Started | Nov 22 01:44:17 PM PST 23 |
| Finished | Nov 22 01:57:26 PM PST 23 |
| Peak memory | 200144 kb |
| Host | smart-a145c8ac-0096-4803-8f52-6cd5dd5d4f2b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97248042538774893348378382847952316369329834570513132283734130474677472234984 -assert nopost proc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 15.uart_intr.97248042538774893348378382847952316369329834570513132283734130474677472234984 |
| Directory | /workspace/15.uart_intr/latest |
| Test location | /workspace/coverage/default/15.uart_long_xfer_wo_dly.107618447414650296213128770018087161565952735044916618456426659970242165719919 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 93387746707 ps |
| CPU time | 356.19 seconds |
| Started | Nov 22 01:44:04 PM PST 23 |
| Finished | Nov 22 01:50:05 PM PST 23 |
| Peak memory | 200136 kb |
| Host | smart-152267bd-0823-400a-b7d8-e1b23848a8f8 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=107618447414650296213128770018087161565952735044916618456426659970242165719919 -assert nopostproc +UVM_TE STNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 15.uart_long_xfer_wo_dly.107618447414650296213128770018087161565952735044916618456426659970242165719919 |
| Directory | /workspace/15.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/15.uart_loopback.60282293853337382138886366159812773116235410196028197599227810698136130266764 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 14572448663 ps |
| CPU time | 16.05 seconds |
| Started | Nov 22 01:44:31 PM PST 23 |
| Finished | Nov 22 01:44:53 PM PST 23 |
| Peak memory | 200044 kb |
| Host | smart-792e426e-1b87-43b2-b4b3-afa38edf60f6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=60282293853337382138886366159812773116235410196028197599227810698136130266764 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 15.uart_loopback.60282293853337382138886366159812773116235410196028197599227810698136130266764 |
| Directory | /workspace/15.uart_loopback/latest |
| Test location | /workspace/coverage/default/15.uart_noise_filter.77805723668226252696360401830208552045163265697770052550553078472070869495576 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 94501577082 ps |
| CPU time | 97.45 seconds |
| Started | Nov 22 01:44:31 PM PST 23 |
| Finished | Nov 22 01:46:15 PM PST 23 |
| Peak memory | 200240 kb |
| Host | smart-25e20d20-032d-4d43-8520-6b7e5b3c3a3e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=77805723668226252696360401830208552045163265697770052550553078472070869495576 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_noise_filter.77805723668226252696360401830208552045163265697770052550553078472070869495576 |
| Directory | /workspace/15.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/15.uart_perf.20255068732558268863141592988801704263969868809210677520123062586632519443127 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 14098773881 ps |
| CPU time | 467.69 seconds |
| Started | Nov 22 01:44:33 PM PST 23 |
| Finished | Nov 22 01:52:26 PM PST 23 |
| Peak memory | 200152 kb |
| Host | smart-33dbf361-333d-4cc7-a330-5278536f63e5 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=20255068732558268863141592988801704263969868809210677520123062586632519443127 -assert nopostproc +UVM_TES TNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 15.uart_perf.20255068732558268863141592988801704263969868809210677520123062586632519443127 |
| Directory | /workspace/15.uart_perf/latest |
| Test location | /workspace/coverage/default/15.uart_rx_oversample.1172292331764499284287210619818264232264807681011785237396101403084556025577 |
| Short name | T973 |
| Test name | |
| Test status | |
| Simulation time | 4370280281 ps |
| CPU time | 21.07 seconds |
| Started | Nov 22 01:44:07 PM PST 23 |
| Finished | Nov 22 01:44:33 PM PST 23 |
| Peak memory | 198972 kb |
| Host | smart-1de64120-c8e0-4fee-8c8f-1c9e444b7e9a |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1172292331764499284287210619818264232264807681011785237396101403084556025577 -assert nopostproc +UVM_TEST NAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 15.uart_rx_oversample.1172292331764499284287210619818264232264807681011785237396101403084556025577 |
| Directory | /workspace/15.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/15.uart_rx_parity_err.34426292126906063235183587301228246207081840373202233255762009472845742761170 |
| Short name | T892 |
| Test name | |
| Test status | |
| Simulation time | 36616611594 ps |
| CPU time | 37.88 seconds |
| Started | Nov 22 01:44:44 PM PST 23 |
| Finished | Nov 22 01:45:23 PM PST 23 |
| Peak memory | 199936 kb |
| Host | smart-161aa8a8-9005-46ad-bb13-79b1b2e1e26c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=34426292126906063235183587301228246207081840373202233255762009472845742761170 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 15.uart_rx_parity_err.34426292126906063235183587301228246207081840373202233255762009472845742761170 |
| Directory | /workspace/15.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/15.uart_rx_start_bit_filter.79384205775639364374679630329092159102296055117758247982130524293905192738784 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 4267638245 ps |
| CPU time | 4.75 seconds |
| Started | Nov 22 01:44:19 PM PST 23 |
| Finished | Nov 22 01:44:27 PM PST 23 |
| Peak memory | 195988 kb |
| Host | smart-46e4da79-537b-4c78-af76-1f80200554d6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=79384205775639364374679630329092159102296055117758247982130524293905192738784 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 15.uart_rx_start_bit_filter.79384205775639364374679630329092159102296055117758247982130524293905192738784 |
| Directory | /workspace/15.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/15.uart_smoke.75550861196592247317056412273853347756703215793663265326096250009573398224670 |
| Short name | T763 |
| Test name | |
| Test status | |
| Simulation time | 5759626309 ps |
| CPU time | 19.05 seconds |
| Started | Nov 22 01:44:17 PM PST 23 |
| Finished | Nov 22 01:44:40 PM PST 23 |
| Peak memory | 199644 kb |
| Host | smart-2b7b2392-89cc-48fb-90e6-b20d14a70a9f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=75550861196592247317056412273853347756703215793663265326096250009573398224670 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 15.uart_smoke.75550861196592247317056412273853347756703215793663265326096250009573398224670 |
| Directory | /workspace/15.uart_smoke/latest |
| Test location | /workspace/coverage/default/15.uart_stress_all.45066781046117255684310558149241876175610620674109193801043317135932645079452 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 43402307308 ps |
| CPU time | 57.65 seconds |
| Started | Nov 22 01:44:39 PM PST 23 |
| Finished | Nov 22 01:45:39 PM PST 23 |
| Peak memory | 200128 kb |
| Host | smart-37cd8e7c-d8d0-4a4d-934e-1f9bbefd5517 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45066781046117255684310558149241876175610620674109193801043317135932645079452 -assert nopos tproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 15.uart_stress_all.45066781046117255684310558149241876175610620674109193801043317135932645079452 |
| Directory | /workspace/15.uart_stress_all/latest |
| Test location | /workspace/coverage/default/15.uart_stress_all_with_rand_reset.5872383103491456405632885919452494621411476822690293898050440667434477487277 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 87476847566 ps |
| CPU time | 465.27 seconds |
| Started | Nov 22 01:44:38 PM PST 23 |
| Finished | Nov 22 01:52:25 PM PST 23 |
| Peak memory | 226208 kb |
| Host | smart-8a23bebb-07aa-43d8-a7d9-d7ef3e14f2e9 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58723831034914564056328859 19452494621411476822690293898050440667434477487277 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_stress_all_with_rand_reset.58723831034914 56405632885919452494621411476822690293898050440667434477487277 |
| Directory | /workspace/15.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/15.uart_tx_ovrd.14086479608402980466599182390379353679159522257110707676543372652514562058238 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 485186362 ps |
| CPU time | 1.27 seconds |
| Started | Nov 22 01:44:05 PM PST 23 |
| Finished | Nov 22 01:44:12 PM PST 23 |
| Peak memory | 197992 kb |
| Host | smart-8dbd9df1-08a2-4440-b925-4bb6c40a0e60 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=14086479608402980466599182390379353679159522257110707676543372652514562058238 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 15.uart_tx_ovrd.14086479608402980466599182390379353679159522257110707676543372652514562058238 |
| Directory | /workspace/15.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/15.uart_tx_rx.7338632323777458678898171066497464331440696233895785591287177319123291361168 |
| Short name | T856 |
| Test name | |
| Test status | |
| Simulation time | 57391945390 ps |
| CPU time | 63.36 seconds |
| Started | Nov 22 01:44:03 PM PST 23 |
| Finished | Nov 22 01:45:11 PM PST 23 |
| Peak memory | 200040 kb |
| Host | smart-8f522892-677f-4890-b70d-cf4a7dac96f5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=7338632323777458678898171066497464331440696233895785591287177319123291361168 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 15.uart_tx_rx.7338632323777458678898171066497464331440696233895785591287177319123291361168 |
| Directory | /workspace/15.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/150.uart_fifo_reset.60999558779334125854913274325185157970392860046336534570263502638284746963984 |
| Short name | T1274 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 113.53 seconds |
| Started | Nov 22 01:46:06 PM PST 23 |
| Finished | Nov 22 01:48:06 PM PST 23 |
| Peak memory | 198872 kb |
| Host | smart-7f58e0b1-c07e-4ddb-876b-2a2ab147d0b7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=60999558779334125854913274325185157970392860046336534570263502638284746963984 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 150.uart_fifo_reset.60999558779334125854913274325185157970392860046336534570263502638284746963984 |
| Directory | /workspace/150.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/151.uart_fifo_reset.48643182349751425067448080651025314477943966227732128042052228401379273168637 |
| Short name | T1133 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 113.18 seconds |
| Started | Nov 22 01:46:02 PM PST 23 |
| Finished | Nov 22 01:48:01 PM PST 23 |
| Peak memory | 198892 kb |
| Host | smart-56139734-55ce-48a0-86d7-c02ccfb877f3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=48643182349751425067448080651025314477943966227732128042052228401379273168637 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 151.uart_fifo_reset.48643182349751425067448080651025314477943966227732128042052228401379273168637 |
| Directory | /workspace/151.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/152.uart_fifo_reset.101756584858510948257978700761066730063790858936300506999387357446897389244406 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 113.09 seconds |
| Started | Nov 22 01:46:09 PM PST 23 |
| Finished | Nov 22 01:48:07 PM PST 23 |
| Peak memory | 198904 kb |
| Host | smart-a944a006-b5a5-4811-b9fe-b5053dc20d10 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=101756584858510948257978700761066730063790858936300506999387357446897389244406 -assert nopostproc +UVM_TESTNAME=uart_bas e_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.uart_fifo_reset.101756584858510948257978700761066730063790858936300506999387357446897389244406 |
| Directory | /workspace/152.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/153.uart_fifo_reset.15342787023061543199819307258526920233704608259061389517646854012378571130058 |
| Short name | T802 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 112.54 seconds |
| Started | Nov 22 01:46:20 PM PST 23 |
| Finished | Nov 22 01:48:14 PM PST 23 |
| Peak memory | 198908 kb |
| Host | smart-4473530b-2c68-4594-a964-ac77e5d26203 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=15342787023061543199819307258526920233704608259061389517646854012378571130058 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 153.uart_fifo_reset.15342787023061543199819307258526920233704608259061389517646854012378571130058 |
| Directory | /workspace/153.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/154.uart_fifo_reset.87094426634990012804337688990928312416947982357549942725531515889343324397316 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 112.85 seconds |
| Started | Nov 22 01:46:01 PM PST 23 |
| Finished | Nov 22 01:48:00 PM PST 23 |
| Peak memory | 198732 kb |
| Host | smart-d137e44f-8f46-4afa-a68c-4780d22c4c4f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=87094426634990012804337688990928312416947982357549942725531515889343324397316 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 154.uart_fifo_reset.87094426634990012804337688990928312416947982357549942725531515889343324397316 |
| Directory | /workspace/154.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/155.uart_fifo_reset.109835003025044702600434919541823864582856785120349633015084482268729041166415 |
| Short name | T1126 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 113.06 seconds |
| Started | Nov 22 01:46:00 PM PST 23 |
| Finished | Nov 22 01:48:00 PM PST 23 |
| Peak memory | 198704 kb |
| Host | smart-fe95de2d-c780-4b54-a96a-400402491036 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=109835003025044702600434919541823864582856785120349633015084482268729041166415 -assert nopostproc +UVM_TESTNAME=uart_bas e_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.uart_fifo_reset.109835003025044702600434919541823864582856785120349633015084482268729041166415 |
| Directory | /workspace/155.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/156.uart_fifo_reset.16340232028750024389153595471718349878453070491984237370640142862684213288897 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 112.91 seconds |
| Started | Nov 22 01:46:10 PM PST 23 |
| Finished | Nov 22 01:48:08 PM PST 23 |
| Peak memory | 198844 kb |
| Host | smart-a1c69324-8fb8-4f57-8063-1d025fee0c85 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=16340232028750024389153595471718349878453070491984237370640142862684213288897 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 156.uart_fifo_reset.16340232028750024389153595471718349878453070491984237370640142862684213288897 |
| Directory | /workspace/156.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/157.uart_fifo_reset.33497668403949346079836360834726351684971852941232334139190232561098249539478 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 113.13 seconds |
| Started | Nov 22 01:46:03 PM PST 23 |
| Finished | Nov 22 01:48:01 PM PST 23 |
| Peak memory | 198760 kb |
| Host | smart-fab4e9c6-072c-4a6c-8edc-f710373a1d9f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=33497668403949346079836360834726351684971852941232334139190232561098249539478 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 157.uart_fifo_reset.33497668403949346079836360834726351684971852941232334139190232561098249539478 |
| Directory | /workspace/157.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/158.uart_fifo_reset.11566894881157277311399739066577514388325349634717325571648966238071406653953 |
| Short name | T1245 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 113.89 seconds |
| Started | Nov 22 01:45:48 PM PST 23 |
| Finished | Nov 22 01:47:43 PM PST 23 |
| Peak memory | 198756 kb |
| Host | smart-f308a88b-f00d-4c51-bda5-f00c3c5d2754 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=11566894881157277311399739066577514388325349634717325571648966238071406653953 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 158.uart_fifo_reset.11566894881157277311399739066577514388325349634717325571648966238071406653953 |
| Directory | /workspace/158.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/159.uart_fifo_reset.69875738503595307844331048869217930082513114799812833799722463849020785978767 |
| Short name | T1075 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 113.06 seconds |
| Started | Nov 22 01:46:09 PM PST 23 |
| Finished | Nov 22 01:48:07 PM PST 23 |
| Peak memory | 198844 kb |
| Host | smart-86ecaef9-a56c-4265-ac42-9d56d8c3223b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=69875738503595307844331048869217930082513114799812833799722463849020785978767 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 159.uart_fifo_reset.69875738503595307844331048869217930082513114799812833799722463849020785978767 |
| Directory | /workspace/159.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/16.uart_alert_test.44894746217823999918752876825515255402704472656458127324418759809793161735246 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 16368684 ps |
| CPU time | 0.53 seconds |
| Started | Nov 22 01:44:40 PM PST 23 |
| Finished | Nov 22 01:44:42 PM PST 23 |
| Peak memory | 194564 kb |
| Host | smart-e409868e-aa51-4371-938f-9747b0d42542 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44894746217823999918752876825515255402704472656458127324418759809793161735246 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 16.uart_alert_test.44894746217823999918752876825515255402704472656458127324418759809793161735246 |
| Directory | /workspace/16.uart_alert_test/latest |
| Test location | /workspace/coverage/default/16.uart_fifo_full.81508351841643978845216284775203401123165799715934063662570726720946061591007 |
| Short name | T1192 |
| Test name | |
| Test status | |
| Simulation time | 61777160308 ps |
| CPU time | 60.93 seconds |
| Started | Nov 22 01:44:14 PM PST 23 |
| Finished | Nov 22 01:45:19 PM PST 23 |
| Peak memory | 200016 kb |
| Host | smart-b18fef3e-d69f-4b1a-8441-9dbb6f580988 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=81508351841643978845216284775203401123165799715934063662570726720946061591007 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 16.uart_fifo_full.81508351841643978845216284775203401123165799715934063662570726720946061591007 |
| Directory | /workspace/16.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/16.uart_fifo_overflow.54440523641696045518255239748177007900946555536082911520147206381161512642896 |
| Short name | T1158 |
| Test name | |
| Test status | |
| Simulation time | 58551936110 ps |
| CPU time | 54.93 seconds |
| Started | Nov 22 01:44:19 PM PST 23 |
| Finished | Nov 22 01:45:17 PM PST 23 |
| Peak memory | 199528 kb |
| Host | smart-f009e425-ab48-4480-84ef-83b57b4c1591 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=54440523641696045518255239748177007900946555536082911520147206381161512642896 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 16.uart_fifo_overflow.54440523641696045518255239748177007900946555536082911520147206381161512642896 |
| Directory | /workspace/16.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/16.uart_fifo_reset.110051246319388328635285620089605695084316114767769006175406190789964796135160 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 113.62 seconds |
| Started | Nov 22 01:44:18 PM PST 23 |
| Finished | Nov 22 01:46:15 PM PST 23 |
| Peak memory | 198880 kb |
| Host | smart-0e0a773b-5e76-42d3-8f80-827ccb8d41f2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=110051246319388328635285620089605695084316114767769006175406190789964796135160 -assert nopostproc +UVM_TESTNAME=uart_bas e_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_reset.110051246319388328635285620089605695084316114767769006175406190789964796135160 |
| Directory | /workspace/16.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/16.uart_intr.97420168417714238271396916823657272787178484346078069758598764794623285116892 |
| Short name | T966 |
| Test name | |
| Test status | |
| Simulation time | 787145125175 ps |
| CPU time | 785.9 seconds |
| Started | Nov 22 01:44:34 PM PST 23 |
| Finished | Nov 22 01:57:44 PM PST 23 |
| Peak memory | 200000 kb |
| Host | smart-4a3c556f-660c-4b5d-8476-a9726b948c5e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97420168417714238271396916823657272787178484346078069758598764794623285116892 -assert nopost proc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 16.uart_intr.97420168417714238271396916823657272787178484346078069758598764794623285116892 |
| Directory | /workspace/16.uart_intr/latest |
| Test location | /workspace/coverage/default/16.uart_long_xfer_wo_dly.107823670320479131284463280664378718050321769851927243975645933014504559861519 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 93387746707 ps |
| CPU time | 350.72 seconds |
| Started | Nov 22 01:44:23 PM PST 23 |
| Finished | Nov 22 01:50:20 PM PST 23 |
| Peak memory | 200080 kb |
| Host | smart-b3daa85d-98cc-48e3-a103-dc8321e66981 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=107823670320479131284463280664378718050321769851927243975645933014504559861519 -assert nopostproc +UVM_TE STNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 16.uart_long_xfer_wo_dly.107823670320479131284463280664378718050321769851927243975645933014504559861519 |
| Directory | /workspace/16.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/16.uart_loopback.29653398002605600010977771488581432303595111975577613636113081026993265817332 |
| Short name | T812 |
| Test name | |
| Test status | |
| Simulation time | 14572448663 ps |
| CPU time | 16.54 seconds |
| Started | Nov 22 01:44:22 PM PST 23 |
| Finished | Nov 22 01:44:44 PM PST 23 |
| Peak memory | 200064 kb |
| Host | smart-e43d4ea1-fec7-4f7a-ba24-96cdb0095827 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=29653398002605600010977771488581432303595111975577613636113081026993265817332 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 16.uart_loopback.29653398002605600010977771488581432303595111975577613636113081026993265817332 |
| Directory | /workspace/16.uart_loopback/latest |
| Test location | /workspace/coverage/default/16.uart_noise_filter.22360725905776005916184394554881525185876530304415188685759688236482607578053 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 94501577082 ps |
| CPU time | 97.58 seconds |
| Started | Nov 22 01:44:31 PM PST 23 |
| Finished | Nov 22 01:46:15 PM PST 23 |
| Peak memory | 200284 kb |
| Host | smart-b1f78716-27a8-4c7a-b46e-58a6ca2293a2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=22360725905776005916184394554881525185876530304415188685759688236482607578053 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_noise_filter.22360725905776005916184394554881525185876530304415188685759688236482607578053 |
| Directory | /workspace/16.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/16.uart_perf.53881178047538461728571321154025828339573847995273187945383731541057948016818 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 14098773881 ps |
| CPU time | 469.33 seconds |
| Started | Nov 22 01:44:27 PM PST 23 |
| Finished | Nov 22 01:52:22 PM PST 23 |
| Peak memory | 200116 kb |
| Host | smart-365729a7-916b-49bb-812c-9c6575b48442 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=53881178047538461728571321154025828339573847995273187945383731541057948016818 -assert nopostproc +UVM_TES TNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 16.uart_perf.53881178047538461728571321154025828339573847995273187945383731541057948016818 |
| Directory | /workspace/16.uart_perf/latest |
| Test location | /workspace/coverage/default/16.uart_rx_oversample.96055457105477968978727457186462215044504661450083181858670022611591818055408 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 4370280281 ps |
| CPU time | 20.22 seconds |
| Started | Nov 22 01:44:16 PM PST 23 |
| Finished | Nov 22 01:44:41 PM PST 23 |
| Peak memory | 198940 kb |
| Host | smart-4807f105-af15-49bc-8252-f521bd16bcdc |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=96055457105477968978727457186462215044504661450083181858670022611591818055408 -assert nopostproc +UVM_TES TNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 16.uart_rx_oversample.96055457105477968978727457186462215044504661450083181858670022611591818055408 |
| Directory | /workspace/16.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/16.uart_rx_parity_err.99623058310370720017564842904814209547983619158408278631433117919372990800133 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 36616611594 ps |
| CPU time | 38.02 seconds |
| Started | Nov 22 01:44:36 PM PST 23 |
| Finished | Nov 22 01:45:17 PM PST 23 |
| Peak memory | 200136 kb |
| Host | smart-d9355b4e-200a-4229-9182-dc81533b25c5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=99623058310370720017564842904814209547983619158408278631433117919372990800133 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 16.uart_rx_parity_err.99623058310370720017564842904814209547983619158408278631433117919372990800133 |
| Directory | /workspace/16.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/16.uart_rx_start_bit_filter.19280249606018955677661424386751132919597798510114739071840549495199609119572 |
| Short name | T1209 |
| Test name | |
| Test status | |
| Simulation time | 4267638245 ps |
| CPU time | 4.78 seconds |
| Started | Nov 22 01:44:21 PM PST 23 |
| Finished | Nov 22 01:44:32 PM PST 23 |
| Peak memory | 196016 kb |
| Host | smart-2a9e6248-ed1e-4608-a853-6fb69a99e479 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=19280249606018955677661424386751132919597798510114739071840549495199609119572 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 16.uart_rx_start_bit_filter.19280249606018955677661424386751132919597798510114739071840549495199609119572 |
| Directory | /workspace/16.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/16.uart_smoke.88923308181471226937100861449221847282727599289499549889158376661020806161355 |
| Short name | T1038 |
| Test name | |
| Test status | |
| Simulation time | 5759626309 ps |
| CPU time | 18.7 seconds |
| Started | Nov 22 01:44:18 PM PST 23 |
| Finished | Nov 22 01:44:40 PM PST 23 |
| Peak memory | 199632 kb |
| Host | smart-7547e06d-9f38-425e-ab19-a535bec8b2ec |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=88923308181471226937100861449221847282727599289499549889158376661020806161355 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 16.uart_smoke.88923308181471226937100861449221847282727599289499549889158376661020806161355 |
| Directory | /workspace/16.uart_smoke/latest |
| Test location | /workspace/coverage/default/16.uart_stress_all.8691708393727568278545801787926734223897048972119570146382191955154862812956 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 43402307308 ps |
| CPU time | 57.25 seconds |
| Started | Nov 22 01:44:31 PM PST 23 |
| Finished | Nov 22 01:45:34 PM PST 23 |
| Peak memory | 200100 kb |
| Host | smart-76ad9bb1-2147-4945-bc07-7c274d18b661 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8691708393727568278545801787926734223897048972119570146382191955154862812956 -assert nopost proc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 16.uart_stress_all.8691708393727568278545801787926734223897048972119570146382191955154862812956 |
| Directory | /workspace/16.uart_stress_all/latest |
| Test location | /workspace/coverage/default/16.uart_stress_all_with_rand_reset.97582424450516515757365909165495355203496835888653174458540948751503640906731 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 87476847566 ps |
| CPU time | 475.97 seconds |
| Started | Nov 22 01:44:09 PM PST 23 |
| Finished | Nov 22 01:52:10 PM PST 23 |
| Peak memory | 226244 kb |
| Host | smart-5b04c5bd-b979-4d80-88fc-53cd96989290 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97582424450516515757365909 165495355203496835888653174458540948751503640906731 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_stress_all_with_rand_reset.9758242445051 6515757365909165495355203496835888653174458540948751503640906731 |
| Directory | /workspace/16.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/16.uart_tx_ovrd.14225489582893942637315059204697528864347211523855460639620802525927994826475 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 485186362 ps |
| CPU time | 1.27 seconds |
| Started | Nov 22 01:44:24 PM PST 23 |
| Finished | Nov 22 01:44:31 PM PST 23 |
| Peak memory | 197928 kb |
| Host | smart-7f48bfb0-6cbe-495e-ac0c-371f9eef4e05 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=14225489582893942637315059204697528864347211523855460639620802525927994826475 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 16.uart_tx_ovrd.14225489582893942637315059204697528864347211523855460639620802525927994826475 |
| Directory | /workspace/16.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/16.uart_tx_rx.78568247199391586284294378173206427946128926268800397136925638207109512649174 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 57391945390 ps |
| CPU time | 63.52 seconds |
| Started | Nov 22 01:44:24 PM PST 23 |
| Finished | Nov 22 01:45:33 PM PST 23 |
| Peak memory | 200060 kb |
| Host | smart-ef52cbe4-8842-4815-bee7-aaeddc3e8303 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=78568247199391586284294378173206427946128926268800397136925638207109512649174 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 16.uart_tx_rx.78568247199391586284294378173206427946128926268800397136925638207109512649174 |
| Directory | /workspace/16.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/160.uart_fifo_reset.66447359223042608550590485161153173880321622102525883292225326187231416523523 |
| Short name | T1058 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 112.54 seconds |
| Started | Nov 22 01:46:13 PM PST 23 |
| Finished | Nov 22 01:48:09 PM PST 23 |
| Peak memory | 198880 kb |
| Host | smart-3c72b405-d497-438c-b730-ccafdf21a264 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=66447359223042608550590485161153173880321622102525883292225326187231416523523 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 160.uart_fifo_reset.66447359223042608550590485161153173880321622102525883292225326187231416523523 |
| Directory | /workspace/160.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/161.uart_fifo_reset.60001963480177337770179431321726146662069721423432057254786536925135538102690 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 113.92 seconds |
| Started | Nov 22 01:46:07 PM PST 23 |
| Finished | Nov 22 01:48:07 PM PST 23 |
| Peak memory | 198904 kb |
| Host | smart-a982d00f-f5ad-41a0-b7ac-4762c06f05bb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=60001963480177337770179431321726146662069721423432057254786536925135538102690 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 161.uart_fifo_reset.60001963480177337770179431321726146662069721423432057254786536925135538102690 |
| Directory | /workspace/161.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/162.uart_fifo_reset.67573203709301459275352231888320269208589049742758146820294893942118475613628 |
| Short name | T1263 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 112.92 seconds |
| Started | Nov 22 01:46:05 PM PST 23 |
| Finished | Nov 22 01:48:05 PM PST 23 |
| Peak memory | 198908 kb |
| Host | smart-1764c456-a136-4cee-b488-4b498463c1e2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=67573203709301459275352231888320269208589049742758146820294893942118475613628 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 162.uart_fifo_reset.67573203709301459275352231888320269208589049742758146820294893942118475613628 |
| Directory | /workspace/162.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/163.uart_fifo_reset.32066776922372154370975304083571299959046846463466634778907911198551053621626 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 113.52 seconds |
| Started | Nov 22 01:45:46 PM PST 23 |
| Finished | Nov 22 01:47:42 PM PST 23 |
| Peak memory | 198756 kb |
| Host | smart-f359937c-ad58-4554-b92c-d9c3d33e139b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=32066776922372154370975304083571299959046846463466634778907911198551053621626 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 163.uart_fifo_reset.32066776922372154370975304083571299959046846463466634778907911198551053621626 |
| Directory | /workspace/163.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/164.uart_fifo_reset.34271783993229871333594262184655391970134628002060877455754532507158822606455 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 113.52 seconds |
| Started | Nov 22 01:46:02 PM PST 23 |
| Finished | Nov 22 01:48:01 PM PST 23 |
| Peak memory | 198760 kb |
| Host | smart-84687cf5-4613-450a-a7d8-de9bddc5236e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=34271783993229871333594262184655391970134628002060877455754532507158822606455 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 164.uart_fifo_reset.34271783993229871333594262184655391970134628002060877455754532507158822606455 |
| Directory | /workspace/164.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/165.uart_fifo_reset.110792490945392208804513586589446296402374651230932353123764352612978419654906 |
| Short name | T997 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 112.77 seconds |
| Started | Nov 22 01:46:05 PM PST 23 |
| Finished | Nov 22 01:48:05 PM PST 23 |
| Peak memory | 198884 kb |
| Host | smart-51a7c7ad-19ea-4fc3-8e73-023683eb905a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=110792490945392208804513586589446296402374651230932353123764352612978419654906 -assert nopostproc +UVM_TESTNAME=uart_bas e_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.uart_fifo_reset.110792490945392208804513586589446296402374651230932353123764352612978419654906 |
| Directory | /workspace/165.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/166.uart_fifo_reset.22535645259439143360557939400747973114041192118068257876051073790030456197477 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 113.43 seconds |
| Started | Nov 22 01:45:57 PM PST 23 |
| Finished | Nov 22 01:47:57 PM PST 23 |
| Peak memory | 198864 kb |
| Host | smart-20c5d68c-a8e7-4e8c-a994-a39a82d4e6ef |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=22535645259439143360557939400747973114041192118068257876051073790030456197477 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 166.uart_fifo_reset.22535645259439143360557939400747973114041192118068257876051073790030456197477 |
| Directory | /workspace/166.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/167.uart_fifo_reset.17459173805429292576002731982140511123150476368464543007547253179653043352707 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 113.84 seconds |
| Started | Nov 22 01:46:23 PM PST 23 |
| Finished | Nov 22 01:48:18 PM PST 23 |
| Peak memory | 198884 kb |
| Host | smart-ef10f70a-fa9d-403f-9690-c7d82f31937c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=17459173805429292576002731982140511123150476368464543007547253179653043352707 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 167.uart_fifo_reset.17459173805429292576002731982140511123150476368464543007547253179653043352707 |
| Directory | /workspace/167.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/168.uart_fifo_reset.31235766834716214555948102635716862554565538465171282576035914054841211377855 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 114.64 seconds |
| Started | Nov 22 01:46:07 PM PST 23 |
| Finished | Nov 22 01:48:08 PM PST 23 |
| Peak memory | 198904 kb |
| Host | smart-a9750d27-ccb7-47c2-99a5-6351f0f8ee61 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=31235766834716214555948102635716862554565538465171282576035914054841211377855 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 168.uart_fifo_reset.31235766834716214555948102635716862554565538465171282576035914054841211377855 |
| Directory | /workspace/168.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/169.uart_fifo_reset.81059241195199630125373727770801459912963643897891615591480023694720012164309 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 113.05 seconds |
| Started | Nov 22 01:46:05 PM PST 23 |
| Finished | Nov 22 01:48:05 PM PST 23 |
| Peak memory | 198868 kb |
| Host | smart-cb1366dd-417c-4ccf-9da1-d59534a6ad84 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=81059241195199630125373727770801459912963643897891615591480023694720012164309 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 169.uart_fifo_reset.81059241195199630125373727770801459912963643897891615591480023694720012164309 |
| Directory | /workspace/169.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/17.uart_alert_test.35863849275133554533409889604539121596386362934556541218181976368601447054324 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 16368684 ps |
| CPU time | 0.53 seconds |
| Started | Nov 22 01:44:14 PM PST 23 |
| Finished | Nov 22 01:44:18 PM PST 23 |
| Peak memory | 194584 kb |
| Host | smart-0375005b-5b24-45f0-b18f-070bc2f345ac |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35863849275133554533409889604539121596386362934556541218181976368601447054324 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 17.uart_alert_test.35863849275133554533409889604539121596386362934556541218181976368601447054324 |
| Directory | /workspace/17.uart_alert_test/latest |
| Test location | /workspace/coverage/default/17.uart_fifo_full.52063204158925421290176541255377607651317912261382211928942270615092667638156 |
| Short name | T854 |
| Test name | |
| Test status | |
| Simulation time | 61777160308 ps |
| CPU time | 60.28 seconds |
| Started | Nov 22 01:44:23 PM PST 23 |
| Finished | Nov 22 01:45:30 PM PST 23 |
| Peak memory | 200048 kb |
| Host | smart-a9a761fd-30cf-4ec7-acd4-f5ac5e49ff21 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=52063204158925421290176541255377607651317912261382211928942270615092667638156 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 17.uart_fifo_full.52063204158925421290176541255377607651317912261382211928942270615092667638156 |
| Directory | /workspace/17.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/17.uart_fifo_overflow.82138048321294364609667710540704694490880787709194021141630983902201444790823 |
| Short name | T1082 |
| Test name | |
| Test status | |
| Simulation time | 58551936110 ps |
| CPU time | 54.82 seconds |
| Started | Nov 22 01:44:24 PM PST 23 |
| Finished | Nov 22 01:45:24 PM PST 23 |
| Peak memory | 199888 kb |
| Host | smart-ff06f574-d306-456a-ae9f-1519086d84b8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=82138048321294364609667710540704694490880787709194021141630983902201444790823 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 17.uart_fifo_overflow.82138048321294364609667710540704694490880787709194021141630983902201444790823 |
| Directory | /workspace/17.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/17.uart_fifo_reset.58839284958349516289517619541333976163409139001342734688719603169332114280569 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 113.47 seconds |
| Started | Nov 22 01:44:31 PM PST 23 |
| Finished | Nov 22 01:46:31 PM PST 23 |
| Peak memory | 198884 kb |
| Host | smart-85dc0e2d-a616-4497-af9d-312753ddd4a9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=58839284958349516289517619541333976163409139001342734688719603169332114280569 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 17.uart_fifo_reset.58839284958349516289517619541333976163409139001342734688719603169332114280569 |
| Directory | /workspace/17.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/17.uart_long_xfer_wo_dly.1670608107681211933693665066845571843011080680071105760027450582664201751385 |
| Short name | T945 |
| Test name | |
| Test status | |
| Simulation time | 93387746707 ps |
| CPU time | 348.03 seconds |
| Started | Nov 22 01:44:24 PM PST 23 |
| Finished | Nov 22 01:50:18 PM PST 23 |
| Peak memory | 200012 kb |
| Host | smart-a6756253-5c4d-46a5-85b2-758912d66050 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1670608107681211933693665066845571843011080680071105760027450582664201751385 -assert nopostproc +UVM_TEST NAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_long_xfer_wo_dly.1670608107681211933693665066845571843011080680071105760027450582664201751385 |
| Directory | /workspace/17.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/17.uart_loopback.41717897554868736339001898503603031801330159268571845062200810845365812970717 |
| Short name | T1035 |
| Test name | |
| Test status | |
| Simulation time | 14572448663 ps |
| CPU time | 16.11 seconds |
| Started | Nov 22 01:44:06 PM PST 23 |
| Finished | Nov 22 01:44:27 PM PST 23 |
| Peak memory | 200048 kb |
| Host | smart-9e351e35-67d0-4106-b63d-818dd5571581 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=41717897554868736339001898503603031801330159268571845062200810845365812970717 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 17.uart_loopback.41717897554868736339001898503603031801330159268571845062200810845365812970717 |
| Directory | /workspace/17.uart_loopback/latest |
| Test location | /workspace/coverage/default/17.uart_noise_filter.77240753986030181143991304058879964833637435250285589906785546241618447188194 |
| Short name | T918 |
| Test name | |
| Test status | |
| Simulation time | 94501577082 ps |
| CPU time | 96.8 seconds |
| Started | Nov 22 01:44:18 PM PST 23 |
| Finished | Nov 22 01:45:58 PM PST 23 |
| Peak memory | 200236 kb |
| Host | smart-86bfb27c-f083-436b-b957-501606778011 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=77240753986030181143991304058879964833637435250285589906785546241618447188194 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_noise_filter.77240753986030181143991304058879964833637435250285589906785546241618447188194 |
| Directory | /workspace/17.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/17.uart_perf.56574580174781279456214760998428892352382742299440219783933330544760716302553 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 14098773881 ps |
| CPU time | 472.61 seconds |
| Started | Nov 22 01:44:40 PM PST 23 |
| Finished | Nov 22 01:52:34 PM PST 23 |
| Peak memory | 200120 kb |
| Host | smart-2bd6c103-19db-4ad0-9c66-f508b567a7c9 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=56574580174781279456214760998428892352382742299440219783933330544760716302553 -assert nopostproc +UVM_TES TNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 17.uart_perf.56574580174781279456214760998428892352382742299440219783933330544760716302553 |
| Directory | /workspace/17.uart_perf/latest |
| Test location | /workspace/coverage/default/17.uart_rx_oversample.66642956647005840419695835329892901062350643603348538587418496491590231802127 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 4370280281 ps |
| CPU time | 19.91 seconds |
| Started | Nov 22 01:44:35 PM PST 23 |
| Finished | Nov 22 01:44:58 PM PST 23 |
| Peak memory | 198980 kb |
| Host | smart-e5aa5d53-6226-41fc-9a4f-75dff6dbe4ff |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=66642956647005840419695835329892901062350643603348538587418496491590231802127 -assert nopostproc +UVM_TES TNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 17.uart_rx_oversample.66642956647005840419695835329892901062350643603348538587418496491590231802127 |
| Directory | /workspace/17.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/17.uart_rx_parity_err.7117755890108542460675547752436124870378444645465836437929649517196057495655 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 36616611594 ps |
| CPU time | 37.67 seconds |
| Started | Nov 22 01:44:23 PM PST 23 |
| Finished | Nov 22 01:45:07 PM PST 23 |
| Peak memory | 200092 kb |
| Host | smart-fb74eaef-929f-49ed-85e6-6d4ad344f510 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=7117755890108542460675547752436124870378444645465836437929649517196057495655 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_parity_err.7117755890108542460675547752436124870378444645465836437929649517196057495655 |
| Directory | /workspace/17.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/17.uart_rx_start_bit_filter.55018713625447928370177460799625037121248669931727817052132953322166432800872 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 4267638245 ps |
| CPU time | 4.69 seconds |
| Started | Nov 22 01:44:11 PM PST 23 |
| Finished | Nov 22 01:44:20 PM PST 23 |
| Peak memory | 195892 kb |
| Host | smart-38d8ac93-a59a-46eb-a0e3-309d03d818b3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=55018713625447928370177460799625037121248669931727817052132953322166432800872 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 17.uart_rx_start_bit_filter.55018713625447928370177460799625037121248669931727817052132953322166432800872 |
| Directory | /workspace/17.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/17.uart_smoke.115032245905529322828762156662668928394497476688518276348992009197040354477971 |
| Short name | T965 |
| Test name | |
| Test status | |
| Simulation time | 5759626309 ps |
| CPU time | 18.75 seconds |
| Started | Nov 22 01:44:25 PM PST 23 |
| Finished | Nov 22 01:44:49 PM PST 23 |
| Peak memory | 199624 kb |
| Host | smart-b7b2578d-8244-4b3f-acb9-f37855d5282b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=115032245905529322828762156662668928394497476688518276348992009197040354477971 -assert nopostproc +UVM_TESTNAME=uart_bas e_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 17.uart_smoke.115032245905529322828762156662668928394497476688518276348992009197040354477971 |
| Directory | /workspace/17.uart_smoke/latest |
| Test location | /workspace/coverage/default/17.uart_stress_all.49456016860981491974509979063238635539154946495360606814348882994680233132792 |
| Short name | T1068 |
| Test name | |
| Test status | |
| Simulation time | 43402307308 ps |
| CPU time | 56.88 seconds |
| Started | Nov 22 01:44:24 PM PST 23 |
| Finished | Nov 22 01:45:27 PM PST 23 |
| Peak memory | 200064 kb |
| Host | smart-1bb1fb4c-08d6-4a42-ad2d-ab58d4815e57 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49456016860981491974509979063238635539154946495360606814348882994680233132792 -assert nopos tproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 17.uart_stress_all.49456016860981491974509979063238635539154946495360606814348882994680233132792 |
| Directory | /workspace/17.uart_stress_all/latest |
| Test location | /workspace/coverage/default/17.uart_stress_all_with_rand_reset.66012553675319837638279120111360902241388730418057592910089319389011065349212 |
| Short name | T1046 |
| Test name | |
| Test status | |
| Simulation time | 87476847566 ps |
| CPU time | 468.29 seconds |
| Started | Nov 22 01:44:26 PM PST 23 |
| Finished | Nov 22 01:52:18 PM PST 23 |
| Peak memory | 226252 kb |
| Host | smart-c119237d-6b35-4b11-a036-7af27802dbdb |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66012553675319837638279120 111360902241388730418057592910089319389011065349212 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_stress_all_with_rand_reset.6601255367531 9837638279120111360902241388730418057592910089319389011065349212 |
| Directory | /workspace/17.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/17.uart_tx_ovrd.60026271405430550343497349532081239452358882741851397127857452604231217864768 |
| Short name | T703 |
| Test name | |
| Test status | |
| Simulation time | 485186362 ps |
| CPU time | 1.29 seconds |
| Started | Nov 22 01:44:28 PM PST 23 |
| Finished | Nov 22 01:44:37 PM PST 23 |
| Peak memory | 197896 kb |
| Host | smart-6faa919b-b335-4234-82ae-fa2d756fc15c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=60026271405430550343497349532081239452358882741851397127857452604231217864768 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 17.uart_tx_ovrd.60026271405430550343497349532081239452358882741851397127857452604231217864768 |
| Directory | /workspace/17.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/17.uart_tx_rx.62198770714348854973599475250123310442543197464186420727816719448328391265463 |
| Short name | T913 |
| Test name | |
| Test status | |
| Simulation time | 57391945390 ps |
| CPU time | 63.82 seconds |
| Started | Nov 22 01:44:33 PM PST 23 |
| Finished | Nov 22 01:45:42 PM PST 23 |
| Peak memory | 199992 kb |
| Host | smart-683f21b9-d1e7-4ac2-ac25-3cb4770811fa |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=62198770714348854973599475250123310442543197464186420727816719448328391265463 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 17.uart_tx_rx.62198770714348854973599475250123310442543197464186420727816719448328391265463 |
| Directory | /workspace/17.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/170.uart_fifo_reset.84692017602876917385307235915684065244636723037424713295386850402482429164963 |
| Short name | T911 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 112.27 seconds |
| Started | Nov 22 01:46:11 PM PST 23 |
| Finished | Nov 22 01:48:08 PM PST 23 |
| Peak memory | 198844 kb |
| Host | smart-b9365ddc-8925-477b-8aea-a6e06c4f652c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=84692017602876917385307235915684065244636723037424713295386850402482429164963 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 170.uart_fifo_reset.84692017602876917385307235915684065244636723037424713295386850402482429164963 |
| Directory | /workspace/170.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/171.uart_fifo_reset.11156512634555188152331106132292755954564618673027525839838451284244790061489 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 113.54 seconds |
| Started | Nov 22 01:46:20 PM PST 23 |
| Finished | Nov 22 01:48:14 PM PST 23 |
| Peak memory | 198864 kb |
| Host | smart-83ecd985-9e84-4bfb-b9eb-13f6bb8f7662 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=11156512634555188152331106132292755954564618673027525839838451284244790061489 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 171.uart_fifo_reset.11156512634555188152331106132292755954564618673027525839838451284244790061489 |
| Directory | /workspace/171.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/172.uart_fifo_reset.67858531019921623319823947912446674312565304571263762007840140060716114649404 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 112.79 seconds |
| Started | Nov 22 01:46:16 PM PST 23 |
| Finished | Nov 22 01:48:10 PM PST 23 |
| Peak memory | 198880 kb |
| Host | smart-61f04736-b4ea-4378-8862-77753b5cf93a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=67858531019921623319823947912446674312565304571263762007840140060716114649404 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 172.uart_fifo_reset.67858531019921623319823947912446674312565304571263762007840140060716114649404 |
| Directory | /workspace/172.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/173.uart_fifo_reset.91796742307628557772724893565170549685651935741710719853400213740182530753423 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 112.64 seconds |
| Started | Nov 22 01:46:09 PM PST 23 |
| Finished | Nov 22 01:48:07 PM PST 23 |
| Peak memory | 198844 kb |
| Host | smart-3a72ee60-8a82-4a8a-b57a-704b1dbc643a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=91796742307628557772724893565170549685651935741710719853400213740182530753423 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 173.uart_fifo_reset.91796742307628557772724893565170549685651935741710719853400213740182530753423 |
| Directory | /workspace/173.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/174.uart_fifo_reset.22945181445038826546772008065264794488016058357084515956063379833902291035989 |
| Short name | T1233 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 113.13 seconds |
| Started | Nov 22 01:46:14 PM PST 23 |
| Finished | Nov 22 01:48:10 PM PST 23 |
| Peak memory | 198932 kb |
| Host | smart-55efa097-4990-4fbd-918c-e3dce4fe3ac6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=22945181445038826546772008065264794488016058357084515956063379833902291035989 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 174.uart_fifo_reset.22945181445038826546772008065264794488016058357084515956063379833902291035989 |
| Directory | /workspace/174.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/175.uart_fifo_reset.62898439434441246421604141361708409751087573794109685689870099902276159665646 |
| Short name | T1246 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 114.21 seconds |
| Started | Nov 22 01:46:21 PM PST 23 |
| Finished | Nov 22 01:48:16 PM PST 23 |
| Peak memory | 198888 kb |
| Host | smart-b8a58f3d-1b70-4f7f-97b7-be28871d5e91 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=62898439434441246421604141361708409751087573794109685689870099902276159665646 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 175.uart_fifo_reset.62898439434441246421604141361708409751087573794109685689870099902276159665646 |
| Directory | /workspace/175.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/176.uart_fifo_reset.101578922111545167744924851462284599092752608178002831024930816875888881358255 |
| Short name | T741 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 113.74 seconds |
| Started | Nov 22 01:46:23 PM PST 23 |
| Finished | Nov 22 01:48:17 PM PST 23 |
| Peak memory | 198924 kb |
| Host | smart-339ccf6a-1a69-46be-b4e9-08e60534b335 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=101578922111545167744924851462284599092752608178002831024930816875888881358255 -assert nopostproc +UVM_TESTNAME=uart_bas e_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.uart_fifo_reset.101578922111545167744924851462284599092752608178002831024930816875888881358255 |
| Directory | /workspace/176.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/177.uart_fifo_reset.69271419133808397245116110412911204309359083289774085492437103536070106906936 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 112.58 seconds |
| Started | Nov 22 01:46:01 PM PST 23 |
| Finished | Nov 22 01:48:00 PM PST 23 |
| Peak memory | 198892 kb |
| Host | smart-03f561df-5b63-4214-9447-10fac00543f2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=69271419133808397245116110412911204309359083289774085492437103536070106906936 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 177.uart_fifo_reset.69271419133808397245116110412911204309359083289774085492437103536070106906936 |
| Directory | /workspace/177.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/178.uart_fifo_reset.19956363001876706965384573109512221293276978315073243050576053312194144330166 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 113.11 seconds |
| Started | Nov 22 01:46:18 PM PST 23 |
| Finished | Nov 22 01:48:12 PM PST 23 |
| Peak memory | 198908 kb |
| Host | smart-f3287bf4-ab19-4b95-a5c0-386272343f88 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=19956363001876706965384573109512221293276978315073243050576053312194144330166 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 178.uart_fifo_reset.19956363001876706965384573109512221293276978315073243050576053312194144330166 |
| Directory | /workspace/178.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/179.uart_fifo_reset.84615471178386712224147033694680438906747848332109479196301183348756842798781 |
| Short name | T749 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 112.96 seconds |
| Started | Nov 22 01:45:59 PM PST 23 |
| Finished | Nov 22 01:48:00 PM PST 23 |
| Peak memory | 198804 kb |
| Host | smart-66095956-17eb-447c-8656-c934b8f6dc0c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=84615471178386712224147033694680438906747848332109479196301183348756842798781 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 179.uart_fifo_reset.84615471178386712224147033694680438906747848332109479196301183348756842798781 |
| Directory | /workspace/179.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/18.uart_alert_test.86167196692396555985360597977569913527560562002452563834210490431619702819155 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 16368684 ps |
| CPU time | 0.54 seconds |
| Started | Nov 22 01:44:34 PM PST 23 |
| Finished | Nov 22 01:44:38 PM PST 23 |
| Peak memory | 194624 kb |
| Host | smart-3e55940d-05a6-419c-a3ee-89ad0f411089 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86167196692396555985360597977569913527560562002452563834210490431619702819155 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 18.uart_alert_test.86167196692396555985360597977569913527560562002452563834210490431619702819155 |
| Directory | /workspace/18.uart_alert_test/latest |
| Test location | /workspace/coverage/default/18.uart_fifo_full.87127164742254405392275718719962435123500524416600485066211555090979802163308 |
| Short name | T1122 |
| Test name | |
| Test status | |
| Simulation time | 61777160308 ps |
| CPU time | 61.41 seconds |
| Started | Nov 22 01:44:40 PM PST 23 |
| Finished | Nov 22 01:45:43 PM PST 23 |
| Peak memory | 200108 kb |
| Host | smart-13a74bc6-672c-447d-9d79-d415126ff476 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=87127164742254405392275718719962435123500524416600485066211555090979802163308 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 18.uart_fifo_full.87127164742254405392275718719962435123500524416600485066211555090979802163308 |
| Directory | /workspace/18.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/18.uart_fifo_overflow.73631650249317307894166538293264058319301757360217341565712387781088677742168 |
| Short name | T891 |
| Test name | |
| Test status | |
| Simulation time | 58551936110 ps |
| CPU time | 54.82 seconds |
| Started | Nov 22 01:44:21 PM PST 23 |
| Finished | Nov 22 01:45:22 PM PST 23 |
| Peak memory | 199784 kb |
| Host | smart-f72819cc-0fbc-454a-9625-09378faaec1c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=73631650249317307894166538293264058319301757360217341565712387781088677742168 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 18.uart_fifo_overflow.73631650249317307894166538293264058319301757360217341565712387781088677742168 |
| Directory | /workspace/18.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/18.uart_fifo_reset.96550805028323498042452341685314850673616757830002804629590604039869163888388 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 113.17 seconds |
| Started | Nov 22 01:44:22 PM PST 23 |
| Finished | Nov 22 01:46:22 PM PST 23 |
| Peak memory | 198908 kb |
| Host | smart-c5e04b09-fc8e-4ec4-80ba-789cd485e5e2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=96550805028323498042452341685314850673616757830002804629590604039869163888388 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 18.uart_fifo_reset.96550805028323498042452341685314850673616757830002804629590604039869163888388 |
| Directory | /workspace/18.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/18.uart_intr.92726756415631344715872199157475262185455644341615053384934678159243400568550 |
| Short name | T1177 |
| Test name | |
| Test status | |
| Simulation time | 787145125175 ps |
| CPU time | 786.41 seconds |
| Started | Nov 22 01:44:30 PM PST 23 |
| Finished | Nov 22 01:57:44 PM PST 23 |
| Peak memory | 200128 kb |
| Host | smart-396138b7-ff9b-4fd5-922e-bcb851f6c36f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92726756415631344715872199157475262185455644341615053384934678159243400568550 -assert nopost proc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 18.uart_intr.92726756415631344715872199157475262185455644341615053384934678159243400568550 |
| Directory | /workspace/18.uart_intr/latest |
| Test location | /workspace/coverage/default/18.uart_long_xfer_wo_dly.38483134453038430148282998929287670793400899204736673816634254080122612741419 |
| Short name | T1231 |
| Test name | |
| Test status | |
| Simulation time | 93387746707 ps |
| CPU time | 357.72 seconds |
| Started | Nov 22 01:44:38 PM PST 23 |
| Finished | Nov 22 01:50:37 PM PST 23 |
| Peak memory | 200140 kb |
| Host | smart-7d67e962-1e8d-4330-800f-580f110a29e7 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=38483134453038430148282998929287670793400899204736673816634254080122612741419 -assert nopostproc +UVM_TES TNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 18.uart_long_xfer_wo_dly.38483134453038430148282998929287670793400899204736673816634254080122612741419 |
| Directory | /workspace/18.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/18.uart_loopback.81693380288151650061984207823866203785404280536379289349808185006413114618433 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 14572448663 ps |
| CPU time | 15.95 seconds |
| Started | Nov 22 01:44:35 PM PST 23 |
| Finished | Nov 22 01:44:54 PM PST 23 |
| Peak memory | 199992 kb |
| Host | smart-68511aa3-eeff-4a29-97a6-1a68e395e900 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=81693380288151650061984207823866203785404280536379289349808185006413114618433 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 18.uart_loopback.81693380288151650061984207823866203785404280536379289349808185006413114618433 |
| Directory | /workspace/18.uart_loopback/latest |
| Test location | /workspace/coverage/default/18.uart_noise_filter.64363991486079036824564970868427534247721136044457630313388311801860634022202 |
| Short name | T748 |
| Test name | |
| Test status | |
| Simulation time | 94501577082 ps |
| CPU time | 97.1 seconds |
| Started | Nov 22 01:44:06 PM PST 23 |
| Finished | Nov 22 01:45:48 PM PST 23 |
| Peak memory | 200356 kb |
| Host | smart-e5c91f08-2033-4c9c-bbf6-5a077121d7a4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=64363991486079036824564970868427534247721136044457630313388311801860634022202 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_noise_filter.64363991486079036824564970868427534247721136044457630313388311801860634022202 |
| Directory | /workspace/18.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/18.uart_perf.13849944574782684905185292507133579873390819146939162330078479578779446688179 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 14098773881 ps |
| CPU time | 472.16 seconds |
| Started | Nov 22 01:44:41 PM PST 23 |
| Finished | Nov 22 01:52:35 PM PST 23 |
| Peak memory | 200052 kb |
| Host | smart-f8d88161-b92c-4aab-8d8b-2b79ce96f9fc |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=13849944574782684905185292507133579873390819146939162330078479578779446688179 -assert nopostproc +UVM_TES TNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 18.uart_perf.13849944574782684905185292507133579873390819146939162330078479578779446688179 |
| Directory | /workspace/18.uart_perf/latest |
| Test location | /workspace/coverage/default/18.uart_rx_oversample.61584304578769272103939990421182179942833161402933295421430838614373131689056 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 4370280281 ps |
| CPU time | 20.35 seconds |
| Started | Nov 22 01:44:40 PM PST 23 |
| Finished | Nov 22 01:45:02 PM PST 23 |
| Peak memory | 198980 kb |
| Host | smart-77df2b1e-e50d-4643-94fd-73985461e7b8 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=61584304578769272103939990421182179942833161402933295421430838614373131689056 -assert nopostproc +UVM_TES TNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 18.uart_rx_oversample.61584304578769272103939990421182179942833161402933295421430838614373131689056 |
| Directory | /workspace/18.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/18.uart_rx_start_bit_filter.105128324160753174026883393277775117977836338991619074743162069812965382731361 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 4267638245 ps |
| CPU time | 4.73 seconds |
| Started | Nov 22 01:44:38 PM PST 23 |
| Finished | Nov 22 01:44:45 PM PST 23 |
| Peak memory | 195988 kb |
| Host | smart-5273ce71-3654-44b9-85a0-965d9859f102 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=105128324160753174026883393277775117977836338991619074743162069812965382731361 -assert nopostproc +UVM_TESTNAME=uart_bas e_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 18.uart_rx_start_bit_filter.105128324160753174026883393277775117977836338991619074743162069812965382731361 |
| Directory | /workspace/18.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/18.uart_smoke.38531783592158084072620972071010157959411730512159290499680621827977321822630 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 5759626309 ps |
| CPU time | 18.68 seconds |
| Started | Nov 22 01:44:04 PM PST 23 |
| Finished | Nov 22 01:44:27 PM PST 23 |
| Peak memory | 199640 kb |
| Host | smart-7333adfd-9511-405d-b596-4d0ed807c11c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=38531783592158084072620972071010157959411730512159290499680621827977321822630 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 18.uart_smoke.38531783592158084072620972071010157959411730512159290499680621827977321822630 |
| Directory | /workspace/18.uart_smoke/latest |
| Test location | /workspace/coverage/default/18.uart_stress_all.48052970236875151071145914040012164877796763369250017797697685059541705108567 |
| Short name | T1203 |
| Test name | |
| Test status | |
| Simulation time | 43402307308 ps |
| CPU time | 57.47 seconds |
| Started | Nov 22 01:44:23 PM PST 23 |
| Finished | Nov 22 01:45:27 PM PST 23 |
| Peak memory | 200096 kb |
| Host | smart-7e7a43ea-b98f-4074-948b-b4eabdd351d6 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48052970236875151071145914040012164877796763369250017797697685059541705108567 -assert nopos tproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 18.uart_stress_all.48052970236875151071145914040012164877796763369250017797697685059541705108567 |
| Directory | /workspace/18.uart_stress_all/latest |
| Test location | /workspace/coverage/default/18.uart_stress_all_with_rand_reset.35101912121189635552555782530728749226299256649788748049008715694922248939423 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 87476847566 ps |
| CPU time | 464.53 seconds |
| Started | Nov 22 01:44:46 PM PST 23 |
| Finished | Nov 22 01:52:33 PM PST 23 |
| Peak memory | 226168 kb |
| Host | smart-67fd299f-6e84-4013-8582-47cae4532873 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35101912121189635552555782 530728749226299256649788748049008715694922248939423 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_stress_all_with_rand_reset.3510191212118 9635552555782530728749226299256649788748049008715694922248939423 |
| Directory | /workspace/18.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/18.uart_tx_ovrd.21817778392205557421746258415674318514307911691553880742995528360463988389159 |
| Short name | T1264 |
| Test name | |
| Test status | |
| Simulation time | 485186362 ps |
| CPU time | 1.26 seconds |
| Started | Nov 22 01:44:14 PM PST 23 |
| Finished | Nov 22 01:44:19 PM PST 23 |
| Peak memory | 197904 kb |
| Host | smart-ee3fb5b0-1de7-434a-8f58-b68a92ca4d4e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=21817778392205557421746258415674318514307911691553880742995528360463988389159 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 18.uart_tx_ovrd.21817778392205557421746258415674318514307911691553880742995528360463988389159 |
| Directory | /workspace/18.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/18.uart_tx_rx.93794656302829959977488118845411236078522236588336683610348352106811661012514 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 57391945390 ps |
| CPU time | 63.37 seconds |
| Started | Nov 22 01:44:11 PM PST 23 |
| Finished | Nov 22 01:45:18 PM PST 23 |
| Peak memory | 200096 kb |
| Host | smart-45bffd32-59e3-4270-8b4a-bd5c750ed828 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=93794656302829959977488118845411236078522236588336683610348352106811661012514 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 18.uart_tx_rx.93794656302829959977488118845411236078522236588336683610348352106811661012514 |
| Directory | /workspace/18.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/180.uart_fifo_reset.83213516217276759664104506853660365437386437603388831681009414666473195451943 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 113.67 seconds |
| Started | Nov 22 01:46:21 PM PST 23 |
| Finished | Nov 22 01:48:16 PM PST 23 |
| Peak memory | 198856 kb |
| Host | smart-2440c3da-1cec-4eae-9d05-e61d7bd0c32a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=83213516217276759664104506853660365437386437603388831681009414666473195451943 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 180.uart_fifo_reset.83213516217276759664104506853660365437386437603388831681009414666473195451943 |
| Directory | /workspace/180.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/181.uart_fifo_reset.8352966242424064508100899733394938399763004512984694648405323759909001533494 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 112.45 seconds |
| Started | Nov 22 01:46:19 PM PST 23 |
| Finished | Nov 22 01:48:13 PM PST 23 |
| Peak memory | 198816 kb |
| Host | smart-b1bd46a8-56e6-4223-b269-9c4271986ec3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=8352966242424064508100899733394938399763004512984694648405323759909001533494 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 181.uart_fifo_reset.8352966242424064508100899733394938399763004512984694648405323759909001533494 |
| Directory | /workspace/181.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/182.uart_fifo_reset.62738458551337928033066954568144607525088706562800698749281876259743486407607 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 113.4 seconds |
| Started | Nov 22 01:46:23 PM PST 23 |
| Finished | Nov 22 01:48:17 PM PST 23 |
| Peak memory | 198768 kb |
| Host | smart-2ecac5bf-7770-485d-9340-464c693b991c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=62738458551337928033066954568144607525088706562800698749281876259743486407607 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 182.uart_fifo_reset.62738458551337928033066954568144607525088706562800698749281876259743486407607 |
| Directory | /workspace/182.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/183.uart_fifo_reset.6539298327183394534836115499411914251889141602457784033779569009103441728557 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 112.92 seconds |
| Started | Nov 22 01:46:26 PM PST 23 |
| Finished | Nov 22 01:48:21 PM PST 23 |
| Peak memory | 198936 kb |
| Host | smart-ae428b7b-0f6a-4964-b32c-24b94a474a6e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=6539298327183394534836115499411914251889141602457784033779569009103441728557 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 183.uart_fifo_reset.6539298327183394534836115499411914251889141602457784033779569009103441728557 |
| Directory | /workspace/183.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/184.uart_fifo_reset.97449388040040355099199212401673723707644785493189419891371366314706051484025 |
| Short name | T668 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 113.35 seconds |
| Started | Nov 22 01:46:26 PM PST 23 |
| Finished | Nov 22 01:48:20 PM PST 23 |
| Peak memory | 198912 kb |
| Host | smart-8fcd518d-6ff5-4888-bce4-1c902862a117 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=97449388040040355099199212401673723707644785493189419891371366314706051484025 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 184.uart_fifo_reset.97449388040040355099199212401673723707644785493189419891371366314706051484025 |
| Directory | /workspace/184.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/185.uart_fifo_reset.59602497734818584153692028686678409546649381071597346522010126073426545860122 |
| Short name | T1050 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 113.13 seconds |
| Started | Nov 22 01:46:36 PM PST 23 |
| Finished | Nov 22 01:48:31 PM PST 23 |
| Peak memory | 198916 kb |
| Host | smart-c75b6ca4-7bbc-440c-b8ff-c8b3de819cd3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=59602497734818584153692028686678409546649381071597346522010126073426545860122 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 185.uart_fifo_reset.59602497734818584153692028686678409546649381071597346522010126073426545860122 |
| Directory | /workspace/185.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/186.uart_fifo_reset.40495084946984649773843816662309537622226852989507450375316448979917298472840 |
| Short name | T974 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 112.86 seconds |
| Started | Nov 22 01:46:26 PM PST 23 |
| Finished | Nov 22 01:48:20 PM PST 23 |
| Peak memory | 198936 kb |
| Host | smart-4a76b26a-339e-47ca-8eb9-5fe8acb7c94b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=40495084946984649773843816662309537622226852989507450375316448979917298472840 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 186.uart_fifo_reset.40495084946984649773843816662309537622226852989507450375316448979917298472840 |
| Directory | /workspace/186.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/187.uart_fifo_reset.27493611330042730706448534277156864815614389355061762724137675555589879974808 |
| Short name | T1239 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 113.86 seconds |
| Started | Nov 22 01:46:26 PM PST 23 |
| Finished | Nov 22 01:48:21 PM PST 23 |
| Peak memory | 198896 kb |
| Host | smart-da0c47fc-b046-4f5e-a449-a61a58bcfc46 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=27493611330042730706448534277156864815614389355061762724137675555589879974808 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 187.uart_fifo_reset.27493611330042730706448534277156864815614389355061762724137675555589879974808 |
| Directory | /workspace/187.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/188.uart_fifo_reset.19636329508312116690303586250218550605325447281651862651846788206403998531385 |
| Short name | T1147 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 113.47 seconds |
| Started | Nov 22 01:46:36 PM PST 23 |
| Finished | Nov 22 01:48:31 PM PST 23 |
| Peak memory | 198892 kb |
| Host | smart-69702f38-d2e5-4c1f-b723-31e2590cbd4a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=19636329508312116690303586250218550605325447281651862651846788206403998531385 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 188.uart_fifo_reset.19636329508312116690303586250218550605325447281651862651846788206403998531385 |
| Directory | /workspace/188.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/189.uart_fifo_reset.50329507983638351021661362738116290971903485215016977359496084672133630662943 |
| Short name | T1215 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 113.7 seconds |
| Started | Nov 22 01:46:33 PM PST 23 |
| Finished | Nov 22 01:48:27 PM PST 23 |
| Peak memory | 198912 kb |
| Host | smart-fa710446-c26b-4551-ad8a-445919e672b6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=50329507983638351021661362738116290971903485215016977359496084672133630662943 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 189.uart_fifo_reset.50329507983638351021661362738116290971903485215016977359496084672133630662943 |
| Directory | /workspace/189.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/19.uart_alert_test.91323805448920436391964041722693982043820663914860312649033286711481999818935 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 16368684 ps |
| CPU time | 0.52 seconds |
| Started | Nov 22 01:44:41 PM PST 23 |
| Finished | Nov 22 01:44:43 PM PST 23 |
| Peak memory | 194624 kb |
| Host | smart-d55e7ce8-0148-4b5d-99fd-7694d4dc0d40 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91323805448920436391964041722693982043820663914860312649033286711481999818935 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 19.uart_alert_test.91323805448920436391964041722693982043820663914860312649033286711481999818935 |
| Directory | /workspace/19.uart_alert_test/latest |
| Test location | /workspace/coverage/default/19.uart_fifo_full.48614826753032604350239821397252651402032181936359969562508307000902749365426 |
| Short name | T811 |
| Test name | |
| Test status | |
| Simulation time | 61777160308 ps |
| CPU time | 60.21 seconds |
| Started | Nov 22 01:44:45 PM PST 23 |
| Finished | Nov 22 01:45:48 PM PST 23 |
| Peak memory | 200088 kb |
| Host | smart-57702539-5e6d-427e-90bd-35fce09134da |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=48614826753032604350239821397252651402032181936359969562508307000902749365426 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 19.uart_fifo_full.48614826753032604350239821397252651402032181936359969562508307000902749365426 |
| Directory | /workspace/19.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/19.uart_fifo_overflow.80773385250164869024536576612846309142008052470569670890719477972564974275760 |
| Short name | T982 |
| Test name | |
| Test status | |
| Simulation time | 58551936110 ps |
| CPU time | 55.54 seconds |
| Started | Nov 22 01:44:49 PM PST 23 |
| Finished | Nov 22 01:45:47 PM PST 23 |
| Peak memory | 199892 kb |
| Host | smart-8d0749ad-be27-45b6-a7cb-5bc20dceb4d5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=80773385250164869024536576612846309142008052470569670890719477972564974275760 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 19.uart_fifo_overflow.80773385250164869024536576612846309142008052470569670890719477972564974275760 |
| Directory | /workspace/19.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/19.uart_fifo_reset.41036999528666498666097942573980966912189975764217698680949159863169682085864 |
| Short name | T1241 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 112.54 seconds |
| Started | Nov 22 01:44:43 PM PST 23 |
| Finished | Nov 22 01:46:37 PM PST 23 |
| Peak memory | 198900 kb |
| Host | smart-1b5efbf7-041e-4cd9-9de6-07c78aec33f6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=41036999528666498666097942573980966912189975764217698680949159863169682085864 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 19.uart_fifo_reset.41036999528666498666097942573980966912189975764217698680949159863169682085864 |
| Directory | /workspace/19.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/19.uart_intr.2260099965543581396273014601103470228762994840313288850926479755950892243444 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 787145125175 ps |
| CPU time | 786.56 seconds |
| Started | Nov 22 01:44:42 PM PST 23 |
| Finished | Nov 22 01:57:51 PM PST 23 |
| Peak memory | 199964 kb |
| Host | smart-5c98619d-f1cc-4924-8862-fe364fd1c59e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260099965543581396273014601103470228762994840313288850926479755950892243444 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 19.uart_intr.2260099965543581396273014601103470228762994840313288850926479755950892243444 |
| Directory | /workspace/19.uart_intr/latest |
| Test location | /workspace/coverage/default/19.uart_long_xfer_wo_dly.97232782336186688463683727092155864695701320728855721920576124736860734324254 |
| Short name | T829 |
| Test name | |
| Test status | |
| Simulation time | 93387746707 ps |
| CPU time | 356.92 seconds |
| Started | Nov 22 01:44:45 PM PST 23 |
| Finished | Nov 22 01:50:45 PM PST 23 |
| Peak memory | 200136 kb |
| Host | smart-79f22db3-970e-42f3-afc2-e55838b15803 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=97232782336186688463683727092155864695701320728855721920576124736860734324254 -assert nopostproc +UVM_TES TNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 19.uart_long_xfer_wo_dly.97232782336186688463683727092155864695701320728855721920576124736860734324254 |
| Directory | /workspace/19.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/19.uart_loopback.73161074313462538179061940291290136483958950709348326803504658146292169790211 |
| Short name | T823 |
| Test name | |
| Test status | |
| Simulation time | 14572448663 ps |
| CPU time | 16 seconds |
| Started | Nov 22 01:44:38 PM PST 23 |
| Finished | Nov 22 01:44:56 PM PST 23 |
| Peak memory | 200048 kb |
| Host | smart-97696774-c291-4e44-a8ad-861f6128afe9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=73161074313462538179061940291290136483958950709348326803504658146292169790211 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 19.uart_loopback.73161074313462538179061940291290136483958950709348326803504658146292169790211 |
| Directory | /workspace/19.uart_loopback/latest |
| Test location | /workspace/coverage/default/19.uart_noise_filter.190183103927684547414822735623307140510769457070697465952180048148306863753 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 94501577082 ps |
| CPU time | 97.18 seconds |
| Started | Nov 22 01:44:44 PM PST 23 |
| Finished | Nov 22 01:46:23 PM PST 23 |
| Peak memory | 200236 kb |
| Host | smart-8083ee12-a2d5-47bb-a93c-bedba5ae4d27 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=190183103927684547414822735623307140510769457070697465952180048148306863753 -assert nopostproc +UVM_TESTNAME=uart_base_t est +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 19.uart_noise_filter.190183103927684547414822735623307140510769457070697465952180048148306863753 |
| Directory | /workspace/19.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/19.uart_perf.19767551554500320887071104378699487791129429975168478529005026058299362775939 |
| Short name | T980 |
| Test name | |
| Test status | |
| Simulation time | 14098773881 ps |
| CPU time | 469.77 seconds |
| Started | Nov 22 01:44:43 PM PST 23 |
| Finished | Nov 22 01:52:35 PM PST 23 |
| Peak memory | 200112 kb |
| Host | smart-3f476e21-cec4-40b7-b72b-38f530134012 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=19767551554500320887071104378699487791129429975168478529005026058299362775939 -assert nopostproc +UVM_TES TNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 19.uart_perf.19767551554500320887071104378699487791129429975168478529005026058299362775939 |
| Directory | /workspace/19.uart_perf/latest |
| Test location | /workspace/coverage/default/19.uart_rx_oversample.36807064863981624193554232757406780472368052000076858953706911851326822524268 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 4370280281 ps |
| CPU time | 20.49 seconds |
| Started | Nov 22 01:44:42 PM PST 23 |
| Finished | Nov 22 01:45:05 PM PST 23 |
| Peak memory | 198976 kb |
| Host | smart-3a0afd00-f67a-4893-9bd2-15a91f779006 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=36807064863981624193554232757406780472368052000076858953706911851326822524268 -assert nopostproc +UVM_TES TNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 19.uart_rx_oversample.36807064863981624193554232757406780472368052000076858953706911851326822524268 |
| Directory | /workspace/19.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/19.uart_rx_parity_err.102574273516771910798684952839746696146797431695516360346588475376675998048977 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 36616611594 ps |
| CPU time | 38.27 seconds |
| Started | Nov 22 01:44:40 PM PST 23 |
| Finished | Nov 22 01:45:20 PM PST 23 |
| Peak memory | 200040 kb |
| Host | smart-cbe302e8-296a-4c36-a7e4-48da48da791a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=102574273516771910798684952839746696146797431695516360346588475376675998048977 -assert nopostproc +UVM_TESTNAME=uart_bas e_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 19.uart_rx_parity_err.102574273516771910798684952839746696146797431695516360346588475376675998048977 |
| Directory | /workspace/19.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/19.uart_rx_start_bit_filter.7094601347995636533199866300933970850968771182086452830575119313978122546676 |
| Short name | T840 |
| Test name | |
| Test status | |
| Simulation time | 4267638245 ps |
| CPU time | 4.66 seconds |
| Started | Nov 22 01:44:42 PM PST 23 |
| Finished | Nov 22 01:44:48 PM PST 23 |
| Peak memory | 195876 kb |
| Host | smart-0eb7131b-0e8a-4021-8d4f-93ed21680213 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=7094601347995636533199866300933970850968771182086452830575119313978122546676 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 19.uart_rx_start_bit_filter.7094601347995636533199866300933970850968771182086452830575119313978122546676 |
| Directory | /workspace/19.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/19.uart_smoke.92932962834761253686422400448970872654018966110531662261066116778320592869086 |
| Short name | T1128 |
| Test name | |
| Test status | |
| Simulation time | 5759626309 ps |
| CPU time | 18.93 seconds |
| Started | Nov 22 01:44:41 PM PST 23 |
| Finished | Nov 22 01:45:02 PM PST 23 |
| Peak memory | 199536 kb |
| Host | smart-2131f1d3-cf50-4722-ad10-889e6b0c332d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=92932962834761253686422400448970872654018966110531662261066116778320592869086 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 19.uart_smoke.92932962834761253686422400448970872654018966110531662261066116778320592869086 |
| Directory | /workspace/19.uart_smoke/latest |
| Test location | /workspace/coverage/default/19.uart_stress_all.34283305657743389926443860409453923741494088598308552064811685150156352292273 |
| Short name | T704 |
| Test name | |
| Test status | |
| Simulation time | 43402307308 ps |
| CPU time | 56.6 seconds |
| Started | Nov 22 01:44:48 PM PST 23 |
| Finished | Nov 22 01:45:48 PM PST 23 |
| Peak memory | 200064 kb |
| Host | smart-8ddc9d4e-b045-48dc-95e6-d8c3ebdaac81 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34283305657743389926443860409453923741494088598308552064811685150156352292273 -assert nopos tproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 19.uart_stress_all.34283305657743389926443860409453923741494088598308552064811685150156352292273 |
| Directory | /workspace/19.uart_stress_all/latest |
| Test location | /workspace/coverage/default/19.uart_stress_all_with_rand_reset.35301273932131699531557105845129160370973881952964213087642675697942050025416 |
| Short name | T744 |
| Test name | |
| Test status | |
| Simulation time | 87476847566 ps |
| CPU time | 467.19 seconds |
| Started | Nov 22 01:44:48 PM PST 23 |
| Finished | Nov 22 01:52:38 PM PST 23 |
| Peak memory | 226196 kb |
| Host | smart-6e8af771-0400-4d68-9a58-69836863d2ca |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35301273932131699531557105 845129160370973881952964213087642675697942050025416 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_stress_all_with_rand_reset.3530127393213 1699531557105845129160370973881952964213087642675697942050025416 |
| Directory | /workspace/19.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/19.uart_tx_ovrd.36288366829959505503946951544738046693106698774488472397007019467867912117649 |
| Short name | T883 |
| Test name | |
| Test status | |
| Simulation time | 485186362 ps |
| CPU time | 1.23 seconds |
| Started | Nov 22 01:44:47 PM PST 23 |
| Finished | Nov 22 01:44:51 PM PST 23 |
| Peak memory | 197916 kb |
| Host | smart-f0a932ad-2735-4761-b2d0-06382e87856b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=36288366829959505503946951544738046693106698774488472397007019467867912117649 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 19.uart_tx_ovrd.36288366829959505503946951544738046693106698774488472397007019467867912117649 |
| Directory | /workspace/19.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/19.uart_tx_rx.32219684118033801118578958659993721057470179882694543201487227539318972961493 |
| Short name | T725 |
| Test name | |
| Test status | |
| Simulation time | 57391945390 ps |
| CPU time | 63.61 seconds |
| Started | Nov 22 01:44:43 PM PST 23 |
| Finished | Nov 22 01:45:48 PM PST 23 |
| Peak memory | 200052 kb |
| Host | smart-4d31bf01-40d9-47d6-9ef6-15d5272cfff0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=32219684118033801118578958659993721057470179882694543201487227539318972961493 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 19.uart_tx_rx.32219684118033801118578958659993721057470179882694543201487227539318972961493 |
| Directory | /workspace/19.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/190.uart_fifo_reset.115268745488176021769779088103318182981686358928698260612946957080779971504819 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 113.8 seconds |
| Started | Nov 22 01:46:34 PM PST 23 |
| Finished | Nov 22 01:48:29 PM PST 23 |
| Peak memory | 198924 kb |
| Host | smart-79dc0085-3ecc-49ed-98e0-17126af8f05b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=115268745488176021769779088103318182981686358928698260612946957080779971504819 -assert nopostproc +UVM_TESTNAME=uart_bas e_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.uart_fifo_reset.115268745488176021769779088103318182981686358928698260612946957080779971504819 |
| Directory | /workspace/190.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/191.uart_fifo_reset.94421892899885328917633463870909217679660777611391074527347097198928800046948 |
| Short name | T877 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 113.38 seconds |
| Started | Nov 22 01:46:36 PM PST 23 |
| Finished | Nov 22 01:48:30 PM PST 23 |
| Peak memory | 198904 kb |
| Host | smart-1ba3ed8b-1ae3-4684-bf14-47be632a3088 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=94421892899885328917633463870909217679660777611391074527347097198928800046948 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 191.uart_fifo_reset.94421892899885328917633463870909217679660777611391074527347097198928800046948 |
| Directory | /workspace/191.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/192.uart_fifo_reset.64545788864737088628790242445697629560674370162532871896612806571334127046744 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 113 seconds |
| Started | Nov 22 01:46:31 PM PST 23 |
| Finished | Nov 22 01:48:25 PM PST 23 |
| Peak memory | 198880 kb |
| Host | smart-b2f85fe6-ed9d-4feb-9da2-202a63dae1b3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=64545788864737088628790242445697629560674370162532871896612806571334127046744 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 192.uart_fifo_reset.64545788864737088628790242445697629560674370162532871896612806571334127046744 |
| Directory | /workspace/192.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/193.uart_fifo_reset.26192574138265395247328812779986329598718888085399495273030214956493072800026 |
| Short name | T1194 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 113.66 seconds |
| Started | Nov 22 01:46:23 PM PST 23 |
| Finished | Nov 22 01:48:17 PM PST 23 |
| Peak memory | 198768 kb |
| Host | smart-3672cadf-1c12-4949-97eb-a93e08ab6705 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=26192574138265395247328812779986329598718888085399495273030214956493072800026 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 193.uart_fifo_reset.26192574138265395247328812779986329598718888085399495273030214956493072800026 |
| Directory | /workspace/193.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/194.uart_fifo_reset.47176220739878460067350682631175868975626372360948505783526739666213434592038 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 113.51 seconds |
| Started | Nov 22 01:45:57 PM PST 23 |
| Finished | Nov 22 01:47:59 PM PST 23 |
| Peak memory | 198852 kb |
| Host | smart-e76e42f1-abd6-47d3-a1ff-dc5b056d7ede |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=47176220739878460067350682631175868975626372360948505783526739666213434592038 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 194.uart_fifo_reset.47176220739878460067350682631175868975626372360948505783526739666213434592038 |
| Directory | /workspace/194.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/195.uart_fifo_reset.37977695528074848048184548558232209673334873430723017126057461674813674593597 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 112.36 seconds |
| Started | Nov 22 01:46:16 PM PST 23 |
| Finished | Nov 22 01:48:10 PM PST 23 |
| Peak memory | 198760 kb |
| Host | smart-0a0892d8-3556-4371-9c41-97c9ae188ca1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=37977695528074848048184548558232209673334873430723017126057461674813674593597 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 195.uart_fifo_reset.37977695528074848048184548558232209673334873430723017126057461674813674593597 |
| Directory | /workspace/195.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/196.uart_fifo_reset.50595113075410725015258060604544506895381066197049476606125741462495474766281 |
| Short name | T989 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 112.89 seconds |
| Started | Nov 22 01:45:59 PM PST 23 |
| Finished | Nov 22 01:48:00 PM PST 23 |
| Peak memory | 198912 kb |
| Host | smart-b222d727-42e1-46f7-aa73-d509cc657bc2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=50595113075410725015258060604544506895381066197049476606125741462495474766281 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 196.uart_fifo_reset.50595113075410725015258060604544506895381066197049476606125741462495474766281 |
| Directory | /workspace/196.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/197.uart_fifo_reset.7685156527297319268809467722553570101241442809954800052852222679412742041695 |
| Short name | T941 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 113.18 seconds |
| Started | Nov 22 01:46:02 PM PST 23 |
| Finished | Nov 22 01:48:01 PM PST 23 |
| Peak memory | 199016 kb |
| Host | smart-e03f186a-9bab-48d8-bfab-feb2317a8d11 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=7685156527297319268809467722553570101241442809954800052852222679412742041695 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 197.uart_fifo_reset.7685156527297319268809467722553570101241442809954800052852222679412742041695 |
| Directory | /workspace/197.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/198.uart_fifo_reset.107759101825954287700601999678453163166482756949109706787342103135109863127716 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 113.39 seconds |
| Started | Nov 22 01:46:10 PM PST 23 |
| Finished | Nov 22 01:48:08 PM PST 23 |
| Peak memory | 198904 kb |
| Host | smart-3d4b305c-4a05-4380-b06b-51dfa21a1200 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=107759101825954287700601999678453163166482756949109706787342103135109863127716 -assert nopostproc +UVM_TESTNAME=uart_bas e_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.uart_fifo_reset.107759101825954287700601999678453163166482756949109706787342103135109863127716 |
| Directory | /workspace/198.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/199.uart_fifo_reset.89981978246429890125370722373817297204446755437603228604198509258382461470869 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 112.87 seconds |
| Started | Nov 22 01:46:16 PM PST 23 |
| Finished | Nov 22 01:48:10 PM PST 23 |
| Peak memory | 198816 kb |
| Host | smart-ba46306f-f37d-4896-a1ab-a39b963bd1ec |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=89981978246429890125370722373817297204446755437603228604198509258382461470869 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 199.uart_fifo_reset.89981978246429890125370722373817297204446755437603228604198509258382461470869 |
| Directory | /workspace/199.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/2.uart_alert_test.84145886677067554611148701546111461735828086328677787611139042805872301667690 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 16368684 ps |
| CPU time | 0.54 seconds |
| Started | Nov 22 01:43:45 PM PST 23 |
| Finished | Nov 22 01:43:47 PM PST 23 |
| Peak memory | 194676 kb |
| Host | smart-ce3bdfb7-0c71-4d6f-a4fd-d5cb079361f0 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84145886677067554611148701546111461735828086328677787611139042805872301667690 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 2.uart_alert_test.84145886677067554611148701546111461735828086328677787611139042805872301667690 |
| Directory | /workspace/2.uart_alert_test/latest |
| Test location | /workspace/coverage/default/2.uart_fifo_full.8407204753851648710183365020414190606505166322669389050561631835694968593534 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 61777160308 ps |
| CPU time | 61.59 seconds |
| Started | Nov 22 01:43:56 PM PST 23 |
| Finished | Nov 22 01:45:01 PM PST 23 |
| Peak memory | 200136 kb |
| Host | smart-c513c4d8-e16f-46a0-8033-ada4db863b20 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=8407204753851648710183365020414190606505166322669389050561631835694968593534 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 2.uart_fifo_full.8407204753851648710183365020414190606505166322669389050561631835694968593534 |
| Directory | /workspace/2.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/2.uart_fifo_overflow.20965108198973338513549016375477930187049434605488415034840978535782996839194 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 58551936110 ps |
| CPU time | 54.51 seconds |
| Started | Nov 22 01:43:55 PM PST 23 |
| Finished | Nov 22 01:44:53 PM PST 23 |
| Peak memory | 199884 kb |
| Host | smart-fd98bc32-569e-4fec-85df-999e0fb9bae3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=20965108198973338513549016375477930187049434605488415034840978535782996839194 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 2.uart_fifo_overflow.20965108198973338513549016375477930187049434605488415034840978535782996839194 |
| Directory | /workspace/2.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/2.uart_fifo_reset.105693419353712078637058557215387359931438264192061228979068065767178728401591 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 114.2 seconds |
| Started | Nov 22 01:43:53 PM PST 23 |
| Finished | Nov 22 01:45:51 PM PST 23 |
| Peak memory | 198900 kb |
| Host | smart-046a4168-6a0e-4ff2-9696-23a33f1f8aa5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=105693419353712078637058557215387359931438264192061228979068065767178728401591 -assert nopostproc +UVM_TESTNAME=uart_bas e_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_reset.105693419353712078637058557215387359931438264192061228979068065767178728401591 |
| Directory | /workspace/2.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/2.uart_intr.45042240166751624183948998917685698540773248247679793485139195650974644846232 |
| Short name | T750 |
| Test name | |
| Test status | |
| Simulation time | 787145125175 ps |
| CPU time | 785.45 seconds |
| Started | Nov 22 01:43:58 PM PST 23 |
| Finished | Nov 22 01:57:07 PM PST 23 |
| Peak memory | 199956 kb |
| Host | smart-40b2ae29-0c5e-429a-8d6c-00c3a1d55327 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45042240166751624183948998917685698540773248247679793485139195650974644846232 -assert nopost proc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 2.uart_intr.45042240166751624183948998917685698540773248247679793485139195650974644846232 |
| Directory | /workspace/2.uart_intr/latest |
| Test location | /workspace/coverage/default/2.uart_long_xfer_wo_dly.86428258156294570653551253438499732970122441549491009956358010963129883935652 |
| Short name | T1090 |
| Test name | |
| Test status | |
| Simulation time | 93387746707 ps |
| CPU time | 350.51 seconds |
| Started | Nov 22 01:43:38 PM PST 23 |
| Finished | Nov 22 01:49:30 PM PST 23 |
| Peak memory | 200144 kb |
| Host | smart-f768d48f-0ab5-44c5-a40e-941875f0616a |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=86428258156294570653551253438499732970122441549491009956358010963129883935652 -assert nopostproc +UVM_TES TNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 2.uart_long_xfer_wo_dly.86428258156294570653551253438499732970122441549491009956358010963129883935652 |
| Directory | /workspace/2.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/2.uart_loopback.10711027316355451351472764097153979149467917870898421457283321215846171207750 |
| Short name | T1021 |
| Test name | |
| Test status | |
| Simulation time | 14572448663 ps |
| CPU time | 16.18 seconds |
| Started | Nov 22 01:43:59 PM PST 23 |
| Finished | Nov 22 01:44:19 PM PST 23 |
| Peak memory | 199980 kb |
| Host | smart-260924cc-dc85-40e6-b472-8ca4d140919e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=10711027316355451351472764097153979149467917870898421457283321215846171207750 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 2.uart_loopback.10711027316355451351472764097153979149467917870898421457283321215846171207750 |
| Directory | /workspace/2.uart_loopback/latest |
| Test location | /workspace/coverage/default/2.uart_noise_filter.92785398780028542806927105580636942685012121462002469263948010354473902045622 |
| Short name | T1127 |
| Test name | |
| Test status | |
| Simulation time | 94501577082 ps |
| CPU time | 97.08 seconds |
| Started | Nov 22 01:43:56 PM PST 23 |
| Finished | Nov 22 01:45:37 PM PST 23 |
| Peak memory | 200180 kb |
| Host | smart-d012f6a3-5164-4aa5-a505-af4fc4ab1780 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=92785398780028542806927105580636942685012121462002469263948010354473902045622 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_noise_filter.92785398780028542806927105580636942685012121462002469263948010354473902045622 |
| Directory | /workspace/2.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/2.uart_perf.33039664832056078714101916702041321627712764673164603527302415629551286640363 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 14098773881 ps |
| CPU time | 472.78 seconds |
| Started | Nov 22 01:44:00 PM PST 23 |
| Finished | Nov 22 01:51:57 PM PST 23 |
| Peak memory | 200024 kb |
| Host | smart-c9a8ce24-8b70-4f30-9f10-0769c2b30131 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=33039664832056078714101916702041321627712764673164603527302415629551286640363 -assert nopostproc +UVM_TES TNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 2.uart_perf.33039664832056078714101916702041321627712764673164603527302415629551286640363 |
| Directory | /workspace/2.uart_perf/latest |
| Test location | /workspace/coverage/default/2.uart_rx_oversample.60916067084330516840018896183264669285736995694072702762512582769370391503353 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 4370280281 ps |
| CPU time | 19.72 seconds |
| Started | Nov 22 01:43:46 PM PST 23 |
| Finished | Nov 22 01:44:07 PM PST 23 |
| Peak memory | 198812 kb |
| Host | smart-9507b5a3-ef63-44d2-a668-629143409f5a |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=60916067084330516840018896183264669285736995694072702762512582769370391503353 -assert nopostproc +UVM_TES TNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 2.uart_rx_oversample.60916067084330516840018896183264669285736995694072702762512582769370391503353 |
| Directory | /workspace/2.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/2.uart_rx_parity_err.62554848544371426014703443709488628852342422458706123543847007238580391459497 |
| Short name | T853 |
| Test name | |
| Test status | |
| Simulation time | 36616611594 ps |
| CPU time | 38.38 seconds |
| Started | Nov 22 01:43:53 PM PST 23 |
| Finished | Nov 22 01:44:34 PM PST 23 |
| Peak memory | 200148 kb |
| Host | smart-2892d693-5483-4365-8fe5-7b27c65ae4d8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=62554848544371426014703443709488628852342422458706123543847007238580391459497 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 2.uart_rx_parity_err.62554848544371426014703443709488628852342422458706123543847007238580391459497 |
| Directory | /workspace/2.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/2.uart_rx_start_bit_filter.25717209490956102145389152489939327194167120884630076262258640876902405577597 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 4267638245 ps |
| CPU time | 4.67 seconds |
| Started | Nov 22 01:43:56 PM PST 23 |
| Finished | Nov 22 01:44:04 PM PST 23 |
| Peak memory | 195940 kb |
| Host | smart-52fdc60f-bd5a-46d5-9735-c4fb3b9f0145 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=25717209490956102145389152489939327194167120884630076262258640876902405577597 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 2.uart_rx_start_bit_filter.25717209490956102145389152489939327194167120884630076262258640876902405577597 |
| Directory | /workspace/2.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/2.uart_sec_cm.31723527172744410098793049876543152144735244282644203753582481236763434476996 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 100582296 ps |
| CPU time | 0.85 seconds |
| Started | Nov 22 01:43:58 PM PST 23 |
| Finished | Nov 22 01:44:02 PM PST 23 |
| Peak memory | 218396 kb |
| Host | smart-fbb2ad3f-f7cc-4dc7-95bf-f45087ae74bf |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31723527172744410098793049876543152144735244282644203753582481236763434476996 -assert nopostpro c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 2.uart_sec_cm.31723527172744410098793049876543152144735244282644203753582481236763434476996 |
| Directory | /workspace/2.uart_sec_cm/latest |
| Test location | /workspace/coverage/default/2.uart_smoke.243073752306685893494456474077969100525539379609639809393762321347377657886 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 5759626309 ps |
| CPU time | 18.75 seconds |
| Started | Nov 22 01:43:53 PM PST 23 |
| Finished | Nov 22 01:44:16 PM PST 23 |
| Peak memory | 199612 kb |
| Host | smart-7c2dce2b-0788-48b6-b4ed-8f51cdc12ef7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=243073752306685893494456474077969100525539379609639809393762321347377657886 -assert nopostproc +UVM_TESTNAME=uart_base_t est +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_smoke.243073752306685893494456474077969100525539379609639809393762321347377657886 |
| Directory | /workspace/2.uart_smoke/latest |
| Test location | /workspace/coverage/default/2.uart_stress_all.1855234253512178992927107363436027519335135437110490413383172175483657421887 |
| Short name | T1019 |
| Test name | |
| Test status | |
| Simulation time | 43402307308 ps |
| CPU time | 56.9 seconds |
| Started | Nov 22 01:43:48 PM PST 23 |
| Finished | Nov 22 01:44:47 PM PST 23 |
| Peak memory | 200092 kb |
| Host | smart-5747872f-bf36-4830-b34c-b03c33478895 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855234253512178992927107363436027519335135437110490413383172175483657421887 -assert nopost proc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 2.uart_stress_all.1855234253512178992927107363436027519335135437110490413383172175483657421887 |
| Directory | /workspace/2.uart_stress_all/latest |
| Test location | /workspace/coverage/default/2.uart_stress_all_with_rand_reset.48230068070456656288838308239620000219488017544773249749329429268683989931068 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 87476847566 ps |
| CPU time | 456.74 seconds |
| Started | Nov 22 01:44:05 PM PST 23 |
| Finished | Nov 22 01:51:46 PM PST 23 |
| Peak memory | 226228 kb |
| Host | smart-9948044f-c194-4d47-af31-72daf7bf4a68 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48230068070456656288838308 239620000219488017544773249749329429268683989931068 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_stress_all_with_rand_reset.48230068070456 656288838308239620000219488017544773249749329429268683989931068 |
| Directory | /workspace/2.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/2.uart_tx_ovrd.56186484443527636386083579164454996404056539294736662643470121487977061981176 |
| Short name | T936 |
| Test name | |
| Test status | |
| Simulation time | 485186362 ps |
| CPU time | 1.27 seconds |
| Started | Nov 22 01:44:04 PM PST 23 |
| Finished | Nov 22 01:44:09 PM PST 23 |
| Peak memory | 197864 kb |
| Host | smart-20185904-1a87-4e6a-ae8f-e26fd77f3953 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=56186484443527636386083579164454996404056539294736662643470121487977061981176 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 2.uart_tx_ovrd.56186484443527636386083579164454996404056539294736662643470121487977061981176 |
| Directory | /workspace/2.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/2.uart_tx_rx.32706535035999515362440312006676418176845204451191340610954258465053957749841 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 57391945390 ps |
| CPU time | 64.46 seconds |
| Started | Nov 22 01:43:52 PM PST 23 |
| Finished | Nov 22 01:45:00 PM PST 23 |
| Peak memory | 200072 kb |
| Host | smart-447c5c00-e2b2-4cb1-a0b9-5f01faa839bc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=32706535035999515362440312006676418176845204451191340610954258465053957749841 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 2.uart_tx_rx.32706535035999515362440312006676418176845204451191340610954258465053957749841 |
| Directory | /workspace/2.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/20.uart_alert_test.93762998391982074971079568793006930384625033487543027275773601829860501700784 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 16368684 ps |
| CPU time | 0.54 seconds |
| Started | Nov 22 01:44:41 PM PST 23 |
| Finished | Nov 22 01:44:43 PM PST 23 |
| Peak memory | 194620 kb |
| Host | smart-75219e70-fa5e-4434-9cc4-f1dd02c4c548 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93762998391982074971079568793006930384625033487543027275773601829860501700784 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 20.uart_alert_test.93762998391982074971079568793006930384625033487543027275773601829860501700784 |
| Directory | /workspace/20.uart_alert_test/latest |
| Test location | /workspace/coverage/default/20.uart_fifo_full.19341903189555946956050268275592064495228999647818936885297651819717597487292 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 61777160308 ps |
| CPU time | 60.08 seconds |
| Started | Nov 22 01:44:43 PM PST 23 |
| Finished | Nov 22 01:45:45 PM PST 23 |
| Peak memory | 200128 kb |
| Host | smart-abe842b4-9552-4fbb-b56e-d930a55a523a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=19341903189555946956050268275592064495228999647818936885297651819717597487292 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 20.uart_fifo_full.19341903189555946956050268275592064495228999647818936885297651819717597487292 |
| Directory | /workspace/20.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/20.uart_fifo_overflow.76903698721227963247981773388880512693543236794690410466911794814627562347347 |
| Short name | T1151 |
| Test name | |
| Test status | |
| Simulation time | 58551936110 ps |
| CPU time | 54.81 seconds |
| Started | Nov 22 01:44:42 PM PST 23 |
| Finished | Nov 22 01:45:38 PM PST 23 |
| Peak memory | 199812 kb |
| Host | smart-3a4beb94-15d7-44cf-b4a4-ff4469afe508 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=76903698721227963247981773388880512693543236794690410466911794814627562347347 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 20.uart_fifo_overflow.76903698721227963247981773388880512693543236794690410466911794814627562347347 |
| Directory | /workspace/20.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/20.uart_fifo_reset.101913514601052507644098600168826679751267517255312896453587174426778147914966 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 113.29 seconds |
| Started | Nov 22 01:44:45 PM PST 23 |
| Finished | Nov 22 01:46:41 PM PST 23 |
| Peak memory | 198908 kb |
| Host | smart-ca9e6ee2-94e7-46ce-9213-4a42720a7016 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=101913514601052507644098600168826679751267517255312896453587174426778147914966 -assert nopostproc +UVM_TESTNAME=uart_bas e_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_reset.101913514601052507644098600168826679751267517255312896453587174426778147914966 |
| Directory | /workspace/20.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/20.uart_intr.77066827507097436369953298365368131633082155043264860176134532720229678446722 |
| Short name | T723 |
| Test name | |
| Test status | |
| Simulation time | 787145125175 ps |
| CPU time | 787.22 seconds |
| Started | Nov 22 01:44:44 PM PST 23 |
| Finished | Nov 22 01:57:53 PM PST 23 |
| Peak memory | 200132 kb |
| Host | smart-f21b8705-87fa-44b6-b2e6-a760f8bb047b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77066827507097436369953298365368131633082155043264860176134532720229678446722 -assert nopost proc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 20.uart_intr.77066827507097436369953298365368131633082155043264860176134532720229678446722 |
| Directory | /workspace/20.uart_intr/latest |
| Test location | /workspace/coverage/default/20.uart_long_xfer_wo_dly.26373370330898970733964728765331564801145002876355792915259749578264095222944 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 93387746707 ps |
| CPU time | 357.61 seconds |
| Started | Nov 22 01:44:38 PM PST 23 |
| Finished | Nov 22 01:50:37 PM PST 23 |
| Peak memory | 200084 kb |
| Host | smart-c5fa9c86-1703-4d46-af37-1e2b4a6ff629 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=26373370330898970733964728765331564801145002876355792915259749578264095222944 -assert nopostproc +UVM_TES TNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 20.uart_long_xfer_wo_dly.26373370330898970733964728765331564801145002876355792915259749578264095222944 |
| Directory | /workspace/20.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/20.uart_loopback.87613047469127267192361328424488940102730737647044644963687214327072723549376 |
| Short name | T975 |
| Test name | |
| Test status | |
| Simulation time | 14572448663 ps |
| CPU time | 16.09 seconds |
| Started | Nov 22 01:44:35 PM PST 23 |
| Finished | Nov 22 01:44:54 PM PST 23 |
| Peak memory | 200084 kb |
| Host | smart-447159fe-b427-4588-ab01-a34af3fa9010 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=87613047469127267192361328424488940102730737647044644963687214327072723549376 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 20.uart_loopback.87613047469127267192361328424488940102730737647044644963687214327072723549376 |
| Directory | /workspace/20.uart_loopback/latest |
| Test location | /workspace/coverage/default/20.uart_noise_filter.77512976307672315268288252122393027174864133299060590048196107178268188799926 |
| Short name | T1107 |
| Test name | |
| Test status | |
| Simulation time | 94501577082 ps |
| CPU time | 97.26 seconds |
| Started | Nov 22 01:44:41 PM PST 23 |
| Finished | Nov 22 01:46:20 PM PST 23 |
| Peak memory | 200248 kb |
| Host | smart-bc7e0140-71e4-4339-8557-9da28c36f095 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=77512976307672315268288252122393027174864133299060590048196107178268188799926 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_noise_filter.77512976307672315268288252122393027174864133299060590048196107178268188799926 |
| Directory | /workspace/20.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/20.uart_perf.40693273442163974388858844501843138610003286853342416209444316996456840206936 |
| Short name | T1173 |
| Test name | |
| Test status | |
| Simulation time | 14098773881 ps |
| CPU time | 473.83 seconds |
| Started | Nov 22 01:44:43 PM PST 23 |
| Finished | Nov 22 01:52:39 PM PST 23 |
| Peak memory | 200164 kb |
| Host | smart-306d5113-7671-4aa7-a3f6-1e27fc6a496a |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=40693273442163974388858844501843138610003286853342416209444316996456840206936 -assert nopostproc +UVM_TES TNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 20.uart_perf.40693273442163974388858844501843138610003286853342416209444316996456840206936 |
| Directory | /workspace/20.uart_perf/latest |
| Test location | /workspace/coverage/default/20.uart_rx_oversample.105365469624877367485886345983286885732663460418967510504966947233005388475328 |
| Short name | T1111 |
| Test name | |
| Test status | |
| Simulation time | 4370280281 ps |
| CPU time | 20.19 seconds |
| Started | Nov 22 01:44:44 PM PST 23 |
| Finished | Nov 22 01:45:06 PM PST 23 |
| Peak memory | 198888 kb |
| Host | smart-f2c4b1f1-8ada-47f2-81e3-a73f8dffca7e |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=105365469624877367485886345983286885732663460418967510504966947233005388475328 -assert nopostproc +UVM_TE STNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_oversample.105365469624877367485886345983286885732663460418967510504966947233005388475328 |
| Directory | /workspace/20.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/20.uart_rx_parity_err.114458105350778913080550559115359196958867484076126893316211830993205214597402 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 36616611594 ps |
| CPU time | 37.78 seconds |
| Started | Nov 22 01:44:45 PM PST 23 |
| Finished | Nov 22 01:45:25 PM PST 23 |
| Peak memory | 200028 kb |
| Host | smart-0abbe7d3-b3e5-41bb-9d73-7c79b0b11c17 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=114458105350778913080550559115359196958867484076126893316211830993205214597402 -assert nopostproc +UVM_TESTNAME=uart_bas e_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 20.uart_rx_parity_err.114458105350778913080550559115359196958867484076126893316211830993205214597402 |
| Directory | /workspace/20.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/20.uart_rx_start_bit_filter.78892487319397160746636228663721712871122398929320182125979789950332906739980 |
| Short name | T1170 |
| Test name | |
| Test status | |
| Simulation time | 4267638245 ps |
| CPU time | 4.71 seconds |
| Started | Nov 22 01:44:45 PM PST 23 |
| Finished | Nov 22 01:44:52 PM PST 23 |
| Peak memory | 195848 kb |
| Host | smart-41c70c95-04d3-4a29-a3e7-d6c34cf8b56b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=78892487319397160746636228663721712871122398929320182125979789950332906739980 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 20.uart_rx_start_bit_filter.78892487319397160746636228663721712871122398929320182125979789950332906739980 |
| Directory | /workspace/20.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/20.uart_smoke.13446260229507086322373163949542263713895654353569043397000025128189201903496 |
| Short name | T1099 |
| Test name | |
| Test status | |
| Simulation time | 5759626309 ps |
| CPU time | 18.08 seconds |
| Started | Nov 22 01:44:49 PM PST 23 |
| Finished | Nov 22 01:45:10 PM PST 23 |
| Peak memory | 199480 kb |
| Host | smart-19848284-e385-4270-9f30-505366b8fb07 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=13446260229507086322373163949542263713895654353569043397000025128189201903496 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 20.uart_smoke.13446260229507086322373163949542263713895654353569043397000025128189201903496 |
| Directory | /workspace/20.uart_smoke/latest |
| Test location | /workspace/coverage/default/20.uart_stress_all.61238301385977243867121572296621239343499572739558268530540031206598242689677 |
| Short name | T917 |
| Test name | |
| Test status | |
| Simulation time | 43402307308 ps |
| CPU time | 56.68 seconds |
| Started | Nov 22 01:44:37 PM PST 23 |
| Finished | Nov 22 01:45:36 PM PST 23 |
| Peak memory | 200052 kb |
| Host | smart-5f2ecc5d-f91c-4c2b-bdaf-1994a8bf3c07 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61238301385977243867121572296621239343499572739558268530540031206598242689677 -assert nopos tproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 20.uart_stress_all.61238301385977243867121572296621239343499572739558268530540031206598242689677 |
| Directory | /workspace/20.uart_stress_all/latest |
| Test location | /workspace/coverage/default/20.uart_stress_all_with_rand_reset.98012202964299112575666141575744494334428115020248504234815760871192583122977 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 87476847566 ps |
| CPU time | 461.89 seconds |
| Started | Nov 22 01:44:41 PM PST 23 |
| Finished | Nov 22 01:52:25 PM PST 23 |
| Peak memory | 226260 kb |
| Host | smart-95d7f66f-c176-4ae8-8fe2-4a88f8083360 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98012202964299112575666141 575744494334428115020248504234815760871192583122977 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_stress_all_with_rand_reset.9801220296429 9112575666141575744494334428115020248504234815760871192583122977 |
| Directory | /workspace/20.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/20.uart_tx_ovrd.17034741505902693820858302195697947605617094400859055019258361520669332257575 |
| Short name | T697 |
| Test name | |
| Test status | |
| Simulation time | 485186362 ps |
| CPU time | 1.27 seconds |
| Started | Nov 22 01:44:46 PM PST 23 |
| Finished | Nov 22 01:44:50 PM PST 23 |
| Peak memory | 197940 kb |
| Host | smart-a69b1656-2f1f-46d1-b87f-9837d5f0b1a5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=17034741505902693820858302195697947605617094400859055019258361520669332257575 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 20.uart_tx_ovrd.17034741505902693820858302195697947605617094400859055019258361520669332257575 |
| Directory | /workspace/20.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/20.uart_tx_rx.110898900791691132610021880085021579762042811390129129190538039030784298676664 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 57391945390 ps |
| CPU time | 63.97 seconds |
| Started | Nov 22 01:44:31 PM PST 23 |
| Finished | Nov 22 01:45:42 PM PST 23 |
| Peak memory | 199980 kb |
| Host | smart-b3b306b9-8887-4863-b8d6-e19486f84147 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=110898900791691132610021880085021579762042811390129129190538039030784298676664 -assert nopostproc +UVM_TESTNAME=uart_bas e_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 20.uart_tx_rx.110898900791691132610021880085021579762042811390129129190538039030784298676664 |
| Directory | /workspace/20.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/200.uart_fifo_reset.84257137244382061611564492580890667917769562360692941663684783609205575435910 |
| Short name | T732 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 113.38 seconds |
| Started | Nov 22 01:46:07 PM PST 23 |
| Finished | Nov 22 01:48:07 PM PST 23 |
| Peak memory | 198892 kb |
| Host | smart-f011b955-9b20-4c09-baa3-784f676600d2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=84257137244382061611564492580890667917769562360692941663684783609205575435910 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 200.uart_fifo_reset.84257137244382061611564492580890667917769562360692941663684783609205575435910 |
| Directory | /workspace/200.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/201.uart_fifo_reset.75430045723540358012010279153645169300654593245410478543116275844234121207000 |
| Short name | T1166 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 112.56 seconds |
| Started | Nov 22 01:46:10 PM PST 23 |
| Finished | Nov 22 01:48:08 PM PST 23 |
| Peak memory | 198920 kb |
| Host | smart-77921057-43f4-4b24-82c2-4b3c32aa6f27 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=75430045723540358012010279153645169300654593245410478543116275844234121207000 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 201.uart_fifo_reset.75430045723540358012010279153645169300654593245410478543116275844234121207000 |
| Directory | /workspace/201.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/202.uart_fifo_reset.77475882671084844862766542806802404726999590030925139249703064275843678460676 |
| Short name | T1130 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 113.35 seconds |
| Started | Nov 22 01:46:04 PM PST 23 |
| Finished | Nov 22 01:48:03 PM PST 23 |
| Peak memory | 198908 kb |
| Host | smart-683fb15c-4ace-4309-b207-ec8ae7e936b2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=77475882671084844862766542806802404726999590030925139249703064275843678460676 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 202.uart_fifo_reset.77475882671084844862766542806802404726999590030925139249703064275843678460676 |
| Directory | /workspace/202.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/203.uart_fifo_reset.4981072730288798300584681056576892101835677196418677108203976764796019972038 |
| Short name | T867 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 112.8 seconds |
| Started | Nov 22 01:46:01 PM PST 23 |
| Finished | Nov 22 01:48:00 PM PST 23 |
| Peak memory | 198828 kb |
| Host | smart-441169a0-1726-467c-b2a3-4f90eddfec17 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4981072730288798300584681056576892101835677196418677108203976764796019972038 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 203.uart_fifo_reset.4981072730288798300584681056576892101835677196418677108203976764796019972038 |
| Directory | /workspace/203.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/204.uart_fifo_reset.43685973712690214673539047088251319668620206077457820691074922605896766747734 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 113.59 seconds |
| Started | Nov 22 01:46:11 PM PST 23 |
| Finished | Nov 22 01:48:09 PM PST 23 |
| Peak memory | 198924 kb |
| Host | smart-7092123c-fccb-4abd-812d-07d1757f3df4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=43685973712690214673539047088251319668620206077457820691074922605896766747734 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 204.uart_fifo_reset.43685973712690214673539047088251319668620206077457820691074922605896766747734 |
| Directory | /workspace/204.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/205.uart_fifo_reset.23036518218281636523042838881073787573418563970044011441464520896069575110486 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 113.89 seconds |
| Started | Nov 22 01:46:04 PM PST 23 |
| Finished | Nov 22 01:48:03 PM PST 23 |
| Peak memory | 198896 kb |
| Host | smart-b417930f-9fc3-4321-9301-40afdf56ac1d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=23036518218281636523042838881073787573418563970044011441464520896069575110486 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 205.uart_fifo_reset.23036518218281636523042838881073787573418563970044011441464520896069575110486 |
| Directory | /workspace/205.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/206.uart_fifo_reset.9679263642639524766259331842508545878278534651323386971920739465124447148958 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 113.68 seconds |
| Started | Nov 22 01:46:06 PM PST 23 |
| Finished | Nov 22 01:48:07 PM PST 23 |
| Peak memory | 198924 kb |
| Host | smart-00c9b9f9-8a58-43f2-8866-7cbc42bab892 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=9679263642639524766259331842508545878278534651323386971920739465124447148958 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 206.uart_fifo_reset.9679263642639524766259331842508545878278534651323386971920739465124447148958 |
| Directory | /workspace/206.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/207.uart_fifo_reset.110720193766150279130945287757817980738273440114217507101288757991827447396076 |
| Short name | T827 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 113.28 seconds |
| Started | Nov 22 01:46:13 PM PST 23 |
| Finished | Nov 22 01:48:10 PM PST 23 |
| Peak memory | 198900 kb |
| Host | smart-9b2e93d7-736e-42b5-8c81-6519bdce7059 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=110720193766150279130945287757817980738273440114217507101288757991827447396076 -assert nopostproc +UVM_TESTNAME=uart_bas e_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.uart_fifo_reset.110720193766150279130945287757817980738273440114217507101288757991827447396076 |
| Directory | /workspace/207.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/208.uart_fifo_reset.10948138693547725705272507187729990368090982564318741295547389937137399666615 |
| Short name | T1256 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 113.63 seconds |
| Started | Nov 22 01:46:19 PM PST 23 |
| Finished | Nov 22 01:48:14 PM PST 23 |
| Peak memory | 198992 kb |
| Host | smart-7000c811-32bc-4421-8ab2-75a21c778ee1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=10948138693547725705272507187729990368090982564318741295547389937137399666615 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 208.uart_fifo_reset.10948138693547725705272507187729990368090982564318741295547389937137399666615 |
| Directory | /workspace/208.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/209.uart_fifo_reset.64700263609300068430103780505565349251560328222677893717901440612357973678667 |
| Short name | T1201 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 112.36 seconds |
| Started | Nov 22 01:46:23 PM PST 23 |
| Finished | Nov 22 01:48:17 PM PST 23 |
| Peak memory | 198904 kb |
| Host | smart-38870fec-d01f-47e3-b22f-9d5b630204a3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=64700263609300068430103780505565349251560328222677893717901440612357973678667 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 209.uart_fifo_reset.64700263609300068430103780505565349251560328222677893717901440612357973678667 |
| Directory | /workspace/209.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/21.uart_alert_test.79683645010779762737408422876412862533167403608407190967088473156262116523836 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 16368684 ps |
| CPU time | 0.53 seconds |
| Started | Nov 22 01:44:35 PM PST 23 |
| Finished | Nov 22 01:44:39 PM PST 23 |
| Peak memory | 194504 kb |
| Host | smart-baeee64a-33ce-4ece-b314-90d269bd312c |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79683645010779762737408422876412862533167403608407190967088473156262116523836 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 21.uart_alert_test.79683645010779762737408422876412862533167403608407190967088473156262116523836 |
| Directory | /workspace/21.uart_alert_test/latest |
| Test location | /workspace/coverage/default/21.uart_fifo_full.67371654235519660967151826038621570301786524485778922808283651957332444672331 |
| Short name | T904 |
| Test name | |
| Test status | |
| Simulation time | 61777160308 ps |
| CPU time | 60.49 seconds |
| Started | Nov 22 01:44:42 PM PST 23 |
| Finished | Nov 22 01:45:45 PM PST 23 |
| Peak memory | 200088 kb |
| Host | smart-217db2c0-13b2-4328-a62d-243a3bb40936 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=67371654235519660967151826038621570301786524485778922808283651957332444672331 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 21.uart_fifo_full.67371654235519660967151826038621570301786524485778922808283651957332444672331 |
| Directory | /workspace/21.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/21.uart_fifo_overflow.41431888475095779436095835713846693509884078045059316328769096786299960425365 |
| Short name | T1214 |
| Test name | |
| Test status | |
| Simulation time | 58551936110 ps |
| CPU time | 54.86 seconds |
| Started | Nov 22 01:44:41 PM PST 23 |
| Finished | Nov 22 01:45:38 PM PST 23 |
| Peak memory | 199864 kb |
| Host | smart-b63df5b7-cf0e-420b-8474-eedfc2aa7730 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=41431888475095779436095835713846693509884078045059316328769096786299960425365 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 21.uart_fifo_overflow.41431888475095779436095835713846693509884078045059316328769096786299960425365 |
| Directory | /workspace/21.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/21.uart_fifo_reset.50747279479006620790063124835491231496222430469880462448035459077040368309166 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 114 seconds |
| Started | Nov 22 01:44:41 PM PST 23 |
| Finished | Nov 22 01:46:37 PM PST 23 |
| Peak memory | 198888 kb |
| Host | smart-2c6fcf82-55d1-4ee2-aa45-812e53e5fe4e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=50747279479006620790063124835491231496222430469880462448035459077040368309166 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 21.uart_fifo_reset.50747279479006620790063124835491231496222430469880462448035459077040368309166 |
| Directory | /workspace/21.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/21.uart_intr.72385086965821207911425304840004998427007950224835941918565236450953203080536 |
| Short name | T695 |
| Test name | |
| Test status | |
| Simulation time | 787145125175 ps |
| CPU time | 787.23 seconds |
| Started | Nov 22 01:44:46 PM PST 23 |
| Finished | Nov 22 01:57:56 PM PST 23 |
| Peak memory | 200184 kb |
| Host | smart-bd437acf-aa55-4c1d-be54-4fc6f0c06bca |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72385086965821207911425304840004998427007950224835941918565236450953203080536 -assert nopost proc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 21.uart_intr.72385086965821207911425304840004998427007950224835941918565236450953203080536 |
| Directory | /workspace/21.uart_intr/latest |
| Test location | /workspace/coverage/default/21.uart_long_xfer_wo_dly.16618653318902509446568486508291733535536277340469633005325304081513682482140 |
| Short name | T972 |
| Test name | |
| Test status | |
| Simulation time | 93387746707 ps |
| CPU time | 364.08 seconds |
| Started | Nov 22 01:44:42 PM PST 23 |
| Finished | Nov 22 01:50:48 PM PST 23 |
| Peak memory | 200120 kb |
| Host | smart-333d9fc3-74ad-4220-8368-fffc9e6c996c |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=16618653318902509446568486508291733535536277340469633005325304081513682482140 -assert nopostproc +UVM_TES TNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 21.uart_long_xfer_wo_dly.16618653318902509446568486508291733535536277340469633005325304081513682482140 |
| Directory | /workspace/21.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/21.uart_loopback.76166813379489109435815313686569887038502679029837267573247475849715568196944 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 14572448663 ps |
| CPU time | 16.04 seconds |
| Started | Nov 22 01:44:42 PM PST 23 |
| Finished | Nov 22 01:45:00 PM PST 23 |
| Peak memory | 200048 kb |
| Host | smart-b4c7dc6e-60dc-4362-90b1-800b720deb58 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=76166813379489109435815313686569887038502679029837267573247475849715568196944 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 21.uart_loopback.76166813379489109435815313686569887038502679029837267573247475849715568196944 |
| Directory | /workspace/21.uart_loopback/latest |
| Test location | /workspace/coverage/default/21.uart_perf.72968584756707702799594663983711509611712373052938701485447167561254490256245 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 14098773881 ps |
| CPU time | 469.07 seconds |
| Started | Nov 22 01:44:37 PM PST 23 |
| Finished | Nov 22 01:52:29 PM PST 23 |
| Peak memory | 200044 kb |
| Host | smart-7e6e523e-90d8-480d-b2c2-9fe5d4f97c3a |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=72968584756707702799594663983711509611712373052938701485447167561254490256245 -assert nopostproc +UVM_TES TNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 21.uart_perf.72968584756707702799594663983711509611712373052938701485447167561254490256245 |
| Directory | /workspace/21.uart_perf/latest |
| Test location | /workspace/coverage/default/21.uart_rx_oversample.97226941736467514357928839305939605901886537649508134184436547585977716337578 |
| Short name | T935 |
| Test name | |
| Test status | |
| Simulation time | 4370280281 ps |
| CPU time | 20.45 seconds |
| Started | Nov 22 01:44:44 PM PST 23 |
| Finished | Nov 22 01:45:06 PM PST 23 |
| Peak memory | 198944 kb |
| Host | smart-fba3b29f-3f65-4a6b-b790-fd2a057c19b3 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=97226941736467514357928839305939605901886537649508134184436547585977716337578 -assert nopostproc +UVM_TES TNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 21.uart_rx_oversample.97226941736467514357928839305939605901886537649508134184436547585977716337578 |
| Directory | /workspace/21.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/21.uart_rx_parity_err.27812679654644604941254902008326126592374525217636439284705213684065539813847 |
| Short name | T739 |
| Test name | |
| Test status | |
| Simulation time | 36616611594 ps |
| CPU time | 37.97 seconds |
| Started | Nov 22 01:44:40 PM PST 23 |
| Finished | Nov 22 01:45:20 PM PST 23 |
| Peak memory | 200004 kb |
| Host | smart-f60c12ba-951c-4568-a600-d41414e7ebf3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=27812679654644604941254902008326126592374525217636439284705213684065539813847 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 21.uart_rx_parity_err.27812679654644604941254902008326126592374525217636439284705213684065539813847 |
| Directory | /workspace/21.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/21.uart_rx_start_bit_filter.47828168987490549575848497242024801646619441307216348448622240508337699914953 |
| Short name | T860 |
| Test name | |
| Test status | |
| Simulation time | 4267638245 ps |
| CPU time | 4.62 seconds |
| Started | Nov 22 01:44:41 PM PST 23 |
| Finished | Nov 22 01:44:47 PM PST 23 |
| Peak memory | 196016 kb |
| Host | smart-9b312a45-08f0-4af8-afcf-4de1210ef268 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=47828168987490549575848497242024801646619441307216348448622240508337699914953 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 21.uart_rx_start_bit_filter.47828168987490549575848497242024801646619441307216348448622240508337699914953 |
| Directory | /workspace/21.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/21.uart_smoke.44740177615069232882449225180066619495934946262639914676334513664923573542823 |
| Short name | T1070 |
| Test name | |
| Test status | |
| Simulation time | 5759626309 ps |
| CPU time | 18.99 seconds |
| Started | Nov 22 01:44:40 PM PST 23 |
| Finished | Nov 22 01:45:01 PM PST 23 |
| Peak memory | 199664 kb |
| Host | smart-5d0b625d-4a6e-469e-a66e-607a4fd1d260 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=44740177615069232882449225180066619495934946262639914676334513664923573542823 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 21.uart_smoke.44740177615069232882449225180066619495934946262639914676334513664923573542823 |
| Directory | /workspace/21.uart_smoke/latest |
| Test location | /workspace/coverage/default/21.uart_stress_all.83788184287603446265258498865555359091396956029767835908419619638097588531526 |
| Short name | T1048 |
| Test name | |
| Test status | |
| Simulation time | 43402307308 ps |
| CPU time | 57.05 seconds |
| Started | Nov 22 01:44:38 PM PST 23 |
| Finished | Nov 22 01:45:37 PM PST 23 |
| Peak memory | 200100 kb |
| Host | smart-195c3b28-57ee-4fe4-98dd-89e27c88650c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83788184287603446265258498865555359091396956029767835908419619638097588531526 -assert nopos tproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 21.uart_stress_all.83788184287603446265258498865555359091396956029767835908419619638097588531526 |
| Directory | /workspace/21.uart_stress_all/latest |
| Test location | /workspace/coverage/default/21.uart_stress_all_with_rand_reset.7975782744025721849424159649830571520330218554669641562718997738642433160282 |
| Short name | T656 |
| Test name | |
| Test status | |
| Simulation time | 87476847566 ps |
| CPU time | 458.62 seconds |
| Started | Nov 22 01:44:38 PM PST 23 |
| Finished | Nov 22 01:52:19 PM PST 23 |
| Peak memory | 226220 kb |
| Host | smart-79bd3273-e6d8-4541-a1cb-c24dc8d1b34c |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79757827440257218494241596 49830571520330218554669641562718997738642433160282 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_stress_all_with_rand_reset.79757827440257 21849424159649830571520330218554669641562718997738642433160282 |
| Directory | /workspace/21.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/21.uart_tx_ovrd.13429277593845693554089024193828904945588885305040600880230404242687068776317 |
| Short name | T1064 |
| Test name | |
| Test status | |
| Simulation time | 485186362 ps |
| CPU time | 1.26 seconds |
| Started | Nov 22 01:44:40 PM PST 23 |
| Finished | Nov 22 01:44:43 PM PST 23 |
| Peak memory | 197996 kb |
| Host | smart-0d34116f-3c54-4040-98c0-07d77cf42f22 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=13429277593845693554089024193828904945588885305040600880230404242687068776317 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 21.uart_tx_ovrd.13429277593845693554089024193828904945588885305040600880230404242687068776317 |
| Directory | /workspace/21.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/21.uart_tx_rx.28069625380005197116622422339560679825881397191832991131240566079731233499497 |
| Short name | T900 |
| Test name | |
| Test status | |
| Simulation time | 57391945390 ps |
| CPU time | 63.87 seconds |
| Started | Nov 22 01:44:30 PM PST 23 |
| Finished | Nov 22 01:45:41 PM PST 23 |
| Peak memory | 200024 kb |
| Host | smart-fbbfb43c-e5dc-415c-9e57-beff816a4ac1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=28069625380005197116622422339560679825881397191832991131240566079731233499497 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 21.uart_tx_rx.28069625380005197116622422339560679825881397191832991131240566079731233499497 |
| Directory | /workspace/21.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/210.uart_fifo_reset.101470037848404528397907191648678502925576729578222047221931012635355370470296 |
| Short name | T1115 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 113.04 seconds |
| Started | Nov 22 01:46:23 PM PST 23 |
| Finished | Nov 22 01:48:17 PM PST 23 |
| Peak memory | 198692 kb |
| Host | smart-17ce2b8c-47b5-453a-9c1a-601637e496c6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=101470037848404528397907191648678502925576729578222047221931012635355370470296 -assert nopostproc +UVM_TESTNAME=uart_bas e_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.uart_fifo_reset.101470037848404528397907191648678502925576729578222047221931012635355370470296 |
| Directory | /workspace/210.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/211.uart_fifo_reset.46237594738693859506488191476319376294380557166454835173406810800834801896560 |
| Short name | T807 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 112.65 seconds |
| Started | Nov 22 01:46:23 PM PST 23 |
| Finished | Nov 22 01:48:16 PM PST 23 |
| Peak memory | 198740 kb |
| Host | smart-b12cafbe-2b12-4e82-a7db-f8097b0cb637 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=46237594738693859506488191476319376294380557166454835173406810800834801896560 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 211.uart_fifo_reset.46237594738693859506488191476319376294380557166454835173406810800834801896560 |
| Directory | /workspace/211.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/212.uart_fifo_reset.21582302426904405734625982226477654108344381192023895291977261798637948981291 |
| Short name | T826 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 112.81 seconds |
| Started | Nov 22 01:46:23 PM PST 23 |
| Finished | Nov 22 01:48:16 PM PST 23 |
| Peak memory | 198868 kb |
| Host | smart-ab4e1256-627c-4df8-8e2a-1417978f8639 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=21582302426904405734625982226477654108344381192023895291977261798637948981291 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 212.uart_fifo_reset.21582302426904405734625982226477654108344381192023895291977261798637948981291 |
| Directory | /workspace/212.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/213.uart_fifo_reset.63081812350905751115190644267593967201282016941595360796125844717161505146545 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 113.47 seconds |
| Started | Nov 22 01:45:57 PM PST 23 |
| Finished | Nov 22 01:47:59 PM PST 23 |
| Peak memory | 198760 kb |
| Host | smart-cc4fd87c-d425-4b3a-ac37-6aa032eeda86 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=63081812350905751115190644267593967201282016941595360796125844717161505146545 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 213.uart_fifo_reset.63081812350905751115190644267593967201282016941595360796125844717161505146545 |
| Directory | /workspace/213.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/214.uart_fifo_reset.62966850397741860007496150059869837879749063649367161019663962293141418572398 |
| Short name | T1002 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 113.8 seconds |
| Started | Nov 22 01:46:04 PM PST 23 |
| Finished | Nov 22 01:48:05 PM PST 23 |
| Peak memory | 198896 kb |
| Host | smart-f29ad9bd-9f86-415a-b3fb-65c9c3472337 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=62966850397741860007496150059869837879749063649367161019663962293141418572398 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 214.uart_fifo_reset.62966850397741860007496150059869837879749063649367161019663962293141418572398 |
| Directory | /workspace/214.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/215.uart_fifo_reset.68908993569860494695492645201523893278877943870916794095204738057017222223416 |
| Short name | T1183 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 112.65 seconds |
| Started | Nov 22 01:46:12 PM PST 23 |
| Finished | Nov 22 01:48:08 PM PST 23 |
| Peak memory | 198760 kb |
| Host | smart-7793fde8-2ab7-41d1-9bbe-d9d1418398ac |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=68908993569860494695492645201523893278877943870916794095204738057017222223416 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 215.uart_fifo_reset.68908993569860494695492645201523893278877943870916794095204738057017222223416 |
| Directory | /workspace/215.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/216.uart_fifo_reset.101490595431217938477759641357314048319984785942013943244759809717983101049454 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 112.78 seconds |
| Started | Nov 22 01:46:18 PM PST 23 |
| Finished | Nov 22 01:48:12 PM PST 23 |
| Peak memory | 198900 kb |
| Host | smart-1d1ef42e-a015-4e5f-a2f6-0d50d9d53120 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=101490595431217938477759641357314048319984785942013943244759809717983101049454 -assert nopostproc +UVM_TESTNAME=uart_bas e_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.uart_fifo_reset.101490595431217938477759641357314048319984785942013943244759809717983101049454 |
| Directory | /workspace/216.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/217.uart_fifo_reset.64273121739656588067598161266689529338819188353374286373846012569469076520329 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 112.52 seconds |
| Started | Nov 22 01:46:25 PM PST 23 |
| Finished | Nov 22 01:48:18 PM PST 23 |
| Peak memory | 198936 kb |
| Host | smart-0e2425f6-11f0-46d7-98ba-8c4ee380cf1a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=64273121739656588067598161266689529338819188353374286373846012569469076520329 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 217.uart_fifo_reset.64273121739656588067598161266689529338819188353374286373846012569469076520329 |
| Directory | /workspace/217.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/218.uart_fifo_reset.93973318765395249770926179667796687533588851547562107380426689247591516307273 |
| Short name | T987 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 113.54 seconds |
| Started | Nov 22 01:46:04 PM PST 23 |
| Finished | Nov 22 01:48:05 PM PST 23 |
| Peak memory | 198908 kb |
| Host | smart-a0208403-06d6-4ac5-bbfb-3ae0057f0335 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=93973318765395249770926179667796687533588851547562107380426689247591516307273 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 218.uart_fifo_reset.93973318765395249770926179667796687533588851547562107380426689247591516307273 |
| Directory | /workspace/218.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/219.uart_fifo_reset.81556285287767968405344468324797450966022019452546791898600810266936774368401 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 113.99 seconds |
| Started | Nov 22 01:46:19 PM PST 23 |
| Finished | Nov 22 01:48:14 PM PST 23 |
| Peak memory | 198900 kb |
| Host | smart-77765632-fcfa-4e94-9bee-4e4211eddca7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=81556285287767968405344468324797450966022019452546791898600810266936774368401 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 219.uart_fifo_reset.81556285287767968405344468324797450966022019452546791898600810266936774368401 |
| Directory | /workspace/219.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/22.uart_alert_test.105780611925910070511844779828217931026564445539135126066396337093465863999373 |
| Short name | T1266 |
| Test name | |
| Test status | |
| Simulation time | 16368684 ps |
| CPU time | 0.54 seconds |
| Started | Nov 22 01:44:47 PM PST 23 |
| Finished | Nov 22 01:44:51 PM PST 23 |
| Peak memory | 194708 kb |
| Host | smart-7a3bfbd7-59a2-4894-9e58-57aaf8e27b77 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105780611925910070511844779828217931026564445539135126066396337093465863999373 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 22.uart_alert_test.105780611925910070511844779828217931026564445539135126066396337093465863999373 |
| Directory | /workspace/22.uart_alert_test/latest |
| Test location | /workspace/coverage/default/22.uart_fifo_full.102666873763414205515167194750328125558026173018585696803596157008411327417828 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 61777160308 ps |
| CPU time | 61.33 seconds |
| Started | Nov 22 01:44:30 PM PST 23 |
| Finished | Nov 22 01:45:38 PM PST 23 |
| Peak memory | 200016 kb |
| Host | smart-dd71c0e6-207a-4323-8e20-80085028d439 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=102666873763414205515167194750328125558026173018585696803596157008411327417828 -assert nopostproc +UVM_TESTNAME=uart_bas e_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 22.uart_fifo_full.102666873763414205515167194750328125558026173018585696803596157008411327417828 |
| Directory | /workspace/22.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/22.uart_fifo_overflow.20710305261566132428397870659256798632090086527648643694067223133799673809118 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 58551936110 ps |
| CPU time | 54.84 seconds |
| Started | Nov 22 01:44:35 PM PST 23 |
| Finished | Nov 22 01:45:33 PM PST 23 |
| Peak memory | 199864 kb |
| Host | smart-2a92ac75-a9e9-4eed-855f-de2d401890db |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=20710305261566132428397870659256798632090086527648643694067223133799673809118 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 22.uart_fifo_overflow.20710305261566132428397870659256798632090086527648643694067223133799673809118 |
| Directory | /workspace/22.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/22.uart_fifo_reset.43480373582485194504147962317843490193190860948693451634183242322892078015317 |
| Short name | T810 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 113.18 seconds |
| Started | Nov 22 01:45:02 PM PST 23 |
| Finished | Nov 22 01:46:56 PM PST 23 |
| Peak memory | 198932 kb |
| Host | smart-8c7d2452-160c-43d8-93b8-04fc06706277 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=43480373582485194504147962317843490193190860948693451634183242322892078015317 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 22.uart_fifo_reset.43480373582485194504147962317843490193190860948693451634183242322892078015317 |
| Directory | /workspace/22.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/22.uart_intr.29791721142358052464604456513906190545607300523334677945026811673765423388243 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 787145125175 ps |
| CPU time | 790.12 seconds |
| Started | Nov 22 01:44:49 PM PST 23 |
| Finished | Nov 22 01:58:02 PM PST 23 |
| Peak memory | 200120 kb |
| Host | smart-44b089ae-0833-45cc-ab93-c3b8aa60990f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29791721142358052464604456513906190545607300523334677945026811673765423388243 -assert nopost proc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 22.uart_intr.29791721142358052464604456513906190545607300523334677945026811673765423388243 |
| Directory | /workspace/22.uart_intr/latest |
| Test location | /workspace/coverage/default/22.uart_long_xfer_wo_dly.102998650524763940972662158786181886116250021037059420116835212389019669729367 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 93387746707 ps |
| CPU time | 355.37 seconds |
| Started | Nov 22 01:44:42 PM PST 23 |
| Finished | Nov 22 01:50:40 PM PST 23 |
| Peak memory | 200120 kb |
| Host | smart-28c70c2c-40f2-4a12-8ddb-c5da8bd58436 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=102998650524763940972662158786181886116250021037059420116835212389019669729367 -assert nopostproc +UVM_TE STNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 22.uart_long_xfer_wo_dly.102998650524763940972662158786181886116250021037059420116835212389019669729367 |
| Directory | /workspace/22.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/22.uart_loopback.71227170528064814348652893243616002723853158958890127677884178053777749113188 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 14572448663 ps |
| CPU time | 15.95 seconds |
| Started | Nov 22 01:44:42 PM PST 23 |
| Finished | Nov 22 01:45:00 PM PST 23 |
| Peak memory | 200024 kb |
| Host | smart-5acd093a-786f-4040-a8f8-8b23bcf302ae |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=71227170528064814348652893243616002723853158958890127677884178053777749113188 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 22.uart_loopback.71227170528064814348652893243616002723853158958890127677884178053777749113188 |
| Directory | /workspace/22.uart_loopback/latest |
| Test location | /workspace/coverage/default/22.uart_noise_filter.66279185728179514168545139751813188532351131698790789299149166943455708303643 |
| Short name | T946 |
| Test name | |
| Test status | |
| Simulation time | 94501577082 ps |
| CPU time | 98.96 seconds |
| Started | Nov 22 01:44:46 PM PST 23 |
| Finished | Nov 22 01:46:27 PM PST 23 |
| Peak memory | 200268 kb |
| Host | smart-e6bf3e0c-b2c6-4e69-9a2f-30aa9b147f18 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=66279185728179514168545139751813188532351131698790789299149166943455708303643 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_noise_filter.66279185728179514168545139751813188532351131698790789299149166943455708303643 |
| Directory | /workspace/22.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/22.uart_perf.61865497399325983466050775845796549408622388999904480455337153442847827735343 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 14098773881 ps |
| CPU time | 464.53 seconds |
| Started | Nov 22 01:44:45 PM PST 23 |
| Finished | Nov 22 01:52:31 PM PST 23 |
| Peak memory | 200164 kb |
| Host | smart-81161456-73ed-4441-8800-e5a66b76d24a |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=61865497399325983466050775845796549408622388999904480455337153442847827735343 -assert nopostproc +UVM_TES TNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 22.uart_perf.61865497399325983466050775845796549408622388999904480455337153442847827735343 |
| Directory | /workspace/22.uart_perf/latest |
| Test location | /workspace/coverage/default/22.uart_rx_oversample.100423783664519250921905470529100051719734705057851683049639481184835473889889 |
| Short name | T1030 |
| Test name | |
| Test status | |
| Simulation time | 4370280281 ps |
| CPU time | 19.79 seconds |
| Started | Nov 22 01:44:37 PM PST 23 |
| Finished | Nov 22 01:44:58 PM PST 23 |
| Peak memory | 198964 kb |
| Host | smart-b3d5a4d3-edee-432e-93af-8fc51982f7e1 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=100423783664519250921905470529100051719734705057851683049639481184835473889889 -assert nopostproc +UVM_TE STNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_oversample.100423783664519250921905470529100051719734705057851683049639481184835473889889 |
| Directory | /workspace/22.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/22.uart_rx_parity_err.102140898504120141283042811771802965758945289967870002085918430071209559222606 |
| Short name | T1228 |
| Test name | |
| Test status | |
| Simulation time | 36616611594 ps |
| CPU time | 37.95 seconds |
| Started | Nov 22 01:44:37 PM PST 23 |
| Finished | Nov 22 01:45:17 PM PST 23 |
| Peak memory | 200120 kb |
| Host | smart-eb3b9ea2-116e-4924-b5f3-2838c34a54a0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=102140898504120141283042811771802965758945289967870002085918430071209559222606 -assert nopostproc +UVM_TESTNAME=uart_bas e_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 22.uart_rx_parity_err.102140898504120141283042811771802965758945289967870002085918430071209559222606 |
| Directory | /workspace/22.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/22.uart_rx_start_bit_filter.61331626051337902147190640019255705591425692707068499952184968189538260730843 |
| Short name | T1159 |
| Test name | |
| Test status | |
| Simulation time | 4267638245 ps |
| CPU time | 4.66 seconds |
| Started | Nov 22 01:44:41 PM PST 23 |
| Finished | Nov 22 01:44:47 PM PST 23 |
| Peak memory | 195968 kb |
| Host | smart-d1c6cc7a-10e3-4cf1-9676-157dded1ea33 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=61331626051337902147190640019255705591425692707068499952184968189538260730843 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 22.uart_rx_start_bit_filter.61331626051337902147190640019255705591425692707068499952184968189538260730843 |
| Directory | /workspace/22.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/22.uart_smoke.38519778192699090097547500482132095818659844208721663090755118950242205289391 |
| Short name | T733 |
| Test name | |
| Test status | |
| Simulation time | 5759626309 ps |
| CPU time | 18.58 seconds |
| Started | Nov 22 01:44:47 PM PST 23 |
| Finished | Nov 22 01:45:08 PM PST 23 |
| Peak memory | 199572 kb |
| Host | smart-1b21f63f-7ca5-42a7-9dd0-be3646df22af |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=38519778192699090097547500482132095818659844208721663090755118950242205289391 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 22.uart_smoke.38519778192699090097547500482132095818659844208721663090755118950242205289391 |
| Directory | /workspace/22.uart_smoke/latest |
| Test location | /workspace/coverage/default/22.uart_stress_all.4674020077740744201165946425048006505360047841255443536022130834770408262867 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 43402307308 ps |
| CPU time | 57.79 seconds |
| Started | Nov 22 01:44:47 PM PST 23 |
| Finished | Nov 22 01:45:47 PM PST 23 |
| Peak memory | 200032 kb |
| Host | smart-1056765e-8a8e-4e6d-bc50-3aae2cb68915 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4674020077740744201165946425048006505360047841255443536022130834770408262867 -assert nopost proc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 22.uart_stress_all.4674020077740744201165946425048006505360047841255443536022130834770408262867 |
| Directory | /workspace/22.uart_stress_all/latest |
| Test location | /workspace/coverage/default/22.uart_tx_ovrd.67096761612927408511684631727768428805856244928051969393006777080271668683985 |
| Short name | T837 |
| Test name | |
| Test status | |
| Simulation time | 485186362 ps |
| CPU time | 1.26 seconds |
| Started | Nov 22 01:44:39 PM PST 23 |
| Finished | Nov 22 01:44:43 PM PST 23 |
| Peak memory | 197940 kb |
| Host | smart-0dbdbb0e-6954-4415-9000-33feac2475d7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=67096761612927408511684631727768428805856244928051969393006777080271668683985 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 22.uart_tx_ovrd.67096761612927408511684631727768428805856244928051969393006777080271668683985 |
| Directory | /workspace/22.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/22.uart_tx_rx.109394646826031162849187881068085124109695003590879981615403336946362011704996 |
| Short name | T1223 |
| Test name | |
| Test status | |
| Simulation time | 57391945390 ps |
| CPU time | 63.23 seconds |
| Started | Nov 22 01:44:45 PM PST 23 |
| Finished | Nov 22 01:45:50 PM PST 23 |
| Peak memory | 200056 kb |
| Host | smart-1f5f490d-2f5e-4e50-8320-573fe98046f6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=109394646826031162849187881068085124109695003590879981615403336946362011704996 -assert nopostproc +UVM_TESTNAME=uart_bas e_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 22.uart_tx_rx.109394646826031162849187881068085124109695003590879981615403336946362011704996 |
| Directory | /workspace/22.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/220.uart_fifo_reset.16968657605574290879162765388386411624463802534529985338426093758754224934673 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 115.1 seconds |
| Started | Nov 22 01:46:16 PM PST 23 |
| Finished | Nov 22 01:48:13 PM PST 23 |
| Peak memory | 198912 kb |
| Host | smart-9843af9c-1fcb-4cfc-9114-92a13ead1a3b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=16968657605574290879162765388386411624463802534529985338426093758754224934673 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 220.uart_fifo_reset.16968657605574290879162765388386411624463802534529985338426093758754224934673 |
| Directory | /workspace/220.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/221.uart_fifo_reset.6229090824622317451820715497536813916022277233725332874361312256084295612836 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 112.68 seconds |
| Started | Nov 22 01:46:13 PM PST 23 |
| Finished | Nov 22 01:48:09 PM PST 23 |
| Peak memory | 198884 kb |
| Host | smart-4d7081c2-28ca-4b31-aa69-8f840a174cd6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=6229090824622317451820715497536813916022277233725332874361312256084295612836 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 221.uart_fifo_reset.6229090824622317451820715497536813916022277233725332874361312256084295612836 |
| Directory | /workspace/221.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/222.uart_fifo_reset.67815040430499023442556965976918962839924531198079364303296084867615487781994 |
| Short name | T822 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 113.75 seconds |
| Started | Nov 22 01:46:09 PM PST 23 |
| Finished | Nov 22 01:48:08 PM PST 23 |
| Peak memory | 198964 kb |
| Host | smart-729fac07-d371-4d8f-8879-c14dbb7df428 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=67815040430499023442556965976918962839924531198079364303296084867615487781994 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 222.uart_fifo_reset.67815040430499023442556965976918962839924531198079364303296084867615487781994 |
| Directory | /workspace/222.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/223.uart_fifo_reset.22343507009919458205859516700742739454896687625194981768560980917487580409521 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 113.23 seconds |
| Started | Nov 22 01:46:23 PM PST 23 |
| Finished | Nov 22 01:48:17 PM PST 23 |
| Peak memory | 198852 kb |
| Host | smart-8ef0c263-aeee-43b6-9a67-d8816d22e4d2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=22343507009919458205859516700742739454896687625194981768560980917487580409521 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 223.uart_fifo_reset.22343507009919458205859516700742739454896687625194981768560980917487580409521 |
| Directory | /workspace/223.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/224.uart_fifo_reset.37889126736570049984640345690603372827985586605496448517365550335359061695687 |
| Short name | T1024 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 113.28 seconds |
| Started | Nov 22 01:46:06 PM PST 23 |
| Finished | Nov 22 01:48:06 PM PST 23 |
| Peak memory | 198864 kb |
| Host | smart-8973574c-db04-4ffb-819b-c13ae3c9cbde |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=37889126736570049984640345690603372827985586605496448517365550335359061695687 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 224.uart_fifo_reset.37889126736570049984640345690603372827985586605496448517365550335359061695687 |
| Directory | /workspace/224.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/225.uart_fifo_reset.51741388106182250753229058495847398212028161822479183483111576941661630677606 |
| Short name | T699 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 112.44 seconds |
| Started | Nov 22 01:46:23 PM PST 23 |
| Finished | Nov 22 01:48:16 PM PST 23 |
| Peak memory | 198936 kb |
| Host | smart-98f62ea9-cf81-46bf-91e6-7d9c8ed2a867 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=51741388106182250753229058495847398212028161822479183483111576941661630677606 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 225.uart_fifo_reset.51741388106182250753229058495847398212028161822479183483111576941661630677606 |
| Directory | /workspace/225.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/226.uart_fifo_reset.83383546062003414252892256958737055435497100480481484254239148619047399574898 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 113.31 seconds |
| Started | Nov 22 01:46:12 PM PST 23 |
| Finished | Nov 22 01:48:09 PM PST 23 |
| Peak memory | 198924 kb |
| Host | smart-1647ed3a-8022-461c-b739-f2cd6f3aabad |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=83383546062003414252892256958737055435497100480481484254239148619047399574898 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 226.uart_fifo_reset.83383546062003414252892256958737055435497100480481484254239148619047399574898 |
| Directory | /workspace/226.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/227.uart_fifo_reset.39645105670570406255563535251885129215721105697311756606923195615601071445126 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 113.58 seconds |
| Started | Nov 22 01:46:24 PM PST 23 |
| Finished | Nov 22 01:48:18 PM PST 23 |
| Peak memory | 198864 kb |
| Host | smart-05e984a0-962b-4463-9128-6b4a5041b6da |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=39645105670570406255563535251885129215721105697311756606923195615601071445126 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 227.uart_fifo_reset.39645105670570406255563535251885129215721105697311756606923195615601071445126 |
| Directory | /workspace/227.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/228.uart_fifo_reset.85370820263421358338984775676134791755747628971536290588955712324388232764621 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 113.34 seconds |
| Started | Nov 22 01:46:24 PM PST 23 |
| Finished | Nov 22 01:48:19 PM PST 23 |
| Peak memory | 198884 kb |
| Host | smart-a2285ef4-0b22-4cd3-9bf4-aa323181aa99 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=85370820263421358338984775676134791755747628971536290588955712324388232764621 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 228.uart_fifo_reset.85370820263421358338984775676134791755747628971536290588955712324388232764621 |
| Directory | /workspace/228.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/229.uart_fifo_reset.51693225738708986689285419849481465559558744928938409322848806088795653757518 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 112.96 seconds |
| Started | Nov 22 01:46:07 PM PST 23 |
| Finished | Nov 22 01:48:06 PM PST 23 |
| Peak memory | 198860 kb |
| Host | smart-4b27a62b-33a2-4323-9a02-4f0b9e91d97b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=51693225738708986689285419849481465559558744928938409322848806088795653757518 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 229.uart_fifo_reset.51693225738708986689285419849481465559558744928938409322848806088795653757518 |
| Directory | /workspace/229.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/23.uart_alert_test.1159491624502766226729534451445682451066547736313824617859595286360666429593 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 16368684 ps |
| CPU time | 0.54 seconds |
| Started | Nov 22 01:44:42 PM PST 23 |
| Finished | Nov 22 01:44:44 PM PST 23 |
| Peak memory | 194648 kb |
| Host | smart-68f430c7-15c8-4c2c-bebc-e5d243ba070e |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159491624502766226729534451445682451066547736313824617859595286360666429593 -assert nopostpro c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 23.uart_alert_test.1159491624502766226729534451445682451066547736313824617859595286360666429593 |
| Directory | /workspace/23.uart_alert_test/latest |
| Test location | /workspace/coverage/default/23.uart_fifo_full.57176606209860839012937208643683737388841221927409524697225960226820125397376 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 61777160308 ps |
| CPU time | 61.1 seconds |
| Started | Nov 22 01:44:50 PM PST 23 |
| Finished | Nov 22 01:45:53 PM PST 23 |
| Peak memory | 200100 kb |
| Host | smart-5917bead-4bb5-4280-8984-8868f5c5f4a0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=57176606209860839012937208643683737388841221927409524697225960226820125397376 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 23.uart_fifo_full.57176606209860839012937208643683737388841221927409524697225960226820125397376 |
| Directory | /workspace/23.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/23.uart_fifo_overflow.7303731090082263734883603264881397038481958382639977489424413804286275030505 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 58551936110 ps |
| CPU time | 55.06 seconds |
| Started | Nov 22 01:44:37 PM PST 23 |
| Finished | Nov 22 01:45:34 PM PST 23 |
| Peak memory | 199744 kb |
| Host | smart-29955089-c370-42f6-a58b-98e7af1b6bda |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=7303731090082263734883603264881397038481958382639977489424413804286275030505 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_overflow.7303731090082263734883603264881397038481958382639977489424413804286275030505 |
| Directory | /workspace/23.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/23.uart_fifo_reset.18945642458028936543094345346908707500734830415830172378705024996944921617429 |
| Short name | T950 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 113.83 seconds |
| Started | Nov 22 01:44:43 PM PST 23 |
| Finished | Nov 22 01:46:38 PM PST 23 |
| Peak memory | 198892 kb |
| Host | smart-2b3d49d1-935e-44a5-8847-8d9d5a21f029 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=18945642458028936543094345346908707500734830415830172378705024996944921617429 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 23.uart_fifo_reset.18945642458028936543094345346908707500734830415830172378705024996944921617429 |
| Directory | /workspace/23.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/23.uart_intr.111689958531887855171694085175392046816384971498918350975082394681693363938037 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 787145125175 ps |
| CPU time | 788.83 seconds |
| Started | Nov 22 01:44:41 PM PST 23 |
| Finished | Nov 22 01:57:52 PM PST 23 |
| Peak memory | 200048 kb |
| Host | smart-fd58a3d3-896e-4d6f-b960-0471f8dc9cd5 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111689958531887855171694085175392046816384971498918350975082394681693363938037 -assert nopos tproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 23.uart_intr.111689958531887855171694085175392046816384971498918350975082394681693363938037 |
| Directory | /workspace/23.uart_intr/latest |
| Test location | /workspace/coverage/default/23.uart_long_xfer_wo_dly.19743735769345609189126651989297392937311542021545684378621935158742327045316 |
| Short name | T1087 |
| Test name | |
| Test status | |
| Simulation time | 93387746707 ps |
| CPU time | 351.02 seconds |
| Started | Nov 22 01:44:45 PM PST 23 |
| Finished | Nov 22 01:50:38 PM PST 23 |
| Peak memory | 200088 kb |
| Host | smart-d705edc4-8c08-48b3-b111-f181e23aa0b1 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=19743735769345609189126651989297392937311542021545684378621935158742327045316 -assert nopostproc +UVM_TES TNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 23.uart_long_xfer_wo_dly.19743735769345609189126651989297392937311542021545684378621935158742327045316 |
| Directory | /workspace/23.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/23.uart_loopback.57272180165706565056849089402477019903685674275713927750968700979178354879667 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 14572448663 ps |
| CPU time | 16.04 seconds |
| Started | Nov 22 01:44:44 PM PST 23 |
| Finished | Nov 22 01:45:02 PM PST 23 |
| Peak memory | 200060 kb |
| Host | smart-f4da96f5-04c5-4bb0-9d03-a5c5431dc353 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=57272180165706565056849089402477019903685674275713927750968700979178354879667 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 23.uart_loopback.57272180165706565056849089402477019903685674275713927750968700979178354879667 |
| Directory | /workspace/23.uart_loopback/latest |
| Test location | /workspace/coverage/default/23.uart_noise_filter.69225653505543093659991099384507433838125363061154630905515551940036695115422 |
| Short name | T801 |
| Test name | |
| Test status | |
| Simulation time | 94501577082 ps |
| CPU time | 97.54 seconds |
| Started | Nov 22 01:44:45 PM PST 23 |
| Finished | Nov 22 01:46:25 PM PST 23 |
| Peak memory | 200204 kb |
| Host | smart-4b1e6e44-9c5a-45a8-8662-4ae9df032062 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=69225653505543093659991099384507433838125363061154630905515551940036695115422 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_noise_filter.69225653505543093659991099384507433838125363061154630905515551940036695115422 |
| Directory | /workspace/23.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/23.uart_perf.95994812232949527642293757909603683268786637054393053641608721882023165656545 |
| Short name | T745 |
| Test name | |
| Test status | |
| Simulation time | 14098773881 ps |
| CPU time | 480.86 seconds |
| Started | Nov 22 01:44:42 PM PST 23 |
| Finished | Nov 22 01:52:45 PM PST 23 |
| Peak memory | 200152 kb |
| Host | smart-c2a44a5d-83ad-490c-8627-3f954c7a2943 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=95994812232949527642293757909603683268786637054393053641608721882023165656545 -assert nopostproc +UVM_TES TNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 23.uart_perf.95994812232949527642293757909603683268786637054393053641608721882023165656545 |
| Directory | /workspace/23.uart_perf/latest |
| Test location | /workspace/coverage/default/23.uart_rx_oversample.32828951553233596439018090569351973738235588663326982498223598042757447144300 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 4370280281 ps |
| CPU time | 20.24 seconds |
| Started | Nov 22 01:44:51 PM PST 23 |
| Finished | Nov 22 01:45:13 PM PST 23 |
| Peak memory | 198916 kb |
| Host | smart-85d632c1-03bb-435e-9a75-fda510b2e407 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=32828951553233596439018090569351973738235588663326982498223598042757447144300 -assert nopostproc +UVM_TES TNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 23.uart_rx_oversample.32828951553233596439018090569351973738235588663326982498223598042757447144300 |
| Directory | /workspace/23.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/23.uart_rx_parity_err.49666732517295284687788742521430187408349668844832807719602085130468588578123 |
| Short name | T1080 |
| Test name | |
| Test status | |
| Simulation time | 36616611594 ps |
| CPU time | 37.98 seconds |
| Started | Nov 22 01:44:41 PM PST 23 |
| Finished | Nov 22 01:45:21 PM PST 23 |
| Peak memory | 200080 kb |
| Host | smart-af813135-4e28-42a9-a1c0-e920afc67586 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=49666732517295284687788742521430187408349668844832807719602085130468588578123 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 23.uart_rx_parity_err.49666732517295284687788742521430187408349668844832807719602085130468588578123 |
| Directory | /workspace/23.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/23.uart_rx_start_bit_filter.40612732088304150806989750276084081765038015872020588408807131683117766934912 |
| Short name | T1140 |
| Test name | |
| Test status | |
| Simulation time | 4267638245 ps |
| CPU time | 4.79 seconds |
| Started | Nov 22 01:44:40 PM PST 23 |
| Finished | Nov 22 01:44:47 PM PST 23 |
| Peak memory | 196016 kb |
| Host | smart-709ea22a-5c95-497e-9c0f-407a247c507a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=40612732088304150806989750276084081765038015872020588408807131683117766934912 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 23.uart_rx_start_bit_filter.40612732088304150806989750276084081765038015872020588408807131683117766934912 |
| Directory | /workspace/23.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/23.uart_smoke.29630069928966351466420812332628731261835953188680018794535930364818024003310 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 5759626309 ps |
| CPU time | 18.47 seconds |
| Started | Nov 22 01:44:45 PM PST 23 |
| Finished | Nov 22 01:45:05 PM PST 23 |
| Peak memory | 199640 kb |
| Host | smart-f167e739-d9d5-4efc-80fa-62fd7028d600 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=29630069928966351466420812332628731261835953188680018794535930364818024003310 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 23.uart_smoke.29630069928966351466420812332628731261835953188680018794535930364818024003310 |
| Directory | /workspace/23.uart_smoke/latest |
| Test location | /workspace/coverage/default/23.uart_stress_all.11228820091324485356433152955469321386195142498148838898624448876553031541533 |
| Short name | T1053 |
| Test name | |
| Test status | |
| Simulation time | 43402307308 ps |
| CPU time | 57.44 seconds |
| Started | Nov 22 01:44:41 PM PST 23 |
| Finished | Nov 22 01:45:41 PM PST 23 |
| Peak memory | 200076 kb |
| Host | smart-411e6787-dfd5-4ae9-8b4e-f361871a8747 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11228820091324485356433152955469321386195142498148838898624448876553031541533 -assert nopos tproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 23.uart_stress_all.11228820091324485356433152955469321386195142498148838898624448876553031541533 |
| Directory | /workspace/23.uart_stress_all/latest |
| Test location | /workspace/coverage/default/23.uart_stress_all_with_rand_reset.18729276716676251957838605617331560336905508977601354364354704815643001245442 |
| Short name | T977 |
| Test name | |
| Test status | |
| Simulation time | 87476847566 ps |
| CPU time | 463.42 seconds |
| Started | Nov 22 01:44:42 PM PST 23 |
| Finished | Nov 22 01:52:28 PM PST 23 |
| Peak memory | 226228 kb |
| Host | smart-12296c95-bbe4-4613-9b74-6e357948ca0f |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18729276716676251957838605 617331560336905508977601354364354704815643001245442 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_stress_all_with_rand_reset.1872927671667 6251957838605617331560336905508977601354364354704815643001245442 |
| Directory | /workspace/23.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/23.uart_tx_ovrd.17495171449405129540388602915707164573683670545309864132062451995523609992494 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 485186362 ps |
| CPU time | 1.24 seconds |
| Started | Nov 22 01:44:41 PM PST 23 |
| Finished | Nov 22 01:44:44 PM PST 23 |
| Peak memory | 197912 kb |
| Host | smart-69d59074-a7da-4c0c-a292-5b12f9a8302e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=17495171449405129540388602915707164573683670545309864132062451995523609992494 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 23.uart_tx_ovrd.17495171449405129540388602915707164573683670545309864132062451995523609992494 |
| Directory | /workspace/23.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/23.uart_tx_rx.37130431575707390653072081221808507929788756862183214320161503340337182192210 |
| Short name | T674 |
| Test name | |
| Test status | |
| Simulation time | 57391945390 ps |
| CPU time | 63.28 seconds |
| Started | Nov 22 01:44:45 PM PST 23 |
| Finished | Nov 22 01:45:50 PM PST 23 |
| Peak memory | 200072 kb |
| Host | smart-90a713fe-a68d-4e50-90aa-91f61ddcdb35 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=37130431575707390653072081221808507929788756862183214320161503340337182192210 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 23.uart_tx_rx.37130431575707390653072081221808507929788756862183214320161503340337182192210 |
| Directory | /workspace/23.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/230.uart_fifo_reset.71468374619203536753796411663525971666708166445569628591706462613496095669567 |
| Short name | T958 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 112.88 seconds |
| Started | Nov 22 01:46:11 PM PST 23 |
| Finished | Nov 22 01:48:08 PM PST 23 |
| Peak memory | 198924 kb |
| Host | smart-17c5e3d9-751b-4b8e-9d25-8b87cbca5519 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=71468374619203536753796411663525971666708166445569628591706462613496095669567 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 230.uart_fifo_reset.71468374619203536753796411663525971666708166445569628591706462613496095669567 |
| Directory | /workspace/230.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/231.uart_fifo_reset.80643020352735221528562735152693974098195232972993024777354419377492897933373 |
| Short name | T698 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 113.46 seconds |
| Started | Nov 22 01:46:20 PM PST 23 |
| Finished | Nov 22 01:48:14 PM PST 23 |
| Peak memory | 198908 kb |
| Host | smart-fe223d24-2317-4d10-a870-3d2a9e10cc63 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=80643020352735221528562735152693974098195232972993024777354419377492897933373 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 231.uart_fifo_reset.80643020352735221528562735152693974098195232972993024777354419377492897933373 |
| Directory | /workspace/231.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/232.uart_fifo_reset.102457715591829652279157247278431038316617493013910271036643656627402989576665 |
| Short name | T1007 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 113.48 seconds |
| Started | Nov 22 01:46:08 PM PST 23 |
| Finished | Nov 22 01:48:07 PM PST 23 |
| Peak memory | 198836 kb |
| Host | smart-206ae16a-57c9-4ac2-961a-0aa03042e577 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=102457715591829652279157247278431038316617493013910271036643656627402989576665 -assert nopostproc +UVM_TESTNAME=uart_bas e_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.uart_fifo_reset.102457715591829652279157247278431038316617493013910271036643656627402989576665 |
| Directory | /workspace/232.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/233.uart_fifo_reset.19791649491811268407065657272824150383548304952358163012386280838569230978398 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 112.37 seconds |
| Started | Nov 22 01:46:12 PM PST 23 |
| Finished | Nov 22 01:48:08 PM PST 23 |
| Peak memory | 198884 kb |
| Host | smart-3b69497e-0fcf-4e04-8d48-1c9ef6d443d5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=19791649491811268407065657272824150383548304952358163012386280838569230978398 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 233.uart_fifo_reset.19791649491811268407065657272824150383548304952358163012386280838569230978398 |
| Directory | /workspace/233.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/234.uart_fifo_reset.8069154421455907009119601055636883885527219905931494222926949361038780616968 |
| Short name | T1198 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 112.31 seconds |
| Started | Nov 22 01:46:14 PM PST 23 |
| Finished | Nov 22 01:48:09 PM PST 23 |
| Peak memory | 198760 kb |
| Host | smart-2ee4eb06-a996-442c-9cb3-97c0f33b8cd6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=8069154421455907009119601055636883885527219905931494222926949361038780616968 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 234.uart_fifo_reset.8069154421455907009119601055636883885527219905931494222926949361038780616968 |
| Directory | /workspace/234.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/235.uart_fifo_reset.98986264132962075598991475095438845929906224902828454267373706316773851286775 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 112.87 seconds |
| Started | Nov 22 01:46:05 PM PST 23 |
| Finished | Nov 22 01:48:05 PM PST 23 |
| Peak memory | 198908 kb |
| Host | smart-ce951336-783e-4981-9d7d-78fc4b9acc77 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=98986264132962075598991475095438845929906224902828454267373706316773851286775 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 235.uart_fifo_reset.98986264132962075598991475095438845929906224902828454267373706316773851286775 |
| Directory | /workspace/235.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/236.uart_fifo_reset.66564530654231508707209667490949763491306293280480066550879673362156175960844 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 112.98 seconds |
| Started | Nov 22 01:46:20 PM PST 23 |
| Finished | Nov 22 01:48:14 PM PST 23 |
| Peak memory | 198816 kb |
| Host | smart-71f24d8c-b5e1-4061-9f72-89e9fadd0596 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=66564530654231508707209667490949763491306293280480066550879673362156175960844 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 236.uart_fifo_reset.66564530654231508707209667490949763491306293280480066550879673362156175960844 |
| Directory | /workspace/236.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/237.uart_fifo_reset.81127513742608607372025376847366329876857866821445422076936378328191129981042 |
| Short name | T754 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 112.96 seconds |
| Started | Nov 22 01:46:16 PM PST 23 |
| Finished | Nov 22 01:48:11 PM PST 23 |
| Peak memory | 198828 kb |
| Host | smart-e3c5ff11-f114-465b-929e-b4e3d5c037b0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=81127513742608607372025376847366329876857866821445422076936378328191129981042 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 237.uart_fifo_reset.81127513742608607372025376847366329876857866821445422076936378328191129981042 |
| Directory | /workspace/237.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/238.uart_fifo_reset.65219023662322196808399891314765501887790292445843454109040490887939033545209 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 113.1 seconds |
| Started | Nov 22 01:46:23 PM PST 23 |
| Finished | Nov 22 01:48:16 PM PST 23 |
| Peak memory | 198936 kb |
| Host | smart-b66d6a20-8e7d-442f-9585-629558c3fbf1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=65219023662322196808399891314765501887790292445843454109040490887939033545209 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 238.uart_fifo_reset.65219023662322196808399891314765501887790292445843454109040490887939033545209 |
| Directory | /workspace/238.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/239.uart_fifo_reset.18127366243189818025788286781101068737886871896076500126184635122618163140528 |
| Short name | T1015 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 112.42 seconds |
| Started | Nov 22 01:46:25 PM PST 23 |
| Finished | Nov 22 01:48:19 PM PST 23 |
| Peak memory | 198936 kb |
| Host | smart-b6c1bdd2-2662-4212-82a9-7a953cd6b822 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=18127366243189818025788286781101068737886871896076500126184635122618163140528 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 239.uart_fifo_reset.18127366243189818025788286781101068737886871896076500126184635122618163140528 |
| Directory | /workspace/239.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/24.uart_alert_test.85063485708074226427886999848553616555927171723479407729470051876606634756389 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 16368684 ps |
| CPU time | 0.51 seconds |
| Started | Nov 22 01:44:47 PM PST 23 |
| Finished | Nov 22 01:44:50 PM PST 23 |
| Peak memory | 194504 kb |
| Host | smart-5ff39cf2-1a41-46be-910d-e5217cc01a8d |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85063485708074226427886999848553616555927171723479407729470051876606634756389 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 24.uart_alert_test.85063485708074226427886999848553616555927171723479407729470051876606634756389 |
| Directory | /workspace/24.uart_alert_test/latest |
| Test location | /workspace/coverage/default/24.uart_fifo_full.43049345942120015440143479012393792248101839464689312678728226268520029681292 |
| Short name | T1139 |
| Test name | |
| Test status | |
| Simulation time | 61777160308 ps |
| CPU time | 61.26 seconds |
| Started | Nov 22 01:44:51 PM PST 23 |
| Finished | Nov 22 01:45:54 PM PST 23 |
| Peak memory | 200128 kb |
| Host | smart-d418bf10-a9f9-4b3e-b17b-f9bd9c461235 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=43049345942120015440143479012393792248101839464689312678728226268520029681292 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 24.uart_fifo_full.43049345942120015440143479012393792248101839464689312678728226268520029681292 |
| Directory | /workspace/24.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/24.uart_fifo_overflow.42452618510712997681460522119745500650878392253301781322926829090323935244837 |
| Short name | T844 |
| Test name | |
| Test status | |
| Simulation time | 58551936110 ps |
| CPU time | 54.5 seconds |
| Started | Nov 22 01:44:42 PM PST 23 |
| Finished | Nov 22 01:45:38 PM PST 23 |
| Peak memory | 199760 kb |
| Host | smart-3f7697e2-9739-4560-b0b9-7811dcf5a765 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=42452618510712997681460522119745500650878392253301781322926829090323935244837 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 24.uart_fifo_overflow.42452618510712997681460522119745500650878392253301781322926829090323935244837 |
| Directory | /workspace/24.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/24.uart_fifo_reset.33570726521151932210225995796770808604743707114616709882912962310257070562906 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 113.18 seconds |
| Started | Nov 22 01:44:47 PM PST 23 |
| Finished | Nov 22 01:46:43 PM PST 23 |
| Peak memory | 198860 kb |
| Host | smart-7059b7bf-055f-4571-9fd0-2b3d52fb4358 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=33570726521151932210225995796770808604743707114616709882912962310257070562906 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 24.uart_fifo_reset.33570726521151932210225995796770808604743707114616709882912962310257070562906 |
| Directory | /workspace/24.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/24.uart_intr.27557521107883570944779120346247696256930393049263064315342424050439524968851 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 787145125175 ps |
| CPU time | 783.97 seconds |
| Started | Nov 22 01:44:50 PM PST 23 |
| Finished | Nov 22 01:57:56 PM PST 23 |
| Peak memory | 200044 kb |
| Host | smart-b0217310-20e2-44ae-92df-a92a9dcfe281 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27557521107883570944779120346247696256930393049263064315342424050439524968851 -assert nopost proc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 24.uart_intr.27557521107883570944779120346247696256930393049263064315342424050439524968851 |
| Directory | /workspace/24.uart_intr/latest |
| Test location | /workspace/coverage/default/24.uart_long_xfer_wo_dly.78452166326046643020548103604433189414946025065596698294645204825016395936115 |
| Short name | T952 |
| Test name | |
| Test status | |
| Simulation time | 93387746707 ps |
| CPU time | 349.84 seconds |
| Started | Nov 22 01:44:43 PM PST 23 |
| Finished | Nov 22 01:50:34 PM PST 23 |
| Peak memory | 200136 kb |
| Host | smart-f7ed88d4-1b4d-48c3-ac44-3a35a12981c9 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=78452166326046643020548103604433189414946025065596698294645204825016395936115 -assert nopostproc +UVM_TES TNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 24.uart_long_xfer_wo_dly.78452166326046643020548103604433189414946025065596698294645204825016395936115 |
| Directory | /workspace/24.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/24.uart_loopback.43728549063246298582757849403680594296755808618058043872012979155578466656093 |
| Short name | T1249 |
| Test name | |
| Test status | |
| Simulation time | 14572448663 ps |
| CPU time | 16.6 seconds |
| Started | Nov 22 01:44:44 PM PST 23 |
| Finished | Nov 22 01:45:03 PM PST 23 |
| Peak memory | 200016 kb |
| Host | smart-36d1c04e-88f9-4d5a-a4b8-40ea4a221c5c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=43728549063246298582757849403680594296755808618058043872012979155578466656093 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 24.uart_loopback.43728549063246298582757849403680594296755808618058043872012979155578466656093 |
| Directory | /workspace/24.uart_loopback/latest |
| Test location | /workspace/coverage/default/24.uart_noise_filter.34232540987331324364624800757889026289753835437436299579008923238530458079040 |
| Short name | T988 |
| Test name | |
| Test status | |
| Simulation time | 94501577082 ps |
| CPU time | 97.63 seconds |
| Started | Nov 22 01:44:40 PM PST 23 |
| Finished | Nov 22 01:46:20 PM PST 23 |
| Peak memory | 200228 kb |
| Host | smart-bf31e2a4-df6c-4777-973f-a9603e9bc443 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=34232540987331324364624800757889026289753835437436299579008923238530458079040 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_noise_filter.34232540987331324364624800757889026289753835437436299579008923238530458079040 |
| Directory | /workspace/24.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/24.uart_perf.37677581239394470461118167608452986349314403490428397043535013438680032353338 |
| Short name | T964 |
| Test name | |
| Test status | |
| Simulation time | 14098773881 ps |
| CPU time | 461.14 seconds |
| Started | Nov 22 01:44:44 PM PST 23 |
| Finished | Nov 22 01:52:27 PM PST 23 |
| Peak memory | 200164 kb |
| Host | smart-1d857886-f9ec-4ee4-a3bd-310c2d5bbe19 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=37677581239394470461118167608452986349314403490428397043535013438680032353338 -assert nopostproc +UVM_TES TNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 24.uart_perf.37677581239394470461118167608452986349314403490428397043535013438680032353338 |
| Directory | /workspace/24.uart_perf/latest |
| Test location | /workspace/coverage/default/24.uart_rx_oversample.91498311428607106353235683058937999381416408501431712457744591739773767305066 |
| Short name | T1132 |
| Test name | |
| Test status | |
| Simulation time | 4370280281 ps |
| CPU time | 20.1 seconds |
| Started | Nov 22 01:44:50 PM PST 23 |
| Finished | Nov 22 01:45:12 PM PST 23 |
| Peak memory | 198900 kb |
| Host | smart-53e0d0bb-2796-497b-babe-7e7702513dcb |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=91498311428607106353235683058937999381416408501431712457744591739773767305066 -assert nopostproc +UVM_TES TNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 24.uart_rx_oversample.91498311428607106353235683058937999381416408501431712457744591739773767305066 |
| Directory | /workspace/24.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/24.uart_rx_parity_err.54597552468546702795256640599622918931392171384491929924421762014372737168252 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 36616611594 ps |
| CPU time | 37.88 seconds |
| Started | Nov 22 01:44:41 PM PST 23 |
| Finished | Nov 22 01:45:21 PM PST 23 |
| Peak memory | 200108 kb |
| Host | smart-ff0f7e37-200b-4280-b18a-2b44a5aeb512 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=54597552468546702795256640599622918931392171384491929924421762014372737168252 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 24.uart_rx_parity_err.54597552468546702795256640599622918931392171384491929924421762014372737168252 |
| Directory | /workspace/24.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/24.uart_rx_start_bit_filter.22700439533218683074719074860546577517280505437763258534903581157427812738645 |
| Short name | T805 |
| Test name | |
| Test status | |
| Simulation time | 4267638245 ps |
| CPU time | 4.69 seconds |
| Started | Nov 22 01:44:49 PM PST 23 |
| Finished | Nov 22 01:44:56 PM PST 23 |
| Peak memory | 195936 kb |
| Host | smart-4cebbb0e-5dfc-49be-b131-a423356759f1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=22700439533218683074719074860546577517280505437763258534903581157427812738645 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 24.uart_rx_start_bit_filter.22700439533218683074719074860546577517280505437763258534903581157427812738645 |
| Directory | /workspace/24.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/24.uart_smoke.88745976377113624828814460284216554994166302105761758647083698787881682249187 |
| Short name | T821 |
| Test name | |
| Test status | |
| Simulation time | 5759626309 ps |
| CPU time | 18.63 seconds |
| Started | Nov 22 01:44:45 PM PST 23 |
| Finished | Nov 22 01:45:06 PM PST 23 |
| Peak memory | 199616 kb |
| Host | smart-238461cf-0329-4249-bd6b-5e86362cd7d5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=88745976377113624828814460284216554994166302105761758647083698787881682249187 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 24.uart_smoke.88745976377113624828814460284216554994166302105761758647083698787881682249187 |
| Directory | /workspace/24.uart_smoke/latest |
| Test location | /workspace/coverage/default/24.uart_stress_all.92318852273959289959015187320049118945634291612905957231644764669633196360423 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 43402307308 ps |
| CPU time | 56.3 seconds |
| Started | Nov 22 01:44:47 PM PST 23 |
| Finished | Nov 22 01:45:46 PM PST 23 |
| Peak memory | 200064 kb |
| Host | smart-8ba0522e-1ed1-47e2-8e66-28d1531eeac2 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92318852273959289959015187320049118945634291612905957231644764669633196360423 -assert nopos tproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 24.uart_stress_all.92318852273959289959015187320049118945634291612905957231644764669633196360423 |
| Directory | /workspace/24.uart_stress_all/latest |
| Test location | /workspace/coverage/default/24.uart_stress_all_with_rand_reset.108279247164752728696140567837522152693986878293277332963929610607560208347334 |
| Short name | T861 |
| Test name | |
| Test status | |
| Simulation time | 87476847566 ps |
| CPU time | 460.6 seconds |
| Started | Nov 22 01:44:53 PM PST 23 |
| Finished | Nov 22 01:52:36 PM PST 23 |
| Peak memory | 226192 kb |
| Host | smart-7530a8e6-5497-4345-9fd3-601aca57c6e6 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10827924716475272869614056 7837522152693986878293277332963929610607560208347334 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_stress_all_with_rand_reset.108279247164 752728696140567837522152693986878293277332963929610607560208347334 |
| Directory | /workspace/24.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/24.uart_tx_ovrd.52512867939923401297107106197149940303753107157248780669933368061346497619438 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 485186362 ps |
| CPU time | 1.26 seconds |
| Started | Nov 22 01:44:44 PM PST 23 |
| Finished | Nov 22 01:44:46 PM PST 23 |
| Peak memory | 197864 kb |
| Host | smart-42d259de-a10b-435b-8632-6fc67305df45 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=52512867939923401297107106197149940303753107157248780669933368061346497619438 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 24.uart_tx_ovrd.52512867939923401297107106197149940303753107157248780669933368061346497619438 |
| Directory | /workspace/24.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/24.uart_tx_rx.39086601715191554592271461607232975463203951917760474714818531930239581596301 |
| Short name | T845 |
| Test name | |
| Test status | |
| Simulation time | 57391945390 ps |
| CPU time | 63.96 seconds |
| Started | Nov 22 01:44:40 PM PST 23 |
| Finished | Nov 22 01:45:46 PM PST 23 |
| Peak memory | 200052 kb |
| Host | smart-8ec29dcd-5493-419c-bafb-3659fde3002e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=39086601715191554592271461607232975463203951917760474714818531930239581596301 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 24.uart_tx_rx.39086601715191554592271461607232975463203951917760474714818531930239581596301 |
| Directory | /workspace/24.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/240.uart_fifo_reset.112929395632256743623546156031100819646885494175965972762118074512693792515210 |
| Short name | T756 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 113.6 seconds |
| Started | Nov 22 01:46:29 PM PST 23 |
| Finished | Nov 22 01:48:23 PM PST 23 |
| Peak memory | 198964 kb |
| Host | smart-3cf7d41f-1527-4758-8fb3-32c1f50d58df |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=112929395632256743623546156031100819646885494175965972762118074512693792515210 -assert nopostproc +UVM_TESTNAME=uart_bas e_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.uart_fifo_reset.112929395632256743623546156031100819646885494175965972762118074512693792515210 |
| Directory | /workspace/240.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/241.uart_fifo_reset.108273943155665872864817247091904290032635239938851427311515824989367405578333 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 113.69 seconds |
| Started | Nov 22 01:46:22 PM PST 23 |
| Finished | Nov 22 01:48:16 PM PST 23 |
| Peak memory | 198868 kb |
| Host | smart-6b894568-729b-435e-b94d-f6c994dfdbb9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=108273943155665872864817247091904290032635239938851427311515824989367405578333 -assert nopostproc +UVM_TESTNAME=uart_bas e_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.uart_fifo_reset.108273943155665872864817247091904290032635239938851427311515824989367405578333 |
| Directory | /workspace/241.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/242.uart_fifo_reset.76290646151846607515646230301938985182706472831799242521954324021012077063255 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 113.5 seconds |
| Started | Nov 22 01:46:38 PM PST 23 |
| Finished | Nov 22 01:48:33 PM PST 23 |
| Peak memory | 198924 kb |
| Host | smart-cf1b1138-c93b-438b-a451-97a7bb8423af |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=76290646151846607515646230301938985182706472831799242521954324021012077063255 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 242.uart_fifo_reset.76290646151846607515646230301938985182706472831799242521954324021012077063255 |
| Directory | /workspace/242.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/243.uart_fifo_reset.18310189408446227799229483684511689952597803513611575063442296480983197491411 |
| Short name | T1095 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 113.92 seconds |
| Started | Nov 22 01:46:23 PM PST 23 |
| Finished | Nov 22 01:48:18 PM PST 23 |
| Peak memory | 198908 kb |
| Host | smart-d0c0d4e3-e29c-4f97-af4e-72ef27cca3b8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=18310189408446227799229483684511689952597803513611575063442296480983197491411 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 243.uart_fifo_reset.18310189408446227799229483684511689952597803513611575063442296480983197491411 |
| Directory | /workspace/243.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/244.uart_fifo_reset.34606664894317974415705223417324885538063701833368946757741381017206648852876 |
| Short name | T683 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 112.42 seconds |
| Started | Nov 22 01:46:13 PM PST 23 |
| Finished | Nov 22 01:48:08 PM PST 23 |
| Peak memory | 198912 kb |
| Host | smart-d3cb6fca-0f66-40fa-875b-5f8586158d3c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=34606664894317974415705223417324885538063701833368946757741381017206648852876 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 244.uart_fifo_reset.34606664894317974415705223417324885538063701833368946757741381017206648852876 |
| Directory | /workspace/244.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/245.uart_fifo_reset.15927094800584957267573336820924426623459154697902539152515363416105793874884 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 113.86 seconds |
| Started | Nov 22 01:46:25 PM PST 23 |
| Finished | Nov 22 01:48:21 PM PST 23 |
| Peak memory | 198888 kb |
| Host | smart-abf47b44-5f61-4a8c-8e05-2c82a0200600 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=15927094800584957267573336820924426623459154697902539152515363416105793874884 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 245.uart_fifo_reset.15927094800584957267573336820924426623459154697902539152515363416105793874884 |
| Directory | /workspace/245.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/246.uart_fifo_reset.49442256693768109387001286895974962819373662309383532421976900323914301890738 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 114.87 seconds |
| Started | Nov 22 01:46:27 PM PST 23 |
| Finished | Nov 22 01:48:23 PM PST 23 |
| Peak memory | 198908 kb |
| Host | smart-505dba5e-0b6f-409a-95b1-62eb4d929aa5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=49442256693768109387001286895974962819373662309383532421976900323914301890738 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 246.uart_fifo_reset.49442256693768109387001286895974962819373662309383532421976900323914301890738 |
| Directory | /workspace/246.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/247.uart_fifo_reset.86884580496949070140134373607814634666473623778572826652467089715062959598984 |
| Short name | T753 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 113.71 seconds |
| Started | Nov 22 01:46:25 PM PST 23 |
| Finished | Nov 22 01:48:20 PM PST 23 |
| Peak memory | 198888 kb |
| Host | smart-c73324b9-720d-4178-995a-e0177176ef0b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=86884580496949070140134373607814634666473623778572826652467089715062959598984 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 247.uart_fifo_reset.86884580496949070140134373607814634666473623778572826652467089715062959598984 |
| Directory | /workspace/247.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/248.uart_fifo_reset.14347035046033183502175712557214847964211864032549821943323969984881550197816 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 112.7 seconds |
| Started | Nov 22 01:46:10 PM PST 23 |
| Finished | Nov 22 01:48:08 PM PST 23 |
| Peak memory | 198884 kb |
| Host | smart-c09bda8d-6521-4ec9-8852-8d02c18a5103 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=14347035046033183502175712557214847964211864032549821943323969984881550197816 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 248.uart_fifo_reset.14347035046033183502175712557214847964211864032549821943323969984881550197816 |
| Directory | /workspace/248.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/249.uart_fifo_reset.51002613880288764653426244485501675842906310210628821334315297319496018451752 |
| Short name | T692 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 115.09 seconds |
| Started | Nov 22 01:46:17 PM PST 23 |
| Finished | Nov 22 01:48:13 PM PST 23 |
| Peak memory | 198940 kb |
| Host | smart-bfe730e5-e519-4369-ac4a-1d34b096e7a9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=51002613880288764653426244485501675842906310210628821334315297319496018451752 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 249.uart_fifo_reset.51002613880288764653426244485501675842906310210628821334315297319496018451752 |
| Directory | /workspace/249.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/25.uart_alert_test.67388595934122399316157095178416858796566328656571713134641758962319250753959 |
| Short name | T718 |
| Test name | |
| Test status | |
| Simulation time | 16368684 ps |
| CPU time | 0.53 seconds |
| Started | Nov 22 01:44:39 PM PST 23 |
| Finished | Nov 22 01:44:42 PM PST 23 |
| Peak memory | 194584 kb |
| Host | smart-b30f39d7-9129-49ab-8fda-5e7adf44021b |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67388595934122399316157095178416858796566328656571713134641758962319250753959 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 25.uart_alert_test.67388595934122399316157095178416858796566328656571713134641758962319250753959 |
| Directory | /workspace/25.uart_alert_test/latest |
| Test location | /workspace/coverage/default/25.uart_fifo_full.108883377841562933719157014916161551229878631938148566575723100293988733119889 |
| Short name | T1242 |
| Test name | |
| Test status | |
| Simulation time | 61777160308 ps |
| CPU time | 61.04 seconds |
| Started | Nov 22 01:44:40 PM PST 23 |
| Finished | Nov 22 01:45:43 PM PST 23 |
| Peak memory | 200164 kb |
| Host | smart-61c7c268-3dc7-43d8-b65a-4267c1cc7473 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=108883377841562933719157014916161551229878631938148566575723100293988733119889 -assert nopostproc +UVM_TESTNAME=uart_bas e_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 25.uart_fifo_full.108883377841562933719157014916161551229878631938148566575723100293988733119889 |
| Directory | /workspace/25.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/25.uart_fifo_overflow.87299578845250864569043254320202047934091539249492107137727841899604946440949 |
| Short name | T685 |
| Test name | |
| Test status | |
| Simulation time | 58551936110 ps |
| CPU time | 54.73 seconds |
| Started | Nov 22 01:44:49 PM PST 23 |
| Finished | Nov 22 01:45:46 PM PST 23 |
| Peak memory | 199904 kb |
| Host | smart-557116c1-d23d-49f7-bdac-f513ee17dc08 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=87299578845250864569043254320202047934091539249492107137727841899604946440949 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 25.uart_fifo_overflow.87299578845250864569043254320202047934091539249492107137727841899604946440949 |
| Directory | /workspace/25.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/25.uart_fifo_reset.52837483833701038731077842981281071103098005642392327327454858552554764974994 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 113.41 seconds |
| Started | Nov 22 01:44:48 PM PST 23 |
| Finished | Nov 22 01:46:45 PM PST 23 |
| Peak memory | 198900 kb |
| Host | smart-bac6ea7f-fabe-48a4-a767-5ff1e594bd2d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=52837483833701038731077842981281071103098005642392327327454858552554764974994 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 25.uart_fifo_reset.52837483833701038731077842981281071103098005642392327327454858552554764974994 |
| Directory | /workspace/25.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/25.uart_intr.74713753963602442284186405961772921256530195056920307814721225778400083163931 |
| Short name | T782 |
| Test name | |
| Test status | |
| Simulation time | 787145125175 ps |
| CPU time | 783.74 seconds |
| Started | Nov 22 01:44:39 PM PST 23 |
| Finished | Nov 22 01:57:45 PM PST 23 |
| Peak memory | 200100 kb |
| Host | smart-aab447bd-2354-41af-a44d-5bd9b2a4f1f6 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74713753963602442284186405961772921256530195056920307814721225778400083163931 -assert nopost proc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 25.uart_intr.74713753963602442284186405961772921256530195056920307814721225778400083163931 |
| Directory | /workspace/25.uart_intr/latest |
| Test location | /workspace/coverage/default/25.uart_long_xfer_wo_dly.65604440310466837548799471639665485769613862347543326018915219858977747253227 |
| Short name | T1258 |
| Test name | |
| Test status | |
| Simulation time | 93387746707 ps |
| CPU time | 355.56 seconds |
| Started | Nov 22 01:44:41 PM PST 23 |
| Finished | Nov 22 01:50:38 PM PST 23 |
| Peak memory | 200140 kb |
| Host | smart-205c12cc-facd-47a8-a039-8106234d496d |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=65604440310466837548799471639665485769613862347543326018915219858977747253227 -assert nopostproc +UVM_TES TNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 25.uart_long_xfer_wo_dly.65604440310466837548799471639665485769613862347543326018915219858977747253227 |
| Directory | /workspace/25.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/25.uart_loopback.9117893846578164555393654257451009057713808869953581864780696558632757033691 |
| Short name | T1259 |
| Test name | |
| Test status | |
| Simulation time | 14572448663 ps |
| CPU time | 16.07 seconds |
| Started | Nov 22 01:44:41 PM PST 23 |
| Finished | Nov 22 01:44:58 PM PST 23 |
| Peak memory | 200028 kb |
| Host | smart-94a501fe-b476-440a-9028-01e10dc299f1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=9117893846578164555393654257451009057713808869953581864780696558632757033691 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 25.uart_loopback.9117893846578164555393654257451009057713808869953581864780696558632757033691 |
| Directory | /workspace/25.uart_loopback/latest |
| Test location | /workspace/coverage/default/25.uart_noise_filter.39213928341109165889394420544916851663012129653843503525554700546580332411616 |
| Short name | T932 |
| Test name | |
| Test status | |
| Simulation time | 94501577082 ps |
| CPU time | 97.35 seconds |
| Started | Nov 22 01:44:47 PM PST 23 |
| Finished | Nov 22 01:46:27 PM PST 23 |
| Peak memory | 200276 kb |
| Host | smart-80bba15e-7059-40be-a196-4243c589cc33 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=39213928341109165889394420544916851663012129653843503525554700546580332411616 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_noise_filter.39213928341109165889394420544916851663012129653843503525554700546580332411616 |
| Directory | /workspace/25.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/25.uart_perf.63206638586249734677619591559178105177862772928379714857061110723072051234190 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 14098773881 ps |
| CPU time | 468.63 seconds |
| Started | Nov 22 01:44:41 PM PST 23 |
| Finished | Nov 22 01:52:31 PM PST 23 |
| Peak memory | 200124 kb |
| Host | smart-d97c3f1b-aaa8-4c3a-a87e-db1daf99e94c |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=63206638586249734677619591559178105177862772928379714857061110723072051234190 -assert nopostproc +UVM_TES TNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 25.uart_perf.63206638586249734677619591559178105177862772928379714857061110723072051234190 |
| Directory | /workspace/25.uart_perf/latest |
| Test location | /workspace/coverage/default/25.uart_rx_oversample.41337961478897577467943481509897744691872712225649035751048811525853179479637 |
| Short name | T1071 |
| Test name | |
| Test status | |
| Simulation time | 4370280281 ps |
| CPU time | 19.95 seconds |
| Started | Nov 22 01:44:43 PM PST 23 |
| Finished | Nov 22 01:45:05 PM PST 23 |
| Peak memory | 198960 kb |
| Host | smart-1c802e50-d404-4827-90cd-7d4a80a14372 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=41337961478897577467943481509897744691872712225649035751048811525853179479637 -assert nopostproc +UVM_TES TNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 25.uart_rx_oversample.41337961478897577467943481509897744691872712225649035751048811525853179479637 |
| Directory | /workspace/25.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/25.uart_rx_parity_err.100194605880079118615528396017403199571302052819761640338498141565635343005579 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 36616611594 ps |
| CPU time | 37.97 seconds |
| Started | Nov 22 01:44:56 PM PST 23 |
| Finished | Nov 22 01:45:35 PM PST 23 |
| Peak memory | 200204 kb |
| Host | smart-7d4dc47d-6327-43ad-8592-fe94e1fad3a5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=100194605880079118615528396017403199571302052819761640338498141565635343005579 -assert nopostproc +UVM_TESTNAME=uart_bas e_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 25.uart_rx_parity_err.100194605880079118615528396017403199571302052819761640338498141565635343005579 |
| Directory | /workspace/25.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/25.uart_rx_start_bit_filter.48898334100697352751854865815817425092981080001989170644029101589014654569230 |
| Short name | T1074 |
| Test name | |
| Test status | |
| Simulation time | 4267638245 ps |
| CPU time | 4.72 seconds |
| Started | Nov 22 01:44:41 PM PST 23 |
| Finished | Nov 22 01:44:47 PM PST 23 |
| Peak memory | 195916 kb |
| Host | smart-486012d3-cf68-400f-a6fb-c8678c9da0ae |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=48898334100697352751854865815817425092981080001989170644029101589014654569230 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 25.uart_rx_start_bit_filter.48898334100697352751854865815817425092981080001989170644029101589014654569230 |
| Directory | /workspace/25.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/25.uart_smoke.70225542881844074903417333619238636257196239331404978685315998570926753941560 |
| Short name | T871 |
| Test name | |
| Test status | |
| Simulation time | 5759626309 ps |
| CPU time | 17.86 seconds |
| Started | Nov 22 01:44:48 PM PST 23 |
| Finished | Nov 22 01:45:09 PM PST 23 |
| Peak memory | 199492 kb |
| Host | smart-8302ab40-3748-45f7-90e1-b9df8a541abc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=70225542881844074903417333619238636257196239331404978685315998570926753941560 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 25.uart_smoke.70225542881844074903417333619238636257196239331404978685315998570926753941560 |
| Directory | /workspace/25.uart_smoke/latest |
| Test location | /workspace/coverage/default/25.uart_stress_all.89939331362064422485217924696207577212834617193488611890582528266885472625431 |
| Short name | T813 |
| Test name | |
| Test status | |
| Simulation time | 43402307308 ps |
| CPU time | 57.17 seconds |
| Started | Nov 22 01:44:51 PM PST 23 |
| Finished | Nov 22 01:45:50 PM PST 23 |
| Peak memory | 200112 kb |
| Host | smart-0f54fbc1-5b8c-47a9-8b36-8844e10de190 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89939331362064422485217924696207577212834617193488611890582528266885472625431 -assert nopos tproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 25.uart_stress_all.89939331362064422485217924696207577212834617193488611890582528266885472625431 |
| Directory | /workspace/25.uart_stress_all/latest |
| Test location | /workspace/coverage/default/25.uart_stress_all_with_rand_reset.54483490531327071766668162319812599659146977717592293627352955077259047812905 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 87476847566 ps |
| CPU time | 458.22 seconds |
| Started | Nov 22 01:44:47 PM PST 23 |
| Finished | Nov 22 01:52:28 PM PST 23 |
| Peak memory | 226192 kb |
| Host | smart-b19f0e80-bbe2-4eba-9410-3d7375b2a506 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54483490531327071766668162 319812599659146977717592293627352955077259047812905 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_stress_all_with_rand_reset.5448349053132 7071766668162319812599659146977717592293627352955077259047812905 |
| Directory | /workspace/25.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/25.uart_tx_ovrd.5934843881660980855243716220434870520840895882216795633933490489087200424431 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 485186362 ps |
| CPU time | 1.28 seconds |
| Started | Nov 22 01:44:51 PM PST 23 |
| Finished | Nov 22 01:44:54 PM PST 23 |
| Peak memory | 197968 kb |
| Host | smart-133b2a6a-3274-46e2-8b68-9286a7c5c6be |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=5934843881660980855243716220434870520840895882216795633933490489087200424431 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 25.uart_tx_ovrd.5934843881660980855243716220434870520840895882216795633933490489087200424431 |
| Directory | /workspace/25.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/25.uart_tx_rx.22228972097723088529781057546276286618063429191585183793018634429937017026178 |
| Short name | T874 |
| Test name | |
| Test status | |
| Simulation time | 57391945390 ps |
| CPU time | 63.1 seconds |
| Started | Nov 22 01:44:46 PM PST 23 |
| Finished | Nov 22 01:45:52 PM PST 23 |
| Peak memory | 200088 kb |
| Host | smart-83f1b98e-8580-4048-ba06-56642983dd03 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=22228972097723088529781057546276286618063429191585183793018634429937017026178 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 25.uart_tx_rx.22228972097723088529781057546276286618063429191585183793018634429937017026178 |
| Directory | /workspace/25.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/250.uart_fifo_reset.67136795183244251209212779745484861850089852045542051309614782108470503422969 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 114.58 seconds |
| Started | Nov 22 01:46:33 PM PST 23 |
| Finished | Nov 22 01:48:28 PM PST 23 |
| Peak memory | 198912 kb |
| Host | smart-20359de7-be55-4d04-a236-e76d49e898ed |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=67136795183244251209212779745484861850089852045542051309614782108470503422969 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 250.uart_fifo_reset.67136795183244251209212779745484861850089852045542051309614782108470503422969 |
| Directory | /workspace/250.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/251.uart_fifo_reset.80488974712312442593872432763391444304192151210049044943884211072087986552250 |
| Short name | T689 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 114.21 seconds |
| Started | Nov 22 01:46:55 PM PST 23 |
| Finished | Nov 22 01:48:50 PM PST 23 |
| Peak memory | 198916 kb |
| Host | smart-d8e90d56-3c69-4250-9fb5-3c2e1d0d35f9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=80488974712312442593872432763391444304192151210049044943884211072087986552250 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 251.uart_fifo_reset.80488974712312442593872432763391444304192151210049044943884211072087986552250 |
| Directory | /workspace/251.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/252.uart_fifo_reset.60911135671537215994381612668524120111919119985360188157582644091398743514433 |
| Short name | T1184 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 112.78 seconds |
| Started | Nov 22 01:46:34 PM PST 23 |
| Finished | Nov 22 01:48:28 PM PST 23 |
| Peak memory | 198872 kb |
| Host | smart-6d595c9d-e29f-4ed1-b5c0-ce485a9cbd03 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=60911135671537215994381612668524120111919119985360188157582644091398743514433 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 252.uart_fifo_reset.60911135671537215994381612668524120111919119985360188157582644091398743514433 |
| Directory | /workspace/252.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/253.uart_fifo_reset.78447136119618496243879318325380272726985123634112877314293721257241409464907 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 112.53 seconds |
| Started | Nov 22 01:46:32 PM PST 23 |
| Finished | Nov 22 01:48:25 PM PST 23 |
| Peak memory | 198884 kb |
| Host | smart-9a11dc19-a99a-4dd2-9927-dbd55ba8d874 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=78447136119618496243879318325380272726985123634112877314293721257241409464907 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 253.uart_fifo_reset.78447136119618496243879318325380272726985123634112877314293721257241409464907 |
| Directory | /workspace/253.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/254.uart_fifo_reset.17976041882465813673965345732322880508358234431025222929465368520598094645831 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 112.49 seconds |
| Started | Nov 22 01:46:36 PM PST 23 |
| Finished | Nov 22 01:48:30 PM PST 23 |
| Peak memory | 198908 kb |
| Host | smart-a4b0c03b-5e94-4495-80c7-db7e7d973003 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=17976041882465813673965345732322880508358234431025222929465368520598094645831 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 254.uart_fifo_reset.17976041882465813673965345732322880508358234431025222929465368520598094645831 |
| Directory | /workspace/254.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/255.uart_fifo_reset.111628021622337481501727066476749923726793792371120778988374455001852622773675 |
| Short name | T814 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 113.47 seconds |
| Started | Nov 22 01:46:32 PM PST 23 |
| Finished | Nov 22 01:48:27 PM PST 23 |
| Peak memory | 198932 kb |
| Host | smart-4a34a273-1dac-4565-b814-84543def34ff |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=111628021622337481501727066476749923726793792371120778988374455001852622773675 -assert nopostproc +UVM_TESTNAME=uart_bas e_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.uart_fifo_reset.111628021622337481501727066476749923726793792371120778988374455001852622773675 |
| Directory | /workspace/255.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/256.uart_fifo_reset.30438519196395307495069704665207037279461328027910360408922860501062441992472 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 112.28 seconds |
| Started | Nov 22 01:46:37 PM PST 23 |
| Finished | Nov 22 01:48:30 PM PST 23 |
| Peak memory | 198908 kb |
| Host | smart-fe35678b-65c8-49b7-88be-f54dbf900cbe |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=30438519196395307495069704665207037279461328027910360408922860501062441992472 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 256.uart_fifo_reset.30438519196395307495069704665207037279461328027910360408922860501062441992472 |
| Directory | /workspace/256.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/257.uart_fifo_reset.63158896831401176441115766706786306569830875224888553154583584636349419577135 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 114.17 seconds |
| Started | Nov 22 01:45:58 PM PST 23 |
| Finished | Nov 22 01:48:01 PM PST 23 |
| Peak memory | 198808 kb |
| Host | smart-158edeee-6cfd-458a-a816-03c766aed318 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=63158896831401176441115766706786306569830875224888553154583584636349419577135 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 257.uart_fifo_reset.63158896831401176441115766706786306569830875224888553154583584636349419577135 |
| Directory | /workspace/257.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/258.uart_fifo_reset.48202687706913582934096640640835381911922540198958192642244992450553474566573 |
| Short name | T687 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 113.19 seconds |
| Started | Nov 22 01:46:19 PM PST 23 |
| Finished | Nov 22 01:48:14 PM PST 23 |
| Peak memory | 198896 kb |
| Host | smart-cbd561af-d6db-4c44-8e77-5f90832107c8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=48202687706913582934096640640835381911922540198958192642244992450553474566573 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 258.uart_fifo_reset.48202687706913582934096640640835381911922540198958192642244992450553474566573 |
| Directory | /workspace/258.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/259.uart_fifo_reset.45030354951651902595553215880122761918032961459305954477755923533046943999769 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 113.36 seconds |
| Started | Nov 22 01:46:02 PM PST 23 |
| Finished | Nov 22 01:48:01 PM PST 23 |
| Peak memory | 198884 kb |
| Host | smart-aef81ea9-1ced-4fe5-aefa-0d95b299fba0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=45030354951651902595553215880122761918032961459305954477755923533046943999769 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 259.uart_fifo_reset.45030354951651902595553215880122761918032961459305954477755923533046943999769 |
| Directory | /workspace/259.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/26.uart_alert_test.22849757072326680653094707264604126930237450135209613733192326754531464563794 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 16368684 ps |
| CPU time | 0.53 seconds |
| Started | Nov 22 01:44:52 PM PST 23 |
| Finished | Nov 22 01:44:54 PM PST 23 |
| Peak memory | 194568 kb |
| Host | smart-98e60882-4ec1-47a0-97e4-523d272cd6c3 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22849757072326680653094707264604126930237450135209613733192326754531464563794 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 26.uart_alert_test.22849757072326680653094707264604126930237450135209613733192326754531464563794 |
| Directory | /workspace/26.uart_alert_test/latest |
| Test location | /workspace/coverage/default/26.uart_fifo_full.44031642725020462519639452985207242132418688734863688022043481637683302395789 |
| Short name | T870 |
| Test name | |
| Test status | |
| Simulation time | 61777160308 ps |
| CPU time | 60.3 seconds |
| Started | Nov 22 01:44:47 PM PST 23 |
| Finished | Nov 22 01:45:50 PM PST 23 |
| Peak memory | 200092 kb |
| Host | smart-8752d4dd-164d-4b55-9eb5-330228e455f3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=44031642725020462519639452985207242132418688734863688022043481637683302395789 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 26.uart_fifo_full.44031642725020462519639452985207242132418688734863688022043481637683302395789 |
| Directory | /workspace/26.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/26.uart_fifo_overflow.28917479812225459061174253647504199957457835367008090710783534902168054862463 |
| Short name | T664 |
| Test name | |
| Test status | |
| Simulation time | 58551936110 ps |
| CPU time | 55.03 seconds |
| Started | Nov 22 01:44:51 PM PST 23 |
| Finished | Nov 22 01:45:48 PM PST 23 |
| Peak memory | 199888 kb |
| Host | smart-a2450ad2-dd93-44f3-af04-fbd7d9579b0a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=28917479812225459061174253647504199957457835367008090710783534902168054862463 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 26.uart_fifo_overflow.28917479812225459061174253647504199957457835367008090710783534902168054862463 |
| Directory | /workspace/26.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/26.uart_fifo_reset.1986639862648926331306252837202163714149569890810119068322068673924850268232 |
| Short name | T710 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 113.53 seconds |
| Started | Nov 22 01:44:44 PM PST 23 |
| Finished | Nov 22 01:46:39 PM PST 23 |
| Peak memory | 198868 kb |
| Host | smart-55b461f7-de9f-4453-bb64-ed34b71d5c40 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1986639862648926331306252837202163714149569890810119068322068673924850268232 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 26.uart_fifo_reset.1986639862648926331306252837202163714149569890810119068322068673924850268232 |
| Directory | /workspace/26.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/26.uart_intr.109627496968211421007172826672791627118749868767002794900885687335681356846075 |
| Short name | T1060 |
| Test name | |
| Test status | |
| Simulation time | 787145125175 ps |
| CPU time | 781.8 seconds |
| Started | Nov 22 01:44:52 PM PST 23 |
| Finished | Nov 22 01:57:55 PM PST 23 |
| Peak memory | 200116 kb |
| Host | smart-4cca52cd-36ef-44aa-9064-79f2639a1475 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109627496968211421007172826672791627118749868767002794900885687335681356846075 -assert nopos tproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 26.uart_intr.109627496968211421007172826672791627118749868767002794900885687335681356846075 |
| Directory | /workspace/26.uart_intr/latest |
| Test location | /workspace/coverage/default/26.uart_long_xfer_wo_dly.53068894819717218661095896234937108835377908315553461852208395168017219967917 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 93387746707 ps |
| CPU time | 347.59 seconds |
| Started | Nov 22 01:44:52 PM PST 23 |
| Finished | Nov 22 01:50:42 PM PST 23 |
| Peak memory | 200132 kb |
| Host | smart-a79cb590-2faf-4db9-97af-4ef278b1d6fb |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=53068894819717218661095896234937108835377908315553461852208395168017219967917 -assert nopostproc +UVM_TES TNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 26.uart_long_xfer_wo_dly.53068894819717218661095896234937108835377908315553461852208395168017219967917 |
| Directory | /workspace/26.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/26.uart_loopback.99705761938881539074079118209427397405305152838005253880594211713357913350231 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 14572448663 ps |
| CPU time | 16.27 seconds |
| Started | Nov 22 01:44:49 PM PST 23 |
| Finished | Nov 22 01:45:08 PM PST 23 |
| Peak memory | 200004 kb |
| Host | smart-96695227-8afb-4045-9638-9ca86007e2b4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=99705761938881539074079118209427397405305152838005253880594211713357913350231 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 26.uart_loopback.99705761938881539074079118209427397405305152838005253880594211713357913350231 |
| Directory | /workspace/26.uart_loopback/latest |
| Test location | /workspace/coverage/default/26.uart_noise_filter.114417747173136585555614570386964520472869257358571092973954029394227454610303 |
| Short name | T1193 |
| Test name | |
| Test status | |
| Simulation time | 94501577082 ps |
| CPU time | 97.22 seconds |
| Started | Nov 22 01:44:49 PM PST 23 |
| Finished | Nov 22 01:46:29 PM PST 23 |
| Peak memory | 200264 kb |
| Host | smart-1d6c00cc-9f0d-4677-88ab-8f7410629269 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=114417747173136585555614570386964520472869257358571092973954029394227454610303 -assert nopostproc +UVM_TESTNAME=uart_bas e_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 26.uart_noise_filter.114417747173136585555614570386964520472869257358571092973954029394227454610303 |
| Directory | /workspace/26.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/26.uart_perf.50987948658885446495053990019014289415218143905059150530317103271479859055913 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 14098773881 ps |
| CPU time | 474.26 seconds |
| Started | Nov 22 01:44:45 PM PST 23 |
| Finished | Nov 22 01:52:41 PM PST 23 |
| Peak memory | 200156 kb |
| Host | smart-3cddbf9f-6812-4a24-ba43-ff5b9c934d30 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=50987948658885446495053990019014289415218143905059150530317103271479859055913 -assert nopostproc +UVM_TES TNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 26.uart_perf.50987948658885446495053990019014289415218143905059150530317103271479859055913 |
| Directory | /workspace/26.uart_perf/latest |
| Test location | /workspace/coverage/default/26.uart_rx_oversample.7582969385775628047654645075701139020076824117269080767184544781471754288918 |
| Short name | T1136 |
| Test name | |
| Test status | |
| Simulation time | 4370280281 ps |
| CPU time | 20.09 seconds |
| Started | Nov 22 01:44:47 PM PST 23 |
| Finished | Nov 22 01:45:10 PM PST 23 |
| Peak memory | 198956 kb |
| Host | smart-8c0fc53d-517b-453b-8e33-40179bb31563 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=7582969385775628047654645075701139020076824117269080767184544781471754288918 -assert nopostproc +UVM_TEST NAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 26.uart_rx_oversample.7582969385775628047654645075701139020076824117269080767184544781471754288918 |
| Directory | /workspace/26.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/26.uart_rx_parity_err.87710436989593302806529102473334038187959573913154740503987105359895220228851 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 36616611594 ps |
| CPU time | 38.26 seconds |
| Started | Nov 22 01:44:50 PM PST 23 |
| Finished | Nov 22 01:45:31 PM PST 23 |
| Peak memory | 200084 kb |
| Host | smart-c23871e2-39b9-4eee-b3a6-bc4e930d3296 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=87710436989593302806529102473334038187959573913154740503987105359895220228851 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 26.uart_rx_parity_err.87710436989593302806529102473334038187959573913154740503987105359895220228851 |
| Directory | /workspace/26.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/26.uart_rx_start_bit_filter.1204354119966316504837485637422075419142350372979571006728797208736440171942 |
| Short name | T1240 |
| Test name | |
| Test status | |
| Simulation time | 4267638245 ps |
| CPU time | 4.63 seconds |
| Started | Nov 22 01:44:43 PM PST 23 |
| Finished | Nov 22 01:44:49 PM PST 23 |
| Peak memory | 195936 kb |
| Host | smart-6e0a4e25-96b4-439a-aaa7-888425b25631 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1204354119966316504837485637422075419142350372979571006728797208736440171942 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 26.uart_rx_start_bit_filter.1204354119966316504837485637422075419142350372979571006728797208736440171942 |
| Directory | /workspace/26.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/26.uart_smoke.109862651370199261716081231767034281376128836566841873402688191766019411899883 |
| Short name | T661 |
| Test name | |
| Test status | |
| Simulation time | 5759626309 ps |
| CPU time | 18.33 seconds |
| Started | Nov 22 01:44:48 PM PST 23 |
| Finished | Nov 22 01:45:09 PM PST 23 |
| Peak memory | 199520 kb |
| Host | smart-1664509a-08b8-4b3f-827d-6def5ca60efe |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=109862651370199261716081231767034281376128836566841873402688191766019411899883 -assert nopostproc +UVM_TESTNAME=uart_bas e_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 26.uart_smoke.109862651370199261716081231767034281376128836566841873402688191766019411899883 |
| Directory | /workspace/26.uart_smoke/latest |
| Test location | /workspace/coverage/default/26.uart_stress_all.11828585020769237981565014655072923705579840648308121635758798312005115800982 |
| Short name | T1131 |
| Test name | |
| Test status | |
| Simulation time | 43402307308 ps |
| CPU time | 56.91 seconds |
| Started | Nov 22 01:45:01 PM PST 23 |
| Finished | Nov 22 01:45:59 PM PST 23 |
| Peak memory | 200132 kb |
| Host | smart-ce2a196c-edbb-45d7-9bd3-b51e72539875 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11828585020769237981565014655072923705579840648308121635758798312005115800982 -assert nopos tproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 26.uart_stress_all.11828585020769237981565014655072923705579840648308121635758798312005115800982 |
| Directory | /workspace/26.uart_stress_all/latest |
| Test location | /workspace/coverage/default/26.uart_stress_all_with_rand_reset.106067273199092319616591826764069191828662617405298059536242986375612396658130 |
| Short name | T1077 |
| Test name | |
| Test status | |
| Simulation time | 87476847566 ps |
| CPU time | 469.65 seconds |
| Started | Nov 22 01:44:48 PM PST 23 |
| Finished | Nov 22 01:52:41 PM PST 23 |
| Peak memory | 226216 kb |
| Host | smart-343577b8-a1cf-4aa2-ac5c-0e936a28d314 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10606727319909231961659182 6764069191828662617405298059536242986375612396658130 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_stress_all_with_rand_reset.106067273199 092319616591826764069191828662617405298059536242986375612396658130 |
| Directory | /workspace/26.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/26.uart_tx_ovrd.6321820754952552934494459403744795282757402227463074542517746275460953816589 |
| Short name | T984 |
| Test name | |
| Test status | |
| Simulation time | 485186362 ps |
| CPU time | 1.31 seconds |
| Started | Nov 22 01:44:53 PM PST 23 |
| Finished | Nov 22 01:44:56 PM PST 23 |
| Peak memory | 197900 kb |
| Host | smart-ee9205e7-217a-4c08-a41e-f95fbea35ed0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=6321820754952552934494459403744795282757402227463074542517746275460953816589 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 26.uart_tx_ovrd.6321820754952552934494459403744795282757402227463074542517746275460953816589 |
| Directory | /workspace/26.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/26.uart_tx_rx.111660840974331660246277114305909786397833112692287669409856815168724222048099 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 57391945390 ps |
| CPU time | 63.48 seconds |
| Started | Nov 22 01:44:49 PM PST 23 |
| Finished | Nov 22 01:45:55 PM PST 23 |
| Peak memory | 200044 kb |
| Host | smart-d94129f1-7253-43ca-a7c6-b3e3e182b21b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=111660840974331660246277114305909786397833112692287669409856815168724222048099 -assert nopostproc +UVM_TESTNAME=uart_bas e_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 26.uart_tx_rx.111660840974331660246277114305909786397833112692287669409856815168724222048099 |
| Directory | /workspace/26.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/260.uart_fifo_reset.89714890210921187480685984834740749444494124983885815007945838495364334172504 |
| Short name | T852 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 112.55 seconds |
| Started | Nov 22 01:46:19 PM PST 23 |
| Finished | Nov 22 01:48:13 PM PST 23 |
| Peak memory | 198912 kb |
| Host | smart-6c59bd87-1c60-4006-b050-6e1afb8ca701 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=89714890210921187480685984834740749444494124983885815007945838495364334172504 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 260.uart_fifo_reset.89714890210921187480685984834740749444494124983885815007945838495364334172504 |
| Directory | /workspace/260.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/261.uart_fifo_reset.74692834672921019553982282828709183230948451089907610696607267559436947497697 |
| Short name | T797 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 112.69 seconds |
| Started | Nov 22 01:46:12 PM PST 23 |
| Finished | Nov 22 01:48:08 PM PST 23 |
| Peak memory | 198988 kb |
| Host | smart-5247423b-c7e5-499d-902d-9ec16e479478 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=74692834672921019553982282828709183230948451089907610696607267559436947497697 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 261.uart_fifo_reset.74692834672921019553982282828709183230948451089907610696607267559436947497697 |
| Directory | /workspace/261.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/262.uart_fifo_reset.44572947542413113333423628120583273738886435805629319085792313620754932501521 |
| Short name | T1101 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 112.94 seconds |
| Started | Nov 22 01:45:59 PM PST 23 |
| Finished | Nov 22 01:48:00 PM PST 23 |
| Peak memory | 198904 kb |
| Host | smart-85ecc692-4717-429e-bd70-1c65f2a53c34 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=44572947542413113333423628120583273738886435805629319085792313620754932501521 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 262.uart_fifo_reset.44572947542413113333423628120583273738886435805629319085792313620754932501521 |
| Directory | /workspace/262.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/263.uart_fifo_reset.4675322360605854606245291916164736314592534851264500420251337157563746227799 |
| Short name | T690 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 112.77 seconds |
| Started | Nov 22 01:46:16 PM PST 23 |
| Finished | Nov 22 01:48:10 PM PST 23 |
| Peak memory | 198952 kb |
| Host | smart-d333fdfc-7d2c-4996-ba22-48abda1fee91 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4675322360605854606245291916164736314592534851264500420251337157563746227799 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 263.uart_fifo_reset.4675322360605854606245291916164736314592534851264500420251337157563746227799 |
| Directory | /workspace/263.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/264.uart_fifo_reset.12194454319138910272396662981615185144982352770898055031651609344321293958302 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 112.82 seconds |
| Started | Nov 22 01:46:12 PM PST 23 |
| Finished | Nov 22 01:48:09 PM PST 23 |
| Peak memory | 198884 kb |
| Host | smart-28da4fdc-c43f-484c-8d8d-1dd63913a770 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=12194454319138910272396662981615185144982352770898055031651609344321293958302 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 264.uart_fifo_reset.12194454319138910272396662981615185144982352770898055031651609344321293958302 |
| Directory | /workspace/264.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/265.uart_fifo_reset.42419064490816854531829065632331064126525584929918774488863006354723118534178 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 112.73 seconds |
| Started | Nov 22 01:46:24 PM PST 23 |
| Finished | Nov 22 01:48:17 PM PST 23 |
| Peak memory | 198896 kb |
| Host | smart-dcea3895-5386-42e4-8cbd-313a7e21e2e2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=42419064490816854531829065632331064126525584929918774488863006354723118534178 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 265.uart_fifo_reset.42419064490816854531829065632331064126525584929918774488863006354723118534178 |
| Directory | /workspace/265.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/266.uart_fifo_reset.102281514535999711724223530499758500690829217160785245045087498673108193167686 |
| Short name | T1222 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 114.82 seconds |
| Started | Nov 22 01:46:24 PM PST 23 |
| Finished | Nov 22 01:48:20 PM PST 23 |
| Peak memory | 198904 kb |
| Host | smart-d82c901b-f41c-4b7f-8e03-c9d7c98c644d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=102281514535999711724223530499758500690829217160785245045087498673108193167686 -assert nopostproc +UVM_TESTNAME=uart_bas e_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.uart_fifo_reset.102281514535999711724223530499758500690829217160785245045087498673108193167686 |
| Directory | /workspace/266.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/267.uart_fifo_reset.60530825239408211087286750959810759567232008177554747926838751089467862127902 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 112.43 seconds |
| Started | Nov 22 01:46:12 PM PST 23 |
| Finished | Nov 22 01:48:08 PM PST 23 |
| Peak memory | 198884 kb |
| Host | smart-670567e7-5470-4d1c-806a-cb35c651e459 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=60530825239408211087286750959810759567232008177554747926838751089467862127902 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 267.uart_fifo_reset.60530825239408211087286750959810759567232008177554747926838751089467862127902 |
| Directory | /workspace/267.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/268.uart_fifo_reset.77590535161625771513707915622260442850537933121860560007332626855525270514933 |
| Short name | T657 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 112.46 seconds |
| Started | Nov 22 01:46:20 PM PST 23 |
| Finished | Nov 22 01:48:14 PM PST 23 |
| Peak memory | 198908 kb |
| Host | smart-6470e667-bea2-40ba-8ced-c5712b888d38 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=77590535161625771513707915622260442850537933121860560007332626855525270514933 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 268.uart_fifo_reset.77590535161625771513707915622260442850537933121860560007332626855525270514933 |
| Directory | /workspace/268.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/269.uart_fifo_reset.104564488070225671493889896151308529851845960992698225215111927518658863167391 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 113.2 seconds |
| Started | Nov 22 01:46:11 PM PST 23 |
| Finished | Nov 22 01:48:09 PM PST 23 |
| Peak memory | 198908 kb |
| Host | smart-a30b232e-aafb-4c5f-98a7-690e0beca46b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=104564488070225671493889896151308529851845960992698225215111927518658863167391 -assert nopostproc +UVM_TESTNAME=uart_bas e_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.uart_fifo_reset.104564488070225671493889896151308529851845960992698225215111927518658863167391 |
| Directory | /workspace/269.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/27.uart_alert_test.77136030461408777211135150896692672051286033438309862865741047302920289835897 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 16368684 ps |
| CPU time | 0.53 seconds |
| Started | Nov 22 01:44:44 PM PST 23 |
| Finished | Nov 22 01:44:46 PM PST 23 |
| Peak memory | 194648 kb |
| Host | smart-f484f351-6383-4094-a1bd-8bf2e9b73ab5 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77136030461408777211135150896692672051286033438309862865741047302920289835897 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 27.uart_alert_test.77136030461408777211135150896692672051286033438309862865741047302920289835897 |
| Directory | /workspace/27.uart_alert_test/latest |
| Test location | /workspace/coverage/default/27.uart_fifo_full.38691173857963292800383814204876022384489619386125828733093088289477808117453 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 61777160308 ps |
| CPU time | 61.12 seconds |
| Started | Nov 22 01:44:45 PM PST 23 |
| Finished | Nov 22 01:45:48 PM PST 23 |
| Peak memory | 200116 kb |
| Host | smart-a3cff9d4-2609-4105-9f80-f853c9f6a733 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=38691173857963292800383814204876022384489619386125828733093088289477808117453 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 27.uart_fifo_full.38691173857963292800383814204876022384489619386125828733093088289477808117453 |
| Directory | /workspace/27.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/27.uart_fifo_overflow.108204257281235131206571251161327322784979293277078910861542425977119107755216 |
| Short name | T947 |
| Test name | |
| Test status | |
| Simulation time | 58551936110 ps |
| CPU time | 54.89 seconds |
| Started | Nov 22 01:44:53 PM PST 23 |
| Finished | Nov 22 01:45:50 PM PST 23 |
| Peak memory | 199884 kb |
| Host | smart-ee57acdb-2c5f-4ff3-9a21-9b575f9ece71 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=108204257281235131206571251161327322784979293277078910861542425977119107755216 -assert nopostproc +UVM_TESTNAME=uart_bas e_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 27.uart_fifo_overflow.108204257281235131206571251161327322784979293277078910861542425977119107755216 |
| Directory | /workspace/27.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/27.uart_fifo_reset.87909482450147686068075687231998313509708571566462065552061878688887031239846 |
| Short name | T1216 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 112.78 seconds |
| Started | Nov 22 01:44:51 PM PST 23 |
| Finished | Nov 22 01:46:45 PM PST 23 |
| Peak memory | 198884 kb |
| Host | smart-82a0887a-ef7f-4bf9-95ea-e6b58c753214 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=87909482450147686068075687231998313509708571566462065552061878688887031239846 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 27.uart_fifo_reset.87909482450147686068075687231998313509708571566462065552061878688887031239846 |
| Directory | /workspace/27.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/27.uart_intr.54277099424186301500776073458116831126286141618080090717135958959393037989805 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 787145125175 ps |
| CPU time | 783.52 seconds |
| Started | Nov 22 01:44:53 PM PST 23 |
| Finished | Nov 22 01:57:58 PM PST 23 |
| Peak memory | 200128 kb |
| Host | smart-44ed5fc0-cb4d-468e-83d4-8e9f6153842b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54277099424186301500776073458116831126286141618080090717135958959393037989805 -assert nopost proc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 27.uart_intr.54277099424186301500776073458116831126286141618080090717135958959393037989805 |
| Directory | /workspace/27.uart_intr/latest |
| Test location | /workspace/coverage/default/27.uart_long_xfer_wo_dly.3767169377228826911501734554076855461900104649214684750569783702491386836814 |
| Short name | T842 |
| Test name | |
| Test status | |
| Simulation time | 93387746707 ps |
| CPU time | 346.33 seconds |
| Started | Nov 22 01:44:43 PM PST 23 |
| Finished | Nov 22 01:50:31 PM PST 23 |
| Peak memory | 200140 kb |
| Host | smart-d962a3fa-9a34-40f4-babb-1a863bc8132c |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3767169377228826911501734554076855461900104649214684750569783702491386836814 -assert nopostproc +UVM_TEST NAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_long_xfer_wo_dly.3767169377228826911501734554076855461900104649214684750569783702491386836814 |
| Directory | /workspace/27.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/27.uart_loopback.24210774400462255021893231181218453701857287012188551209170199411582197648499 |
| Short name | T825 |
| Test name | |
| Test status | |
| Simulation time | 14572448663 ps |
| CPU time | 16.56 seconds |
| Started | Nov 22 01:44:48 PM PST 23 |
| Finished | Nov 22 01:45:07 PM PST 23 |
| Peak memory | 200072 kb |
| Host | smart-10e687eb-8b10-4954-a4a5-2febe623c3fb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=24210774400462255021893231181218453701857287012188551209170199411582197648499 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 27.uart_loopback.24210774400462255021893231181218453701857287012188551209170199411582197648499 |
| Directory | /workspace/27.uart_loopback/latest |
| Test location | /workspace/coverage/default/27.uart_noise_filter.80911694777705899491667965881678988592251443608313535457153614191375330515932 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 94501577082 ps |
| CPU time | 96.35 seconds |
| Started | Nov 22 01:44:48 PM PST 23 |
| Finished | Nov 22 01:46:27 PM PST 23 |
| Peak memory | 200244 kb |
| Host | smart-d0f2a2ed-0363-4e6e-8528-c44098c2c646 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=80911694777705899491667965881678988592251443608313535457153614191375330515932 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_noise_filter.80911694777705899491667965881678988592251443608313535457153614191375330515932 |
| Directory | /workspace/27.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/27.uart_perf.39255908483319533369702828766644442940101150500253159631329893513365384839115 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 14098773881 ps |
| CPU time | 471.27 seconds |
| Started | Nov 22 01:44:46 PM PST 23 |
| Finished | Nov 22 01:52:40 PM PST 23 |
| Peak memory | 200152 kb |
| Host | smart-9b9682d8-a43d-4847-b0e1-293bea13dd5f |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=39255908483319533369702828766644442940101150500253159631329893513365384839115 -assert nopostproc +UVM_TES TNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 27.uart_perf.39255908483319533369702828766644442940101150500253159631329893513365384839115 |
| Directory | /workspace/27.uart_perf/latest |
| Test location | /workspace/coverage/default/27.uart_rx_oversample.85995001582259300344982731507491415131891515818863318122821632260506421599543 |
| Short name | T730 |
| Test name | |
| Test status | |
| Simulation time | 4370280281 ps |
| CPU time | 20.29 seconds |
| Started | Nov 22 01:44:46 PM PST 23 |
| Finished | Nov 22 01:45:10 PM PST 23 |
| Peak memory | 198992 kb |
| Host | smart-6a98968b-8a24-4175-9b22-7e290fe321d7 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=85995001582259300344982731507491415131891515818863318122821632260506421599543 -assert nopostproc +UVM_TES TNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 27.uart_rx_oversample.85995001582259300344982731507491415131891515818863318122821632260506421599543 |
| Directory | /workspace/27.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/27.uart_rx_parity_err.81668818748098069764424941082243194592309314525679603261216530990699458068882 |
| Short name | T951 |
| Test name | |
| Test status | |
| Simulation time | 36616611594 ps |
| CPU time | 38.09 seconds |
| Started | Nov 22 01:44:41 PM PST 23 |
| Finished | Nov 22 01:45:20 PM PST 23 |
| Peak memory | 200116 kb |
| Host | smart-d671eafa-6be6-4fb0-9e07-45222b2a8314 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=81668818748098069764424941082243194592309314525679603261216530990699458068882 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 27.uart_rx_parity_err.81668818748098069764424941082243194592309314525679603261216530990699458068882 |
| Directory | /workspace/27.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/27.uart_rx_start_bit_filter.98566271613060339359867282842712018824629870316513924791724970894884880724783 |
| Short name | T1135 |
| Test name | |
| Test status | |
| Simulation time | 4267638245 ps |
| CPU time | 4.64 seconds |
| Started | Nov 22 01:44:46 PM PST 23 |
| Finished | Nov 22 01:44:54 PM PST 23 |
| Peak memory | 196012 kb |
| Host | smart-127f6393-cac8-4ef4-a1d9-6731ca71ab5f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=98566271613060339359867282842712018824629870316513924791724970894884880724783 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 27.uart_rx_start_bit_filter.98566271613060339359867282842712018824629870316513924791724970894884880724783 |
| Directory | /workspace/27.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/27.uart_smoke.55896797023812200518632872339347588453645584913961724462462792554046226796853 |
| Short name | T1273 |
| Test name | |
| Test status | |
| Simulation time | 5759626309 ps |
| CPU time | 17.84 seconds |
| Started | Nov 22 01:44:45 PM PST 23 |
| Finished | Nov 22 01:45:05 PM PST 23 |
| Peak memory | 199604 kb |
| Host | smart-70bb349d-416c-47e3-a0ba-0f5f9ee19182 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=55896797023812200518632872339347588453645584913961724462462792554046226796853 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 27.uart_smoke.55896797023812200518632872339347588453645584913961724462462792554046226796853 |
| Directory | /workspace/27.uart_smoke/latest |
| Test location | /workspace/coverage/default/27.uart_stress_all.32454359223902070275198221404106422446988121025977155348603983444987575461852 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 43402307308 ps |
| CPU time | 56.54 seconds |
| Started | Nov 22 01:44:53 PM PST 23 |
| Finished | Nov 22 01:45:51 PM PST 23 |
| Peak memory | 200056 kb |
| Host | smart-4d3299b4-faf5-4077-a899-ff5e5de3ee1c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32454359223902070275198221404106422446988121025977155348603983444987575461852 -assert nopos tproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 27.uart_stress_all.32454359223902070275198221404106422446988121025977155348603983444987575461852 |
| Directory | /workspace/27.uart_stress_all/latest |
| Test location | /workspace/coverage/default/27.uart_stress_all_with_rand_reset.63328512206353767837368373789203336711391202563367295717378008673097864259895 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 87476847566 ps |
| CPU time | 472.86 seconds |
| Started | Nov 22 01:44:43 PM PST 23 |
| Finished | Nov 22 01:52:37 PM PST 23 |
| Peak memory | 226240 kb |
| Host | smart-9aea3415-e3cf-4baa-9a67-7390fbd96da4 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63328512206353767837368373 789203336711391202563367295717378008673097864259895 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_stress_all_with_rand_reset.6332851220635 3767837368373789203336711391202563367295717378008673097864259895 |
| Directory | /workspace/27.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/27.uart_tx_ovrd.96591560133770624778380076888176911795178216961510658769600782462401440863382 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 485186362 ps |
| CPU time | 1.26 seconds |
| Started | Nov 22 01:44:47 PM PST 23 |
| Finished | Nov 22 01:44:51 PM PST 23 |
| Peak memory | 197908 kb |
| Host | smart-499bf7af-692f-4f4b-92a9-a984fbd0d739 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=96591560133770624778380076888176911795178216961510658769600782462401440863382 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 27.uart_tx_ovrd.96591560133770624778380076888176911795178216961510658769600782462401440863382 |
| Directory | /workspace/27.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/27.uart_tx_rx.15094518660070204172620600965036427593179074611534527010019519433669179639307 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 57391945390 ps |
| CPU time | 63.05 seconds |
| Started | Nov 22 01:44:49 PM PST 23 |
| Finished | Nov 22 01:45:55 PM PST 23 |
| Peak memory | 200080 kb |
| Host | smart-9cd53582-d5ed-4285-b98b-76942f34e051 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=15094518660070204172620600965036427593179074611534527010019519433669179639307 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 27.uart_tx_rx.15094518660070204172620600965036427593179074611534527010019519433669179639307 |
| Directory | /workspace/27.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/270.uart_fifo_reset.80994053252235078134815243641374944405284570076526600397717315715235512116024 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 112.67 seconds |
| Started | Nov 22 01:46:08 PM PST 23 |
| Finished | Nov 22 01:48:06 PM PST 23 |
| Peak memory | 198964 kb |
| Host | smart-b0190c35-b17e-486b-affe-c6fc4d570771 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=80994053252235078134815243641374944405284570076526600397717315715235512116024 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 270.uart_fifo_reset.80994053252235078134815243641374944405284570076526600397717315715235512116024 |
| Directory | /workspace/270.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/271.uart_fifo_reset.77021994035036130854354859389362475479281180903581425406721208778617871779930 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 113.75 seconds |
| Started | Nov 22 01:46:21 PM PST 23 |
| Finished | Nov 22 01:48:16 PM PST 23 |
| Peak memory | 198900 kb |
| Host | smart-0a6baafe-7587-4a99-9020-95f0776e6ad8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=77021994035036130854354859389362475479281180903581425406721208778617871779930 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 271.uart_fifo_reset.77021994035036130854354859389362475479281180903581425406721208778617871779930 |
| Directory | /workspace/271.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/272.uart_fifo_reset.24190665567743335861313746590943771103167620868162423432757682512541772467315 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 112.89 seconds |
| Started | Nov 22 01:46:23 PM PST 23 |
| Finished | Nov 22 01:48:17 PM PST 23 |
| Peak memory | 198840 kb |
| Host | smart-a97f539c-2d3c-44a1-8dad-dc64f4eb6e69 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=24190665567743335861313746590943771103167620868162423432757682512541772467315 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 272.uart_fifo_reset.24190665567743335861313746590943771103167620868162423432757682512541772467315 |
| Directory | /workspace/272.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/273.uart_fifo_reset.86264120416335427655332256278128231066795115222947869793743508633483466443213 |
| Short name | T777 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 112.74 seconds |
| Started | Nov 22 01:46:04 PM PST 23 |
| Finished | Nov 22 01:48:02 PM PST 23 |
| Peak memory | 198840 kb |
| Host | smart-2a2a7503-a2bc-4660-9500-dff701763fcd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=86264120416335427655332256278128231066795115222947869793743508633483466443213 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 273.uart_fifo_reset.86264120416335427655332256278128231066795115222947869793743508633483466443213 |
| Directory | /workspace/273.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/274.uart_fifo_reset.79831881983083631897494080848992866083959597809875851249762195021825099207860 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 112.64 seconds |
| Started | Nov 22 01:46:22 PM PST 23 |
| Finished | Nov 22 01:48:16 PM PST 23 |
| Peak memory | 198936 kb |
| Host | smart-e95856e7-3188-4208-a779-59d629581933 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=79831881983083631897494080848992866083959597809875851249762195021825099207860 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 274.uart_fifo_reset.79831881983083631897494080848992866083959597809875851249762195021825099207860 |
| Directory | /workspace/274.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/275.uart_fifo_reset.27925776762459857156913368261788838060643204973690214355164344125314760362798 |
| Short name | T1094 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 115.18 seconds |
| Started | Nov 22 01:46:06 PM PST 23 |
| Finished | Nov 22 01:48:08 PM PST 23 |
| Peak memory | 198864 kb |
| Host | smart-4273a61c-7a7b-4cb6-8c30-7a81d0f1aa87 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=27925776762459857156913368261788838060643204973690214355164344125314760362798 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 275.uart_fifo_reset.27925776762459857156913368261788838060643204973690214355164344125314760362798 |
| Directory | /workspace/275.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/276.uart_fifo_reset.67140764893039289907813697156921135734514044776604379736477903884283272492708 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 113.92 seconds |
| Started | Nov 22 01:45:58 PM PST 23 |
| Finished | Nov 22 01:48:00 PM PST 23 |
| Peak memory | 198908 kb |
| Host | smart-a0e7dc1a-6f12-402c-aea3-ea025c4842f9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=67140764893039289907813697156921135734514044776604379736477903884283272492708 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 276.uart_fifo_reset.67140764893039289907813697156921135734514044776604379736477903884283272492708 |
| Directory | /workspace/276.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/277.uart_fifo_reset.24030988448931408607753909839854788944192311910923104023693096965313023679738 |
| Short name | T1235 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 113.93 seconds |
| Started | Nov 22 01:46:04 PM PST 23 |
| Finished | Nov 22 01:48:03 PM PST 23 |
| Peak memory | 198912 kb |
| Host | smart-9839e25c-5a41-418f-9c3f-8789f37f1330 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=24030988448931408607753909839854788944192311910923104023693096965313023679738 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 277.uart_fifo_reset.24030988448931408607753909839854788944192311910923104023693096965313023679738 |
| Directory | /workspace/277.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/278.uart_fifo_reset.71914884645551023465796475839360841965864198321817849983851287059208747023073 |
| Short name | T902 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 113.02 seconds |
| Started | Nov 22 01:46:14 PM PST 23 |
| Finished | Nov 22 01:48:10 PM PST 23 |
| Peak memory | 198920 kb |
| Host | smart-50616f00-ef45-442e-8991-e09f65a1cae2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=71914884645551023465796475839360841965864198321817849983851287059208747023073 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 278.uart_fifo_reset.71914884645551023465796475839360841965864198321817849983851287059208747023073 |
| Directory | /workspace/278.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/279.uart_fifo_reset.96380379662767725331072291800552315263031471906779819381660412433776874304911 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 113.68 seconds |
| Started | Nov 22 01:46:00 PM PST 23 |
| Finished | Nov 22 01:48:01 PM PST 23 |
| Peak memory | 198808 kb |
| Host | smart-646de54f-4228-4895-b822-ebae7ab49e7e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=96380379662767725331072291800552315263031471906779819381660412433776874304911 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 279.uart_fifo_reset.96380379662767725331072291800552315263031471906779819381660412433776874304911 |
| Directory | /workspace/279.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/28.uart_alert_test.20338921060024768809192592815379855036130480316095956050391279838675993576288 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 16368684 ps |
| CPU time | 0.53 seconds |
| Started | Nov 22 01:44:48 PM PST 23 |
| Finished | Nov 22 01:44:51 PM PST 23 |
| Peak memory | 194624 kb |
| Host | smart-657c8a95-be45-42e0-a97a-b628a4ebdca5 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20338921060024768809192592815379855036130480316095956050391279838675993576288 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 28.uart_alert_test.20338921060024768809192592815379855036130480316095956050391279838675993576288 |
| Directory | /workspace/28.uart_alert_test/latest |
| Test location | /workspace/coverage/default/28.uart_fifo_full.93960450357954113744049199835265112610516613009157508137434471729971026176659 |
| Short name | T1129 |
| Test name | |
| Test status | |
| Simulation time | 61777160308 ps |
| CPU time | 60.78 seconds |
| Started | Nov 22 01:44:51 PM PST 23 |
| Finished | Nov 22 01:45:54 PM PST 23 |
| Peak memory | 200124 kb |
| Host | smart-379e1b56-f173-4695-855a-21799c51449a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=93960450357954113744049199835265112610516613009157508137434471729971026176659 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 28.uart_fifo_full.93960450357954113744049199835265112610516613009157508137434471729971026176659 |
| Directory | /workspace/28.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/28.uart_fifo_overflow.58227379341677729599386353078259174637242879383410910596345595001574972135113 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 58551936110 ps |
| CPU time | 54.92 seconds |
| Started | Nov 22 01:44:48 PM PST 23 |
| Finished | Nov 22 01:45:46 PM PST 23 |
| Peak memory | 199872 kb |
| Host | smart-50cce96f-b80d-4e9d-a4cd-0f4a676a1502 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=58227379341677729599386353078259174637242879383410910596345595001574972135113 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 28.uart_fifo_overflow.58227379341677729599386353078259174637242879383410910596345595001574972135113 |
| Directory | /workspace/28.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/28.uart_fifo_reset.19501799026808705877779858965114303240931796071022036878037190138592368036380 |
| Short name | T1269 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 113.07 seconds |
| Started | Nov 22 01:44:42 PM PST 23 |
| Finished | Nov 22 01:46:37 PM PST 23 |
| Peak memory | 198884 kb |
| Host | smart-73fa2484-4c48-49e1-b823-b9006913433d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=19501799026808705877779858965114303240931796071022036878037190138592368036380 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 28.uart_fifo_reset.19501799026808705877779858965114303240931796071022036878037190138592368036380 |
| Directory | /workspace/28.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/28.uart_intr.110482734226422991981217792372247942452121060637913502050041486475224429617422 |
| Short name | T894 |
| Test name | |
| Test status | |
| Simulation time | 787145125175 ps |
| CPU time | 785.89 seconds |
| Started | Nov 22 01:44:45 PM PST 23 |
| Finished | Nov 22 01:57:54 PM PST 23 |
| Peak memory | 200104 kb |
| Host | smart-5ecd17a0-641b-44fc-9289-ea1fad303346 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110482734226422991981217792372247942452121060637913502050041486475224429617422 -assert nopos tproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 28.uart_intr.110482734226422991981217792372247942452121060637913502050041486475224429617422 |
| Directory | /workspace/28.uart_intr/latest |
| Test location | /workspace/coverage/default/28.uart_long_xfer_wo_dly.80066819250819204389294501576386629454597554348760534316437676686474141398689 |
| Short name | T1034 |
| Test name | |
| Test status | |
| Simulation time | 93387746707 ps |
| CPU time | 356.66 seconds |
| Started | Nov 22 01:44:50 PM PST 23 |
| Finished | Nov 22 01:50:49 PM PST 23 |
| Peak memory | 200136 kb |
| Host | smart-c150dd88-40b6-4319-8fe7-290b4c2a0dc0 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=80066819250819204389294501576386629454597554348760534316437676686474141398689 -assert nopostproc +UVM_TES TNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 28.uart_long_xfer_wo_dly.80066819250819204389294501576386629454597554348760534316437676686474141398689 |
| Directory | /workspace/28.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/28.uart_loopback.60573897618598669412560212742033651916993651471420925030590421061252607655700 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 14572448663 ps |
| CPU time | 16.1 seconds |
| Started | Nov 22 01:44:50 PM PST 23 |
| Finished | Nov 22 01:45:08 PM PST 23 |
| Peak memory | 200048 kb |
| Host | smart-57b3eb5e-f2be-4c74-b320-f36ca8da9353 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=60573897618598669412560212742033651916993651471420925030590421061252607655700 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 28.uart_loopback.60573897618598669412560212742033651916993651471420925030590421061252607655700 |
| Directory | /workspace/28.uart_loopback/latest |
| Test location | /workspace/coverage/default/28.uart_noise_filter.19450051019546927116151833618022775064882520416976398129004244508767681936768 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 94501577082 ps |
| CPU time | 96.89 seconds |
| Started | Nov 22 01:44:44 PM PST 23 |
| Finished | Nov 22 01:46:22 PM PST 23 |
| Peak memory | 200272 kb |
| Host | smart-6c31d0f3-130f-445f-a1ea-442a016b830d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=19450051019546927116151833618022775064882520416976398129004244508767681936768 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_noise_filter.19450051019546927116151833618022775064882520416976398129004244508767681936768 |
| Directory | /workspace/28.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/28.uart_perf.69743730077360530911686132120662978106159248583703009705738766638491283925093 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 14098773881 ps |
| CPU time | 471.79 seconds |
| Started | Nov 22 01:44:48 PM PST 23 |
| Finished | Nov 22 01:52:42 PM PST 23 |
| Peak memory | 200008 kb |
| Host | smart-e70fce88-dd41-410d-8f53-34235e07eafe |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=69743730077360530911686132120662978106159248583703009705738766638491283925093 -assert nopostproc +UVM_TES TNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 28.uart_perf.69743730077360530911686132120662978106159248583703009705738766638491283925093 |
| Directory | /workspace/28.uart_perf/latest |
| Test location | /workspace/coverage/default/28.uart_rx_oversample.28406244549773027171076192680134201391778860879181594144896062428062245341373 |
| Short name | T1088 |
| Test name | |
| Test status | |
| Simulation time | 4370280281 ps |
| CPU time | 20.03 seconds |
| Started | Nov 22 01:44:50 PM PST 23 |
| Finished | Nov 22 01:45:12 PM PST 23 |
| Peak memory | 198960 kb |
| Host | smart-659b67f6-948d-4de7-b7d5-90b6b666ca0d |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=28406244549773027171076192680134201391778860879181594144896062428062245341373 -assert nopostproc +UVM_TES TNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 28.uart_rx_oversample.28406244549773027171076192680134201391778860879181594144896062428062245341373 |
| Directory | /workspace/28.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/28.uart_rx_parity_err.49397560445133253414814608938887670450553240664246547735474358190664888597035 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 36616611594 ps |
| CPU time | 38.19 seconds |
| Started | Nov 22 01:44:48 PM PST 23 |
| Finished | Nov 22 01:45:29 PM PST 23 |
| Peak memory | 200112 kb |
| Host | smart-538fc8d2-5d50-4ae3-a609-0d863db0d0dc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=49397560445133253414814608938887670450553240664246547735474358190664888597035 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 28.uart_rx_parity_err.49397560445133253414814608938887670450553240664246547735474358190664888597035 |
| Directory | /workspace/28.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/28.uart_rx_start_bit_filter.719733208243138198796764054421511886492539890734316066476277680356405328037 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 4267638245 ps |
| CPU time | 4.67 seconds |
| Started | Nov 22 01:44:49 PM PST 23 |
| Finished | Nov 22 01:44:56 PM PST 23 |
| Peak memory | 195940 kb |
| Host | smart-b5b6aef1-c1a1-447a-9a25-98c2ab658ca5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=719733208243138198796764054421511886492539890734316066476277680356405328037 -assert nopostproc +UVM_TESTNAME=uart_base_t est +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 28.uart_rx_start_bit_filter.719733208243138198796764054421511886492539890734316066476277680356405328037 |
| Directory | /workspace/28.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/28.uart_smoke.113456201004142133257654945141917098334183158662753551729733587179619426198093 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 5759626309 ps |
| CPU time | 18.63 seconds |
| Started | Nov 22 01:44:46 PM PST 23 |
| Finished | Nov 22 01:45:07 PM PST 23 |
| Peak memory | 199616 kb |
| Host | smart-1ade162d-0be9-4a9f-980b-f9a3518907a7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=113456201004142133257654945141917098334183158662753551729733587179619426198093 -assert nopostproc +UVM_TESTNAME=uart_bas e_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 28.uart_smoke.113456201004142133257654945141917098334183158662753551729733587179619426198093 |
| Directory | /workspace/28.uart_smoke/latest |
| Test location | /workspace/coverage/default/28.uart_stress_all.115212710881984837940466895926754073084724646265121902957450569870050869545303 |
| Short name | T1083 |
| Test name | |
| Test status | |
| Simulation time | 43402307308 ps |
| CPU time | 57.31 seconds |
| Started | Nov 22 01:44:48 PM PST 23 |
| Finished | Nov 22 01:45:48 PM PST 23 |
| Peak memory | 200024 kb |
| Host | smart-c9eb07f1-1f7a-4a36-b1f5-caf6cd3afcc8 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115212710881984837940466895926754073084724646265121902957450569870050869545303 -assert nopo stproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 28.uart_stress_all.115212710881984837940466895926754073084724646265121902957450569870050869545303 |
| Directory | /workspace/28.uart_stress_all/latest |
| Test location | /workspace/coverage/default/28.uart_stress_all_with_rand_reset.94285499782997281191627458042595716321657323580639414069782214917031331132274 |
| Short name | T1176 |
| Test name | |
| Test status | |
| Simulation time | 87476847566 ps |
| CPU time | 451.52 seconds |
| Started | Nov 22 01:44:47 PM PST 23 |
| Finished | Nov 22 01:52:21 PM PST 23 |
| Peak memory | 226256 kb |
| Host | smart-a4522755-6911-4035-9825-f795c2726552 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94285499782997281191627458 042595716321657323580639414069782214917031331132274 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_stress_all_with_rand_reset.9428549978299 7281191627458042595716321657323580639414069782214917031331132274 |
| Directory | /workspace/28.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/28.uart_tx_ovrd.84167422472273608642530389593303425101748966020031456872349655161206881934372 |
| Short name | T1244 |
| Test name | |
| Test status | |
| Simulation time | 485186362 ps |
| CPU time | 1.27 seconds |
| Started | Nov 22 01:44:47 PM PST 23 |
| Finished | Nov 22 01:44:51 PM PST 23 |
| Peak memory | 197900 kb |
| Host | smart-52c7ff4e-e16c-4e39-884c-a5a6fcbf011b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=84167422472273608642530389593303425101748966020031456872349655161206881934372 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 28.uart_tx_ovrd.84167422472273608642530389593303425101748966020031456872349655161206881934372 |
| Directory | /workspace/28.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/28.uart_tx_rx.71818425357053817316943184814010951666186072349933520562489780410778412194209 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 57391945390 ps |
| CPU time | 63.9 seconds |
| Started | Nov 22 01:44:47 PM PST 23 |
| Finished | Nov 22 01:45:54 PM PST 23 |
| Peak memory | 200088 kb |
| Host | smart-f1b196fa-d0a8-4d45-8deb-0e9628296fee |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=71818425357053817316943184814010951666186072349933520562489780410778412194209 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 28.uart_tx_rx.71818425357053817316943184814010951666186072349933520562489780410778412194209 |
| Directory | /workspace/28.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/280.uart_fifo_reset.60864632973925652973278765536386938331955037910792542095437703151802834284636 |
| Short name | T991 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 113.23 seconds |
| Started | Nov 22 01:46:13 PM PST 23 |
| Finished | Nov 22 01:48:09 PM PST 23 |
| Peak memory | 198884 kb |
| Host | smart-6992f533-fb31-4d77-bde8-03d9c44e33fa |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=60864632973925652973278765536386938331955037910792542095437703151802834284636 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 280.uart_fifo_reset.60864632973925652973278765536386938331955037910792542095437703151802834284636 |
| Directory | /workspace/280.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/281.uart_fifo_reset.91769311141399774877384032894613210666623182901092023822788840668851851865132 |
| Short name | T720 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 113.34 seconds |
| Started | Nov 22 01:46:06 PM PST 23 |
| Finished | Nov 22 01:48:06 PM PST 23 |
| Peak memory | 198856 kb |
| Host | smart-c973af15-05c7-474f-8594-92f3f70faabc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=91769311141399774877384032894613210666623182901092023822788840668851851865132 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 281.uart_fifo_reset.91769311141399774877384032894613210666623182901092023822788840668851851865132 |
| Directory | /workspace/281.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/282.uart_fifo_reset.54864736168012114856844554165837597237122700567352843410358381081230837530316 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 112.92 seconds |
| Started | Nov 22 01:46:24 PM PST 23 |
| Finished | Nov 22 01:48:17 PM PST 23 |
| Peak memory | 198860 kb |
| Host | smart-6330496d-a6a3-4084-8b7a-36a51b35361d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=54864736168012114856844554165837597237122700567352843410358381081230837530316 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 282.uart_fifo_reset.54864736168012114856844554165837597237122700567352843410358381081230837530316 |
| Directory | /workspace/282.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/283.uart_fifo_reset.113565381714666934941504592252194601668152162795210724899249787368534318689694 |
| Short name | T848 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 114.08 seconds |
| Started | Nov 22 01:46:21 PM PST 23 |
| Finished | Nov 22 01:48:16 PM PST 23 |
| Peak memory | 198892 kb |
| Host | smart-378c44d0-9e03-4a4b-a9c8-68109cc508d8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=113565381714666934941504592252194601668152162795210724899249787368534318689694 -assert nopostproc +UVM_TESTNAME=uart_bas e_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.uart_fifo_reset.113565381714666934941504592252194601668152162795210724899249787368534318689694 |
| Directory | /workspace/283.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/284.uart_fifo_reset.5113812259751620039267536228809140412648787100206554227512980699540282623760 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 112.39 seconds |
| Started | Nov 22 01:46:17 PM PST 23 |
| Finished | Nov 22 01:48:10 PM PST 23 |
| Peak memory | 198880 kb |
| Host | smart-c78db554-800a-48a5-95f8-d68586031e2d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=5113812259751620039267536228809140412648787100206554227512980699540282623760 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 284.uart_fifo_reset.5113812259751620039267536228809140412648787100206554227512980699540282623760 |
| Directory | /workspace/284.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/285.uart_fifo_reset.39475272559217776189282419589044000390080493046337406306568945692134239803173 |
| Short name | T702 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 113.47 seconds |
| Started | Nov 22 01:46:26 PM PST 23 |
| Finished | Nov 22 01:48:21 PM PST 23 |
| Peak memory | 198884 kb |
| Host | smart-340890a6-5adf-4e63-8a82-8a8efd13259f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=39475272559217776189282419589044000390080493046337406306568945692134239803173 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 285.uart_fifo_reset.39475272559217776189282419589044000390080493046337406306568945692134239803173 |
| Directory | /workspace/285.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/286.uart_fifo_reset.102722271560324367641991989475525665933239429127468214703812728153858246270086 |
| Short name | T824 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 112.93 seconds |
| Started | Nov 22 01:46:20 PM PST 23 |
| Finished | Nov 22 01:48:14 PM PST 23 |
| Peak memory | 198812 kb |
| Host | smart-e53d3bf9-3840-46aa-b3e2-ae05c39f6f23 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=102722271560324367641991989475525665933239429127468214703812728153858246270086 -assert nopostproc +UVM_TESTNAME=uart_bas e_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.uart_fifo_reset.102722271560324367641991989475525665933239429127468214703812728153858246270086 |
| Directory | /workspace/286.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/287.uart_fifo_reset.31589701074874408815509574696835400101252586856868855360431644811443452096951 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 113.6 seconds |
| Started | Nov 22 01:46:24 PM PST 23 |
| Finished | Nov 22 01:48:18 PM PST 23 |
| Peak memory | 198840 kb |
| Host | smart-dfc2ccb7-e465-4057-a3dc-9355ae5b6978 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=31589701074874408815509574696835400101252586856868855360431644811443452096951 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 287.uart_fifo_reset.31589701074874408815509574696835400101252586856868855360431644811443452096951 |
| Directory | /workspace/287.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/288.uart_fifo_reset.3886258596743515745834088534627083458612565183619944077297563648167952642193 |
| Short name | T780 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 112.64 seconds |
| Started | Nov 22 01:46:11 PM PST 23 |
| Finished | Nov 22 01:48:08 PM PST 23 |
| Peak memory | 198892 kb |
| Host | smart-25345738-f7e1-4377-9526-34eb5c4edabc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3886258596743515745834088534627083458612565183619944077297563648167952642193 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 288.uart_fifo_reset.3886258596743515745834088534627083458612565183619944077297563648167952642193 |
| Directory | /workspace/288.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/289.uart_fifo_reset.74070481823018774343632239391673716131663517312554502046155796270184476369123 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 112.57 seconds |
| Started | Nov 22 01:46:09 PM PST 23 |
| Finished | Nov 22 01:48:07 PM PST 23 |
| Peak memory | 198920 kb |
| Host | smart-8aa4321f-dad0-47fd-86f3-07d0e85e6e87 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=74070481823018774343632239391673716131663517312554502046155796270184476369123 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 289.uart_fifo_reset.74070481823018774343632239391673716131663517312554502046155796270184476369123 |
| Directory | /workspace/289.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/29.uart_alert_test.35478305192606481250500746276098774391639626285552893016956787480163696902376 |
| Short name | T1137 |
| Test name | |
| Test status | |
| Simulation time | 16368684 ps |
| CPU time | 0.53 seconds |
| Started | Nov 22 01:44:47 PM PST 23 |
| Finished | Nov 22 01:44:51 PM PST 23 |
| Peak memory | 194504 kb |
| Host | smart-d817a2e8-c5e1-4651-944f-b2ee1b1e4936 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35478305192606481250500746276098774391639626285552893016956787480163696902376 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 29.uart_alert_test.35478305192606481250500746276098774391639626285552893016956787480163696902376 |
| Directory | /workspace/29.uart_alert_test/latest |
| Test location | /workspace/coverage/default/29.uart_fifo_full.109803707597639388774716390539940262620773465904712141575494584380438574944156 |
| Short name | T1042 |
| Test name | |
| Test status | |
| Simulation time | 61777160308 ps |
| CPU time | 60.63 seconds |
| Started | Nov 22 01:44:52 PM PST 23 |
| Finished | Nov 22 01:45:55 PM PST 23 |
| Peak memory | 200004 kb |
| Host | smart-0fc46989-15c7-4a6d-a3d3-a415fe40206f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=109803707597639388774716390539940262620773465904712141575494584380438574944156 -assert nopostproc +UVM_TESTNAME=uart_bas e_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 29.uart_fifo_full.109803707597639388774716390539940262620773465904712141575494584380438574944156 |
| Directory | /workspace/29.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/29.uart_fifo_overflow.94121516477687654814945969348878539881742608871206462430959870564008298091992 |
| Short name | T1199 |
| Test name | |
| Test status | |
| Simulation time | 58551936110 ps |
| CPU time | 54.61 seconds |
| Started | Nov 22 01:44:47 PM PST 23 |
| Finished | Nov 22 01:45:45 PM PST 23 |
| Peak memory | 199864 kb |
| Host | smart-74c14f83-a192-4a33-acd4-3d849caf6a45 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=94121516477687654814945969348878539881742608871206462430959870564008298091992 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 29.uart_fifo_overflow.94121516477687654814945969348878539881742608871206462430959870564008298091992 |
| Directory | /workspace/29.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/29.uart_fifo_reset.101580483636078960799273012853585333742804906839188652491118395539755333646947 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 112.86 seconds |
| Started | Nov 22 01:44:45 PM PST 23 |
| Finished | Nov 22 01:46:40 PM PST 23 |
| Peak memory | 198908 kb |
| Host | smart-14bef1ca-a4ab-4012-9a7f-654cf3b19f6f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=101580483636078960799273012853585333742804906839188652491118395539755333646947 -assert nopostproc +UVM_TESTNAME=uart_bas e_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_reset.101580483636078960799273012853585333742804906839188652491118395539755333646947 |
| Directory | /workspace/29.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/29.uart_intr.64852347149404352682250777685884036535147172345072166524568832623663550800064 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 787145125175 ps |
| CPU time | 786.25 seconds |
| Started | Nov 22 01:44:43 PM PST 23 |
| Finished | Nov 22 01:57:51 PM PST 23 |
| Peak memory | 200132 kb |
| Host | smart-edea09c7-73b8-4728-b3d2-b5aebd47db03 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64852347149404352682250777685884036535147172345072166524568832623663550800064 -assert nopost proc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 29.uart_intr.64852347149404352682250777685884036535147172345072166524568832623663550800064 |
| Directory | /workspace/29.uart_intr/latest |
| Test location | /workspace/coverage/default/29.uart_long_xfer_wo_dly.59567039619895596163073088019356130741687847117405388846181870433371317250212 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 93387746707 ps |
| CPU time | 346.58 seconds |
| Started | Nov 22 01:44:45 PM PST 23 |
| Finished | Nov 22 01:50:34 PM PST 23 |
| Peak memory | 200064 kb |
| Host | smart-af902973-ba87-4baf-8293-6edd03c5fc68 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=59567039619895596163073088019356130741687847117405388846181870433371317250212 -assert nopostproc +UVM_TES TNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 29.uart_long_xfer_wo_dly.59567039619895596163073088019356130741687847117405388846181870433371317250212 |
| Directory | /workspace/29.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/29.uart_loopback.95602266327420619408341704772878226235889410376424490741678014502687505514185 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 14572448663 ps |
| CPU time | 16.17 seconds |
| Started | Nov 22 01:44:51 PM PST 23 |
| Finished | Nov 22 01:45:09 PM PST 23 |
| Peak memory | 199984 kb |
| Host | smart-b4d30c03-412c-413a-ad7c-b8dbd6a14968 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=95602266327420619408341704772878226235889410376424490741678014502687505514185 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 29.uart_loopback.95602266327420619408341704772878226235889410376424490741678014502687505514185 |
| Directory | /workspace/29.uart_loopback/latest |
| Test location | /workspace/coverage/default/29.uart_noise_filter.46604599198521424709381360989349078625636997417792208135900176070651110622047 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 94501577082 ps |
| CPU time | 97.37 seconds |
| Started | Nov 22 01:44:51 PM PST 23 |
| Finished | Nov 22 01:46:30 PM PST 23 |
| Peak memory | 200244 kb |
| Host | smart-621af7c3-068a-431c-8abd-0b5fc7506b5b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=46604599198521424709381360989349078625636997417792208135900176070651110622047 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_noise_filter.46604599198521424709381360989349078625636997417792208135900176070651110622047 |
| Directory | /workspace/29.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/29.uart_perf.9828765797049353192670960332316414593209466333732323208532102614534777422747 |
| Short name | T994 |
| Test name | |
| Test status | |
| Simulation time | 14098773881 ps |
| CPU time | 476.16 seconds |
| Started | Nov 22 01:44:51 PM PST 23 |
| Finished | Nov 22 01:52:49 PM PST 23 |
| Peak memory | 200164 kb |
| Host | smart-062fdd99-9471-4f81-b23c-e0d80b1b52a0 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=9828765797049353192670960332316414593209466333732323208532102614534777422747 -assert nopostproc +UVM_TEST NAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 29.uart_perf.9828765797049353192670960332316414593209466333732323208532102614534777422747 |
| Directory | /workspace/29.uart_perf/latest |
| Test location | /workspace/coverage/default/29.uart_rx_oversample.82739668345194034204720085699585554990350596173741146658385891022004111598327 |
| Short name | T676 |
| Test name | |
| Test status | |
| Simulation time | 4370280281 ps |
| CPU time | 20.18 seconds |
| Started | Nov 22 01:44:46 PM PST 23 |
| Finished | Nov 22 01:45:08 PM PST 23 |
| Peak memory | 198956 kb |
| Host | smart-fc17ff76-910f-454e-b208-ca5f85a4a296 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=82739668345194034204720085699585554990350596173741146658385891022004111598327 -assert nopostproc +UVM_TES TNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 29.uart_rx_oversample.82739668345194034204720085699585554990350596173741146658385891022004111598327 |
| Directory | /workspace/29.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/29.uart_rx_parity_err.51990342602446374378111182586947117532220939524181182611360806877344438599962 |
| Short name | T1186 |
| Test name | |
| Test status | |
| Simulation time | 36616611594 ps |
| CPU time | 37.75 seconds |
| Started | Nov 22 01:44:48 PM PST 23 |
| Finished | Nov 22 01:45:29 PM PST 23 |
| Peak memory | 199964 kb |
| Host | smart-31e36088-6f56-4560-95a5-0929f86bf9bc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=51990342602446374378111182586947117532220939524181182611360806877344438599962 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 29.uart_rx_parity_err.51990342602446374378111182586947117532220939524181182611360806877344438599962 |
| Directory | /workspace/29.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/29.uart_rx_start_bit_filter.95082032333323234450949824158719348038688970665248895548842161676397957638468 |
| Short name | T786 |
| Test name | |
| Test status | |
| Simulation time | 4267638245 ps |
| CPU time | 4.72 seconds |
| Started | Nov 22 01:44:51 PM PST 23 |
| Finished | Nov 22 01:44:58 PM PST 23 |
| Peak memory | 195924 kb |
| Host | smart-7f10a6f4-9606-42e7-b65a-0059f0ad0cf4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=95082032333323234450949824158719348038688970665248895548842161676397957638468 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 29.uart_rx_start_bit_filter.95082032333323234450949824158719348038688970665248895548842161676397957638468 |
| Directory | /workspace/29.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/29.uart_smoke.18773287180669299620446734231405362136983123940961261483189444916890424008664 |
| Short name | T758 |
| Test name | |
| Test status | |
| Simulation time | 5759626309 ps |
| CPU time | 18.25 seconds |
| Started | Nov 22 01:44:49 PM PST 23 |
| Finished | Nov 22 01:45:10 PM PST 23 |
| Peak memory | 199640 kb |
| Host | smart-abcdb23b-3cf7-4062-9e41-0fdabba1d24f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=18773287180669299620446734231405362136983123940961261483189444916890424008664 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 29.uart_smoke.18773287180669299620446734231405362136983123940961261483189444916890424008664 |
| Directory | /workspace/29.uart_smoke/latest |
| Test location | /workspace/coverage/default/29.uart_stress_all.19167704753117260316080325564207130142562013258033219799988707945041799054419 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 43402307308 ps |
| CPU time | 57.44 seconds |
| Started | Nov 22 01:44:50 PM PST 23 |
| Finished | Nov 22 01:45:50 PM PST 23 |
| Peak memory | 200116 kb |
| Host | smart-0be07e24-b464-41eb-9219-067aee509ba0 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19167704753117260316080325564207130142562013258033219799988707945041799054419 -assert nopos tproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 29.uart_stress_all.19167704753117260316080325564207130142562013258033219799988707945041799054419 |
| Directory | /workspace/29.uart_stress_all/latest |
| Test location | /workspace/coverage/default/29.uart_stress_all_with_rand_reset.7486109946287584376573787340137276061572662817604562157293686866957863532292 |
| Short name | T659 |
| Test name | |
| Test status | |
| Simulation time | 87476847566 ps |
| CPU time | 467.61 seconds |
| Started | Nov 22 01:44:45 PM PST 23 |
| Finished | Nov 22 01:52:35 PM PST 23 |
| Peak memory | 226208 kb |
| Host | smart-c1348d2d-e5da-4fb3-92c8-a7d4895ea995 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74861099462875843765737873 40137276061572662817604562157293686866957863532292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_stress_all_with_rand_reset.74861099462875 84376573787340137276061572662817604562157293686866957863532292 |
| Directory | /workspace/29.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/29.uart_tx_ovrd.158871296690897495989639905309734203674289553640062840520024628103542232563 |
| Short name | T1096 |
| Test name | |
| Test status | |
| Simulation time | 485186362 ps |
| CPU time | 1.3 seconds |
| Started | Nov 22 01:44:44 PM PST 23 |
| Finished | Nov 22 01:44:47 PM PST 23 |
| Peak memory | 197940 kb |
| Host | smart-f2e87f9d-f8c3-4c71-ac76-a78f145e897d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=158871296690897495989639905309734203674289553640062840520024628103542232563 -assert nopostproc +UVM_TESTNAME=uart_base_t est +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 29.uart_tx_ovrd.158871296690897495989639905309734203674289553640062840520024628103542232563 |
| Directory | /workspace/29.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/29.uart_tx_rx.21737607898042043740552479029062765799664361196967431582177231864900747946716 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 57391945390 ps |
| CPU time | 63.3 seconds |
| Started | Nov 22 01:44:44 PM PST 23 |
| Finished | Nov 22 01:45:49 PM PST 23 |
| Peak memory | 200064 kb |
| Host | smart-6e083b8d-d8cf-4cdc-9c5b-12d585659dfa |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=21737607898042043740552479029062765799664361196967431582177231864900747946716 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 29.uart_tx_rx.21737607898042043740552479029062765799664361196967431582177231864900747946716 |
| Directory | /workspace/29.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/290.uart_fifo_reset.99480340548496530950137753432378038430442493033248575047580206293545743674535 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 111.91 seconds |
| Started | Nov 22 01:46:09 PM PST 23 |
| Finished | Nov 22 01:48:06 PM PST 23 |
| Peak memory | 198760 kb |
| Host | smart-8591be7c-fdab-4f28-9bac-284ded099f48 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=99480340548496530950137753432378038430442493033248575047580206293545743674535 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 290.uart_fifo_reset.99480340548496530950137753432378038430442493033248575047580206293545743674535 |
| Directory | /workspace/290.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/291.uart_fifo_reset.50128418721697312175834330764243000557367113425131746033389033829606593818791 |
| Short name | T1270 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 112.98 seconds |
| Started | Nov 22 01:46:10 PM PST 23 |
| Finished | Nov 22 01:48:08 PM PST 23 |
| Peak memory | 198884 kb |
| Host | smart-5f5a3f40-ea97-4d9e-904b-243fe097113f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=50128418721697312175834330764243000557367113425131746033389033829606593818791 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 291.uart_fifo_reset.50128418721697312175834330764243000557367113425131746033389033829606593818791 |
| Directory | /workspace/291.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/292.uart_fifo_reset.87038465860692889539646751928997588406674299499130414237605817335639751928448 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 112.12 seconds |
| Started | Nov 22 01:46:16 PM PST 23 |
| Finished | Nov 22 01:48:09 PM PST 23 |
| Peak memory | 198760 kb |
| Host | smart-df5d0530-2f16-4b37-9d1f-04b1901d2140 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=87038465860692889539646751928997588406674299499130414237605817335639751928448 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 292.uart_fifo_reset.87038465860692889539646751928997588406674299499130414237605817335639751928448 |
| Directory | /workspace/292.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/293.uart_fifo_reset.44678548399443508178069445241593690492685297255072201222606273666196889829903 |
| Short name | T832 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 112.93 seconds |
| Started | Nov 22 01:46:05 PM PST 23 |
| Finished | Nov 22 01:48:05 PM PST 23 |
| Peak memory | 198760 kb |
| Host | smart-f9117fe2-aa88-4e44-bc52-aff6da29fc8f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=44678548399443508178069445241593690492685297255072201222606273666196889829903 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 293.uart_fifo_reset.44678548399443508178069445241593690492685297255072201222606273666196889829903 |
| Directory | /workspace/293.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/294.uart_fifo_reset.69445879138719668192775809043084777128987272754469717909381789817591918265342 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 112.76 seconds |
| Started | Nov 22 01:46:26 PM PST 23 |
| Finished | Nov 22 01:48:20 PM PST 23 |
| Peak memory | 198936 kb |
| Host | smart-6d66354b-4c9c-45ce-8f12-31ac04d6a812 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=69445879138719668192775809043084777128987272754469717909381789817591918265342 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 294.uart_fifo_reset.69445879138719668192775809043084777128987272754469717909381789817591918265342 |
| Directory | /workspace/294.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/295.uart_fifo_reset.23477531586059255417307325941149806089913515851010245479751722663472845693806 |
| Short name | T1168 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 113 seconds |
| Started | Nov 22 01:46:10 PM PST 23 |
| Finished | Nov 22 01:48:08 PM PST 23 |
| Peak memory | 198920 kb |
| Host | smart-f57c9dcf-8ed4-449b-baa3-5caf49d6f5a9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=23477531586059255417307325941149806089913515851010245479751722663472845693806 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 295.uart_fifo_reset.23477531586059255417307325941149806089913515851010245479751722663472845693806 |
| Directory | /workspace/295.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/296.uart_fifo_reset.30015916249195831254665748916273051289807735524121768157856387341514700701445 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 113.03 seconds |
| Started | Nov 22 01:46:17 PM PST 23 |
| Finished | Nov 22 01:48:12 PM PST 23 |
| Peak memory | 198816 kb |
| Host | smart-a812c297-a672-48f5-bf63-1df7c70bdafc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=30015916249195831254665748916273051289807735524121768157856387341514700701445 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 296.uart_fifo_reset.30015916249195831254665748916273051289807735524121768157856387341514700701445 |
| Directory | /workspace/296.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/297.uart_fifo_reset.63520341721084487834066869026163731002873954892252524231215372808883554339607 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 112.41 seconds |
| Started | Nov 22 01:46:10 PM PST 23 |
| Finished | Nov 22 01:48:07 PM PST 23 |
| Peak memory | 198760 kb |
| Host | smart-248dab9e-d2a2-4bf5-88d9-57ecce377eea |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=63520341721084487834066869026163731002873954892252524231215372808883554339607 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 297.uart_fifo_reset.63520341721084487834066869026163731002873954892252524231215372808883554339607 |
| Directory | /workspace/297.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/298.uart_fifo_reset.49550840012530104856344676592148586786741298654686787758374934902826298145753 |
| Short name | T830 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 112.77 seconds |
| Started | Nov 22 01:46:20 PM PST 23 |
| Finished | Nov 22 01:48:14 PM PST 23 |
| Peak memory | 198908 kb |
| Host | smart-12c8ce45-84bf-40e0-bd3c-0cdf55e18b34 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=49550840012530104856344676592148586786741298654686787758374934902826298145753 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 298.uart_fifo_reset.49550840012530104856344676592148586786741298654686787758374934902826298145753 |
| Directory | /workspace/298.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/299.uart_fifo_reset.87189336088771597896961191947067633897063748077397709489527584302730320802461 |
| Short name | T762 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 113.04 seconds |
| Started | Nov 22 01:46:17 PM PST 23 |
| Finished | Nov 22 01:48:11 PM PST 23 |
| Peak memory | 198952 kb |
| Host | smart-54d80712-331f-4ae5-bc83-8542e0fd5ed0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=87189336088771597896961191947067633897063748077397709489527584302730320802461 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 299.uart_fifo_reset.87189336088771597896961191947067633897063748077397709489527584302730320802461 |
| Directory | /workspace/299.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/3.uart_alert_test.9593431546490821914377803153489356847264812832668314890149717139610628473193 |
| Short name | T1160 |
| Test name | |
| Test status | |
| Simulation time | 16368684 ps |
| CPU time | 0.54 seconds |
| Started | Nov 22 01:44:02 PM PST 23 |
| Finished | Nov 22 01:44:07 PM PST 23 |
| Peak memory | 194628 kb |
| Host | smart-6f5460ba-4098-42d0-8952-6fa632b42f6b |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9593431546490821914377803153489356847264812832668314890149717139610628473193 -assert nopostpro c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 3.uart_alert_test.9593431546490821914377803153489356847264812832668314890149717139610628473193 |
| Directory | /workspace/3.uart_alert_test/latest |
| Test location | /workspace/coverage/default/3.uart_fifo_full.106907822824421779297393337824571590344680635389014604232218675641898648885621 |
| Short name | T709 |
| Test name | |
| Test status | |
| Simulation time | 61777160308 ps |
| CPU time | 60.5 seconds |
| Started | Nov 22 01:44:14 PM PST 23 |
| Finished | Nov 22 01:45:18 PM PST 23 |
| Peak memory | 200020 kb |
| Host | smart-646f91b6-6aef-427e-9013-f05882eaf16d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=106907822824421779297393337824571590344680635389014604232218675641898648885621 -assert nopostproc +UVM_TESTNAME=uart_bas e_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 3.uart_fifo_full.106907822824421779297393337824571590344680635389014604232218675641898648885621 |
| Directory | /workspace/3.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/3.uart_fifo_overflow.7461399806927356970349366499611355404169992940719584338368252745364906416418 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 58551936110 ps |
| CPU time | 54.39 seconds |
| Started | Nov 22 01:44:00 PM PST 23 |
| Finished | Nov 22 01:44:58 PM PST 23 |
| Peak memory | 199712 kb |
| Host | smart-19978a94-d3fd-4e14-8cb9-e8039f8e75bf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=7461399806927356970349366499611355404169992940719584338368252745364906416418 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_overflow.7461399806927356970349366499611355404169992940719584338368252745364906416418 |
| Directory | /workspace/3.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/3.uart_fifo_reset.22066610711580923398766548811617563397660376392277988937221027252254079656790 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 113.56 seconds |
| Started | Nov 22 01:44:03 PM PST 23 |
| Finished | Nov 22 01:46:01 PM PST 23 |
| Peak memory | 198920 kb |
| Host | smart-9cf50a6b-776c-4357-b62a-6acc80798300 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=22066610711580923398766548811617563397660376392277988937221027252254079656790 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 3.uart_fifo_reset.22066610711580923398766548811617563397660376392277988937221027252254079656790 |
| Directory | /workspace/3.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/3.uart_intr.68900570285465296512122000403647687172607077482873520946796261961269334724434 |
| Short name | T1093 |
| Test name | |
| Test status | |
| Simulation time | 787145125175 ps |
| CPU time | 779.81 seconds |
| Started | Nov 22 01:43:49 PM PST 23 |
| Finished | Nov 22 01:56:52 PM PST 23 |
| Peak memory | 200136 kb |
| Host | smart-085e7d61-1544-4f4b-aa5f-dc00f6ff1de4 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68900570285465296512122000403647687172607077482873520946796261961269334724434 -assert nopost proc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 3.uart_intr.68900570285465296512122000403647687172607077482873520946796261961269334724434 |
| Directory | /workspace/3.uart_intr/latest |
| Test location | /workspace/coverage/default/3.uart_long_xfer_wo_dly.42100906253307957765373255310204604053482096387514110317614508800524905042451 |
| Short name | T1265 |
| Test name | |
| Test status | |
| Simulation time | 93387746707 ps |
| CPU time | 353.49 seconds |
| Started | Nov 22 01:43:53 PM PST 23 |
| Finished | Nov 22 01:49:50 PM PST 23 |
| Peak memory | 200024 kb |
| Host | smart-f9ab2166-dbba-4144-b94d-20e94102dcb0 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=42100906253307957765373255310204604053482096387514110317614508800524905042451 -assert nopostproc +UVM_TES TNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 3.uart_long_xfer_wo_dly.42100906253307957765373255310204604053482096387514110317614508800524905042451 |
| Directory | /workspace/3.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/3.uart_loopback.12583702911616444994920754518223940733219277696387094318439634869836707191648 |
| Short name | T1210 |
| Test name | |
| Test status | |
| Simulation time | 14572448663 ps |
| CPU time | 16.03 seconds |
| Started | Nov 22 01:43:51 PM PST 23 |
| Finished | Nov 22 01:44:09 PM PST 23 |
| Peak memory | 199944 kb |
| Host | smart-cf893841-86ef-46ab-8368-aff46b24f09c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=12583702911616444994920754518223940733219277696387094318439634869836707191648 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 3.uart_loopback.12583702911616444994920754518223940733219277696387094318439634869836707191648 |
| Directory | /workspace/3.uart_loopback/latest |
| Test location | /workspace/coverage/default/3.uart_noise_filter.66976609104077725702763214445786531032554308467713477995558668803161660468189 |
| Short name | T884 |
| Test name | |
| Test status | |
| Simulation time | 94501577082 ps |
| CPU time | 96.59 seconds |
| Started | Nov 22 01:44:04 PM PST 23 |
| Finished | Nov 22 01:45:45 PM PST 23 |
| Peak memory | 200192 kb |
| Host | smart-4f040c6f-d5f7-4f91-9468-7f1e2bcce820 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=66976609104077725702763214445786531032554308467713477995558668803161660468189 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_noise_filter.66976609104077725702763214445786531032554308467713477995558668803161660468189 |
| Directory | /workspace/3.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/3.uart_perf.25229064081069605659713580611353760947521160220141168008536502314807180092417 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 14098773881 ps |
| CPU time | 470.06 seconds |
| Started | Nov 22 01:44:04 PM PST 23 |
| Finished | Nov 22 01:51:58 PM PST 23 |
| Peak memory | 200152 kb |
| Host | smart-01c5a6eb-6a54-47cc-a9c0-109e3ccc42a2 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=25229064081069605659713580611353760947521160220141168008536502314807180092417 -assert nopostproc +UVM_TES TNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 3.uart_perf.25229064081069605659713580611353760947521160220141168008536502314807180092417 |
| Directory | /workspace/3.uart_perf/latest |
| Test location | /workspace/coverage/default/3.uart_rx_oversample.16918130485454484311209369507017586269135766277691621250458118049121100989382 |
| Short name | T1025 |
| Test name | |
| Test status | |
| Simulation time | 4370280281 ps |
| CPU time | 20.12 seconds |
| Started | Nov 22 01:43:55 PM PST 23 |
| Finished | Nov 22 01:44:19 PM PST 23 |
| Peak memory | 199000 kb |
| Host | smart-9fd84e13-db62-4d24-9957-7bf1d7e7655e |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=16918130485454484311209369507017586269135766277691621250458118049121100989382 -assert nopostproc +UVM_TES TNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 3.uart_rx_oversample.16918130485454484311209369507017586269135766277691621250458118049121100989382 |
| Directory | /workspace/3.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/3.uart_rx_parity_err.13953713661120445899814144653644753206619920630752499139322389303169059956008 |
| Short name | T942 |
| Test name | |
| Test status | |
| Simulation time | 36616611594 ps |
| CPU time | 37.6 seconds |
| Started | Nov 22 01:44:01 PM PST 23 |
| Finished | Nov 22 01:44:42 PM PST 23 |
| Peak memory | 200104 kb |
| Host | smart-5df04d0d-fc4f-4aae-9807-eab0c22b3464 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=13953713661120445899814144653644753206619920630752499139322389303169059956008 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 3.uart_rx_parity_err.13953713661120445899814144653644753206619920630752499139322389303169059956008 |
| Directory | /workspace/3.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/3.uart_rx_start_bit_filter.75072810832321584544441303425543878830478361159031096097350750797445266009037 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 4267638245 ps |
| CPU time | 5.1 seconds |
| Started | Nov 22 01:44:02 PM PST 23 |
| Finished | Nov 22 01:44:12 PM PST 23 |
| Peak memory | 196008 kb |
| Host | smart-64688c99-8ffc-40e8-9ea8-f85be03ff658 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=75072810832321584544441303425543878830478361159031096097350750797445266009037 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 3.uart_rx_start_bit_filter.75072810832321584544441303425543878830478361159031096097350750797445266009037 |
| Directory | /workspace/3.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/3.uart_sec_cm.10001269284301145750355935879725201891016977887834621435165095579029160963196 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 100582296 ps |
| CPU time | 0.9 seconds |
| Started | Nov 22 01:43:53 PM PST 23 |
| Finished | Nov 22 01:43:57 PM PST 23 |
| Peak memory | 218408 kb |
| Host | smart-fc4bbdc1-02c2-4a4e-a0cc-30b05ef95baa |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10001269284301145750355935879725201891016977887834621435165095579029160963196 -assert nopostpro c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 3.uart_sec_cm.10001269284301145750355935879725201891016977887834621435165095579029160963196 |
| Directory | /workspace/3.uart_sec_cm/latest |
| Test location | /workspace/coverage/default/3.uart_smoke.83335657840194691950644824945673356656361797078311882427721681907306228108992 |
| Short name | T1172 |
| Test name | |
| Test status | |
| Simulation time | 5759626309 ps |
| CPU time | 18.53 seconds |
| Started | Nov 22 01:43:53 PM PST 23 |
| Finished | Nov 22 01:44:15 PM PST 23 |
| Peak memory | 199620 kb |
| Host | smart-60095b90-3648-418d-aa60-525f2f01c3df |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=83335657840194691950644824945673356656361797078311882427721681907306228108992 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 3.uart_smoke.83335657840194691950644824945673356656361797078311882427721681907306228108992 |
| Directory | /workspace/3.uart_smoke/latest |
| Test location | /workspace/coverage/default/3.uart_stress_all.91275734125245018203410867148217161703396075330802665664343248996835278761228 |
| Short name | T806 |
| Test name | |
| Test status | |
| Simulation time | 43402307308 ps |
| CPU time | 56.91 seconds |
| Started | Nov 22 01:44:06 PM PST 23 |
| Finished | Nov 22 01:45:08 PM PST 23 |
| Peak memory | 200104 kb |
| Host | smart-d880b408-4bbe-413e-8c76-b441b47e5562 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91275734125245018203410867148217161703396075330802665664343248996835278761228 -assert nopos tproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 3.uart_stress_all.91275734125245018203410867148217161703396075330802665664343248996835278761228 |
| Directory | /workspace/3.uart_stress_all/latest |
| Test location | /workspace/coverage/default/3.uart_stress_all_with_rand_reset.85380631601597900823004510494183229065903705473049835457191788613332619704364 |
| Short name | T851 |
| Test name | |
| Test status | |
| Simulation time | 87476847566 ps |
| CPU time | 452.59 seconds |
| Started | Nov 22 01:43:54 PM PST 23 |
| Finished | Nov 22 01:51:30 PM PST 23 |
| Peak memory | 226124 kb |
| Host | smart-d7f34036-84d9-4a80-8c27-a9af408c9bc9 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85380631601597900823004510 494183229065903705473049835457191788613332619704364 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_stress_all_with_rand_reset.85380631601597 900823004510494183229065903705473049835457191788613332619704364 |
| Directory | /workspace/3.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/3.uart_tx_ovrd.86648426708279628326006707086161805000872624920878864521756790401492461441129 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 485186362 ps |
| CPU time | 1.26 seconds |
| Started | Nov 22 01:43:52 PM PST 23 |
| Finished | Nov 22 01:43:57 PM PST 23 |
| Peak memory | 197940 kb |
| Host | smart-d9290cb3-d52d-4ed4-8612-caa23cbf0ca6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=86648426708279628326006707086161805000872624920878864521756790401492461441129 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 3.uart_tx_ovrd.86648426708279628326006707086161805000872624920878864521756790401492461441129 |
| Directory | /workspace/3.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/3.uart_tx_rx.85419084244286424510952741310808062455643955457683498052963827754197426581048 |
| Short name | T865 |
| Test name | |
| Test status | |
| Simulation time | 57391945390 ps |
| CPU time | 63.32 seconds |
| Started | Nov 22 01:43:57 PM PST 23 |
| Finished | Nov 22 01:45:04 PM PST 23 |
| Peak memory | 200028 kb |
| Host | smart-893e2ca2-8f28-4c87-9755-1f631975970c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=85419084244286424510952741310808062455643955457683498052963827754197426581048 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 3.uart_tx_rx.85419084244286424510952741310808062455643955457683498052963827754197426581048 |
| Directory | /workspace/3.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/30.uart_alert_test.85375651964464094311215071156100469471335282789020772516320348236053821019089 |
| Short name | T1262 |
| Test name | |
| Test status | |
| Simulation time | 16368684 ps |
| CPU time | 0.56 seconds |
| Started | Nov 22 01:45:09 PM PST 23 |
| Finished | Nov 22 01:45:11 PM PST 23 |
| Peak memory | 194580 kb |
| Host | smart-863f288a-f3ec-4efd-a6ab-f20aa4dd0495 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85375651964464094311215071156100469471335282789020772516320348236053821019089 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 30.uart_alert_test.85375651964464094311215071156100469471335282789020772516320348236053821019089 |
| Directory | /workspace/30.uart_alert_test/latest |
| Test location | /workspace/coverage/default/30.uart_fifo_full.21724268583265374873698474376379507955968672626919969374573751956488633504839 |
| Short name | T1272 |
| Test name | |
| Test status | |
| Simulation time | 61777160308 ps |
| CPU time | 61.13 seconds |
| Started | Nov 22 01:44:48 PM PST 23 |
| Finished | Nov 22 01:45:52 PM PST 23 |
| Peak memory | 200128 kb |
| Host | smart-c97124de-7c26-4a1f-ab74-92c7bebee08d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=21724268583265374873698474376379507955968672626919969374573751956488633504839 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 30.uart_fifo_full.21724268583265374873698474376379507955968672626919969374573751956488633504839 |
| Directory | /workspace/30.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/30.uart_fifo_overflow.108857986808684755177470804874451724642504891612313794460937833534410926646417 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 58551936110 ps |
| CPU time | 54.93 seconds |
| Started | Nov 22 01:45:01 PM PST 23 |
| Finished | Nov 22 01:45:57 PM PST 23 |
| Peak memory | 199880 kb |
| Host | smart-ad2f861c-5eaa-4d48-bf18-40f66ffb73df |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=108857986808684755177470804874451724642504891612313794460937833534410926646417 -assert nopostproc +UVM_TESTNAME=uart_bas e_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 30.uart_fifo_overflow.108857986808684755177470804874451724642504891612313794460937833534410926646417 |
| Directory | /workspace/30.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/30.uart_fifo_reset.28419510914447446843783936967698864775183743404220771934549034054703562273294 |
| Short name | T858 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 114.43 seconds |
| Started | Nov 22 01:44:56 PM PST 23 |
| Finished | Nov 22 01:46:52 PM PST 23 |
| Peak memory | 198836 kb |
| Host | smart-2aac13ee-5cc6-4893-b003-00d93e4e24e1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=28419510914447446843783936967698864775183743404220771934549034054703562273294 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 30.uart_fifo_reset.28419510914447446843783936967698864775183743404220771934549034054703562273294 |
| Directory | /workspace/30.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/30.uart_intr.24146241603440820591924324626170306743904684818633080595828296213423344439630 |
| Short name | T767 |
| Test name | |
| Test status | |
| Simulation time | 787145125175 ps |
| CPU time | 785.81 seconds |
| Started | Nov 22 01:44:50 PM PST 23 |
| Finished | Nov 22 01:57:58 PM PST 23 |
| Peak memory | 200132 kb |
| Host | smart-7604f7d9-7594-488c-b966-7735bc16a1f0 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24146241603440820591924324626170306743904684818633080595828296213423344439630 -assert nopost proc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 30.uart_intr.24146241603440820591924324626170306743904684818633080595828296213423344439630 |
| Directory | /workspace/30.uart_intr/latest |
| Test location | /workspace/coverage/default/30.uart_long_xfer_wo_dly.56421905666014816451823028009248803728519357391984500996357872231198601992070 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 93387746707 ps |
| CPU time | 345.72 seconds |
| Started | Nov 22 01:44:58 PM PST 23 |
| Finished | Nov 22 01:50:45 PM PST 23 |
| Peak memory | 200124 kb |
| Host | smart-4f32fbf1-34f5-48fe-8a49-68a4e836b9fb |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=56421905666014816451823028009248803728519357391984500996357872231198601992070 -assert nopostproc +UVM_TES TNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 30.uart_long_xfer_wo_dly.56421905666014816451823028009248803728519357391984500996357872231198601992070 |
| Directory | /workspace/30.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/30.uart_loopback.59597060785137300055622330476817388309109292119613880754028627737230590733448 |
| Short name | T660 |
| Test name | |
| Test status | |
| Simulation time | 14572448663 ps |
| CPU time | 16.37 seconds |
| Started | Nov 22 01:44:50 PM PST 23 |
| Finished | Nov 22 01:45:08 PM PST 23 |
| Peak memory | 199996 kb |
| Host | smart-f944beee-d6d8-4911-9d05-8362cfbcf45a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=59597060785137300055622330476817388309109292119613880754028627737230590733448 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 30.uart_loopback.59597060785137300055622330476817388309109292119613880754028627737230590733448 |
| Directory | /workspace/30.uart_loopback/latest |
| Test location | /workspace/coverage/default/30.uart_noise_filter.92245283174714687994955649721221663810106502726273407731901773332801648614743 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 94501577082 ps |
| CPU time | 97.36 seconds |
| Started | Nov 22 01:44:52 PM PST 23 |
| Finished | Nov 22 01:46:31 PM PST 23 |
| Peak memory | 200236 kb |
| Host | smart-be2e31f2-e553-4e43-9f19-349277de176d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=92245283174714687994955649721221663810106502726273407731901773332801648614743 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_noise_filter.92245283174714687994955649721221663810106502726273407731901773332801648614743 |
| Directory | /workspace/30.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/30.uart_perf.31108144425701056780942014703837766183492769355666541212371506367149492280957 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 14098773881 ps |
| CPU time | 472.33 seconds |
| Started | Nov 22 01:44:52 PM PST 23 |
| Finished | Nov 22 01:52:46 PM PST 23 |
| Peak memory | 200008 kb |
| Host | smart-a9e723e3-4821-4010-8f50-534c1d024ed8 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=31108144425701056780942014703837766183492769355666541212371506367149492280957 -assert nopostproc +UVM_TES TNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 30.uart_perf.31108144425701056780942014703837766183492769355666541212371506367149492280957 |
| Directory | /workspace/30.uart_perf/latest |
| Test location | /workspace/coverage/default/30.uart_rx_oversample.67570925308713924542920489527751851979763049695271303586623148386382078111531 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 4370280281 ps |
| CPU time | 20.24 seconds |
| Started | Nov 22 01:44:45 PM PST 23 |
| Finished | Nov 22 01:45:08 PM PST 23 |
| Peak memory | 198976 kb |
| Host | smart-990ae011-cdc3-41bf-ad17-3bb321d1454b |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=67570925308713924542920489527751851979763049695271303586623148386382078111531 -assert nopostproc +UVM_TES TNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 30.uart_rx_oversample.67570925308713924542920489527751851979763049695271303586623148386382078111531 |
| Directory | /workspace/30.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/30.uart_rx_parity_err.7463361848489418307191371511709196837618227986608908381533517222651915235360 |
| Short name | T1248 |
| Test name | |
| Test status | |
| Simulation time | 36616611594 ps |
| CPU time | 38.03 seconds |
| Started | Nov 22 01:44:47 PM PST 23 |
| Finished | Nov 22 01:45:28 PM PST 23 |
| Peak memory | 200024 kb |
| Host | smart-ee7b8724-65d0-46f6-83e9-01d48d112ba6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=7463361848489418307191371511709196837618227986608908381533517222651915235360 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_parity_err.7463361848489418307191371511709196837618227986608908381533517222651915235360 |
| Directory | /workspace/30.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/30.uart_rx_start_bit_filter.78529302694050751383490675460796895136646004516158896723587848698169097917632 |
| Short name | T1169 |
| Test name | |
| Test status | |
| Simulation time | 4267638245 ps |
| CPU time | 4.7 seconds |
| Started | Nov 22 01:45:05 PM PST 23 |
| Finished | Nov 22 01:45:11 PM PST 23 |
| Peak memory | 195964 kb |
| Host | smart-fc6342e7-8113-4949-8ad7-c26713c3cc58 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=78529302694050751383490675460796895136646004516158896723587848698169097917632 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 30.uart_rx_start_bit_filter.78529302694050751383490675460796895136646004516158896723587848698169097917632 |
| Directory | /workspace/30.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/30.uart_smoke.59314104608179048887252625491129192281153125967763486978559852978688306687179 |
| Short name | T743 |
| Test name | |
| Test status | |
| Simulation time | 5759626309 ps |
| CPU time | 18.21 seconds |
| Started | Nov 22 01:44:51 PM PST 23 |
| Finished | Nov 22 01:45:11 PM PST 23 |
| Peak memory | 199592 kb |
| Host | smart-837ddea1-04ef-4353-aab0-08551378d48b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=59314104608179048887252625491129192281153125967763486978559852978688306687179 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 30.uart_smoke.59314104608179048887252625491129192281153125967763486978559852978688306687179 |
| Directory | /workspace/30.uart_smoke/latest |
| Test location | /workspace/coverage/default/30.uart_stress_all.2727372125464980926170774960125694317500687620112145339497715272969418746771 |
| Short name | T993 |
| Test name | |
| Test status | |
| Simulation time | 43402307308 ps |
| CPU time | 56.44 seconds |
| Started | Nov 22 01:45:25 PM PST 23 |
| Finished | Nov 22 01:46:22 PM PST 23 |
| Peak memory | 200108 kb |
| Host | smart-a8c8c8f9-c3db-4140-869c-930b40b77241 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727372125464980926170774960125694317500687620112145339497715272969418746771 -assert nopost proc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 30.uart_stress_all.2727372125464980926170774960125694317500687620112145339497715272969418746771 |
| Directory | /workspace/30.uart_stress_all/latest |
| Test location | /workspace/coverage/default/30.uart_stress_all_with_rand_reset.56166243414525008838584754980560608758014272464886948828590674632891020985198 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 87476847566 ps |
| CPU time | 471.23 seconds |
| Started | Nov 22 01:44:50 PM PST 23 |
| Finished | Nov 22 01:52:43 PM PST 23 |
| Peak memory | 226228 kb |
| Host | smart-2ce5297d-f515-4abe-8363-36ae88e2894c |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56166243414525008838584754 980560608758014272464886948828590674632891020985198 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_stress_all_with_rand_reset.5616624341452 5008838584754980560608758014272464886948828590674632891020985198 |
| Directory | /workspace/30.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/30.uart_tx_ovrd.72932346387562321675035278417144458100573002631522953807899046796951819380194 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 485186362 ps |
| CPU time | 1.27 seconds |
| Started | Nov 22 01:45:07 PM PST 23 |
| Finished | Nov 22 01:45:10 PM PST 23 |
| Peak memory | 197916 kb |
| Host | smart-33c0b182-3be7-4857-b7a8-351105f65d89 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=72932346387562321675035278417144458100573002631522953807899046796951819380194 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 30.uart_tx_ovrd.72932346387562321675035278417144458100573002631522953807899046796951819380194 |
| Directory | /workspace/30.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/30.uart_tx_rx.43050909625556533020081238023212338143877832041936938462424034287954558908651 |
| Short name | T684 |
| Test name | |
| Test status | |
| Simulation time | 57391945390 ps |
| CPU time | 63.69 seconds |
| Started | Nov 22 01:44:49 PM PST 23 |
| Finished | Nov 22 01:45:55 PM PST 23 |
| Peak memory | 200076 kb |
| Host | smart-f3da2745-209c-4aa7-8f33-090b29530d73 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=43050909625556533020081238023212338143877832041936938462424034287954558908651 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 30.uart_tx_rx.43050909625556533020081238023212338143877832041936938462424034287954558908651 |
| Directory | /workspace/30.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/31.uart_alert_test.74063833637253542678447730445979054656414690159727967680659857695854119494464 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 16368684 ps |
| CPU time | 0.53 seconds |
| Started | Nov 22 01:45:40 PM PST 23 |
| Finished | Nov 22 01:45:42 PM PST 23 |
| Peak memory | 194592 kb |
| Host | smart-41b15de2-c7ca-4c42-8ddd-e3ca98370664 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74063833637253542678447730445979054656414690159727967680659857695854119494464 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 31.uart_alert_test.74063833637253542678447730445979054656414690159727967680659857695854119494464 |
| Directory | /workspace/31.uart_alert_test/latest |
| Test location | /workspace/coverage/default/31.uart_fifo_full.67383753427922087718346238973145946644841617158400046056583349850798339362302 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 61777160308 ps |
| CPU time | 61.01 seconds |
| Started | Nov 22 01:45:27 PM PST 23 |
| Finished | Nov 22 01:46:29 PM PST 23 |
| Peak memory | 200072 kb |
| Host | smart-4ea57f7d-b5d5-4826-9031-5931fb90555d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=67383753427922087718346238973145946644841617158400046056583349850798339362302 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 31.uart_fifo_full.67383753427922087718346238973145946644841617158400046056583349850798339362302 |
| Directory | /workspace/31.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/31.uart_fifo_overflow.12215690265126975003755325524756103252593247667173283934563138582220336414377 |
| Short name | T857 |
| Test name | |
| Test status | |
| Simulation time | 58551936110 ps |
| CPU time | 54.95 seconds |
| Started | Nov 22 01:44:55 PM PST 23 |
| Finished | Nov 22 01:45:51 PM PST 23 |
| Peak memory | 199872 kb |
| Host | smart-05de27a8-0fc6-4e46-8f2e-790f31a585b0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=12215690265126975003755325524756103252593247667173283934563138582220336414377 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 31.uart_fifo_overflow.12215690265126975003755325524756103252593247667173283934563138582220336414377 |
| Directory | /workspace/31.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/31.uart_fifo_reset.50599591275714459270004728577927302720951029748416467899603306993561281444622 |
| Short name | T658 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 113.43 seconds |
| Started | Nov 22 01:45:24 PM PST 23 |
| Finished | Nov 22 01:47:19 PM PST 23 |
| Peak memory | 198872 kb |
| Host | smart-d385f4e8-e02e-49d0-bbf1-a83b030830e9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=50599591275714459270004728577927302720951029748416467899603306993561281444622 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 31.uart_fifo_reset.50599591275714459270004728577927302720951029748416467899603306993561281444622 |
| Directory | /workspace/31.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/31.uart_intr.99912535438684169294151004422676537800936386499078649517883461027445100997009 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 787145125175 ps |
| CPU time | 784.03 seconds |
| Started | Nov 22 01:45:29 PM PST 23 |
| Finished | Nov 22 01:58:35 PM PST 23 |
| Peak memory | 200136 kb |
| Host | smart-acd48b3a-3a54-4940-a2ed-5eb9c34c290d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99912535438684169294151004422676537800936386499078649517883461027445100997009 -assert nopost proc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 31.uart_intr.99912535438684169294151004422676537800936386499078649517883461027445100997009 |
| Directory | /workspace/31.uart_intr/latest |
| Test location | /workspace/coverage/default/31.uart_long_xfer_wo_dly.6693998684773341147758400134627277268192494244527925928121062326248710646273 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 93387746707 ps |
| CPU time | 347.48 seconds |
| Started | Nov 22 01:45:30 PM PST 23 |
| Finished | Nov 22 01:51:19 PM PST 23 |
| Peak memory | 200040 kb |
| Host | smart-0d1f349e-3a69-4649-b0c0-9a39c17a4ce5 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=6693998684773341147758400134627277268192494244527925928121062326248710646273 -assert nopostproc +UVM_TEST NAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_long_xfer_wo_dly.6693998684773341147758400134627277268192494244527925928121062326248710646273 |
| Directory | /workspace/31.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/31.uart_loopback.38426541184186395111184791155161414509971271620075461313005194536179539324859 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 14572448663 ps |
| CPU time | 16.15 seconds |
| Started | Nov 22 01:45:26 PM PST 23 |
| Finished | Nov 22 01:45:43 PM PST 23 |
| Peak memory | 200016 kb |
| Host | smart-8fb9c098-ccb4-4273-bd35-17b164177afc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=38426541184186395111184791155161414509971271620075461313005194536179539324859 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 31.uart_loopback.38426541184186395111184791155161414509971271620075461313005194536179539324859 |
| Directory | /workspace/31.uart_loopback/latest |
| Test location | /workspace/coverage/default/31.uart_noise_filter.111960162864259877736650337418326936280674850623049935409112175932219674470973 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 94501577082 ps |
| CPU time | 97.01 seconds |
| Started | Nov 22 01:45:11 PM PST 23 |
| Finished | Nov 22 01:46:49 PM PST 23 |
| Peak memory | 200260 kb |
| Host | smart-f64cf18c-6149-4725-a93e-c92ac6081a5a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=111960162864259877736650337418326936280674850623049935409112175932219674470973 -assert nopostproc +UVM_TESTNAME=uart_bas e_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 31.uart_noise_filter.111960162864259877736650337418326936280674850623049935409112175932219674470973 |
| Directory | /workspace/31.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/31.uart_perf.58767468165504538363010967105518946461598832176057478261051708647404425154057 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 14098773881 ps |
| CPU time | 470.48 seconds |
| Started | Nov 22 01:45:43 PM PST 23 |
| Finished | Nov 22 01:53:36 PM PST 23 |
| Peak memory | 200152 kb |
| Host | smart-2d2218ad-7d6f-4cd5-a9c2-dc12cdd560f4 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=58767468165504538363010967105518946461598832176057478261051708647404425154057 -assert nopostproc +UVM_TES TNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 31.uart_perf.58767468165504538363010967105518946461598832176057478261051708647404425154057 |
| Directory | /workspace/31.uart_perf/latest |
| Test location | /workspace/coverage/default/31.uart_rx_oversample.99147348344379308501669823547912331634612827303566841881367834471372081610794 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 4370280281 ps |
| CPU time | 19.84 seconds |
| Started | Nov 22 01:45:26 PM PST 23 |
| Finished | Nov 22 01:45:47 PM PST 23 |
| Peak memory | 198968 kb |
| Host | smart-2e18ae7f-99e7-49ba-bf34-a3157080a6f7 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=99147348344379308501669823547912331634612827303566841881367834471372081610794 -assert nopostproc +UVM_TES TNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 31.uart_rx_oversample.99147348344379308501669823547912331634612827303566841881367834471372081610794 |
| Directory | /workspace/31.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/31.uart_rx_parity_err.51157477722485154336003475380740333107974419210314891361898622101102348995050 |
| Short name | T876 |
| Test name | |
| Test status | |
| Simulation time | 36616611594 ps |
| CPU time | 38.25 seconds |
| Started | Nov 22 01:45:23 PM PST 23 |
| Finished | Nov 22 01:46:02 PM PST 23 |
| Peak memory | 200040 kb |
| Host | smart-6c9ad7f3-2696-4c56-8b66-c8a4d843d3b6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=51157477722485154336003475380740333107974419210314891361898622101102348995050 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 31.uart_rx_parity_err.51157477722485154336003475380740333107974419210314891361898622101102348995050 |
| Directory | /workspace/31.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/31.uart_rx_start_bit_filter.91847350782846874542704468817016282301464293261130497834685350608353340175954 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 4267638245 ps |
| CPU time | 4.67 seconds |
| Started | Nov 22 01:45:28 PM PST 23 |
| Finished | Nov 22 01:45:35 PM PST 23 |
| Peak memory | 196048 kb |
| Host | smart-fdce90e2-4182-439d-b5a7-874f78cfc3ed |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=91847350782846874542704468817016282301464293261130497834685350608353340175954 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 31.uart_rx_start_bit_filter.91847350782846874542704468817016282301464293261130497834685350608353340175954 |
| Directory | /workspace/31.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/31.uart_smoke.92893199872535478767175242450476035251142240672119949901270238436272237731003 |
| Short name | T916 |
| Test name | |
| Test status | |
| Simulation time | 5759626309 ps |
| CPU time | 18.77 seconds |
| Started | Nov 22 01:45:02 PM PST 23 |
| Finished | Nov 22 01:45:22 PM PST 23 |
| Peak memory | 199636 kb |
| Host | smart-1d505611-aec4-41b0-8b9a-128d4cf6d2b4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=92893199872535478767175242450476035251142240672119949901270238436272237731003 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 31.uart_smoke.92893199872535478767175242450476035251142240672119949901270238436272237731003 |
| Directory | /workspace/31.uart_smoke/latest |
| Test location | /workspace/coverage/default/31.uart_stress_all.66402836888775345362073527148960230227722435304340837379890550105975074440974 |
| Short name | T669 |
| Test name | |
| Test status | |
| Simulation time | 43402307308 ps |
| CPU time | 58.28 seconds |
| Started | Nov 22 01:45:49 PM PST 23 |
| Finished | Nov 22 01:46:49 PM PST 23 |
| Peak memory | 200012 kb |
| Host | smart-7566ffbd-9859-400e-ab23-4bfe5960d7d2 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66402836888775345362073527148960230227722435304340837379890550105975074440974 -assert nopos tproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 31.uart_stress_all.66402836888775345362073527148960230227722435304340837379890550105975074440974 |
| Directory | /workspace/31.uart_stress_all/latest |
| Test location | /workspace/coverage/default/31.uart_stress_all_with_rand_reset.109733104998180281532578392948954027705572210594597885185514980548757529165488 |
| Short name | T1195 |
| Test name | |
| Test status | |
| Simulation time | 87476847566 ps |
| CPU time | 476.58 seconds |
| Started | Nov 22 01:45:20 PM PST 23 |
| Finished | Nov 22 01:53:18 PM PST 23 |
| Peak memory | 226192 kb |
| Host | smart-226e345e-7ca7-4795-8923-c0d34ec2cfe8 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10973310499818028153257839 2948954027705572210594597885185514980548757529165488 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_stress_all_with_rand_reset.109733104998 180281532578392948954027705572210594597885185514980548757529165488 |
| Directory | /workspace/31.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/31.uart_tx_ovrd.79070340385756594926043892061840871635756193816143140674105929351439387310127 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 485186362 ps |
| CPU time | 1.25 seconds |
| Started | Nov 22 01:45:40 PM PST 23 |
| Finished | Nov 22 01:45:43 PM PST 23 |
| Peak memory | 197900 kb |
| Host | smart-da5a24c3-604b-4465-86fe-d719e146b94c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=79070340385756594926043892061840871635756193816143140674105929351439387310127 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 31.uart_tx_ovrd.79070340385756594926043892061840871635756193816143140674105929351439387310127 |
| Directory | /workspace/31.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/31.uart_tx_rx.24946200611964630580267432863909758927822280358647435900188032342807488304128 |
| Short name | T808 |
| Test name | |
| Test status | |
| Simulation time | 57391945390 ps |
| CPU time | 63.87 seconds |
| Started | Nov 22 01:45:28 PM PST 23 |
| Finished | Nov 22 01:46:34 PM PST 23 |
| Peak memory | 200140 kb |
| Host | smart-5c7311ed-9e9c-493d-916c-5ce4e126331d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=24946200611964630580267432863909758927822280358647435900188032342807488304128 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 31.uart_tx_rx.24946200611964630580267432863909758927822280358647435900188032342807488304128 |
| Directory | /workspace/31.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/32.uart_alert_test.48273134304215704754424349380802351198812749886294535899150112404683585138828 |
| Short name | T1089 |
| Test name | |
| Test status | |
| Simulation time | 16368684 ps |
| CPU time | 0.53 seconds |
| Started | Nov 22 01:44:51 PM PST 23 |
| Finished | Nov 22 01:44:53 PM PST 23 |
| Peak memory | 194636 kb |
| Host | smart-25679d2f-582d-4e92-8637-28c18117531f |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48273134304215704754424349380802351198812749886294535899150112404683585138828 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 32.uart_alert_test.48273134304215704754424349380802351198812749886294535899150112404683585138828 |
| Directory | /workspace/32.uart_alert_test/latest |
| Test location | /workspace/coverage/default/32.uart_fifo_full.36071034024345844894514427634590988249296657447188633608149631542269555915894 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 61777160308 ps |
| CPU time | 62.05 seconds |
| Started | Nov 22 01:45:46 PM PST 23 |
| Finished | Nov 22 01:46:51 PM PST 23 |
| Peak memory | 199956 kb |
| Host | smart-2220a608-86b2-4a48-9111-2ad00918f696 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=36071034024345844894514427634590988249296657447188633608149631542269555915894 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 32.uart_fifo_full.36071034024345844894514427634590988249296657447188633608149631542269555915894 |
| Directory | /workspace/32.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/32.uart_fifo_overflow.87689635459590202449650970135238379419294067764693254114761840132667781372211 |
| Short name | T833 |
| Test name | |
| Test status | |
| Simulation time | 58551936110 ps |
| CPU time | 54.68 seconds |
| Started | Nov 22 01:45:43 PM PST 23 |
| Finished | Nov 22 01:46:39 PM PST 23 |
| Peak memory | 199856 kb |
| Host | smart-e2be266d-fb29-4040-ad03-8e940b489a89 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=87689635459590202449650970135238379419294067764693254114761840132667781372211 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 32.uart_fifo_overflow.87689635459590202449650970135238379419294067764693254114761840132667781372211 |
| Directory | /workspace/32.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/32.uart_fifo_reset.26759116783370688276239337303081932519651137046944856559856978318495475693094 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 113.36 seconds |
| Started | Nov 22 01:45:48 PM PST 23 |
| Finished | Nov 22 01:47:43 PM PST 23 |
| Peak memory | 198936 kb |
| Host | smart-3c3e211a-e2b3-4552-adc6-3ebaddaae3dc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=26759116783370688276239337303081932519651137046944856559856978318495475693094 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 32.uart_fifo_reset.26759116783370688276239337303081932519651137046944856559856978318495475693094 |
| Directory | /workspace/32.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/32.uart_intr.85289793144313500395541949894730452842216936470382436833309101452235954901525 |
| Short name | T1157 |
| Test name | |
| Test status | |
| Simulation time | 787145125175 ps |
| CPU time | 782.38 seconds |
| Started | Nov 22 01:44:44 PM PST 23 |
| Finished | Nov 22 01:57:48 PM PST 23 |
| Peak memory | 200080 kb |
| Host | smart-d7a9218f-07f2-4da9-94c4-40c722a7ae33 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85289793144313500395541949894730452842216936470382436833309101452235954901525 -assert nopost proc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 32.uart_intr.85289793144313500395541949894730452842216936470382436833309101452235954901525 |
| Directory | /workspace/32.uart_intr/latest |
| Test location | /workspace/coverage/default/32.uart_long_xfer_wo_dly.105917637046603185190803848753771948607494464199485825464835438518593594647965 |
| Short name | T1145 |
| Test name | |
| Test status | |
| Simulation time | 93387746707 ps |
| CPU time | 334.64 seconds |
| Started | Nov 22 01:44:47 PM PST 23 |
| Finished | Nov 22 01:50:24 PM PST 23 |
| Peak memory | 200008 kb |
| Host | smart-064822c5-a938-4e67-853d-56ed3cf8f088 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=105917637046603185190803848753771948607494464199485825464835438518593594647965 -assert nopostproc +UVM_TE STNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 32.uart_long_xfer_wo_dly.105917637046603185190803848753771948607494464199485825464835438518593594647965 |
| Directory | /workspace/32.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/32.uart_loopback.7187236439697921088983091307328851690124873067657252968080567295668363471157 |
| Short name | T864 |
| Test name | |
| Test status | |
| Simulation time | 14572448663 ps |
| CPU time | 15.93 seconds |
| Started | Nov 22 01:44:49 PM PST 23 |
| Finished | Nov 22 01:45:08 PM PST 23 |
| Peak memory | 199872 kb |
| Host | smart-bd18ffe5-f2a0-4283-9929-3abbf094074c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=7187236439697921088983091307328851690124873067657252968080567295668363471157 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 32.uart_loopback.7187236439697921088983091307328851690124873067657252968080567295668363471157 |
| Directory | /workspace/32.uart_loopback/latest |
| Test location | /workspace/coverage/default/32.uart_noise_filter.89442649612841554767192003883088247069915310978496098733182680684036788983755 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 94501577082 ps |
| CPU time | 97.13 seconds |
| Started | Nov 22 01:45:54 PM PST 23 |
| Finished | Nov 22 01:47:34 PM PST 23 |
| Peak memory | 200176 kb |
| Host | smart-11a8c938-d8da-4daa-b8e7-6809297076cd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=89442649612841554767192003883088247069915310978496098733182680684036788983755 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_noise_filter.89442649612841554767192003883088247069915310978496098733182680684036788983755 |
| Directory | /workspace/32.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/32.uart_perf.85142147338036632345051386177304371500546454496341073881010289061582823212606 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 14098773881 ps |
| CPU time | 474.62 seconds |
| Started | Nov 22 01:44:52 PM PST 23 |
| Finished | Nov 22 01:52:49 PM PST 23 |
| Peak memory | 200228 kb |
| Host | smart-e44585e7-6c87-45b7-9439-d3de3d177875 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=85142147338036632345051386177304371500546454496341073881010289061582823212606 -assert nopostproc +UVM_TES TNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 32.uart_perf.85142147338036632345051386177304371500546454496341073881010289061582823212606 |
| Directory | /workspace/32.uart_perf/latest |
| Test location | /workspace/coverage/default/32.uart_rx_oversample.191358865463706490286067776290673816452802542810051512554863633327458335070 |
| Short name | T1253 |
| Test name | |
| Test status | |
| Simulation time | 4370280281 ps |
| CPU time | 19.87 seconds |
| Started | Nov 22 01:44:44 PM PST 23 |
| Finished | Nov 22 01:45:06 PM PST 23 |
| Peak memory | 198968 kb |
| Host | smart-d497dde2-2ca1-44c0-83d2-c7363d30f27c |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=191358865463706490286067776290673816452802542810051512554863633327458335070 -assert nopostproc +UVM_TESTN AME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 32.uart_rx_oversample.191358865463706490286067776290673816452802542810051512554863633327458335070 |
| Directory | /workspace/32.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/32.uart_rx_parity_err.94586336891197306825538430480670839050003693315103211286138949247550807366978 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 36616611594 ps |
| CPU time | 38.01 seconds |
| Started | Nov 22 01:44:53 PM PST 23 |
| Finished | Nov 22 01:45:32 PM PST 23 |
| Peak memory | 200188 kb |
| Host | smart-0ec4f8cd-4b77-4ff4-8269-42d120bacaf1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=94586336891197306825538430480670839050003693315103211286138949247550807366978 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 32.uart_rx_parity_err.94586336891197306825538430480670839050003693315103211286138949247550807366978 |
| Directory | /workspace/32.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/32.uart_rx_start_bit_filter.81490031698949981550488168351828845695251865011806067591302521527037751630726 |
| Short name | T1211 |
| Test name | |
| Test status | |
| Simulation time | 4267638245 ps |
| CPU time | 4.7 seconds |
| Started | Nov 22 01:44:52 PM PST 23 |
| Finished | Nov 22 01:44:58 PM PST 23 |
| Peak memory | 196012 kb |
| Host | smart-02010142-1b8f-4323-853c-2fc513a7a126 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=81490031698949981550488168351828845695251865011806067591302521527037751630726 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 32.uart_rx_start_bit_filter.81490031698949981550488168351828845695251865011806067591302521527037751630726 |
| Directory | /workspace/32.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/32.uart_smoke.98803447004605748814597659493404302206257374320021761192672663933388529119466 |
| Short name | T721 |
| Test name | |
| Test status | |
| Simulation time | 5759626309 ps |
| CPU time | 18.54 seconds |
| Started | Nov 22 01:45:40 PM PST 23 |
| Finished | Nov 22 01:46:01 PM PST 23 |
| Peak memory | 199656 kb |
| Host | smart-3a79dbb8-4e77-4d89-ba53-f8653a6fd5b0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=98803447004605748814597659493404302206257374320021761192672663933388529119466 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 32.uart_smoke.98803447004605748814597659493404302206257374320021761192672663933388529119466 |
| Directory | /workspace/32.uart_smoke/latest |
| Test location | /workspace/coverage/default/32.uart_stress_all.55032516831056921538746220639255436873297066050006313390171030605670580925703 |
| Short name | T1121 |
| Test name | |
| Test status | |
| Simulation time | 43402307308 ps |
| CPU time | 56.4 seconds |
| Started | Nov 22 01:44:44 PM PST 23 |
| Finished | Nov 22 01:45:42 PM PST 23 |
| Peak memory | 200080 kb |
| Host | smart-75d714c9-1cf3-4c8b-8d98-6bb646387b01 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55032516831056921538746220639255436873297066050006313390171030605670580925703 -assert nopos tproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 32.uart_stress_all.55032516831056921538746220639255436873297066050006313390171030605670580925703 |
| Directory | /workspace/32.uart_stress_all/latest |
| Test location | /workspace/coverage/default/32.uart_stress_all_with_rand_reset.67656825609412775939333272447868184890613725405550955902344410196007934653479 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 87476847566 ps |
| CPU time | 460.99 seconds |
| Started | Nov 22 01:44:53 PM PST 23 |
| Finished | Nov 22 01:52:35 PM PST 23 |
| Peak memory | 226212 kb |
| Host | smart-4c5a7738-968b-40e5-a538-6db028d73477 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67656825609412775939333272 447868184890613725405550955902344410196007934653479 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_stress_all_with_rand_reset.6765682560941 2775939333272447868184890613725405550955902344410196007934653479 |
| Directory | /workspace/32.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/32.uart_tx_ovrd.43694137140478166603685660505197168256586584818527978006460965206270420544168 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 485186362 ps |
| CPU time | 1.24 seconds |
| Started | Nov 22 01:44:50 PM PST 23 |
| Finished | Nov 22 01:44:53 PM PST 23 |
| Peak memory | 197900 kb |
| Host | smart-31e812cf-b788-4b18-b540-17ebca345e17 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=43694137140478166603685660505197168256586584818527978006460965206270420544168 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 32.uart_tx_ovrd.43694137140478166603685660505197168256586584818527978006460965206270420544168 |
| Directory | /workspace/32.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/32.uart_tx_rx.23304862127773254982590216704407163223110700429716682286272292785682349444140 |
| Short name | T954 |
| Test name | |
| Test status | |
| Simulation time | 57391945390 ps |
| CPU time | 63.84 seconds |
| Started | Nov 22 01:45:33 PM PST 23 |
| Finished | Nov 22 01:46:43 PM PST 23 |
| Peak memory | 200072 kb |
| Host | smart-703dd799-a1be-41f8-8bb9-a38395795057 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=23304862127773254982590216704407163223110700429716682286272292785682349444140 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 32.uart_tx_rx.23304862127773254982590216704407163223110700429716682286272292785682349444140 |
| Directory | /workspace/32.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/33.uart_alert_test.26497850535145724403340142676375710501925005077416384959820843523744289204726 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 16368684 ps |
| CPU time | 0.54 seconds |
| Started | Nov 22 01:44:49 PM PST 23 |
| Finished | Nov 22 01:44:52 PM PST 23 |
| Peak memory | 194624 kb |
| Host | smart-14a80110-6032-4c50-a515-55ea43b88cc5 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26497850535145724403340142676375710501925005077416384959820843523744289204726 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 33.uart_alert_test.26497850535145724403340142676375710501925005077416384959820843523744289204726 |
| Directory | /workspace/33.uart_alert_test/latest |
| Test location | /workspace/coverage/default/33.uart_fifo_full.112725702845747356446611127774196038133482481250612779853166323596015902441382 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 61777160308 ps |
| CPU time | 61.03 seconds |
| Started | Nov 22 01:44:51 PM PST 23 |
| Finished | Nov 22 01:45:54 PM PST 23 |
| Peak memory | 199992 kb |
| Host | smart-6c8493b3-72b5-40ec-9295-71c05931fdaf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=112725702845747356446611127774196038133482481250612779853166323596015902441382 -assert nopostproc +UVM_TESTNAME=uart_bas e_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 33.uart_fifo_full.112725702845747356446611127774196038133482481250612779853166323596015902441382 |
| Directory | /workspace/33.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/33.uart_fifo_overflow.10069135026269198451274447926287795017259530066916439433953795391541026676529 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 58551936110 ps |
| CPU time | 54.6 seconds |
| Started | Nov 22 01:45:03 PM PST 23 |
| Finished | Nov 22 01:45:58 PM PST 23 |
| Peak memory | 199892 kb |
| Host | smart-2f3730b2-5fd9-4e64-bf50-93c397818341 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=10069135026269198451274447926287795017259530066916439433953795391541026676529 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 33.uart_fifo_overflow.10069135026269198451274447926287795017259530066916439433953795391541026676529 |
| Directory | /workspace/33.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/33.uart_fifo_reset.11589587655469218991858774395725837452694093096974600775131977460550853615255 |
| Short name | T1076 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 112.93 seconds |
| Started | Nov 22 01:45:03 PM PST 23 |
| Finished | Nov 22 01:46:56 PM PST 23 |
| Peak memory | 198932 kb |
| Host | smart-96b5f2f7-8730-4627-89e4-c22e697e8eb4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=11589587655469218991858774395725837452694093096974600775131977460550853615255 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 33.uart_fifo_reset.11589587655469218991858774395725837452694093096974600775131977460550853615255 |
| Directory | /workspace/33.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/33.uart_intr.105135958458535625940587409576607452097512582563875676657770376153701459170778 |
| Short name | T677 |
| Test name | |
| Test status | |
| Simulation time | 787145125175 ps |
| CPU time | 784.23 seconds |
| Started | Nov 22 01:44:49 PM PST 23 |
| Finished | Nov 22 01:57:56 PM PST 23 |
| Peak memory | 200084 kb |
| Host | smart-27c99395-794d-42e7-ac02-a61b6e93aef6 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105135958458535625940587409576607452097512582563875676657770376153701459170778 -assert nopos tproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 33.uart_intr.105135958458535625940587409576607452097512582563875676657770376153701459170778 |
| Directory | /workspace/33.uart_intr/latest |
| Test location | /workspace/coverage/default/33.uart_long_xfer_wo_dly.16170438877734699940334195848386847268188122355215679287230176235479867311047 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 93387746707 ps |
| CPU time | 365.95 seconds |
| Started | Nov 22 01:44:50 PM PST 23 |
| Finished | Nov 22 01:50:58 PM PST 23 |
| Peak memory | 200084 kb |
| Host | smart-f9e50923-9318-484b-afba-45a9d558370c |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=16170438877734699940334195848386847268188122355215679287230176235479867311047 -assert nopostproc +UVM_TES TNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 33.uart_long_xfer_wo_dly.16170438877734699940334195848386847268188122355215679287230176235479867311047 |
| Directory | /workspace/33.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/33.uart_loopback.100776023571605084380184100614295622917755919785136487699853480979968969491358 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 14572448663 ps |
| CPU time | 16.5 seconds |
| Started | Nov 22 01:44:53 PM PST 23 |
| Finished | Nov 22 01:45:12 PM PST 23 |
| Peak memory | 199996 kb |
| Host | smart-03cafb66-2b2f-45cf-8d1d-1f6faf7c6229 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=100776023571605084380184100614295622917755919785136487699853480979968969491358 -assert nopostproc +UVM_TESTNAME=uart_bas e_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 33.uart_loopback.100776023571605084380184100614295622917755919785136487699853480979968969491358 |
| Directory | /workspace/33.uart_loopback/latest |
| Test location | /workspace/coverage/default/33.uart_noise_filter.83883841170576587199580164233503977788113774161081562545881129732275251309762 |
| Short name | T769 |
| Test name | |
| Test status | |
| Simulation time | 94501577082 ps |
| CPU time | 97.54 seconds |
| Started | Nov 22 01:45:04 PM PST 23 |
| Finished | Nov 22 01:46:43 PM PST 23 |
| Peak memory | 200272 kb |
| Host | smart-1c02e2ef-3dc6-4912-91d9-e613b9c85e59 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=83883841170576587199580164233503977788113774161081562545881129732275251309762 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_noise_filter.83883841170576587199580164233503977788113774161081562545881129732275251309762 |
| Directory | /workspace/33.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/33.uart_perf.84846685357507603144217700748698966660243766261922124707945915090186572002149 |
| Short name | T1014 |
| Test name | |
| Test status | |
| Simulation time | 14098773881 ps |
| CPU time | 463.79 seconds |
| Started | Nov 22 01:44:46 PM PST 23 |
| Finished | Nov 22 01:52:33 PM PST 23 |
| Peak memory | 200000 kb |
| Host | smart-c780d3c8-1aa8-4b38-b599-5ab2e994aabe |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=84846685357507603144217700748698966660243766261922124707945915090186572002149 -assert nopostproc +UVM_TES TNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 33.uart_perf.84846685357507603144217700748698966660243766261922124707945915090186572002149 |
| Directory | /workspace/33.uart_perf/latest |
| Test location | /workspace/coverage/default/33.uart_rx_oversample.59382720847421330552493761394461979122340449117258707333977649248267980997833 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 4370280281 ps |
| CPU time | 19.7 seconds |
| Started | Nov 22 01:44:54 PM PST 23 |
| Finished | Nov 22 01:45:15 PM PST 23 |
| Peak memory | 198900 kb |
| Host | smart-12c2f08b-178e-43cc-8b28-a757d60bb878 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=59382720847421330552493761394461979122340449117258707333977649248267980997833 -assert nopostproc +UVM_TES TNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 33.uart_rx_oversample.59382720847421330552493761394461979122340449117258707333977649248267980997833 |
| Directory | /workspace/33.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/33.uart_rx_parity_err.77237537598985039206387313025385810451692770599313443988363034131825120506547 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 36616611594 ps |
| CPU time | 37.73 seconds |
| Started | Nov 22 01:44:53 PM PST 23 |
| Finished | Nov 22 01:45:32 PM PST 23 |
| Peak memory | 200116 kb |
| Host | smart-d6224b1b-6124-41da-9cbc-1530f6908163 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=77237537598985039206387313025385810451692770599313443988363034131825120506547 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 33.uart_rx_parity_err.77237537598985039206387313025385810451692770599313443988363034131825120506547 |
| Directory | /workspace/33.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/33.uart_rx_start_bit_filter.81215367780520519002490102227703725194039325684810600364839116166097655833297 |
| Short name | T962 |
| Test name | |
| Test status | |
| Simulation time | 4267638245 ps |
| CPU time | 4.68 seconds |
| Started | Nov 22 01:44:51 PM PST 23 |
| Finished | Nov 22 01:44:57 PM PST 23 |
| Peak memory | 195916 kb |
| Host | smart-6b3d9e36-4a53-4675-a3e8-2bf03cf2a21d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=81215367780520519002490102227703725194039325684810600364839116166097655833297 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 33.uart_rx_start_bit_filter.81215367780520519002490102227703725194039325684810600364839116166097655833297 |
| Directory | /workspace/33.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/33.uart_smoke.7089215196089771141723929025768791440124935684078720984392922512859973934584 |
| Short name | T727 |
| Test name | |
| Test status | |
| Simulation time | 5759626309 ps |
| CPU time | 18.53 seconds |
| Started | Nov 22 01:44:49 PM PST 23 |
| Finished | Nov 22 01:45:10 PM PST 23 |
| Peak memory | 199644 kb |
| Host | smart-03913661-8800-4832-b6f3-4c3567305dc4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=7089215196089771141723929025768791440124935684078720984392922512859973934584 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 33.uart_smoke.7089215196089771141723929025768791440124935684078720984392922512859973934584 |
| Directory | /workspace/33.uart_smoke/latest |
| Test location | /workspace/coverage/default/33.uart_stress_all.43692871283357763650435642509934321232131695431882498893701607094227603612149 |
| Short name | T1163 |
| Test name | |
| Test status | |
| Simulation time | 43402307308 ps |
| CPU time | 57.14 seconds |
| Started | Nov 22 01:44:51 PM PST 23 |
| Finished | Nov 22 01:45:50 PM PST 23 |
| Peak memory | 200144 kb |
| Host | smart-c6fadd19-913a-46d6-a57f-c5e095a2e41d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43692871283357763650435642509934321232131695431882498893701607094227603612149 -assert nopos tproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 33.uart_stress_all.43692871283357763650435642509934321232131695431882498893701607094227603612149 |
| Directory | /workspace/33.uart_stress_all/latest |
| Test location | /workspace/coverage/default/33.uart_stress_all_with_rand_reset.92760765828780018459003023048396316139869048109684473525180956648782228028781 |
| Short name | T1150 |
| Test name | |
| Test status | |
| Simulation time | 87476847566 ps |
| CPU time | 470.93 seconds |
| Started | Nov 22 01:44:49 PM PST 23 |
| Finished | Nov 22 01:52:43 PM PST 23 |
| Peak memory | 226144 kb |
| Host | smart-2fe4024c-dbae-49ba-b8bc-4786ce1e166d |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92760765828780018459003023 048396316139869048109684473525180956648782228028781 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_stress_all_with_rand_reset.9276076582878 0018459003023048396316139869048109684473525180956648782228028781 |
| Directory | /workspace/33.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/33.uart_tx_ovrd.80237921660762985476224697797616625166806528004293295221894820127124012025566 |
| Short name | T1056 |
| Test name | |
| Test status | |
| Simulation time | 485186362 ps |
| CPU time | 1.25 seconds |
| Started | Nov 22 01:44:45 PM PST 23 |
| Finished | Nov 22 01:44:49 PM PST 23 |
| Peak memory | 197940 kb |
| Host | smart-24d3078b-ddd1-421d-a1dc-674075f023a5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=80237921660762985476224697797616625166806528004293295221894820127124012025566 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 33.uart_tx_ovrd.80237921660762985476224697797616625166806528004293295221894820127124012025566 |
| Directory | /workspace/33.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/33.uart_tx_rx.10803214840843010178563733771695815550855139059321369708340889404577483673810 |
| Short name | T746 |
| Test name | |
| Test status | |
| Simulation time | 57391945390 ps |
| CPU time | 63.44 seconds |
| Started | Nov 22 01:45:04 PM PST 23 |
| Finished | Nov 22 01:46:08 PM PST 23 |
| Peak memory | 200084 kb |
| Host | smart-d9757d0b-5cc3-4e95-9117-76c840bf9af8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=10803214840843010178563733771695815550855139059321369708340889404577483673810 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 33.uart_tx_rx.10803214840843010178563733771695815550855139059321369708340889404577483673810 |
| Directory | /workspace/33.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/34.uart_alert_test.1018112066721464131645431572493296697383419449367087237033493991040810670080 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 16368684 ps |
| CPU time | 0.53 seconds |
| Started | Nov 22 01:45:04 PM PST 23 |
| Finished | Nov 22 01:45:05 PM PST 23 |
| Peak memory | 194580 kb |
| Host | smart-21608699-0345-41d0-847b-da7edbcb6adb |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018112066721464131645431572493296697383419449367087237033493991040810670080 -assert nopostpro c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 34.uart_alert_test.1018112066721464131645431572493296697383419449367087237033493991040810670080 |
| Directory | /workspace/34.uart_alert_test/latest |
| Test location | /workspace/coverage/default/34.uart_fifo_full.19200566010750064210623734247601948899508197722313129788383324759376541515442 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 61777160308 ps |
| CPU time | 61.92 seconds |
| Started | Nov 22 01:44:49 PM PST 23 |
| Finished | Nov 22 01:45:54 PM PST 23 |
| Peak memory | 200096 kb |
| Host | smart-9d54222c-b9f9-451a-983c-e21728d1c30c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=19200566010750064210623734247601948899508197722313129788383324759376541515442 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 34.uart_fifo_full.19200566010750064210623734247601948899508197722313129788383324759376541515442 |
| Directory | /workspace/34.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/34.uart_fifo_overflow.6500020345931216490540706248115544726665331379073341932438757822526761769403 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 58551936110 ps |
| CPU time | 54.42 seconds |
| Started | Nov 22 01:45:05 PM PST 23 |
| Finished | Nov 22 01:46:01 PM PST 23 |
| Peak memory | 199796 kb |
| Host | smart-dfdc494c-6d65-4a6b-85ca-9e7aa1e5fb2b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=6500020345931216490540706248115544726665331379073341932438757822526761769403 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_overflow.6500020345931216490540706248115544726665331379073341932438757822526761769403 |
| Directory | /workspace/34.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/34.uart_fifo_reset.30423105149219682189898119033822706100755080278156027027894757654977052194066 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 112.63 seconds |
| Started | Nov 22 01:44:46 PM PST 23 |
| Finished | Nov 22 01:46:41 PM PST 23 |
| Peak memory | 198892 kb |
| Host | smart-a18a9803-9bba-4a7c-bb1b-c682fe4a108d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=30423105149219682189898119033822706100755080278156027027894757654977052194066 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 34.uart_fifo_reset.30423105149219682189898119033822706100755080278156027027894757654977052194066 |
| Directory | /workspace/34.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/34.uart_intr.56109700691043650188401503523480731841730174465606094684834919105036701367859 |
| Short name | T868 |
| Test name | |
| Test status | |
| Simulation time | 787145125175 ps |
| CPU time | 790.11 seconds |
| Started | Nov 22 01:45:07 PM PST 23 |
| Finished | Nov 22 01:58:18 PM PST 23 |
| Peak memory | 200052 kb |
| Host | smart-41b5f431-3dba-4ffa-90ad-edcc9ce56141 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56109700691043650188401503523480731841730174465606094684834919105036701367859 -assert nopost proc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 34.uart_intr.56109700691043650188401503523480731841730174465606094684834919105036701367859 |
| Directory | /workspace/34.uart_intr/latest |
| Test location | /workspace/coverage/default/34.uart_long_xfer_wo_dly.41817487261918411674902203767128482073648469373641580224854910937348632621790 |
| Short name | T1084 |
| Test name | |
| Test status | |
| Simulation time | 93387746707 ps |
| CPU time | 356.2 seconds |
| Started | Nov 22 01:45:21 PM PST 23 |
| Finished | Nov 22 01:51:18 PM PST 23 |
| Peak memory | 200140 kb |
| Host | smart-0ba22b6a-9f96-49c8-ade3-93fa292d5117 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=41817487261918411674902203767128482073648469373641580224854910937348632621790 -assert nopostproc +UVM_TES TNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 34.uart_long_xfer_wo_dly.41817487261918411674902203767128482073648469373641580224854910937348632621790 |
| Directory | /workspace/34.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/34.uart_loopback.44311054082807411363845172660296632631248186944482301248747172545590340363200 |
| Short name | T818 |
| Test name | |
| Test status | |
| Simulation time | 14572448663 ps |
| CPU time | 16.13 seconds |
| Started | Nov 22 01:44:50 PM PST 23 |
| Finished | Nov 22 01:45:08 PM PST 23 |
| Peak memory | 200048 kb |
| Host | smart-46707e3d-636c-4646-847b-a1c4c5f4118a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=44311054082807411363845172660296632631248186944482301248747172545590340363200 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 34.uart_loopback.44311054082807411363845172660296632631248186944482301248747172545590340363200 |
| Directory | /workspace/34.uart_loopback/latest |
| Test location | /workspace/coverage/default/34.uart_noise_filter.51264327049429990808357193348790973300513736495635897082519472428912599352216 |
| Short name | T1061 |
| Test name | |
| Test status | |
| Simulation time | 94501577082 ps |
| CPU time | 96.38 seconds |
| Started | Nov 22 01:44:50 PM PST 23 |
| Finished | Nov 22 01:46:29 PM PST 23 |
| Peak memory | 200248 kb |
| Host | smart-b456fe95-e615-43b0-b484-8aacb72548c2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=51264327049429990808357193348790973300513736495635897082519472428912599352216 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_noise_filter.51264327049429990808357193348790973300513736495635897082519472428912599352216 |
| Directory | /workspace/34.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/34.uart_perf.70711435790889524277099909899097439638343213825845370098731600208713787296290 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 14098773881 ps |
| CPU time | 474.83 seconds |
| Started | Nov 22 01:45:05 PM PST 23 |
| Finished | Nov 22 01:53:02 PM PST 23 |
| Peak memory | 200152 kb |
| Host | smart-306272c4-8f49-4808-91ea-d1732a66a8c6 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=70711435790889524277099909899097439638343213825845370098731600208713787296290 -assert nopostproc +UVM_TES TNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 34.uart_perf.70711435790889524277099909899097439638343213825845370098731600208713787296290 |
| Directory | /workspace/34.uart_perf/latest |
| Test location | /workspace/coverage/default/34.uart_rx_oversample.50286508404296280159780473107316542437762789721557138258311972269661539074775 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 4370280281 ps |
| CPU time | 19.72 seconds |
| Started | Nov 22 01:45:07 PM PST 23 |
| Finished | Nov 22 01:45:28 PM PST 23 |
| Peak memory | 198972 kb |
| Host | smart-932c76a7-7d69-42e1-8263-b0c698aa7f0d |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=50286508404296280159780473107316542437762789721557138258311972269661539074775 -assert nopostproc +UVM_TES TNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 34.uart_rx_oversample.50286508404296280159780473107316542437762789721557138258311972269661539074775 |
| Directory | /workspace/34.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/34.uart_rx_parity_err.61511980517233420195774322889822645421631131017692293203214122204929635083886 |
| Short name | T921 |
| Test name | |
| Test status | |
| Simulation time | 36616611594 ps |
| CPU time | 38.13 seconds |
| Started | Nov 22 01:44:53 PM PST 23 |
| Finished | Nov 22 01:45:33 PM PST 23 |
| Peak memory | 200188 kb |
| Host | smart-0c1a0afa-bcb8-4002-8cdc-08aa39fc14ba |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=61511980517233420195774322889822645421631131017692293203214122204929635083886 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 34.uart_rx_parity_err.61511980517233420195774322889822645421631131017692293203214122204929635083886 |
| Directory | /workspace/34.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/34.uart_rx_start_bit_filter.98105669696754407292189533506247680771637159175905750901961153982718445816372 |
| Short name | T1011 |
| Test name | |
| Test status | |
| Simulation time | 4267638245 ps |
| CPU time | 4.78 seconds |
| Started | Nov 22 01:45:06 PM PST 23 |
| Finished | Nov 22 01:45:12 PM PST 23 |
| Peak memory | 196012 kb |
| Host | smart-6655f3b6-0c8c-457c-8da2-da1b39a98cf3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=98105669696754407292189533506247680771637159175905750901961153982718445816372 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 34.uart_rx_start_bit_filter.98105669696754407292189533506247680771637159175905750901961153982718445816372 |
| Directory | /workspace/34.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/34.uart_smoke.44007391890013878085340872590644817740238214700778739984301576595013687287317 |
| Short name | T803 |
| Test name | |
| Test status | |
| Simulation time | 5759626309 ps |
| CPU time | 18.74 seconds |
| Started | Nov 22 01:44:57 PM PST 23 |
| Finished | Nov 22 01:45:17 PM PST 23 |
| Peak memory | 199536 kb |
| Host | smart-40c60738-0f95-44c7-bce3-7ff8281524e4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=44007391890013878085340872590644817740238214700778739984301576595013687287317 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 34.uart_smoke.44007391890013878085340872590644817740238214700778739984301576595013687287317 |
| Directory | /workspace/34.uart_smoke/latest |
| Test location | /workspace/coverage/default/34.uart_stress_all.100371764943236635328842035978957288971133845451014646225802065696687037266987 |
| Short name | T726 |
| Test name | |
| Test status | |
| Simulation time | 43402307308 ps |
| CPU time | 56.05 seconds |
| Started | Nov 22 01:44:50 PM PST 23 |
| Finished | Nov 22 01:45:48 PM PST 23 |
| Peak memory | 200108 kb |
| Host | smart-6faa2e7b-e624-44ab-86a9-b479cbb11529 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100371764943236635328842035978957288971133845451014646225802065696687037266987 -assert nopo stproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 34.uart_stress_all.100371764943236635328842035978957288971133845451014646225802065696687037266987 |
| Directory | /workspace/34.uart_stress_all/latest |
| Test location | /workspace/coverage/default/34.uart_stress_all_with_rand_reset.109069237694474804815898018818204277124685760288336558243593557377501285390208 |
| Short name | T717 |
| Test name | |
| Test status | |
| Simulation time | 87476847566 ps |
| CPU time | 458.69 seconds |
| Started | Nov 22 01:44:50 PM PST 23 |
| Finished | Nov 22 01:52:31 PM PST 23 |
| Peak memory | 226248 kb |
| Host | smart-8d2684fa-2b36-48e7-8654-6cb29499c6b8 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10906923769447480481589801 8818204277124685760288336558243593557377501285390208 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_stress_all_with_rand_reset.109069237694 474804815898018818204277124685760288336558243593557377501285390208 |
| Directory | /workspace/34.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/34.uart_tx_ovrd.11354412246085626521620152319067729699166787329992817540112719303387141083544 |
| Short name | T959 |
| Test name | |
| Test status | |
| Simulation time | 485186362 ps |
| CPU time | 1.24 seconds |
| Started | Nov 22 01:45:19 PM PST 23 |
| Finished | Nov 22 01:45:22 PM PST 23 |
| Peak memory | 197900 kb |
| Host | smart-0eea60c2-0618-4027-a4b5-ba971f9384dd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=11354412246085626521620152319067729699166787329992817540112719303387141083544 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 34.uart_tx_ovrd.11354412246085626521620152319067729699166787329992817540112719303387141083544 |
| Directory | /workspace/34.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/34.uart_tx_rx.102165004081138914020982999199048858796818937999151100550027294331607011312760 |
| Short name | T890 |
| Test name | |
| Test status | |
| Simulation time | 57391945390 ps |
| CPU time | 63.44 seconds |
| Started | Nov 22 01:44:55 PM PST 23 |
| Finished | Nov 22 01:45:59 PM PST 23 |
| Peak memory | 200112 kb |
| Host | smart-09e0ec1f-f2e1-486c-a6b9-48aba45e9ce6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=102165004081138914020982999199048858796818937999151100550027294331607011312760 -assert nopostproc +UVM_TESTNAME=uart_bas e_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 34.uart_tx_rx.102165004081138914020982999199048858796818937999151100550027294331607011312760 |
| Directory | /workspace/34.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/35.uart_alert_test.79545282051708254190542349173663594427247828523283770678208563122616448754480 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 16368684 ps |
| CPU time | 0.54 seconds |
| Started | Nov 22 01:45:20 PM PST 23 |
| Finished | Nov 22 01:45:22 PM PST 23 |
| Peak memory | 194620 kb |
| Host | smart-509c487a-9847-40a8-ad2e-d379ecfbae86 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79545282051708254190542349173663594427247828523283770678208563122616448754480 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 35.uart_alert_test.79545282051708254190542349173663594427247828523283770678208563122616448754480 |
| Directory | /workspace/35.uart_alert_test/latest |
| Test location | /workspace/coverage/default/35.uart_fifo_full.7954918345377179180155112891613538554052430717173819663632057416042225648608 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 61777160308 ps |
| CPU time | 61.08 seconds |
| Started | Nov 22 01:45:22 PM PST 23 |
| Finished | Nov 22 01:46:24 PM PST 23 |
| Peak memory | 200128 kb |
| Host | smart-fa092612-3f34-45ce-930e-76f6324db329 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=7954918345377179180155112891613538554052430717173819663632057416042225648608 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 35.uart_fifo_full.7954918345377179180155112891613538554052430717173819663632057416042225648608 |
| Directory | /workspace/35.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/35.uart_fifo_overflow.79637128913107180613631875421789347301944846057664265555885955549171203699603 |
| Short name | T910 |
| Test name | |
| Test status | |
| Simulation time | 58551936110 ps |
| CPU time | 55.1 seconds |
| Started | Nov 22 01:44:52 PM PST 23 |
| Finished | Nov 22 01:45:49 PM PST 23 |
| Peak memory | 199796 kb |
| Host | smart-f6e88005-9185-4c7f-a5ee-729bf68a788e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=79637128913107180613631875421789347301944846057664265555885955549171203699603 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 35.uart_fifo_overflow.79637128913107180613631875421789347301944846057664265555885955549171203699603 |
| Directory | /workspace/35.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/35.uart_fifo_reset.103909889532196290976049633653238925930230184303295241111409828155986017591533 |
| Short name | T789 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 113.56 seconds |
| Started | Nov 22 01:44:49 PM PST 23 |
| Finished | Nov 22 01:46:45 PM PST 23 |
| Peak memory | 198908 kb |
| Host | smart-a9857616-719c-4ea8-8739-dcac2f8c1158 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=103909889532196290976049633653238925930230184303295241111409828155986017591533 -assert nopostproc +UVM_TESTNAME=uart_bas e_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_reset.103909889532196290976049633653238925930230184303295241111409828155986017591533 |
| Directory | /workspace/35.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/35.uart_intr.45631542201532844618973381571653018540956691949181573248722688545266197830653 |
| Short name | T764 |
| Test name | |
| Test status | |
| Simulation time | 787145125175 ps |
| CPU time | 788.03 seconds |
| Started | Nov 22 01:44:53 PM PST 23 |
| Finished | Nov 22 01:58:03 PM PST 23 |
| Peak memory | 200092 kb |
| Host | smart-4215c7bd-1919-4611-a1e8-39e2f18ce5dd |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45631542201532844618973381571653018540956691949181573248722688545266197830653 -assert nopost proc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 35.uart_intr.45631542201532844618973381571653018540956691949181573248722688545266197830653 |
| Directory | /workspace/35.uart_intr/latest |
| Test location | /workspace/coverage/default/35.uart_long_xfer_wo_dly.108467903530460013727797532585278193038142221833718547748717515680847169234148 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 93387746707 ps |
| CPU time | 354.71 seconds |
| Started | Nov 22 01:44:57 PM PST 23 |
| Finished | Nov 22 01:50:52 PM PST 23 |
| Peak memory | 200048 kb |
| Host | smart-812469d1-7031-4621-95d1-5ea824128b75 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=108467903530460013727797532585278193038142221833718547748717515680847169234148 -assert nopostproc +UVM_TE STNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 35.uart_long_xfer_wo_dly.108467903530460013727797532585278193038142221833718547748717515680847169234148 |
| Directory | /workspace/35.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/35.uart_loopback.79720060163171569990486667034089156916995516869936745076208071836805462012166 |
| Short name | T736 |
| Test name | |
| Test status | |
| Simulation time | 14572448663 ps |
| CPU time | 16.18 seconds |
| Started | Nov 22 01:45:19 PM PST 23 |
| Finished | Nov 22 01:45:37 PM PST 23 |
| Peak memory | 199920 kb |
| Host | smart-8bafa471-0ab3-4c86-a61d-0dddce02b4c2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=79720060163171569990486667034089156916995516869936745076208071836805462012166 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 35.uart_loopback.79720060163171569990486667034089156916995516869936745076208071836805462012166 |
| Directory | /workspace/35.uart_loopback/latest |
| Test location | /workspace/coverage/default/35.uart_noise_filter.62193437153835201511762407523982291568406486886171728477127237695895008474605 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 94501577082 ps |
| CPU time | 97.19 seconds |
| Started | Nov 22 01:44:57 PM PST 23 |
| Finished | Nov 22 01:46:35 PM PST 23 |
| Peak memory | 200164 kb |
| Host | smart-47d44f90-eecd-42fc-88c4-1756e2f851ea |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=62193437153835201511762407523982291568406486886171728477127237695895008474605 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_noise_filter.62193437153835201511762407523982291568406486886171728477127237695895008474605 |
| Directory | /workspace/35.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/35.uart_perf.103590276499699768778259403986522860159242828070700073953486194537037332714178 |
| Short name | T1055 |
| Test name | |
| Test status | |
| Simulation time | 14098773881 ps |
| CPU time | 467.8 seconds |
| Started | Nov 22 01:44:50 PM PST 23 |
| Finished | Nov 22 01:52:40 PM PST 23 |
| Peak memory | 200164 kb |
| Host | smart-01693059-5e47-4bce-a9e4-c6a17cdd58c6 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=103590276499699768778259403986522860159242828070700073953486194537037332714178 -assert nopostproc +UVM_TE STNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 35.uart_perf.103590276499699768778259403986522860159242828070700073953486194537037332714178 |
| Directory | /workspace/35.uart_perf/latest |
| Test location | /workspace/coverage/default/35.uart_rx_oversample.65606686050917234781832210432210979402740567827663771540598509989711640661146 |
| Short name | T928 |
| Test name | |
| Test status | |
| Simulation time | 4370280281 ps |
| CPU time | 19.68 seconds |
| Started | Nov 22 01:45:16 PM PST 23 |
| Finished | Nov 22 01:45:37 PM PST 23 |
| Peak memory | 198888 kb |
| Host | smart-22659839-5a80-4e73-bfd6-bfd2dfe07871 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=65606686050917234781832210432210979402740567827663771540598509989711640661146 -assert nopostproc +UVM_TES TNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 35.uart_rx_oversample.65606686050917234781832210432210979402740567827663771540598509989711640661146 |
| Directory | /workspace/35.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/35.uart_rx_parity_err.25499690986093102637102266222888562615852186701145735701921860751950527305739 |
| Short name | T785 |
| Test name | |
| Test status | |
| Simulation time | 36616611594 ps |
| CPU time | 38.03 seconds |
| Started | Nov 22 01:45:19 PM PST 23 |
| Finished | Nov 22 01:45:58 PM PST 23 |
| Peak memory | 200032 kb |
| Host | smart-eca84db9-6b9b-47cb-841f-5a46db150fb8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=25499690986093102637102266222888562615852186701145735701921860751950527305739 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 35.uart_rx_parity_err.25499690986093102637102266222888562615852186701145735701921860751950527305739 |
| Directory | /workspace/35.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/35.uart_rx_start_bit_filter.18298491281767732561204898674193050386785404161788445424691838475345311728420 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 4267638245 ps |
| CPU time | 4.67 seconds |
| Started | Nov 22 01:45:22 PM PST 23 |
| Finished | Nov 22 01:45:28 PM PST 23 |
| Peak memory | 195976 kb |
| Host | smart-f6c068a7-8caa-4589-ac02-427f8ade1d79 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=18298491281767732561204898674193050386785404161788445424691838475345311728420 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 35.uart_rx_start_bit_filter.18298491281767732561204898674193050386785404161788445424691838475345311728420 |
| Directory | /workspace/35.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/35.uart_smoke.52311210208172488620554911914835185674604775718154396594797168311559994775977 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 5759626309 ps |
| CPU time | 18.57 seconds |
| Started | Nov 22 01:45:06 PM PST 23 |
| Finished | Nov 22 01:45:26 PM PST 23 |
| Peak memory | 199600 kb |
| Host | smart-da0f5882-9ca1-478a-b37b-f9b52481cdfb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=52311210208172488620554911914835185674604775718154396594797168311559994775977 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 35.uart_smoke.52311210208172488620554911914835185674604775718154396594797168311559994775977 |
| Directory | /workspace/35.uart_smoke/latest |
| Test location | /workspace/coverage/default/35.uart_stress_all.94589547367349410076085281075267087490037970095147421448389185961377173923746 |
| Short name | T914 |
| Test name | |
| Test status | |
| Simulation time | 43402307308 ps |
| CPU time | 56.76 seconds |
| Started | Nov 22 01:45:21 PM PST 23 |
| Finished | Nov 22 01:46:18 PM PST 23 |
| Peak memory | 200080 kb |
| Host | smart-58c1f2b8-87ea-4782-8c27-502160f22551 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94589547367349410076085281075267087490037970095147421448389185961377173923746 -assert nopos tproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 35.uart_stress_all.94589547367349410076085281075267087490037970095147421448389185961377173923746 |
| Directory | /workspace/35.uart_stress_all/latest |
| Test location | /workspace/coverage/default/35.uart_stress_all_with_rand_reset.37083245634751208755673615668197483326571095554478709363537107308669960425403 |
| Short name | T1226 |
| Test name | |
| Test status | |
| Simulation time | 87476847566 ps |
| CPU time | 457.02 seconds |
| Started | Nov 22 01:45:24 PM PST 23 |
| Finished | Nov 22 01:53:02 PM PST 23 |
| Peak memory | 226076 kb |
| Host | smart-0dfc8dd4-8cc3-4efd-aaf2-035c82aeb30b |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37083245634751208755673615 668197483326571095554478709363537107308669960425403 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_stress_all_with_rand_reset.3708324563475 1208755673615668197483326571095554478709363537107308669960425403 |
| Directory | /workspace/35.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/35.uart_tx_ovrd.58494205492060059908025514455919472674271364337338013369817187509546202385761 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 485186362 ps |
| CPU time | 1.26 seconds |
| Started | Nov 22 01:44:51 PM PST 23 |
| Finished | Nov 22 01:44:54 PM PST 23 |
| Peak memory | 197876 kb |
| Host | smart-193a5797-6c24-4ef0-b7c7-3d5dd0d7e0eb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=58494205492060059908025514455919472674271364337338013369817187509546202385761 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 35.uart_tx_ovrd.58494205492060059908025514455919472674271364337338013369817187509546202385761 |
| Directory | /workspace/35.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/35.uart_tx_rx.38816092202737876053774349298390797456905341984212399567946705174829673813906 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 57391945390 ps |
| CPU time | 63.08 seconds |
| Started | Nov 22 01:45:20 PM PST 23 |
| Finished | Nov 22 01:46:25 PM PST 23 |
| Peak memory | 200084 kb |
| Host | smart-bf31ff1d-5157-426f-af68-77fbddb383c1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=38816092202737876053774349298390797456905341984212399567946705174829673813906 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 35.uart_tx_rx.38816092202737876053774349298390797456905341984212399567946705174829673813906 |
| Directory | /workspace/35.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/36.uart_alert_test.111325932320140799186619792723382339317128624699766856702374071751278195687632 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 16368684 ps |
| CPU time | 0.53 seconds |
| Started | Nov 22 01:45:30 PM PST 23 |
| Finished | Nov 22 01:45:32 PM PST 23 |
| Peak memory | 194560 kb |
| Host | smart-1a035d29-dab0-446a-a217-3cc77ee9f62b |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111325932320140799186619792723382339317128624699766856702374071751278195687632 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 36.uart_alert_test.111325932320140799186619792723382339317128624699766856702374071751278195687632 |
| Directory | /workspace/36.uart_alert_test/latest |
| Test location | /workspace/coverage/default/36.uart_fifo_full.47298153837847836989719711359977141678653611326400266837829637738683432597703 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 61777160308 ps |
| CPU time | 61.42 seconds |
| Started | Nov 22 01:44:53 PM PST 23 |
| Finished | Nov 22 01:45:56 PM PST 23 |
| Peak memory | 200080 kb |
| Host | smart-c8c496f6-e5a5-4154-9515-d4f49d13eec0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=47298153837847836989719711359977141678653611326400266837829637738683432597703 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 36.uart_fifo_full.47298153837847836989719711359977141678653611326400266837829637738683432597703 |
| Directory | /workspace/36.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/36.uart_fifo_overflow.51608260403789240114432784068510206307785847916768594251796842918713968960922 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 58551936110 ps |
| CPU time | 55.05 seconds |
| Started | Nov 22 01:45:21 PM PST 23 |
| Finished | Nov 22 01:46:17 PM PST 23 |
| Peak memory | 199892 kb |
| Host | smart-d206d290-1766-4c21-a50f-c6aac4599c5d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=51608260403789240114432784068510206307785847916768594251796842918713968960922 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 36.uart_fifo_overflow.51608260403789240114432784068510206307785847916768594251796842918713968960922 |
| Directory | /workspace/36.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/36.uart_fifo_reset.431457849551408360374406715728319002593887300135374946178765571562141864982 |
| Short name | T949 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 113.76 seconds |
| Started | Nov 22 01:45:41 PM PST 23 |
| Finished | Nov 22 01:47:36 PM PST 23 |
| Peak memory | 198856 kb |
| Host | smart-2eeea970-f6ae-4d34-8591-5e027f8fba45 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=431457849551408360374406715728319002593887300135374946178765571562141864982 -assert nopostproc +UVM_TESTNAME=uart_base_t est +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 36.uart_fifo_reset.431457849551408360374406715728319002593887300135374946178765571562141864982 |
| Directory | /workspace/36.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/36.uart_intr.8650208643108999464947808239428187781089219812501082862466169109785916933542 |
| Short name | T990 |
| Test name | |
| Test status | |
| Simulation time | 787145125175 ps |
| CPU time | 785.69 seconds |
| Started | Nov 22 01:45:39 PM PST 23 |
| Finished | Nov 22 01:58:45 PM PST 23 |
| Peak memory | 200112 kb |
| Host | smart-c01d94a1-4742-4e4e-a4f4-ae6feeada6e1 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8650208643108999464947808239428187781089219812501082862466169109785916933542 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 36.uart_intr.8650208643108999464947808239428187781089219812501082862466169109785916933542 |
| Directory | /workspace/36.uart_intr/latest |
| Test location | /workspace/coverage/default/36.uart_long_xfer_wo_dly.3575477877213596756334814224601423443943698833128972627049900575609052144489 |
| Short name | T731 |
| Test name | |
| Test status | |
| Simulation time | 93387746707 ps |
| CPU time | 355.85 seconds |
| Started | Nov 22 01:45:27 PM PST 23 |
| Finished | Nov 22 01:51:25 PM PST 23 |
| Peak memory | 200128 kb |
| Host | smart-569a0f3c-6c5d-4976-b75a-91ccef274ba4 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3575477877213596756334814224601423443943698833128972627049900575609052144489 -assert nopostproc +UVM_TEST NAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_long_xfer_wo_dly.3575477877213596756334814224601423443943698833128972627049900575609052144489 |
| Directory | /workspace/36.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/36.uart_loopback.54699096374335160033013471278394775462629878546583574785364802551108583159909 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 14572448663 ps |
| CPU time | 16.21 seconds |
| Started | Nov 22 01:45:27 PM PST 23 |
| Finished | Nov 22 01:45:45 PM PST 23 |
| Peak memory | 200040 kb |
| Host | smart-650ceac1-8dcd-475a-b469-b7ec178e7d90 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=54699096374335160033013471278394775462629878546583574785364802551108583159909 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 36.uart_loopback.54699096374335160033013471278394775462629878546583574785364802551108583159909 |
| Directory | /workspace/36.uart_loopback/latest |
| Test location | /workspace/coverage/default/36.uart_noise_filter.90512912107091072310118565935331324743986450517067023114221477349390400890410 |
| Short name | T735 |
| Test name | |
| Test status | |
| Simulation time | 94501577082 ps |
| CPU time | 96.82 seconds |
| Started | Nov 22 01:44:52 PM PST 23 |
| Finished | Nov 22 01:46:30 PM PST 23 |
| Peak memory | 200096 kb |
| Host | smart-be90ab8a-fb9d-43b6-996c-0520968aff82 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=90512912107091072310118565935331324743986450517067023114221477349390400890410 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_noise_filter.90512912107091072310118565935331324743986450517067023114221477349390400890410 |
| Directory | /workspace/36.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/36.uart_perf.82162399183367301124009612653535783883710224875023779335294023271359665206631 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 14098773881 ps |
| CPU time | 471.98 seconds |
| Started | Nov 22 01:45:40 PM PST 23 |
| Finished | Nov 22 01:53:34 PM PST 23 |
| Peak memory | 200100 kb |
| Host | smart-5ecc1035-1f79-4f4d-8c2d-a476d89436bd |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=82162399183367301124009612653535783883710224875023779335294023271359665206631 -assert nopostproc +UVM_TES TNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 36.uart_perf.82162399183367301124009612653535783883710224875023779335294023271359665206631 |
| Directory | /workspace/36.uart_perf/latest |
| Test location | /workspace/coverage/default/36.uart_rx_oversample.48341084384385045599047802092669919505003350903063596661061688288370261528082 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 4370280281 ps |
| CPU time | 20.1 seconds |
| Started | Nov 22 01:45:28 PM PST 23 |
| Finished | Nov 22 01:45:50 PM PST 23 |
| Peak memory | 198972 kb |
| Host | smart-554005ab-e2a3-47e8-ab02-21a1d4b5dcdd |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=48341084384385045599047802092669919505003350903063596661061688288370261528082 -assert nopostproc +UVM_TES TNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 36.uart_rx_oversample.48341084384385045599047802092669919505003350903063596661061688288370261528082 |
| Directory | /workspace/36.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/36.uart_rx_parity_err.91789915499551810214266933738605850873628078146746669124148284986298337357037 |
| Short name | T1027 |
| Test name | |
| Test status | |
| Simulation time | 36616611594 ps |
| CPU time | 38.26 seconds |
| Started | Nov 22 01:45:33 PM PST 23 |
| Finished | Nov 22 01:46:12 PM PST 23 |
| Peak memory | 200112 kb |
| Host | smart-4ebaa624-495f-4dba-a4c4-a5cc3dceee42 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=91789915499551810214266933738605850873628078146746669124148284986298337357037 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 36.uart_rx_parity_err.91789915499551810214266933738605850873628078146746669124148284986298337357037 |
| Directory | /workspace/36.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/36.uart_rx_start_bit_filter.60168623640683379232688567248627491391895176037152520888439993597413748354250 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 4267638245 ps |
| CPU time | 4.69 seconds |
| Started | Nov 22 01:45:38 PM PST 23 |
| Finished | Nov 22 01:45:44 PM PST 23 |
| Peak memory | 195984 kb |
| Host | smart-67c309eb-6e75-482f-a53d-4e0e9d95a97d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=60168623640683379232688567248627491391895176037152520888439993597413748354250 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 36.uart_rx_start_bit_filter.60168623640683379232688567248627491391895176037152520888439993597413748354250 |
| Directory | /workspace/36.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/36.uart_smoke.61491719122584374375130444874635227696350543270103131118192888894440610817406 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 5759626309 ps |
| CPU time | 18.42 seconds |
| Started | Nov 22 01:45:25 PM PST 23 |
| Finished | Nov 22 01:45:45 PM PST 23 |
| Peak memory | 199664 kb |
| Host | smart-1c5c29b8-c250-4ec6-abc9-4c9405947988 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=61491719122584374375130444874635227696350543270103131118192888894440610817406 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 36.uart_smoke.61491719122584374375130444874635227696350543270103131118192888894440610817406 |
| Directory | /workspace/36.uart_smoke/latest |
| Test location | /workspace/coverage/default/36.uart_stress_all.26706807708520885914398896995400756064392510043139638648712870697744613019545 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 43402307308 ps |
| CPU time | 57.21 seconds |
| Started | Nov 22 01:45:56 PM PST 23 |
| Finished | Nov 22 01:47:00 PM PST 23 |
| Peak memory | 199996 kb |
| Host | smart-b4bf065e-c685-4996-b4cf-d71a0121aa62 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26706807708520885914398896995400756064392510043139638648712870697744613019545 -assert nopos tproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 36.uart_stress_all.26706807708520885914398896995400756064392510043139638648712870697744613019545 |
| Directory | /workspace/36.uart_stress_all/latest |
| Test location | /workspace/coverage/default/36.uart_stress_all_with_rand_reset.114042796390629889649629354263849462468308045680302772263757885397041230839478 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 87476847566 ps |
| CPU time | 466.5 seconds |
| Started | Nov 22 01:45:40 PM PST 23 |
| Finished | Nov 22 01:53:28 PM PST 23 |
| Peak memory | 226240 kb |
| Host | smart-c725100d-7d24-4384-84ca-229aafeb918d |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11404279639062988964962935 4263849462468308045680302772263757885397041230839478 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_stress_all_with_rand_reset.114042796390 629889649629354263849462468308045680302772263757885397041230839478 |
| Directory | /workspace/36.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/36.uart_tx_ovrd.45023158889354395132403099444381195502147005723618412622258964181353422173905 |
| Short name | T681 |
| Test name | |
| Test status | |
| Simulation time | 485186362 ps |
| CPU time | 1.27 seconds |
| Started | Nov 22 01:45:37 PM PST 23 |
| Finished | Nov 22 01:45:40 PM PST 23 |
| Peak memory | 197812 kb |
| Host | smart-6be9bd64-c51c-4d9a-af06-4d81efd3c1d6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=45023158889354395132403099444381195502147005723618412622258964181353422173905 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 36.uart_tx_ovrd.45023158889354395132403099444381195502147005723618412622258964181353422173905 |
| Directory | /workspace/36.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/36.uart_tx_rx.82576809872746977366578825593448560972842173138615845989903142474202403402404 |
| Short name | T1085 |
| Test name | |
| Test status | |
| Simulation time | 57391945390 ps |
| CPU time | 63.75 seconds |
| Started | Nov 22 01:45:25 PM PST 23 |
| Finished | Nov 22 01:46:30 PM PST 23 |
| Peak memory | 200064 kb |
| Host | smart-ba556f04-a897-419d-8a31-a38b10736781 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=82576809872746977366578825593448560972842173138615845989903142474202403402404 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 36.uart_tx_rx.82576809872746977366578825593448560972842173138615845989903142474202403402404 |
| Directory | /workspace/36.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/37.uart_alert_test.21916242356928368350345494604688089556147263419394866346676568895222188245086 |
| Short name | T1028 |
| Test name | |
| Test status | |
| Simulation time | 16368684 ps |
| CPU time | 0.53 seconds |
| Started | Nov 22 01:45:56 PM PST 23 |
| Finished | Nov 22 01:46:04 PM PST 23 |
| Peak memory | 194488 kb |
| Host | smart-5b6a9d40-f289-4edb-8bf0-cc890cd50191 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21916242356928368350345494604688089556147263419394866346676568895222188245086 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 37.uart_alert_test.21916242356928368350345494604688089556147263419394866346676568895222188245086 |
| Directory | /workspace/37.uart_alert_test/latest |
| Test location | /workspace/coverage/default/37.uart_fifo_full.58226817332046307129665060938683465438077403613181334532665927306666056412619 |
| Short name | T724 |
| Test name | |
| Test status | |
| Simulation time | 61777160308 ps |
| CPU time | 61.15 seconds |
| Started | Nov 22 01:45:47 PM PST 23 |
| Finished | Nov 22 01:46:50 PM PST 23 |
| Peak memory | 199956 kb |
| Host | smart-0a2c6120-4a93-49c0-a31f-2e766120098a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=58226817332046307129665060938683465438077403613181334532665927306666056412619 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 37.uart_fifo_full.58226817332046307129665060938683465438077403613181334532665927306666056412619 |
| Directory | /workspace/37.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/37.uart_fifo_overflow.37468719619825459729434030504805012004362710401906357021845225984743169646203 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 58551936110 ps |
| CPU time | 54.47 seconds |
| Started | Nov 22 01:45:43 PM PST 23 |
| Finished | Nov 22 01:46:39 PM PST 23 |
| Peak memory | 199944 kb |
| Host | smart-49190a6e-6532-4e1b-9b4b-fdfcf119bb00 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=37468719619825459729434030504805012004362710401906357021845225984743169646203 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 37.uart_fifo_overflow.37468719619825459729434030504805012004362710401906357021845225984743169646203 |
| Directory | /workspace/37.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/37.uart_fifo_reset.28203012204693020505841493872478006687394902972695219129196720444553072886844 |
| Short name | T1213 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 113.33 seconds |
| Started | Nov 22 01:45:51 PM PST 23 |
| Finished | Nov 22 01:47:46 PM PST 23 |
| Peak memory | 198932 kb |
| Host | smart-62aab471-9805-42ae-9f2f-aa4f5f87200b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=28203012204693020505841493872478006687394902972695219129196720444553072886844 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 37.uart_fifo_reset.28203012204693020505841493872478006687394902972695219129196720444553072886844 |
| Directory | /workspace/37.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/37.uart_intr.46133912972674873199965664830234542484542497974079749164858949624235839112171 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 787145125175 ps |
| CPU time | 784.75 seconds |
| Started | Nov 22 01:46:00 PM PST 23 |
| Finished | Nov 22 01:59:12 PM PST 23 |
| Peak memory | 199844 kb |
| Host | smart-c3f0fa3d-7d4a-4390-9030-21392c623e24 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46133912972674873199965664830234542484542497974079749164858949624235839112171 -assert nopost proc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 37.uart_intr.46133912972674873199965664830234542484542497974079749164858949624235839112171 |
| Directory | /workspace/37.uart_intr/latest |
| Test location | /workspace/coverage/default/37.uart_long_xfer_wo_dly.113456393533794143956988738783416727794235187624162895331324517580974290322359 |
| Short name | T1112 |
| Test name | |
| Test status | |
| Simulation time | 93387746707 ps |
| CPU time | 353.39 seconds |
| Started | Nov 22 01:45:53 PM PST 23 |
| Finished | Nov 22 01:51:49 PM PST 23 |
| Peak memory | 200216 kb |
| Host | smart-a681c582-b025-4cc9-824a-e72cd5fb1b54 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=113456393533794143956988738783416727794235187624162895331324517580974290322359 -assert nopostproc +UVM_TE STNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 37.uart_long_xfer_wo_dly.113456393533794143956988738783416727794235187624162895331324517580974290322359 |
| Directory | /workspace/37.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/37.uart_loopback.26278389056596198086352019597203183972052603545849466674195366846503030655429 |
| Short name | T889 |
| Test name | |
| Test status | |
| Simulation time | 14572448663 ps |
| CPU time | 16.12 seconds |
| Started | Nov 22 01:46:00 PM PST 23 |
| Finished | Nov 22 01:46:23 PM PST 23 |
| Peak memory | 199944 kb |
| Host | smart-04d29379-0983-4af2-bcaf-9ffe2f41f51e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=26278389056596198086352019597203183972052603545849466674195366846503030655429 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 37.uart_loopback.26278389056596198086352019597203183972052603545849466674195366846503030655429 |
| Directory | /workspace/37.uart_loopback/latest |
| Test location | /workspace/coverage/default/37.uart_noise_filter.14509408500366850507750658588353008053755470520259292365863044158998966260071 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 94501577082 ps |
| CPU time | 96.33 seconds |
| Started | Nov 22 01:45:45 PM PST 23 |
| Finished | Nov 22 01:47:24 PM PST 23 |
| Peak memory | 200272 kb |
| Host | smart-da129a73-d094-43c9-9780-720f29059d2f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=14509408500366850507750658588353008053755470520259292365863044158998966260071 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_noise_filter.14509408500366850507750658588353008053755470520259292365863044158998966260071 |
| Directory | /workspace/37.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/37.uart_perf.88560327822561626830127181107173981932310327870709627709168383825602715708664 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 14098773881 ps |
| CPU time | 476.24 seconds |
| Started | Nov 22 01:45:54 PM PST 23 |
| Finished | Nov 22 01:53:54 PM PST 23 |
| Peak memory | 200232 kb |
| Host | smart-bb15c702-a88e-4e6b-acc5-8ae38b439664 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=88560327822561626830127181107173981932310327870709627709168383825602715708664 -assert nopostproc +UVM_TES TNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 37.uart_perf.88560327822561626830127181107173981932310327870709627709168383825602715708664 |
| Directory | /workspace/37.uart_perf/latest |
| Test location | /workspace/coverage/default/37.uart_rx_oversample.107523782580670648385180867780098525753653122936345188636421556869085595840572 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 4370280281 ps |
| CPU time | 19.87 seconds |
| Started | Nov 22 01:45:48 PM PST 23 |
| Finished | Nov 22 01:46:10 PM PST 23 |
| Peak memory | 198964 kb |
| Host | smart-5173c9e6-68bf-4c9e-98b5-03a979c8ddec |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=107523782580670648385180867780098525753653122936345188636421556869085595840572 -assert nopostproc +UVM_TE STNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_oversample.107523782580670648385180867780098525753653122936345188636421556869085595840572 |
| Directory | /workspace/37.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/37.uart_rx_parity_err.73172432474529091774233667966411275953985964329103619450500336075348430263123 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 36616611594 ps |
| CPU time | 37.68 seconds |
| Started | Nov 22 01:45:54 PM PST 23 |
| Finished | Nov 22 01:46:36 PM PST 23 |
| Peak memory | 199736 kb |
| Host | smart-0ab549b2-09fd-4603-9f07-0812c35eac8b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=73172432474529091774233667966411275953985964329103619450500336075348430263123 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 37.uart_rx_parity_err.73172432474529091774233667966411275953985964329103619450500336075348430263123 |
| Directory | /workspace/37.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/37.uart_rx_start_bit_filter.89376931224382197089440059671599759810025805757643641353954132924078740470055 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 4267638245 ps |
| CPU time | 4.72 seconds |
| Started | Nov 22 01:45:39 PM PST 23 |
| Finished | Nov 22 01:45:46 PM PST 23 |
| Peak memory | 196024 kb |
| Host | smart-0f2e8d63-f074-4fdf-b3be-7f86df872be2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=89376931224382197089440059671599759810025805757643641353954132924078740470055 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 37.uart_rx_start_bit_filter.89376931224382197089440059671599759810025805757643641353954132924078740470055 |
| Directory | /workspace/37.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/37.uart_smoke.24585771534391806685743508257942936145427796617837713818022763965923435997986 |
| Short name | T843 |
| Test name | |
| Test status | |
| Simulation time | 5759626309 ps |
| CPU time | 18.48 seconds |
| Started | Nov 22 01:45:52 PM PST 23 |
| Finished | Nov 22 01:46:12 PM PST 23 |
| Peak memory | 199656 kb |
| Host | smart-c0638673-80c2-403d-9bbb-0bd00d69b7cf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=24585771534391806685743508257942936145427796617837713818022763965923435997986 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 37.uart_smoke.24585771534391806685743508257942936145427796617837713818022763965923435997986 |
| Directory | /workspace/37.uart_smoke/latest |
| Test location | /workspace/coverage/default/37.uart_stress_all.101415026602591422820278857408173640436359443111880775700529675500069043105417 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 43402307308 ps |
| CPU time | 56.58 seconds |
| Started | Nov 22 01:46:00 PM PST 23 |
| Finished | Nov 22 01:47:04 PM PST 23 |
| Peak memory | 199872 kb |
| Host | smart-e6aed39f-0596-46ce-aa9b-9eeb9ea5575b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101415026602591422820278857408173640436359443111880775700529675500069043105417 -assert nopo stproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 37.uart_stress_all.101415026602591422820278857408173640436359443111880775700529675500069043105417 |
| Directory | /workspace/37.uart_stress_all/latest |
| Test location | /workspace/coverage/default/37.uart_stress_all_with_rand_reset.48385497098469172269357044903840653610145968938465223478625152023600657665965 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 87476847566 ps |
| CPU time | 462.22 seconds |
| Started | Nov 22 01:46:00 PM PST 23 |
| Finished | Nov 22 01:53:49 PM PST 23 |
| Peak memory | 226092 kb |
| Host | smart-bf4dd900-47ba-41ef-849c-a1631d153439 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48385497098469172269357044 903840653610145968938465223478625152023600657665965 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_stress_all_with_rand_reset.4838549709846 9172269357044903840653610145968938465223478625152023600657665965 |
| Directory | /workspace/37.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/37.uart_tx_ovrd.24733034114344292000166010766174181498833098735135817912206385336922908137940 |
| Short name | T1029 |
| Test name | |
| Test status | |
| Simulation time | 485186362 ps |
| CPU time | 1.25 seconds |
| Started | Nov 22 01:45:46 PM PST 23 |
| Finished | Nov 22 01:45:50 PM PST 23 |
| Peak memory | 197912 kb |
| Host | smart-a85312b4-a8e8-464d-ac36-8464b5680b7a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=24733034114344292000166010766174181498833098735135817912206385336922908137940 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 37.uart_tx_ovrd.24733034114344292000166010766174181498833098735135817912206385336922908137940 |
| Directory | /workspace/37.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/37.uart_tx_rx.48219571966733591021896909435911441253968361054947891827947152834637864619370 |
| Short name | T836 |
| Test name | |
| Test status | |
| Simulation time | 57391945390 ps |
| CPU time | 63.37 seconds |
| Started | Nov 22 01:46:02 PM PST 23 |
| Finished | Nov 22 01:47:11 PM PST 23 |
| Peak memory | 200088 kb |
| Host | smart-3c167f9a-833b-498c-ae7f-431324576db5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=48219571966733591021896909435911441253968361054947891827947152834637864619370 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 37.uart_tx_rx.48219571966733591021896909435911441253968361054947891827947152834637864619370 |
| Directory | /workspace/37.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/38.uart_alert_test.57194347701881261728386354298854940079620553371443345763114577509348342207923 |
| Short name | T1268 |
| Test name | |
| Test status | |
| Simulation time | 16368684 ps |
| CPU time | 0.53 seconds |
| Started | Nov 22 01:44:54 PM PST 23 |
| Finished | Nov 22 01:44:56 PM PST 23 |
| Peak memory | 194588 kb |
| Host | smart-1999241c-0c03-444e-9dc4-83e4eb86742a |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57194347701881261728386354298854940079620553371443345763114577509348342207923 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 38.uart_alert_test.57194347701881261728386354298854940079620553371443345763114577509348342207923 |
| Directory | /workspace/38.uart_alert_test/latest |
| Test location | /workspace/coverage/default/38.uart_fifo_full.27964521700639057266318293687611147881312665903988612717382072700359925204904 |
| Short name | T1100 |
| Test name | |
| Test status | |
| Simulation time | 61777160308 ps |
| CPU time | 60.85 seconds |
| Started | Nov 22 01:45:47 PM PST 23 |
| Finished | Nov 22 01:46:50 PM PST 23 |
| Peak memory | 199944 kb |
| Host | smart-8bb2c053-e417-4105-bbf3-84a960b95a0b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=27964521700639057266318293687611147881312665903988612717382072700359925204904 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 38.uart_fifo_full.27964521700639057266318293687611147881312665903988612717382072700359925204904 |
| Directory | /workspace/38.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/38.uart_fifo_overflow.47099183694356747431864860184321686764038638689564482518438547427660808653170 |
| Short name | T1125 |
| Test name | |
| Test status | |
| Simulation time | 58551936110 ps |
| CPU time | 54.56 seconds |
| Started | Nov 22 01:45:54 PM PST 23 |
| Finished | Nov 22 01:46:52 PM PST 23 |
| Peak memory | 199892 kb |
| Host | smart-a91dc557-f8ff-4016-8ed2-137fc72e9e3e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=47099183694356747431864860184321686764038638689564482518438547427660808653170 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 38.uart_fifo_overflow.47099183694356747431864860184321686764038638689564482518438547427660808653170 |
| Directory | /workspace/38.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/38.uart_fifo_reset.3578589063840245977366772382586716344747370300953490498923910442220971880036 |
| Short name | T783 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 113.01 seconds |
| Started | Nov 22 01:45:20 PM PST 23 |
| Finished | Nov 22 01:47:14 PM PST 23 |
| Peak memory | 198952 kb |
| Host | smart-8a4e5b10-eab2-4909-94ce-bdbb81788fc5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3578589063840245977366772382586716344747370300953490498923910442220971880036 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 38.uart_fifo_reset.3578589063840245977366772382586716344747370300953490498923910442220971880036 |
| Directory | /workspace/38.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/38.uart_intr.25133499905069143937370277195188533989313422070226174345977950539816262070257 |
| Short name | T819 |
| Test name | |
| Test status | |
| Simulation time | 787145125175 ps |
| CPU time | 785.94 seconds |
| Started | Nov 22 01:45:23 PM PST 23 |
| Finished | Nov 22 01:58:29 PM PST 23 |
| Peak memory | 200064 kb |
| Host | smart-fe5f3bd1-fcc9-4ed0-b8a5-f9c2a4e8c59b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25133499905069143937370277195188533989313422070226174345977950539816262070257 -assert nopost proc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 38.uart_intr.25133499905069143937370277195188533989313422070226174345977950539816262070257 |
| Directory | /workspace/38.uart_intr/latest |
| Test location | /workspace/coverage/default/38.uart_long_xfer_wo_dly.7957049288512358483362130978257452935161107992737974777364812352885335023130 |
| Short name | T768 |
| Test name | |
| Test status | |
| Simulation time | 93387746707 ps |
| CPU time | 353.13 seconds |
| Started | Nov 22 01:45:25 PM PST 23 |
| Finished | Nov 22 01:51:19 PM PST 23 |
| Peak memory | 200164 kb |
| Host | smart-cf30d31f-1b78-4c57-a6eb-cb08eb164dd9 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=7957049288512358483362130978257452935161107992737974777364812352885335023130 -assert nopostproc +UVM_TEST NAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_long_xfer_wo_dly.7957049288512358483362130978257452935161107992737974777364812352885335023130 |
| Directory | /workspace/38.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/38.uart_loopback.72351922535029233593867610252512557427358994904512892030224965262736884462441 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 14572448663 ps |
| CPU time | 16.19 seconds |
| Started | Nov 22 01:45:23 PM PST 23 |
| Finished | Nov 22 01:45:40 PM PST 23 |
| Peak memory | 200048 kb |
| Host | smart-3e795f5f-6367-4211-8772-8a728ac92bf9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=72351922535029233593867610252512557427358994904512892030224965262736884462441 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 38.uart_loopback.72351922535029233593867610252512557427358994904512892030224965262736884462441 |
| Directory | /workspace/38.uart_loopback/latest |
| Test location | /workspace/coverage/default/38.uart_noise_filter.67894730356281689843665686507783343556471441280119810684447571613585238041509 |
| Short name | T751 |
| Test name | |
| Test status | |
| Simulation time | 94501577082 ps |
| CPU time | 96.96 seconds |
| Started | Nov 22 01:45:21 PM PST 23 |
| Finished | Nov 22 01:46:59 PM PST 23 |
| Peak memory | 200232 kb |
| Host | smart-ec252aa9-47ef-4be1-b8d0-cb3dcd8bc158 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=67894730356281689843665686507783343556471441280119810684447571613585238041509 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_noise_filter.67894730356281689843665686507783343556471441280119810684447571613585238041509 |
| Directory | /workspace/38.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/38.uart_perf.13765446390149616112855165736221459453328201532652155292235719900538132460790 |
| Short name | T1188 |
| Test name | |
| Test status | |
| Simulation time | 14098773881 ps |
| CPU time | 468.93 seconds |
| Started | Nov 22 01:44:55 PM PST 23 |
| Finished | Nov 22 01:52:45 PM PST 23 |
| Peak memory | 200116 kb |
| Host | smart-81089736-2278-46b5-8435-772c417dcd7b |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=13765446390149616112855165736221459453328201532652155292235719900538132460790 -assert nopostproc +UVM_TES TNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 38.uart_perf.13765446390149616112855165736221459453328201532652155292235719900538132460790 |
| Directory | /workspace/38.uart_perf/latest |
| Test location | /workspace/coverage/default/38.uart_rx_oversample.71711702475992393834408486479098355006984192524588059223674852451335876439265 |
| Short name | T956 |
| Test name | |
| Test status | |
| Simulation time | 4370280281 ps |
| CPU time | 20.3 seconds |
| Started | Nov 22 01:44:52 PM PST 23 |
| Finished | Nov 22 01:45:14 PM PST 23 |
| Peak memory | 198924 kb |
| Host | smart-c337f14c-8d90-445b-8d4f-c3c871c6baa6 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=71711702475992393834408486479098355006984192524588059223674852451335876439265 -assert nopostproc +UVM_TES TNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 38.uart_rx_oversample.71711702475992393834408486479098355006984192524588059223674852451335876439265 |
| Directory | /workspace/38.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/38.uart_rx_parity_err.85190770311130732230934625351181210753673855145631589157988200687083717269712 |
| Short name | T1003 |
| Test name | |
| Test status | |
| Simulation time | 36616611594 ps |
| CPU time | 38.29 seconds |
| Started | Nov 22 01:44:53 PM PST 23 |
| Finished | Nov 22 01:45:33 PM PST 23 |
| Peak memory | 200084 kb |
| Host | smart-ba01a46b-895c-48fb-bc17-c8ea782ad3d6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=85190770311130732230934625351181210753673855145631589157988200687083717269712 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 38.uart_rx_parity_err.85190770311130732230934625351181210753673855145631589157988200687083717269712 |
| Directory | /workspace/38.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/38.uart_rx_start_bit_filter.100728193367130999821207189791180430216472034231995180280405900582730222738436 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 4267638245 ps |
| CPU time | 4.66 seconds |
| Started | Nov 22 01:45:19 PM PST 23 |
| Finished | Nov 22 01:45:24 PM PST 23 |
| Peak memory | 195960 kb |
| Host | smart-3497ceb2-480b-4048-8903-c01e99bb8eaf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=100728193367130999821207189791180430216472034231995180280405900582730222738436 -assert nopostproc +UVM_TESTNAME=uart_bas e_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 38.uart_rx_start_bit_filter.100728193367130999821207189791180430216472034231995180280405900582730222738436 |
| Directory | /workspace/38.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/38.uart_smoke.12494330598776191824056877466217074687105139573951665742714737020181658464251 |
| Short name | T999 |
| Test name | |
| Test status | |
| Simulation time | 5759626309 ps |
| CPU time | 18.44 seconds |
| Started | Nov 22 01:45:47 PM PST 23 |
| Finished | Nov 22 01:46:07 PM PST 23 |
| Peak memory | 199492 kb |
| Host | smart-a1820038-c641-4486-ac00-d27a29fee92b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=12494330598776191824056877466217074687105139573951665742714737020181658464251 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 38.uart_smoke.12494330598776191824056877466217074687105139573951665742714737020181658464251 |
| Directory | /workspace/38.uart_smoke/latest |
| Test location | /workspace/coverage/default/38.uart_stress_all.80893840374123194111521612885398722721923987028547480559815261728028529929687 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 43402307308 ps |
| CPU time | 56.18 seconds |
| Started | Nov 22 01:44:52 PM PST 23 |
| Finished | Nov 22 01:45:50 PM PST 23 |
| Peak memory | 200068 kb |
| Host | smart-cb18cee4-b489-4d08-a471-793a24e2b294 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80893840374123194111521612885398722721923987028547480559815261728028529929687 -assert nopos tproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 38.uart_stress_all.80893840374123194111521612885398722721923987028547480559815261728028529929687 |
| Directory | /workspace/38.uart_stress_all/latest |
| Test location | /workspace/coverage/default/38.uart_stress_all_with_rand_reset.38864998231496211555965110523609856395432195983304941795063748815822176308576 |
| Short name | T1204 |
| Test name | |
| Test status | |
| Simulation time | 87476847566 ps |
| CPU time | 455.51 seconds |
| Started | Nov 22 01:44:50 PM PST 23 |
| Finished | Nov 22 01:52:28 PM PST 23 |
| Peak memory | 226244 kb |
| Host | smart-ad1d1745-150e-4d1b-808f-8b84fd43c4f4 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38864998231496211555965110 523609856395432195983304941795063748815822176308576 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_stress_all_with_rand_reset.3886499823149 6211555965110523609856395432195983304941795063748815822176308576 |
| Directory | /workspace/38.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/38.uart_tx_ovrd.101623761728913750795251299532752453980968923555374356669774051524183380032755 |
| Short name | T937 |
| Test name | |
| Test status | |
| Simulation time | 485186362 ps |
| CPU time | 1.27 seconds |
| Started | Nov 22 01:45:22 PM PST 23 |
| Finished | Nov 22 01:45:24 PM PST 23 |
| Peak memory | 198024 kb |
| Host | smart-9b485ca3-a3e8-48dc-bf60-61c2afb196a5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=101623761728913750795251299532752453980968923555374356669774051524183380032755 -assert nopostproc +UVM_TESTNAME=uart_bas e_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 38.uart_tx_ovrd.101623761728913750795251299532752453980968923555374356669774051524183380032755 |
| Directory | /workspace/38.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/38.uart_tx_rx.80725871640339015549371454877692623546414241881878343719347130452154377755001 |
| Short name | T1138 |
| Test name | |
| Test status | |
| Simulation time | 57391945390 ps |
| CPU time | 63 seconds |
| Started | Nov 22 01:45:57 PM PST 23 |
| Finished | Nov 22 01:47:07 PM PST 23 |
| Peak memory | 200024 kb |
| Host | smart-cf19664a-ac9e-41f2-aab1-a72d1cbfcbbf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=80725871640339015549371454877692623546414241881878343719347130452154377755001 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 38.uart_tx_rx.80725871640339015549371454877692623546414241881878343719347130452154377755001 |
| Directory | /workspace/38.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/39.uart_alert_test.26327786082046739604553191194297363181674529402977257462976590996135573693542 |
| Short name | T897 |
| Test name | |
| Test status | |
| Simulation time | 16368684 ps |
| CPU time | 0.59 seconds |
| Started | Nov 22 01:45:10 PM PST 23 |
| Finished | Nov 22 01:45:12 PM PST 23 |
| Peak memory | 194580 kb |
| Host | smart-5f737f7a-c8a2-43cb-9996-93038a3b320a |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26327786082046739604553191194297363181674529402977257462976590996135573693542 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 39.uart_alert_test.26327786082046739604553191194297363181674529402977257462976590996135573693542 |
| Directory | /workspace/39.uart_alert_test/latest |
| Test location | /workspace/coverage/default/39.uart_fifo_full.102830006711177357517888866864072685230894128466945991177259034640267713939491 |
| Short name | T940 |
| Test name | |
| Test status | |
| Simulation time | 61777160308 ps |
| CPU time | 60.84 seconds |
| Started | Nov 22 01:45:27 PM PST 23 |
| Finished | Nov 22 01:46:30 PM PST 23 |
| Peak memory | 200072 kb |
| Host | smart-3f18d328-e396-4577-b05a-e9ee11a02dc6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=102830006711177357517888866864072685230894128466945991177259034640267713939491 -assert nopostproc +UVM_TESTNAME=uart_bas e_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 39.uart_fifo_full.102830006711177357517888866864072685230894128466945991177259034640267713939491 |
| Directory | /workspace/39.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/39.uart_fifo_overflow.68335395507385444332422693147008550216625453307231080180223170045524704253410 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 58551936110 ps |
| CPU time | 54.72 seconds |
| Started | Nov 22 01:45:09 PM PST 23 |
| Finished | Nov 22 01:46:05 PM PST 23 |
| Peak memory | 199796 kb |
| Host | smart-db660f60-af3a-4df0-beab-a551bda0ea03 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=68335395507385444332422693147008550216625453307231080180223170045524704253410 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 39.uart_fifo_overflow.68335395507385444332422693147008550216625453307231080180223170045524704253410 |
| Directory | /workspace/39.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/39.uart_fifo_reset.97879447678784769130155560961824374532012350219043634917660741679167826067154 |
| Short name | T888 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 113.99 seconds |
| Started | Nov 22 01:45:10 PM PST 23 |
| Finished | Nov 22 01:47:05 PM PST 23 |
| Peak memory | 198864 kb |
| Host | smart-5bf1c86b-0745-4275-9f15-4ca7723728cd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=97879447678784769130155560961824374532012350219043634917660741679167826067154 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 39.uart_fifo_reset.97879447678784769130155560961824374532012350219043634917660741679167826067154 |
| Directory | /workspace/39.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/39.uart_intr.83125410771588769716694566683639777729997702249434218200442914432381517310501 |
| Short name | T1144 |
| Test name | |
| Test status | |
| Simulation time | 787145125175 ps |
| CPU time | 789.9 seconds |
| Started | Nov 22 01:45:10 PM PST 23 |
| Finished | Nov 22 01:58:21 PM PST 23 |
| Peak memory | 200132 kb |
| Host | smart-0e28f55a-f11f-4dda-b0e2-e234bfd4b126 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83125410771588769716694566683639777729997702249434218200442914432381517310501 -assert nopost proc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 39.uart_intr.83125410771588769716694566683639777729997702249434218200442914432381517310501 |
| Directory | /workspace/39.uart_intr/latest |
| Test location | /workspace/coverage/default/39.uart_long_xfer_wo_dly.111312610277359793165162271658659646469598475593178358555371781936488949779299 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 93387746707 ps |
| CPU time | 356.58 seconds |
| Started | Nov 22 01:45:24 PM PST 23 |
| Finished | Nov 22 01:51:22 PM PST 23 |
| Peak memory | 200132 kb |
| Host | smart-d08474da-32cd-4144-a9f4-de516378e745 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=111312610277359793165162271658659646469598475593178358555371781936488949779299 -assert nopostproc +UVM_TE STNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 39.uart_long_xfer_wo_dly.111312610277359793165162271658659646469598475593178358555371781936488949779299 |
| Directory | /workspace/39.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/39.uart_loopback.110503878365613211144381285371631413773513489250611251765973162705753852279034 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 14572448663 ps |
| CPU time | 16.15 seconds |
| Started | Nov 22 01:45:28 PM PST 23 |
| Finished | Nov 22 01:45:46 PM PST 23 |
| Peak memory | 200044 kb |
| Host | smart-257429fc-2428-43ae-a48b-59ae2786aa65 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=110503878365613211144381285371631413773513489250611251765973162705753852279034 -assert nopostproc +UVM_TESTNAME=uart_bas e_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 39.uart_loopback.110503878365613211144381285371631413773513489250611251765973162705753852279034 |
| Directory | /workspace/39.uart_loopback/latest |
| Test location | /workspace/coverage/default/39.uart_noise_filter.46113727311084371284168929363795897447839178820479597474422899974632277824366 |
| Short name | T1191 |
| Test name | |
| Test status | |
| Simulation time | 94501577082 ps |
| CPU time | 96.93 seconds |
| Started | Nov 22 01:45:27 PM PST 23 |
| Finished | Nov 22 01:47:05 PM PST 23 |
| Peak memory | 200276 kb |
| Host | smart-6c861e6d-965e-46e9-8acd-e22157251e65 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=46113727311084371284168929363795897447839178820479597474422899974632277824366 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_noise_filter.46113727311084371284168929363795897447839178820479597474422899974632277824366 |
| Directory | /workspace/39.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/39.uart_perf.64235188063664877188774148616656913646171668679508060251667743482482982045915 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 14098773881 ps |
| CPU time | 472.34 seconds |
| Started | Nov 22 01:45:26 PM PST 23 |
| Finished | Nov 22 01:53:20 PM PST 23 |
| Peak memory | 200120 kb |
| Host | smart-cfd5bf2c-a19c-4109-adf4-789c5c21e293 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=64235188063664877188774148616656913646171668679508060251667743482482982045915 -assert nopostproc +UVM_TES TNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 39.uart_perf.64235188063664877188774148616656913646171668679508060251667743482482982045915 |
| Directory | /workspace/39.uart_perf/latest |
| Test location | /workspace/coverage/default/39.uart_rx_oversample.3565548525847504516703572261670364556481511393606066857054665256105037459073 |
| Short name | T859 |
| Test name | |
| Test status | |
| Simulation time | 4370280281 ps |
| CPU time | 20.35 seconds |
| Started | Nov 22 01:45:08 PM PST 23 |
| Finished | Nov 22 01:45:30 PM PST 23 |
| Peak memory | 198948 kb |
| Host | smart-24892d84-634d-4970-8926-7a519fdd341e |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3565548525847504516703572261670364556481511393606066857054665256105037459073 -assert nopostproc +UVM_TEST NAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 39.uart_rx_oversample.3565548525847504516703572261670364556481511393606066857054665256105037459073 |
| Directory | /workspace/39.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/39.uart_rx_parity_err.15607955323450738874511448730273069380417482853393666039611675246114639312969 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 36616611594 ps |
| CPU time | 37.66 seconds |
| Started | Nov 22 01:45:07 PM PST 23 |
| Finished | Nov 22 01:45:46 PM PST 23 |
| Peak memory | 200112 kb |
| Host | smart-3c7f3e2c-cfa5-4ab9-900c-1a9633bebedd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=15607955323450738874511448730273069380417482853393666039611675246114639312969 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 39.uart_rx_parity_err.15607955323450738874511448730273069380417482853393666039611675246114639312969 |
| Directory | /workspace/39.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/39.uart_rx_start_bit_filter.5067042814846816244277998614337053192005922098497086620338079257708326561637 |
| Short name | T1189 |
| Test name | |
| Test status | |
| Simulation time | 4267638245 ps |
| CPU time | 4.64 seconds |
| Started | Nov 22 01:45:13 PM PST 23 |
| Finished | Nov 22 01:45:18 PM PST 23 |
| Peak memory | 195832 kb |
| Host | smart-10a4c9a5-4c3a-40bc-8b9b-59d078b95a2f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=5067042814846816244277998614337053192005922098497086620338079257708326561637 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 39.uart_rx_start_bit_filter.5067042814846816244277998614337053192005922098497086620338079257708326561637 |
| Directory | /workspace/39.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/39.uart_smoke.89801468502850957274536916334785092566178288957866950150356815069217849746322 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 5759626309 ps |
| CPU time | 18.6 seconds |
| Started | Nov 22 01:45:27 PM PST 23 |
| Finished | Nov 22 01:45:47 PM PST 23 |
| Peak memory | 199628 kb |
| Host | smart-71c01a68-1238-48bd-b3c9-4b27f44bd00e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=89801468502850957274536916334785092566178288957866950150356815069217849746322 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 39.uart_smoke.89801468502850957274536916334785092566178288957866950150356815069217849746322 |
| Directory | /workspace/39.uart_smoke/latest |
| Test location | /workspace/coverage/default/39.uart_stress_all.59805462921212644752402392567694873637319808553659407226370641156712853405661 |
| Short name | T1010 |
| Test name | |
| Test status | |
| Simulation time | 43402307308 ps |
| CPU time | 56.38 seconds |
| Started | Nov 22 01:45:26 PM PST 23 |
| Finished | Nov 22 01:46:23 PM PST 23 |
| Peak memory | 200116 kb |
| Host | smart-44127c32-5f76-4754-a2c9-3e8dd0a65ff1 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59805462921212644752402392567694873637319808553659407226370641156712853405661 -assert nopos tproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 39.uart_stress_all.59805462921212644752402392567694873637319808553659407226370641156712853405661 |
| Directory | /workspace/39.uart_stress_all/latest |
| Test location | /workspace/coverage/default/39.uart_stress_all_with_rand_reset.32685356473466794718851976000544283312188024592019067466912384149188614255274 |
| Short name | T896 |
| Test name | |
| Test status | |
| Simulation time | 87476847566 ps |
| CPU time | 456.26 seconds |
| Started | Nov 22 01:45:28 PM PST 23 |
| Finished | Nov 22 01:53:06 PM PST 23 |
| Peak memory | 226248 kb |
| Host | smart-a6ae589d-19b2-41d0-8e33-1006237fbee0 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32685356473466794718851976 000544283312188024592019067466912384149188614255274 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_stress_all_with_rand_reset.3268535647346 6794718851976000544283312188024592019067466912384149188614255274 |
| Directory | /workspace/39.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/39.uart_tx_ovrd.95033003462899021402481221345629328548755176324233742034148530545071806590399 |
| Short name | T906 |
| Test name | |
| Test status | |
| Simulation time | 485186362 ps |
| CPU time | 1.22 seconds |
| Started | Nov 22 01:45:26 PM PST 23 |
| Finished | Nov 22 01:45:29 PM PST 23 |
| Peak memory | 197888 kb |
| Host | smart-1365127a-917b-452f-8bdd-08a02b15cc2f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=95033003462899021402481221345629328548755176324233742034148530545071806590399 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 39.uart_tx_ovrd.95033003462899021402481221345629328548755176324233742034148530545071806590399 |
| Directory | /workspace/39.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/39.uart_tx_rx.25471902358356301437619251670069398140462769156106537006103948645837673837971 |
| Short name | T1252 |
| Test name | |
| Test status | |
| Simulation time | 57391945390 ps |
| CPU time | 62.83 seconds |
| Started | Nov 22 01:45:04 PM PST 23 |
| Finished | Nov 22 01:46:08 PM PST 23 |
| Peak memory | 199924 kb |
| Host | smart-6f6962c4-2dcd-4d88-a6dc-a2b9aba2cb51 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=25471902358356301437619251670069398140462769156106537006103948645837673837971 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 39.uart_tx_rx.25471902358356301437619251670069398140462769156106537006103948645837673837971 |
| Directory | /workspace/39.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/4.uart_alert_test.9034189587408242540840570200763205225502642050537050356372195194116751571437 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 16368684 ps |
| CPU time | 0.53 seconds |
| Started | Nov 22 01:43:57 PM PST 23 |
| Finished | Nov 22 01:44:01 PM PST 23 |
| Peak memory | 194644 kb |
| Host | smart-644de4ee-6be3-4dca-ae42-2b762c8a89ef |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9034189587408242540840570200763205225502642050537050356372195194116751571437 -assert nopostpro c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 4.uart_alert_test.9034189587408242540840570200763205225502642050537050356372195194116751571437 |
| Directory | /workspace/4.uart_alert_test/latest |
| Test location | /workspace/coverage/default/4.uart_fifo_full.113259933465284400939351096075822336389180952946064005629703566610834725544503 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 61777160308 ps |
| CPU time | 60.67 seconds |
| Started | Nov 22 01:43:52 PM PST 23 |
| Finished | Nov 22 01:44:56 PM PST 23 |
| Peak memory | 200120 kb |
| Host | smart-7764f691-a47b-4cda-998d-6f6e00d2e6b5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=113259933465284400939351096075822336389180952946064005629703566610834725544503 -assert nopostproc +UVM_TESTNAME=uart_bas e_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 4.uart_fifo_full.113259933465284400939351096075822336389180952946064005629703566610834725544503 |
| Directory | /workspace/4.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/4.uart_fifo_overflow.30285305671776592406523472708047708765883827667903400542106673779699864991775 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 58551936110 ps |
| CPU time | 54.89 seconds |
| Started | Nov 22 01:44:02 PM PST 23 |
| Finished | Nov 22 01:45:02 PM PST 23 |
| Peak memory | 199888 kb |
| Host | smart-ecf1dd51-6f77-4342-bdd2-f81c1db11f3e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=30285305671776592406523472708047708765883827667903400542106673779699864991775 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 4.uart_fifo_overflow.30285305671776592406523472708047708765883827667903400542106673779699864991775 |
| Directory | /workspace/4.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/4.uart_fifo_reset.4654404128702471543664176333977419756120140624594733467301000178654383443837 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 113.35 seconds |
| Started | Nov 22 01:43:48 PM PST 23 |
| Finished | Nov 22 01:45:44 PM PST 23 |
| Peak memory | 198756 kb |
| Host | smart-5be2692c-0921-4ab7-a9e4-a4fdf04d57d2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4654404128702471543664176333977419756120140624594733467301000178654383443837 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 4.uart_fifo_reset.4654404128702471543664176333977419756120140624594733467301000178654383443837 |
| Directory | /workspace/4.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/4.uart_intr.43380234188270061781061230529057473146552004004837557285302796557077374661699 |
| Short name | T905 |
| Test name | |
| Test status | |
| Simulation time | 787145125175 ps |
| CPU time | 783.16 seconds |
| Started | Nov 22 01:43:55 PM PST 23 |
| Finished | Nov 22 01:57:02 PM PST 23 |
| Peak memory | 200136 kb |
| Host | smart-0ad167ff-81ab-4f48-8177-223bcb8fe2a1 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43380234188270061781061230529057473146552004004837557285302796557077374661699 -assert nopost proc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 4.uart_intr.43380234188270061781061230529057473146552004004837557285302796557077374661699 |
| Directory | /workspace/4.uart_intr/latest |
| Test location | /workspace/coverage/default/4.uart_long_xfer_wo_dly.115537039595419906311851932887332422287444948824878616320249145149127118532395 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 93387746707 ps |
| CPU time | 358.11 seconds |
| Started | Nov 22 01:43:51 PM PST 23 |
| Finished | Nov 22 01:49:52 PM PST 23 |
| Peak memory | 200140 kb |
| Host | smart-ef451363-a7ae-44eb-a054-2469901702cf |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=115537039595419906311851932887332422287444948824878616320249145149127118532395 -assert nopostproc +UVM_TE STNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 4.uart_long_xfer_wo_dly.115537039595419906311851932887332422287444948824878616320249145149127118532395 |
| Directory | /workspace/4.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/4.uart_loopback.62965358835833064224568760744826985086471251367312760491153466901180377335455 |
| Short name | T820 |
| Test name | |
| Test status | |
| Simulation time | 14572448663 ps |
| CPU time | 16.14 seconds |
| Started | Nov 22 01:44:06 PM PST 23 |
| Finished | Nov 22 01:44:27 PM PST 23 |
| Peak memory | 199996 kb |
| Host | smart-4029cca9-b4d0-42b3-8740-1d9a0fe2fea3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=62965358835833064224568760744826985086471251367312760491153466901180377335455 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 4.uart_loopback.62965358835833064224568760744826985086471251367312760491153466901180377335455 |
| Directory | /workspace/4.uart_loopback/latest |
| Test location | /workspace/coverage/default/4.uart_noise_filter.103935821191735904739657298653883524510800219195769608018439778840274565816731 |
| Short name | T1120 |
| Test name | |
| Test status | |
| Simulation time | 94501577082 ps |
| CPU time | 96.85 seconds |
| Started | Nov 22 01:43:57 PM PST 23 |
| Finished | Nov 22 01:45:38 PM PST 23 |
| Peak memory | 200152 kb |
| Host | smart-6cf8fab7-6abb-4dbf-9758-2aec36621876 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=103935821191735904739657298653883524510800219195769608018439778840274565816731 -assert nopostproc +UVM_TESTNAME=uart_bas e_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 4.uart_noise_filter.103935821191735904739657298653883524510800219195769608018439778840274565816731 |
| Directory | /workspace/4.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/4.uart_perf.32789818033464944293286560100790819809956697858278112761433121250537167561239 |
| Short name | T1005 |
| Test name | |
| Test status | |
| Simulation time | 14098773881 ps |
| CPU time | 467.83 seconds |
| Started | Nov 22 01:43:38 PM PST 23 |
| Finished | Nov 22 01:51:28 PM PST 23 |
| Peak memory | 200164 kb |
| Host | smart-b609691d-292f-4bbe-a104-6fc851ee4e5d |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=32789818033464944293286560100790819809956697858278112761433121250537167561239 -assert nopostproc +UVM_TES TNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 4.uart_perf.32789818033464944293286560100790819809956697858278112761433121250537167561239 |
| Directory | /workspace/4.uart_perf/latest |
| Test location | /workspace/coverage/default/4.uart_rx_oversample.61656037297448334850295749882415852574697082618233174744768708733612072809816 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 4370280281 ps |
| CPU time | 19.93 seconds |
| Started | Nov 22 01:43:56 PM PST 23 |
| Finished | Nov 22 01:44:20 PM PST 23 |
| Peak memory | 198964 kb |
| Host | smart-2d81286f-e157-454d-8767-2bb0513dbf0a |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=61656037297448334850295749882415852574697082618233174744768708733612072809816 -assert nopostproc +UVM_TES TNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 4.uart_rx_oversample.61656037297448334850295749882415852574697082618233174744768708733612072809816 |
| Directory | /workspace/4.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/4.uart_rx_parity_err.50457949220532071206829661785711293781789795543013780793897494580804015886324 |
| Short name | T686 |
| Test name | |
| Test status | |
| Simulation time | 36616611594 ps |
| CPU time | 38.02 seconds |
| Started | Nov 22 01:44:12 PM PST 23 |
| Finished | Nov 22 01:44:54 PM PST 23 |
| Peak memory | 200120 kb |
| Host | smart-11d69516-0bb3-4801-b668-ba8cb75d322e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=50457949220532071206829661785711293781789795543013780793897494580804015886324 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 4.uart_rx_parity_err.50457949220532071206829661785711293781789795543013780793897494580804015886324 |
| Directory | /workspace/4.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/4.uart_rx_start_bit_filter.40803680411264513165678636742256630562099443239210460143883229816924480066893 |
| Short name | T1180 |
| Test name | |
| Test status | |
| Simulation time | 4267638245 ps |
| CPU time | 4.78 seconds |
| Started | Nov 22 01:43:57 PM PST 23 |
| Finished | Nov 22 01:44:05 PM PST 23 |
| Peak memory | 195996 kb |
| Host | smart-6e7d3e26-1752-44f3-8ddb-6e508ecec588 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=40803680411264513165678636742256630562099443239210460143883229816924480066893 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 4.uart_rx_start_bit_filter.40803680411264513165678636742256630562099443239210460143883229816924480066893 |
| Directory | /workspace/4.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/4.uart_sec_cm.76612091191567176614181837569477998707290555569151966144638128990798332082274 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 100582296 ps |
| CPU time | 0.83 seconds |
| Started | Nov 22 01:43:43 PM PST 23 |
| Finished | Nov 22 01:43:45 PM PST 23 |
| Peak memory | 218432 kb |
| Host | smart-097c57c5-bcaa-4971-9b53-f4fe5b9bf8c9 |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76612091191567176614181837569477998707290555569151966144638128990798332082274 -assert nopostpro c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 4.uart_sec_cm.76612091191567176614181837569477998707290555569151966144638128990798332082274 |
| Directory | /workspace/4.uart_sec_cm/latest |
| Test location | /workspace/coverage/default/4.uart_smoke.72153259347179491844517154405435513006598137132991589781952332041483720709561 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 5759626309 ps |
| CPU time | 18.81 seconds |
| Started | Nov 22 01:43:50 PM PST 23 |
| Finished | Nov 22 01:44:12 PM PST 23 |
| Peak memory | 199488 kb |
| Host | smart-6d574e27-ad40-4616-8f09-dc7e612f08fb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=72153259347179491844517154405435513006598137132991589781952332041483720709561 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 4.uart_smoke.72153259347179491844517154405435513006598137132991589781952332041483720709561 |
| Directory | /workspace/4.uart_smoke/latest |
| Test location | /workspace/coverage/default/4.uart_stress_all.87577252709787044575091161147283227406594998092652219035414915351922562706463 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 43402307308 ps |
| CPU time | 57.56 seconds |
| Started | Nov 22 01:44:06 PM PST 23 |
| Finished | Nov 22 01:45:09 PM PST 23 |
| Peak memory | 200108 kb |
| Host | smart-2639aa76-8f52-4203-b5e9-3f6e17acc201 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87577252709787044575091161147283227406594998092652219035414915351922562706463 -assert nopos tproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 4.uart_stress_all.87577252709787044575091161147283227406594998092652219035414915351922562706463 |
| Directory | /workspace/4.uart_stress_all/latest |
| Test location | /workspace/coverage/default/4.uart_stress_all_with_rand_reset.6629861338105087199038961642002749985927683043935221323476668880972101049225 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 87476847566 ps |
| CPU time | 461.98 seconds |
| Started | Nov 22 01:44:02 PM PST 23 |
| Finished | Nov 22 01:51:48 PM PST 23 |
| Peak memory | 226112 kb |
| Host | smart-23dd2c97-1ab4-4142-b8d9-0de5fa1fbb6c |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66298613381050871990389616 42002749985927683043935221323476668880972101049225 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_stress_all_with_rand_reset.662986133810508 7199038961642002749985927683043935221323476668880972101049225 |
| Directory | /workspace/4.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/4.uart_tx_ovrd.100490721894473032126839243024107658456934831267263982076505247061190022286519 |
| Short name | T923 |
| Test name | |
| Test status | |
| Simulation time | 485186362 ps |
| CPU time | 1.24 seconds |
| Started | Nov 22 01:43:55 PM PST 23 |
| Finished | Nov 22 01:43:59 PM PST 23 |
| Peak memory | 197932 kb |
| Host | smart-ac6943aa-7cd2-4cdc-b468-e09df83e48b8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=100490721894473032126839243024107658456934831267263982076505247061190022286519 -assert nopostproc +UVM_TESTNAME=uart_bas e_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 4.uart_tx_ovrd.100490721894473032126839243024107658456934831267263982076505247061190022286519 |
| Directory | /workspace/4.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/4.uart_tx_rx.19303412526733929079173576823357893192347529083213756154649010086866657967409 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 57391945390 ps |
| CPU time | 64.17 seconds |
| Started | Nov 22 01:44:10 PM PST 23 |
| Finished | Nov 22 01:45:18 PM PST 23 |
| Peak memory | 200044 kb |
| Host | smart-71a8c1bb-2e6b-4892-9836-22dee8973c62 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=19303412526733929079173576823357893192347529083213756154649010086866657967409 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 4.uart_tx_rx.19303412526733929079173576823357893192347529083213756154649010086866657967409 |
| Directory | /workspace/4.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/40.uart_alert_test.54678578480478608609425038737773680091199380095256499326340079007634991691700 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 16368684 ps |
| CPU time | 0.54 seconds |
| Started | Nov 22 01:45:26 PM PST 23 |
| Finished | Nov 22 01:45:28 PM PST 23 |
| Peak memory | 194612 kb |
| Host | smart-b0766da6-9ee0-4da2-9f14-5479bb454436 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54678578480478608609425038737773680091199380095256499326340079007634991691700 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 40.uart_alert_test.54678578480478608609425038737773680091199380095256499326340079007634991691700 |
| Directory | /workspace/40.uart_alert_test/latest |
| Test location | /workspace/coverage/default/40.uart_fifo_full.26730455971523155199385993422827037265658994825214670303358364848230159918846 |
| Short name | T1260 |
| Test name | |
| Test status | |
| Simulation time | 61777160308 ps |
| CPU time | 61.43 seconds |
| Started | Nov 22 01:45:28 PM PST 23 |
| Finished | Nov 22 01:46:31 PM PST 23 |
| Peak memory | 200108 kb |
| Host | smart-c517fec6-8c94-423a-b579-d5ac50859690 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=26730455971523155199385993422827037265658994825214670303358364848230159918846 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 40.uart_fifo_full.26730455971523155199385993422827037265658994825214670303358364848230159918846 |
| Directory | /workspace/40.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/40.uart_fifo_overflow.99551656597489741386299660421080340530593169536338014399106208772875484557171 |
| Short name | T903 |
| Test name | |
| Test status | |
| Simulation time | 58551936110 ps |
| CPU time | 54.73 seconds |
| Started | Nov 22 01:45:09 PM PST 23 |
| Finished | Nov 22 01:46:05 PM PST 23 |
| Peak memory | 199904 kb |
| Host | smart-0e02bf02-de2d-46be-af30-fc0d2a56cb64 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=99551656597489741386299660421080340530593169536338014399106208772875484557171 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 40.uart_fifo_overflow.99551656597489741386299660421080340530593169536338014399106208772875484557171 |
| Directory | /workspace/40.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/40.uart_fifo_reset.110079422806448826998584250075301960836920468307219876888036100043160441631213 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 112.92 seconds |
| Started | Nov 22 01:45:24 PM PST 23 |
| Finished | Nov 22 01:47:18 PM PST 23 |
| Peak memory | 198888 kb |
| Host | smart-39cf7f4f-1745-46ed-87a2-3b053459e693 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=110079422806448826998584250075301960836920468307219876888036100043160441631213 -assert nopostproc +UVM_TESTNAME=uart_bas e_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_reset.110079422806448826998584250075301960836920468307219876888036100043160441631213 |
| Directory | /workspace/40.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/40.uart_intr.5668258186786495569730399797366189474254036417221071952362317292149713453482 |
| Short name | T747 |
| Test name | |
| Test status | |
| Simulation time | 787145125175 ps |
| CPU time | 784.52 seconds |
| Started | Nov 22 01:45:11 PM PST 23 |
| Finished | Nov 22 01:58:17 PM PST 23 |
| Peak memory | 200112 kb |
| Host | smart-86bee1cc-4127-477e-ae50-8bfc86a11302 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5668258186786495569730399797366189474254036417221071952362317292149713453482 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 40.uart_intr.5668258186786495569730399797366189474254036417221071952362317292149713453482 |
| Directory | /workspace/40.uart_intr/latest |
| Test location | /workspace/coverage/default/40.uart_long_xfer_wo_dly.65785343514827423705914025621559209289840011285833601408799193754096982011759 |
| Short name | T863 |
| Test name | |
| Test status | |
| Simulation time | 93387746707 ps |
| CPU time | 352.64 seconds |
| Started | Nov 22 01:45:23 PM PST 23 |
| Finished | Nov 22 01:51:17 PM PST 23 |
| Peak memory | 200016 kb |
| Host | smart-7ff92376-e815-4391-99af-eabb431f57fe |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=65785343514827423705914025621559209289840011285833601408799193754096982011759 -assert nopostproc +UVM_TES TNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 40.uart_long_xfer_wo_dly.65785343514827423705914025621559209289840011285833601408799193754096982011759 |
| Directory | /workspace/40.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/40.uart_loopback.87809941401727869224851861220477247799046562615072064425548666107098771976485 |
| Short name | T862 |
| Test name | |
| Test status | |
| Simulation time | 14572448663 ps |
| CPU time | 16.14 seconds |
| Started | Nov 22 01:45:29 PM PST 23 |
| Finished | Nov 22 01:45:47 PM PST 23 |
| Peak memory | 200052 kb |
| Host | smart-b2a0a5f5-53e2-46dd-9909-f96fdbc5776e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=87809941401727869224851861220477247799046562615072064425548666107098771976485 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 40.uart_loopback.87809941401727869224851861220477247799046562615072064425548666107098771976485 |
| Directory | /workspace/40.uart_loopback/latest |
| Test location | /workspace/coverage/default/40.uart_noise_filter.49978033129311732662565842784155875473797177782908810048469006804619691297975 |
| Short name | T1098 |
| Test name | |
| Test status | |
| Simulation time | 94501577082 ps |
| CPU time | 96.29 seconds |
| Started | Nov 22 01:45:29 PM PST 23 |
| Finished | Nov 22 01:47:07 PM PST 23 |
| Peak memory | 200236 kb |
| Host | smart-dc538811-dde5-4c59-9ec8-e3eef1fd983f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=49978033129311732662565842784155875473797177782908810048469006804619691297975 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_noise_filter.49978033129311732662565842784155875473797177782908810048469006804619691297975 |
| Directory | /workspace/40.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/40.uart_perf.36312112563986069468877367369525384968460321653883180832589858307039653834292 |
| Short name | T1081 |
| Test name | |
| Test status | |
| Simulation time | 14098773881 ps |
| CPU time | 466.51 seconds |
| Started | Nov 22 01:45:26 PM PST 23 |
| Finished | Nov 22 01:53:14 PM PST 23 |
| Peak memory | 200152 kb |
| Host | smart-b1c9726c-39f0-4bd6-a6a1-94f2e641b5b3 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=36312112563986069468877367369525384968460321653883180832589858307039653834292 -assert nopostproc +UVM_TES TNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 40.uart_perf.36312112563986069468877367369525384968460321653883180832589858307039653834292 |
| Directory | /workspace/40.uart_perf/latest |
| Test location | /workspace/coverage/default/40.uart_rx_oversample.109703769083734556036139645264511385915882217754211625605275348080493888819998 |
| Short name | T799 |
| Test name | |
| Test status | |
| Simulation time | 4370280281 ps |
| CPU time | 19.81 seconds |
| Started | Nov 22 01:45:11 PM PST 23 |
| Finished | Nov 22 01:45:32 PM PST 23 |
| Peak memory | 198964 kb |
| Host | smart-04410202-4d71-4be3-ba76-56e24ed77453 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=109703769083734556036139645264511385915882217754211625605275348080493888819998 -assert nopostproc +UVM_TE STNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_oversample.109703769083734556036139645264511385915882217754211625605275348080493888819998 |
| Directory | /workspace/40.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/40.uart_rx_parity_err.71848349575101765602998641380956492533344783519910111680246075042066781934179 |
| Short name | T938 |
| Test name | |
| Test status | |
| Simulation time | 36616611594 ps |
| CPU time | 37.88 seconds |
| Started | Nov 22 01:45:27 PM PST 23 |
| Finished | Nov 22 01:46:07 PM PST 23 |
| Peak memory | 200128 kb |
| Host | smart-9dbbfa33-df26-4161-9ebe-eab0f18e1c32 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=71848349575101765602998641380956492533344783519910111680246075042066781934179 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 40.uart_rx_parity_err.71848349575101765602998641380956492533344783519910111680246075042066781934179 |
| Directory | /workspace/40.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/40.uart_rx_start_bit_filter.84975533990115551987379552993519249557723228594350778823927762192665899231680 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 4267638245 ps |
| CPU time | 4.64 seconds |
| Started | Nov 22 01:45:29 PM PST 23 |
| Finished | Nov 22 01:45:36 PM PST 23 |
| Peak memory | 196016 kb |
| Host | smart-7b234007-fd34-41bf-a55d-37fab1d90f56 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=84975533990115551987379552993519249557723228594350778823927762192665899231680 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 40.uart_rx_start_bit_filter.84975533990115551987379552993519249557723228594350778823927762192665899231680 |
| Directory | /workspace/40.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/40.uart_smoke.44281972276278912595941818886968355612457688060527561074322771124818568746665 |
| Short name | T983 |
| Test name | |
| Test status | |
| Simulation time | 5759626309 ps |
| CPU time | 18.77 seconds |
| Started | Nov 22 01:45:10 PM PST 23 |
| Finished | Nov 22 01:45:30 PM PST 23 |
| Peak memory | 199652 kb |
| Host | smart-4ac18232-f98f-43f3-a739-c55e83f0920e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=44281972276278912595941818886968355612457688060527561074322771124818568746665 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 40.uart_smoke.44281972276278912595941818886968355612457688060527561074322771124818568746665 |
| Directory | /workspace/40.uart_smoke/latest |
| Test location | /workspace/coverage/default/40.uart_stress_all.107387664499045918456477361572946756238261533514504238182722367113375869922509 |
| Short name | T927 |
| Test name | |
| Test status | |
| Simulation time | 43402307308 ps |
| CPU time | 58.22 seconds |
| Started | Nov 22 01:45:27 PM PST 23 |
| Finished | Nov 22 01:46:27 PM PST 23 |
| Peak memory | 200100 kb |
| Host | smart-a8bd44d6-df24-412b-9ab8-c9cbb212d53c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107387664499045918456477361572946756238261533514504238182722367113375869922509 -assert nopo stproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 40.uart_stress_all.107387664499045918456477361572946756238261533514504238182722367113375869922509 |
| Directory | /workspace/40.uart_stress_all/latest |
| Test location | /workspace/coverage/default/40.uart_stress_all_with_rand_reset.115499865782614522586696904004491184079581682270610000452850644689503007715988 |
| Short name | T996 |
| Test name | |
| Test status | |
| Simulation time | 87476847566 ps |
| CPU time | 466.11 seconds |
| Started | Nov 22 01:45:27 PM PST 23 |
| Finished | Nov 22 01:53:15 PM PST 23 |
| Peak memory | 226208 kb |
| Host | smart-016e3a3f-d878-4dba-9b84-31c2695e0555 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11549986578261452258669690 4004491184079581682270610000452850644689503007715988 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_stress_all_with_rand_reset.115499865782 614522586696904004491184079581682270610000452850644689503007715988 |
| Directory | /workspace/40.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/40.uart_tx_ovrd.74010556071329412542516679841726453409442905914491652687328527496142691575429 |
| Short name | T1196 |
| Test name | |
| Test status | |
| Simulation time | 485186362 ps |
| CPU time | 1.28 seconds |
| Started | Nov 22 01:45:12 PM PST 23 |
| Finished | Nov 22 01:45:15 PM PST 23 |
| Peak memory | 197968 kb |
| Host | smart-1982c504-95f4-4fd7-8182-b13d704976b5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=74010556071329412542516679841726453409442905914491652687328527496142691575429 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 40.uart_tx_ovrd.74010556071329412542516679841726453409442905914491652687328527496142691575429 |
| Directory | /workspace/40.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/40.uart_tx_rx.5764838048310084661811161996922429549543207407862229884784706105690687002811 |
| Short name | T944 |
| Test name | |
| Test status | |
| Simulation time | 57391945390 ps |
| CPU time | 62.87 seconds |
| Started | Nov 22 01:45:27 PM PST 23 |
| Finished | Nov 22 01:46:32 PM PST 23 |
| Peak memory | 199988 kb |
| Host | smart-30bd381c-5c0e-4929-a2c1-4d54c77b3d4e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=5764838048310084661811161996922429549543207407862229884784706105690687002811 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 40.uart_tx_rx.5764838048310084661811161996922429549543207407862229884784706105690687002811 |
| Directory | /workspace/40.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/41.uart_alert_test.91632777547508679623155021557112030696375010233974610121311811904344505331242 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 16368684 ps |
| CPU time | 0.54 seconds |
| Started | Nov 22 01:45:25 PM PST 23 |
| Finished | Nov 22 01:45:26 PM PST 23 |
| Peak memory | 194536 kb |
| Host | smart-18b51278-a82a-4151-945e-260f7978b884 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91632777547508679623155021557112030696375010233974610121311811904344505331242 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 41.uart_alert_test.91632777547508679623155021557112030696375010233974610121311811904344505331242 |
| Directory | /workspace/41.uart_alert_test/latest |
| Test location | /workspace/coverage/default/41.uart_fifo_full.4137142200850123217026249866953882352443163092632369062801809750923202965452 |
| Short name | T1171 |
| Test name | |
| Test status | |
| Simulation time | 61777160308 ps |
| CPU time | 60.84 seconds |
| Started | Nov 22 01:45:13 PM PST 23 |
| Finished | Nov 22 01:46:15 PM PST 23 |
| Peak memory | 199956 kb |
| Host | smart-12a5fe34-122a-4f80-a910-26b3c0f14a4f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4137142200850123217026249866953882352443163092632369062801809750923202965452 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 41.uart_fifo_full.4137142200850123217026249866953882352443163092632369062801809750923202965452 |
| Directory | /workspace/41.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/41.uart_fifo_overflow.48686991827721548428777006912173907981209441640908382785731750200458740623377 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 58551936110 ps |
| CPU time | 54.58 seconds |
| Started | Nov 22 01:45:24 PM PST 23 |
| Finished | Nov 22 01:46:20 PM PST 23 |
| Peak memory | 199800 kb |
| Host | smart-c036291f-a3b5-444f-a701-f56420f95224 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=48686991827721548428777006912173907981209441640908382785731750200458740623377 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 41.uart_fifo_overflow.48686991827721548428777006912173907981209441640908382785731750200458740623377 |
| Directory | /workspace/41.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/41.uart_fifo_reset.78384399801719164354912184953479001686121615078890776301178898871231195195815 |
| Short name | T934 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 113.07 seconds |
| Started | Nov 22 01:45:10 PM PST 23 |
| Finished | Nov 22 01:47:04 PM PST 23 |
| Peak memory | 198860 kb |
| Host | smart-c7f50b0e-e9dc-4261-955b-33979fdf2773 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=78384399801719164354912184953479001686121615078890776301178898871231195195815 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 41.uart_fifo_reset.78384399801719164354912184953479001686121615078890776301178898871231195195815 |
| Directory | /workspace/41.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/41.uart_intr.31734085712576585433266208737559345131441459198788137436449516252046491717174 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 787145125175 ps |
| CPU time | 785.37 seconds |
| Started | Nov 22 01:45:09 PM PST 23 |
| Finished | Nov 22 01:58:16 PM PST 23 |
| Peak memory | 200104 kb |
| Host | smart-42bae51d-67da-439f-ba52-448424ffcb51 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31734085712576585433266208737559345131441459198788137436449516252046491717174 -assert nopost proc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 41.uart_intr.31734085712576585433266208737559345131441459198788137436449516252046491717174 |
| Directory | /workspace/41.uart_intr/latest |
| Test location | /workspace/coverage/default/41.uart_loopback.95157036925173832409105926994794098017718728643124793708616061016780393911318 |
| Short name | T1156 |
| Test name | |
| Test status | |
| Simulation time | 14572448663 ps |
| CPU time | 16.45 seconds |
| Started | Nov 22 01:45:06 PM PST 23 |
| Finished | Nov 22 01:45:24 PM PST 23 |
| Peak memory | 200036 kb |
| Host | smart-fd02eb97-54bc-4c0a-9798-4557206cefc1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=95157036925173832409105926994794098017718728643124793708616061016780393911318 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 41.uart_loopback.95157036925173832409105926994794098017718728643124793708616061016780393911318 |
| Directory | /workspace/41.uart_loopback/latest |
| Test location | /workspace/coverage/default/41.uart_noise_filter.1215580713192241130271639942427844263988014404871856512279904538209042163494 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 94501577082 ps |
| CPU time | 97.68 seconds |
| Started | Nov 22 01:45:41 PM PST 23 |
| Finished | Nov 22 01:47:21 PM PST 23 |
| Peak memory | 200232 kb |
| Host | smart-83e589d6-52c0-4007-928a-e809c46ac2d7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1215580713192241130271639942427844263988014404871856512279904538209042163494 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_noise_filter.1215580713192241130271639942427844263988014404871856512279904538209042163494 |
| Directory | /workspace/41.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/41.uart_perf.23131206601258122050436523693366590483339236956169929271881164868119453542803 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 14098773881 ps |
| CPU time | 472.15 seconds |
| Started | Nov 22 01:45:40 PM PST 23 |
| Finished | Nov 22 01:53:34 PM PST 23 |
| Peak memory | 200152 kb |
| Host | smart-7f04198c-a550-4edd-b29c-b77a6113ca7d |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=23131206601258122050436523693366590483339236956169929271881164868119453542803 -assert nopostproc +UVM_TES TNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 41.uart_perf.23131206601258122050436523693366590483339236956169929271881164868119453542803 |
| Directory | /workspace/41.uart_perf/latest |
| Test location | /workspace/coverage/default/41.uart_rx_oversample.3622319063663328020557575502886439700487943901653242681331195900761688917632 |
| Short name | T713 |
| Test name | |
| Test status | |
| Simulation time | 4370280281 ps |
| CPU time | 20.4 seconds |
| Started | Nov 22 01:45:21 PM PST 23 |
| Finished | Nov 22 01:45:43 PM PST 23 |
| Peak memory | 198980 kb |
| Host | smart-62bd698a-c127-40eb-8782-fd7a0361d437 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3622319063663328020557575502886439700487943901653242681331195900761688917632 -assert nopostproc +UVM_TEST NAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 41.uart_rx_oversample.3622319063663328020557575502886439700487943901653242681331195900761688917632 |
| Directory | /workspace/41.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/41.uart_rx_parity_err.65926088163118989825038391388604290947778706559306403786418808203459626637859 |
| Short name | T706 |
| Test name | |
| Test status | |
| Simulation time | 36616611594 ps |
| CPU time | 38.16 seconds |
| Started | Nov 22 01:45:13 PM PST 23 |
| Finished | Nov 22 01:45:52 PM PST 23 |
| Peak memory | 200084 kb |
| Host | smart-7021906e-5438-4b4b-ae78-70fff86c1c80 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=65926088163118989825038391388604290947778706559306403786418808203459626637859 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 41.uart_rx_parity_err.65926088163118989825038391388604290947778706559306403786418808203459626637859 |
| Directory | /workspace/41.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/41.uart_rx_start_bit_filter.60602670280825486519202609364386915777566216800244894992327538427339095168398 |
| Short name | T1013 |
| Test name | |
| Test status | |
| Simulation time | 4267638245 ps |
| CPU time | 4.69 seconds |
| Started | Nov 22 01:45:07 PM PST 23 |
| Finished | Nov 22 01:45:13 PM PST 23 |
| Peak memory | 195904 kb |
| Host | smart-b76afc70-2caf-40df-9cbc-9ab4d1a66454 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=60602670280825486519202609364386915777566216800244894992327538427339095168398 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 41.uart_rx_start_bit_filter.60602670280825486519202609364386915777566216800244894992327538427339095168398 |
| Directory | /workspace/41.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/41.uart_smoke.56030584393214506193779522500481749407524504774912462890443716693734641443117 |
| Short name | T715 |
| Test name | |
| Test status | |
| Simulation time | 5759626309 ps |
| CPU time | 18.39 seconds |
| Started | Nov 22 01:45:26 PM PST 23 |
| Finished | Nov 22 01:45:45 PM PST 23 |
| Peak memory | 199620 kb |
| Host | smart-ceec8761-337b-4a4b-842b-d353268c2ef7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=56030584393214506193779522500481749407524504774912462890443716693734641443117 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 41.uart_smoke.56030584393214506193779522500481749407524504774912462890443716693734641443117 |
| Directory | /workspace/41.uart_smoke/latest |
| Test location | /workspace/coverage/default/41.uart_stress_all.58357110284940404306233316622972924322235925157205889311319535814665257363088 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 43402307308 ps |
| CPU time | 56.21 seconds |
| Started | Nov 22 01:45:36 PM PST 23 |
| Finished | Nov 22 01:46:33 PM PST 23 |
| Peak memory | 199988 kb |
| Host | smart-847b96f9-c933-4a58-86c8-23e4f8dc4090 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58357110284940404306233316622972924322235925157205889311319535814665257363088 -assert nopos tproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 41.uart_stress_all.58357110284940404306233316622972924322235925157205889311319535814665257363088 |
| Directory | /workspace/41.uart_stress_all/latest |
| Test location | /workspace/coverage/default/41.uart_stress_all_with_rand_reset.42364819454578637460265539742825362361921446697170537413616855142460155831375 |
| Short name | T1174 |
| Test name | |
| Test status | |
| Simulation time | 87476847566 ps |
| CPU time | 456.59 seconds |
| Started | Nov 22 01:45:27 PM PST 23 |
| Finished | Nov 22 01:53:05 PM PST 23 |
| Peak memory | 226248 kb |
| Host | smart-008c40ec-cb43-418c-bc7e-d1ef2aa10ef0 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42364819454578637460265539 742825362361921446697170537413616855142460155831375 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_stress_all_with_rand_reset.4236481945457 8637460265539742825362361921446697170537413616855142460155831375 |
| Directory | /workspace/41.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/41.uart_tx_ovrd.53138491098308859534085244066808002624827250329775517460083058052490135395395 |
| Short name | T775 |
| Test name | |
| Test status | |
| Simulation time | 485186362 ps |
| CPU time | 1.28 seconds |
| Started | Nov 22 01:45:27 PM PST 23 |
| Finished | Nov 22 01:45:30 PM PST 23 |
| Peak memory | 197896 kb |
| Host | smart-01b10f06-6f15-4d56-8bd0-bc81d7dd22a4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=53138491098308859534085244066808002624827250329775517460083058052490135395395 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 41.uart_tx_ovrd.53138491098308859534085244066808002624827250329775517460083058052490135395395 |
| Directory | /workspace/41.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/42.uart_alert_test.106268104049458882679840735333146095657277017908901524535850527089959022527027 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 16368684 ps |
| CPU time | 0.55 seconds |
| Started | Nov 22 01:45:27 PM PST 23 |
| Finished | Nov 22 01:45:29 PM PST 23 |
| Peak memory | 194612 kb |
| Host | smart-dc5c29cb-3359-472b-895d-fca9a2ca01b4 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106268104049458882679840735333146095657277017908901524535850527089959022527027 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 42.uart_alert_test.106268104049458882679840735333146095657277017908901524535850527089959022527027 |
| Directory | /workspace/42.uart_alert_test/latest |
| Test location | /workspace/coverage/default/42.uart_fifo_full.82401387980820822739594350344378294215816280636349467981449141547437865345074 |
| Short name | T1063 |
| Test name | |
| Test status | |
| Simulation time | 61777160308 ps |
| CPU time | 60.67 seconds |
| Started | Nov 22 01:45:24 PM PST 23 |
| Finished | Nov 22 01:46:26 PM PST 23 |
| Peak memory | 200032 kb |
| Host | smart-279e1a26-49ad-44a5-809c-23398b892c46 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=82401387980820822739594350344378294215816280636349467981449141547437865345074 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 42.uart_fifo_full.82401387980820822739594350344378294215816280636349467981449141547437865345074 |
| Directory | /workspace/42.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/42.uart_fifo_overflow.60829854666678324987145924254659025456882848048644719361200121718673509659095 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 58551936110 ps |
| CPU time | 54.2 seconds |
| Started | Nov 22 01:45:12 PM PST 23 |
| Finished | Nov 22 01:46:08 PM PST 23 |
| Peak memory | 199892 kb |
| Host | smart-73a349c1-0970-4f2b-869c-eb4378f14cbe |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=60829854666678324987145924254659025456882848048644719361200121718673509659095 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 42.uart_fifo_overflow.60829854666678324987145924254659025456882848048644719361200121718673509659095 |
| Directory | /workspace/42.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/42.uart_fifo_reset.95564228226905533954605918253760324207362111059918906803444989899967309387443 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 113.53 seconds |
| Started | Nov 22 01:45:08 PM PST 23 |
| Finished | Nov 22 01:47:03 PM PST 23 |
| Peak memory | 198852 kb |
| Host | smart-a548ecae-8ade-48de-af75-8fc1c07f8c90 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=95564228226905533954605918253760324207362111059918906803444989899967309387443 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 42.uart_fifo_reset.95564228226905533954605918253760324207362111059918906803444989899967309387443 |
| Directory | /workspace/42.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/42.uart_intr.93317799923873133610753507310141132500173482049124235698083706747878669971100 |
| Short name | T969 |
| Test name | |
| Test status | |
| Simulation time | 787145125175 ps |
| CPU time | 783.4 seconds |
| Started | Nov 22 01:45:24 PM PST 23 |
| Finished | Nov 22 01:58:28 PM PST 23 |
| Peak memory | 200100 kb |
| Host | smart-dd4e08fa-57c4-4326-af7a-fb0429a2bff6 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93317799923873133610753507310141132500173482049124235698083706747878669971100 -assert nopost proc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 42.uart_intr.93317799923873133610753507310141132500173482049124235698083706747878669971100 |
| Directory | /workspace/42.uart_intr/latest |
| Test location | /workspace/coverage/default/42.uart_long_xfer_wo_dly.14437311801009239776249658845982011573796020143432638301308164630591233517027 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 93387746707 ps |
| CPU time | 351.08 seconds |
| Started | Nov 22 01:45:13 PM PST 23 |
| Finished | Nov 22 01:51:05 PM PST 23 |
| Peak memory | 200164 kb |
| Host | smart-9ed84fb1-93af-4c34-b46e-0ce35ee4c3e6 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=14437311801009239776249658845982011573796020143432638301308164630591233517027 -assert nopostproc +UVM_TES TNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 42.uart_long_xfer_wo_dly.14437311801009239776249658845982011573796020143432638301308164630591233517027 |
| Directory | /workspace/42.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/42.uart_loopback.956691849125733551684962314269524581100561500542704430089933451823972133603 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 14572448663 ps |
| CPU time | 16.13 seconds |
| Started | Nov 22 01:45:26 PM PST 23 |
| Finished | Nov 22 01:45:44 PM PST 23 |
| Peak memory | 199952 kb |
| Host | smart-487500ba-87a3-4435-9cdb-eda971964061 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=956691849125733551684962314269524581100561500542704430089933451823972133603 -assert nopostproc +UVM_TESTNAME=uart_base_t est +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 42.uart_loopback.956691849125733551684962314269524581100561500542704430089933451823972133603 |
| Directory | /workspace/42.uart_loopback/latest |
| Test location | /workspace/coverage/default/42.uart_noise_filter.60801339974089000001803204925717041936656863358444138565737701256911223770232 |
| Short name | T1091 |
| Test name | |
| Test status | |
| Simulation time | 94501577082 ps |
| CPU time | 96.78 seconds |
| Started | Nov 22 01:45:06 PM PST 23 |
| Finished | Nov 22 01:46:44 PM PST 23 |
| Peak memory | 200216 kb |
| Host | smart-59d4d701-9f08-484a-a1ed-db74b7115cb0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=60801339974089000001803204925717041936656863358444138565737701256911223770232 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_noise_filter.60801339974089000001803204925717041936656863358444138565737701256911223770232 |
| Directory | /workspace/42.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/42.uart_perf.6527008273071337004346183141174080164604964226158583018542243963519716533351 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 14098773881 ps |
| CPU time | 456.73 seconds |
| Started | Nov 22 01:45:27 PM PST 23 |
| Finished | Nov 22 01:53:06 PM PST 23 |
| Peak memory | 200044 kb |
| Host | smart-b06f0231-47f5-4cb3-963c-2365eb5aa33f |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=6527008273071337004346183141174080164604964226158583018542243963519716533351 -assert nopostproc +UVM_TEST NAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 42.uart_perf.6527008273071337004346183141174080164604964226158583018542243963519716533351 |
| Directory | /workspace/42.uart_perf/latest |
| Test location | /workspace/coverage/default/42.uart_rx_oversample.99331593468048525853915015812071835346282828530850695199302276791311957291792 |
| Short name | T1205 |
| Test name | |
| Test status | |
| Simulation time | 4370280281 ps |
| CPU time | 19.92 seconds |
| Started | Nov 22 01:45:29 PM PST 23 |
| Finished | Nov 22 01:45:51 PM PST 23 |
| Peak memory | 198972 kb |
| Host | smart-742de12c-718d-4305-9bb4-49984dd6fb44 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=99331593468048525853915015812071835346282828530850695199302276791311957291792 -assert nopostproc +UVM_TES TNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 42.uart_rx_oversample.99331593468048525853915015812071835346282828530850695199302276791311957291792 |
| Directory | /workspace/42.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/42.uart_rx_parity_err.98746182083800611017301176460949444224439869613790167504008228470968570496262 |
| Short name | T1031 |
| Test name | |
| Test status | |
| Simulation time | 36616611594 ps |
| CPU time | 38.1 seconds |
| Started | Nov 22 01:45:21 PM PST 23 |
| Finished | Nov 22 01:46:00 PM PST 23 |
| Peak memory | 200136 kb |
| Host | smart-6e0b6fff-47f9-4f9f-921f-9a7084370677 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=98746182083800611017301176460949444224439869613790167504008228470968570496262 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 42.uart_rx_parity_err.98746182083800611017301176460949444224439869613790167504008228470968570496262 |
| Directory | /workspace/42.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/42.uart_rx_start_bit_filter.61779668423226892766180351304824196495514139076075789214340058615521371002202 |
| Short name | T712 |
| Test name | |
| Test status | |
| Simulation time | 4267638245 ps |
| CPU time | 4.71 seconds |
| Started | Nov 22 01:45:27 PM PST 23 |
| Finished | Nov 22 01:45:33 PM PST 23 |
| Peak memory | 196004 kb |
| Host | smart-52ab71c9-b8d4-4cf3-81d6-758c1769f5f0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=61779668423226892766180351304824196495514139076075789214340058615521371002202 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 42.uart_rx_start_bit_filter.61779668423226892766180351304824196495514139076075789214340058615521371002202 |
| Directory | /workspace/42.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/42.uart_smoke.54877824421934193642255405879651272692874761737910067446450078868812559822590 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 5759626309 ps |
| CPU time | 18.19 seconds |
| Started | Nov 22 01:45:27 PM PST 23 |
| Finished | Nov 22 01:45:47 PM PST 23 |
| Peak memory | 199588 kb |
| Host | smart-980ea022-55e3-4154-92bb-ce9f73a51de5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=54877824421934193642255405879651272692874761737910067446450078868812559822590 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 42.uart_smoke.54877824421934193642255405879651272692874761737910067446450078868812559822590 |
| Directory | /workspace/42.uart_smoke/latest |
| Test location | /workspace/coverage/default/42.uart_stress_all.50510992513015937859469234961766277679262447126598984042229581925394305289426 |
| Short name | T1148 |
| Test name | |
| Test status | |
| Simulation time | 43402307308 ps |
| CPU time | 56.84 seconds |
| Started | Nov 22 01:45:30 PM PST 23 |
| Finished | Nov 22 01:46:29 PM PST 23 |
| Peak memory | 200100 kb |
| Host | smart-fb5cca06-c615-4b93-bebf-52c64da3025c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50510992513015937859469234961766277679262447126598984042229581925394305289426 -assert nopos tproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 42.uart_stress_all.50510992513015937859469234961766277679262447126598984042229581925394305289426 |
| Directory | /workspace/42.uart_stress_all/latest |
| Test location | /workspace/coverage/default/42.uart_stress_all_with_rand_reset.34868979438291827851392449152037406762093634068267172495953837557873066226885 |
| Short name | T711 |
| Test name | |
| Test status | |
| Simulation time | 87476847566 ps |
| CPU time | 467.11 seconds |
| Started | Nov 22 01:45:24 PM PST 23 |
| Finished | Nov 22 01:53:13 PM PST 23 |
| Peak memory | 226228 kb |
| Host | smart-574da288-373a-4259-8ac2-841e34af06a6 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34868979438291827851392449 152037406762093634068267172495953837557873066226885 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_stress_all_with_rand_reset.3486897943829 1827851392449152037406762093634068267172495953837557873066226885 |
| Directory | /workspace/42.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/42.uart_tx_ovrd.63373627913230786915401852466417688577807922154733076226977901449293725983642 |
| Short name | T788 |
| Test name | |
| Test status | |
| Simulation time | 485186362 ps |
| CPU time | 1.27 seconds |
| Started | Nov 22 01:45:27 PM PST 23 |
| Finished | Nov 22 01:45:29 PM PST 23 |
| Peak memory | 197912 kb |
| Host | smart-b0510545-119b-42de-b869-8b428fcba7ef |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=63373627913230786915401852466417688577807922154733076226977901449293725983642 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 42.uart_tx_ovrd.63373627913230786915401852466417688577807922154733076226977901449293725983642 |
| Directory | /workspace/42.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/42.uart_tx_rx.1017609408106675776739478459966289360956076145758309474569835523212343080492 |
| Short name | T766 |
| Test name | |
| Test status | |
| Simulation time | 57391945390 ps |
| CPU time | 63.48 seconds |
| Started | Nov 22 01:45:09 PM PST 23 |
| Finished | Nov 22 01:46:14 PM PST 23 |
| Peak memory | 200060 kb |
| Host | smart-3f8cd177-03e6-43b0-bb60-19186f0312f1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1017609408106675776739478459966289360956076145758309474569835523212343080492 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 42.uart_tx_rx.1017609408106675776739478459966289360956076145758309474569835523212343080492 |
| Directory | /workspace/42.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/43.uart_alert_test.78519192687936516906119528473240060068448440350130181722162957993218795505984 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 16368684 ps |
| CPU time | 0.56 seconds |
| Started | Nov 22 01:46:10 PM PST 23 |
| Finished | Nov 22 01:46:16 PM PST 23 |
| Peak memory | 194584 kb |
| Host | smart-a1cfdee9-09d2-4687-8af3-a94948d3bec6 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78519192687936516906119528473240060068448440350130181722162957993218795505984 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 43.uart_alert_test.78519192687936516906119528473240060068448440350130181722162957993218795505984 |
| Directory | /workspace/43.uart_alert_test/latest |
| Test location | /workspace/coverage/default/43.uart_fifo_overflow.107619344224977800349836932579980999977283314840828637463740702567013090792598 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 58551936110 ps |
| CPU time | 54.65 seconds |
| Started | Nov 22 01:45:31 PM PST 23 |
| Finished | Nov 22 01:46:27 PM PST 23 |
| Peak memory | 199868 kb |
| Host | smart-a068f5e9-375a-42ae-8322-8f18deb88502 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=107619344224977800349836932579980999977283314840828637463740702567013090792598 -assert nopostproc +UVM_TESTNAME=uart_bas e_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 43.uart_fifo_overflow.107619344224977800349836932579980999977283314840828637463740702567013090792598 |
| Directory | /workspace/43.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/43.uart_fifo_reset.85549844903053648530870108986857447842159671519724017744824789380416583201896 |
| Short name | T895 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 113.46 seconds |
| Started | Nov 22 01:46:00 PM PST 23 |
| Finished | Nov 22 01:48:01 PM PST 23 |
| Peak memory | 198896 kb |
| Host | smart-bc40b133-4364-40c9-98be-b52e801e3a13 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=85549844903053648530870108986857447842159671519724017744824789380416583201896 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 43.uart_fifo_reset.85549844903053648530870108986857447842159671519724017744824789380416583201896 |
| Directory | /workspace/43.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/43.uart_intr.26036203699620632441668054566061044394254081798682510107807819405190366441898 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 787145125175 ps |
| CPU time | 780.67 seconds |
| Started | Nov 22 01:45:59 PM PST 23 |
| Finished | Nov 22 01:59:08 PM PST 23 |
| Peak memory | 200076 kb |
| Host | smart-6f0733f3-7581-4a5c-a96a-e96cba5d2c29 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26036203699620632441668054566061044394254081798682510107807819405190366441898 -assert nopost proc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 43.uart_intr.26036203699620632441668054566061044394254081798682510107807819405190366441898 |
| Directory | /workspace/43.uart_intr/latest |
| Test location | /workspace/coverage/default/43.uart_long_xfer_wo_dly.27272086316673389301665978900603483725530043954965687136449393173241425931929 |
| Short name | T1229 |
| Test name | |
| Test status | |
| Simulation time | 93387746707 ps |
| CPU time | 353.73 seconds |
| Started | Nov 22 01:45:59 PM PST 23 |
| Finished | Nov 22 01:52:02 PM PST 23 |
| Peak memory | 200136 kb |
| Host | smart-64d19e50-28f2-4d1c-951b-cc1f555f3f96 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=27272086316673389301665978900603483725530043954965687136449393173241425931929 -assert nopostproc +UVM_TES TNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 43.uart_long_xfer_wo_dly.27272086316673389301665978900603483725530043954965687136449393173241425931929 |
| Directory | /workspace/43.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/43.uart_loopback.6633582879843174254510834215383474470842413912059430618452906149541824326635 |
| Short name | T1062 |
| Test name | |
| Test status | |
| Simulation time | 14572448663 ps |
| CPU time | 16.18 seconds |
| Started | Nov 22 01:45:46 PM PST 23 |
| Finished | Nov 22 01:46:04 PM PST 23 |
| Peak memory | 200024 kb |
| Host | smart-d5cf6682-e8cb-4b84-be4d-d215c2b03974 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=6633582879843174254510834215383474470842413912059430618452906149541824326635 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 43.uart_loopback.6633582879843174254510834215383474470842413912059430618452906149541824326635 |
| Directory | /workspace/43.uart_loopback/latest |
| Test location | /workspace/coverage/default/43.uart_noise_filter.107149718281701441289846674910028010731141696128521864282964226437246561931521 |
| Short name | T909 |
| Test name | |
| Test status | |
| Simulation time | 94501577082 ps |
| CPU time | 95.99 seconds |
| Started | Nov 22 01:46:00 PM PST 23 |
| Finished | Nov 22 01:47:43 PM PST 23 |
| Peak memory | 200240 kb |
| Host | smart-462ce492-3419-4d14-b3f6-2340b422e0c8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=107149718281701441289846674910028010731141696128521864282964226437246561931521 -assert nopostproc +UVM_TESTNAME=uart_bas e_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 43.uart_noise_filter.107149718281701441289846674910028010731141696128521864282964226437246561931521 |
| Directory | /workspace/43.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/43.uart_perf.45020787928625614531703447523152735113607683484547265658293407264560642291992 |
| Short name | T707 |
| Test name | |
| Test status | |
| Simulation time | 14098773881 ps |
| CPU time | 464.03 seconds |
| Started | Nov 22 01:46:02 PM PST 23 |
| Finished | Nov 22 01:53:52 PM PST 23 |
| Peak memory | 200156 kb |
| Host | smart-9beb9945-0ae5-42a4-b9a3-e837f91fb5fe |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=45020787928625614531703447523152735113607683484547265658293407264560642291992 -assert nopostproc +UVM_TES TNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 43.uart_perf.45020787928625614531703447523152735113607683484547265658293407264560642291992 |
| Directory | /workspace/43.uart_perf/latest |
| Test location | /workspace/coverage/default/43.uart_rx_oversample.1807583120637124884502345799598955591013027811806565554398227037525709043280 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 4370280281 ps |
| CPU time | 20.36 seconds |
| Started | Nov 22 01:45:33 PM PST 23 |
| Finished | Nov 22 01:45:54 PM PST 23 |
| Peak memory | 198956 kb |
| Host | smart-4ef1690b-acf0-4869-9fc1-5a50afd719ed |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1807583120637124884502345799598955591013027811806565554398227037525709043280 -assert nopostproc +UVM_TEST NAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 43.uart_rx_oversample.1807583120637124884502345799598955591013027811806565554398227037525709043280 |
| Directory | /workspace/43.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/43.uart_rx_parity_err.1249233049300336431536103606729782325241047847385715943940590177841784020366 |
| Short name | T779 |
| Test name | |
| Test status | |
| Simulation time | 36616611594 ps |
| CPU time | 38.35 seconds |
| Started | Nov 22 01:45:54 PM PST 23 |
| Finished | Nov 22 01:46:36 PM PST 23 |
| Peak memory | 200092 kb |
| Host | smart-417e7f54-f5b9-43d6-b92f-5db945eb92be |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1249233049300336431536103606729782325241047847385715943940590177841784020366 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_parity_err.1249233049300336431536103606729782325241047847385715943940590177841784020366 |
| Directory | /workspace/43.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/43.uart_rx_start_bit_filter.109723613647281799839227930277242571902703867267719209399441219628482781790608 |
| Short name | T1142 |
| Test name | |
| Test status | |
| Simulation time | 4267638245 ps |
| CPU time | 4.7 seconds |
| Started | Nov 22 01:46:00 PM PST 23 |
| Finished | Nov 22 01:46:12 PM PST 23 |
| Peak memory | 195976 kb |
| Host | smart-a7dd0fb8-f7c6-4ece-b91b-4c1a2c2f7806 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=109723613647281799839227930277242571902703867267719209399441219628482781790608 -assert nopostproc +UVM_TESTNAME=uart_bas e_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 43.uart_rx_start_bit_filter.109723613647281799839227930277242571902703867267719209399441219628482781790608 |
| Directory | /workspace/43.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/43.uart_smoke.80973090374936647652155381196245168779927077285568793811999888619630366025871 |
| Short name | T793 |
| Test name | |
| Test status | |
| Simulation time | 5759626309 ps |
| CPU time | 17.81 seconds |
| Started | Nov 22 01:45:50 PM PST 23 |
| Finished | Nov 22 01:46:10 PM PST 23 |
| Peak memory | 199484 kb |
| Host | smart-2855e1dd-7bfd-4913-80df-3112b38fee41 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=80973090374936647652155381196245168779927077285568793811999888619630366025871 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 43.uart_smoke.80973090374936647652155381196245168779927077285568793811999888619630366025871 |
| Directory | /workspace/43.uart_smoke/latest |
| Test location | /workspace/coverage/default/43.uart_stress_all.31362165540371815574409350495313349762333901581363211187997710219617728863213 |
| Short name | T757 |
| Test name | |
| Test status | |
| Simulation time | 43402307308 ps |
| CPU time | 57.1 seconds |
| Started | Nov 22 01:45:42 PM PST 23 |
| Finished | Nov 22 01:46:41 PM PST 23 |
| Peak memory | 200080 kb |
| Host | smart-5464822e-b5fd-4fe2-8952-0ba38d7e2dde |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31362165540371815574409350495313349762333901581363211187997710219617728863213 -assert nopos tproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 43.uart_stress_all.31362165540371815574409350495313349762333901581363211187997710219617728863213 |
| Directory | /workspace/43.uart_stress_all/latest |
| Test location | /workspace/coverage/default/43.uart_stress_all_with_rand_reset.112209914880090895187716202596574717257274686632741806065350144188677294279711 |
| Short name | T898 |
| Test name | |
| Test status | |
| Simulation time | 87476847566 ps |
| CPU time | 463.38 seconds |
| Started | Nov 22 01:45:57 PM PST 23 |
| Finished | Nov 22 01:53:47 PM PST 23 |
| Peak memory | 226240 kb |
| Host | smart-f6456d1b-56c0-44e2-b5f4-9a7a4cbc1bbd |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11220991488009089518771620 2596574717257274686632741806065350144188677294279711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_stress_all_with_rand_reset.112209914880 090895187716202596574717257274686632741806065350144188677294279711 |
| Directory | /workspace/43.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/43.uart_tx_ovrd.111766555183430797002695083517848072456052220856262234328672713330066681929267 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 485186362 ps |
| CPU time | 1.27 seconds |
| Started | Nov 22 01:45:40 PM PST 23 |
| Finished | Nov 22 01:45:43 PM PST 23 |
| Peak memory | 197936 kb |
| Host | smart-cae9714a-14d2-40b8-a51f-d987be1181fa |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=111766555183430797002695083517848072456052220856262234328672713330066681929267 -assert nopostproc +UVM_TESTNAME=uart_bas e_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 43.uart_tx_ovrd.111766555183430797002695083517848072456052220856262234328672713330066681929267 |
| Directory | /workspace/43.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/43.uart_tx_rx.48800598862013640459172526422922507419141145001958908792495468460845985749342 |
| Short name | T1009 |
| Test name | |
| Test status | |
| Simulation time | 57391945390 ps |
| CPU time | 63.59 seconds |
| Started | Nov 22 01:45:39 PM PST 23 |
| Finished | Nov 22 01:46:44 PM PST 23 |
| Peak memory | 200076 kb |
| Host | smart-393abcef-d17e-4e10-a23f-e66dfac3d7d4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=48800598862013640459172526422922507419141145001958908792495468460845985749342 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 43.uart_tx_rx.48800598862013640459172526422922507419141145001958908792495468460845985749342 |
| Directory | /workspace/43.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/44.uart_alert_test.57552881178229913936685400126141013537922124930066447559639587172527126966231 |
| Short name | T1251 |
| Test name | |
| Test status | |
| Simulation time | 16368684 ps |
| CPU time | 0.54 seconds |
| Started | Nov 22 01:45:26 PM PST 23 |
| Finished | Nov 22 01:45:27 PM PST 23 |
| Peak memory | 194608 kb |
| Host | smart-8072011e-00da-4a8f-bc47-354ada028f47 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57552881178229913936685400126141013537922124930066447559639587172527126966231 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 44.uart_alert_test.57552881178229913936685400126141013537922124930066447559639587172527126966231 |
| Directory | /workspace/44.uart_alert_test/latest |
| Test location | /workspace/coverage/default/44.uart_fifo_full.107133407827319740409076467839426498906181353977784091285118180384953822078123 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 61777160308 ps |
| CPU time | 60.34 seconds |
| Started | Nov 22 01:46:19 PM PST 23 |
| Finished | Nov 22 01:47:21 PM PST 23 |
| Peak memory | 200048 kb |
| Host | smart-1568362c-a2cc-45ef-b809-b6c503eaa2f1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=107133407827319740409076467839426498906181353977784091285118180384953822078123 -assert nopostproc +UVM_TESTNAME=uart_bas e_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 44.uart_fifo_full.107133407827319740409076467839426498906181353977784091285118180384953822078123 |
| Directory | /workspace/44.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/44.uart_fifo_overflow.6800012871809908961793219751399148879171336317368429236807788182327786153959 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 58551936110 ps |
| CPU time | 54.22 seconds |
| Started | Nov 22 01:46:24 PM PST 23 |
| Finished | Nov 22 01:47:20 PM PST 23 |
| Peak memory | 199884 kb |
| Host | smart-44738f29-5cb6-4abc-8a35-de79c794981a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=6800012871809908961793219751399148879171336317368429236807788182327786153959 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_overflow.6800012871809908961793219751399148879171336317368429236807788182327786153959 |
| Directory | /workspace/44.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/44.uart_fifo_reset.41525682047402521202072769371525287335526143458926473598338423571750087304448 |
| Short name | T759 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 113.23 seconds |
| Started | Nov 22 01:45:26 PM PST 23 |
| Finished | Nov 22 01:47:20 PM PST 23 |
| Peak memory | 198956 kb |
| Host | smart-d8d51a20-bc34-4fdf-9f50-e31766b64939 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=41525682047402521202072769371525287335526143458926473598338423571750087304448 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 44.uart_fifo_reset.41525682047402521202072769371525287335526143458926473598338423571750087304448 |
| Directory | /workspace/44.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/44.uart_intr.18860768918769605949320512375501452551827044274673748391678410719552267116860 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 787145125175 ps |
| CPU time | 786.81 seconds |
| Started | Nov 22 01:45:22 PM PST 23 |
| Finished | Nov 22 01:58:30 PM PST 23 |
| Peak memory | 200132 kb |
| Host | smart-f8369939-5c7f-4b05-83be-16d1a24e1c7a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18860768918769605949320512375501452551827044274673748391678410719552267116860 -assert nopost proc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 44.uart_intr.18860768918769605949320512375501452551827044274673748391678410719552267116860 |
| Directory | /workspace/44.uart_intr/latest |
| Test location | /workspace/coverage/default/44.uart_long_xfer_wo_dly.61048523946925116900921866258490153890244979454128334243655763850999530130131 |
| Short name | T1221 |
| Test name | |
| Test status | |
| Simulation time | 93387746707 ps |
| CPU time | 349.25 seconds |
| Started | Nov 22 01:45:30 PM PST 23 |
| Finished | Nov 22 01:51:21 PM PST 23 |
| Peak memory | 200144 kb |
| Host | smart-b51f46ae-69bb-4466-9c65-5cfad0b8ca46 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=61048523946925116900921866258490153890244979454128334243655763850999530130131 -assert nopostproc +UVM_TES TNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 44.uart_long_xfer_wo_dly.61048523946925116900921866258490153890244979454128334243655763850999530130131 |
| Directory | /workspace/44.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/44.uart_loopback.99867145444811855642055645619179463834833328709058882966902796059360808098511 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 14572448663 ps |
| CPU time | 16.09 seconds |
| Started | Nov 22 01:45:29 PM PST 23 |
| Finished | Nov 22 01:45:47 PM PST 23 |
| Peak memory | 200004 kb |
| Host | smart-ae6b689d-dec4-492b-a72c-7841436fba76 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=99867145444811855642055645619179463834833328709058882966902796059360808098511 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 44.uart_loopback.99867145444811855642055645619179463834833328709058882966902796059360808098511 |
| Directory | /workspace/44.uart_loopback/latest |
| Test location | /workspace/coverage/default/44.uart_noise_filter.29611639352089058337007136038798349458544052354910700996780332453376329855314 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 94501577082 ps |
| CPU time | 97.66 seconds |
| Started | Nov 22 01:45:24 PM PST 23 |
| Finished | Nov 22 01:47:03 PM PST 23 |
| Peak memory | 200312 kb |
| Host | smart-4e85c9ab-7a1e-4658-b42e-bc7442b6d000 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=29611639352089058337007136038798349458544052354910700996780332453376329855314 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_noise_filter.29611639352089058337007136038798349458544052354910700996780332453376329855314 |
| Directory | /workspace/44.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/44.uart_perf.57189568154236944048676429152987309542960818141577205165178477268755214192633 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 14098773881 ps |
| CPU time | 464.58 seconds |
| Started | Nov 22 01:45:36 PM PST 23 |
| Finished | Nov 22 01:53:22 PM PST 23 |
| Peak memory | 200120 kb |
| Host | smart-0ede3834-3e1c-4a67-bcc2-db611ef41d88 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=57189568154236944048676429152987309542960818141577205165178477268755214192633 -assert nopostproc +UVM_TES TNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 44.uart_perf.57189568154236944048676429152987309542960818141577205165178477268755214192633 |
| Directory | /workspace/44.uart_perf/latest |
| Test location | /workspace/coverage/default/44.uart_rx_oversample.22778046532251035282661658494797862767992213290939896765914098646961685639070 |
| Short name | T978 |
| Test name | |
| Test status | |
| Simulation time | 4370280281 ps |
| CPU time | 19.73 seconds |
| Started | Nov 22 01:45:27 PM PST 23 |
| Finished | Nov 22 01:45:49 PM PST 23 |
| Peak memory | 198964 kb |
| Host | smart-83c45fec-f79c-40d8-83e8-e5bfa034d591 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=22778046532251035282661658494797862767992213290939896765914098646961685639070 -assert nopostproc +UVM_TES TNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 44.uart_rx_oversample.22778046532251035282661658494797862767992213290939896765914098646961685639070 |
| Directory | /workspace/44.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/44.uart_rx_parity_err.34330950890048642768757515098214372430320115557576607144247439036637311876408 |
| Short name | T1054 |
| Test name | |
| Test status | |
| Simulation time | 36616611594 ps |
| CPU time | 38.28 seconds |
| Started | Nov 22 01:45:29 PM PST 23 |
| Finished | Nov 22 01:46:09 PM PST 23 |
| Peak memory | 200152 kb |
| Host | smart-4ba9b401-db24-43e4-a633-a30b19c77c2e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=34330950890048642768757515098214372430320115557576607144247439036637311876408 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 44.uart_rx_parity_err.34330950890048642768757515098214372430320115557576607144247439036637311876408 |
| Directory | /workspace/44.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/44.uart_rx_start_bit_filter.46809620717129553027379494471341164915763481958656536142664707739755371341939 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 4267638245 ps |
| CPU time | 4.66 seconds |
| Started | Nov 22 01:45:25 PM PST 23 |
| Finished | Nov 22 01:45:31 PM PST 23 |
| Peak memory | 195988 kb |
| Host | smart-b0ef5f1a-d60a-4b54-ad39-a0daff4dec9a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=46809620717129553027379494471341164915763481958656536142664707739755371341939 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 44.uart_rx_start_bit_filter.46809620717129553027379494471341164915763481958656536142664707739755371341939 |
| Directory | /workspace/44.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/44.uart_smoke.55584544027741372342081216208001301874796159499644680284125606896829907564167 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 5759626309 ps |
| CPU time | 18.07 seconds |
| Started | Nov 22 01:45:50 PM PST 23 |
| Finished | Nov 22 01:46:10 PM PST 23 |
| Peak memory | 199636 kb |
| Host | smart-6152fa5c-cfc9-49d7-b655-1c4327e16db5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=55584544027741372342081216208001301874796159499644680284125606896829907564167 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 44.uart_smoke.55584544027741372342081216208001301874796159499644680284125606896829907564167 |
| Directory | /workspace/44.uart_smoke/latest |
| Test location | /workspace/coverage/default/44.uart_stress_all.34675702517562619481158297454042233470999016747800957765847295869309377170537 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 43402307308 ps |
| CPU time | 57.18 seconds |
| Started | Nov 22 01:45:09 PM PST 23 |
| Finished | Nov 22 01:46:07 PM PST 23 |
| Peak memory | 200072 kb |
| Host | smart-79af9f21-9f28-45d0-9080-396d0354eaac |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34675702517562619481158297454042233470999016747800957765847295869309377170537 -assert nopos tproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 44.uart_stress_all.34675702517562619481158297454042233470999016747800957765847295869309377170537 |
| Directory | /workspace/44.uart_stress_all/latest |
| Test location | /workspace/coverage/default/44.uart_stress_all_with_rand_reset.6823660765965738672104919771602105333378179937330562633139218971448094600849 |
| Short name | T1237 |
| Test name | |
| Test status | |
| Simulation time | 87476847566 ps |
| CPU time | 456.25 seconds |
| Started | Nov 22 01:45:27 PM PST 23 |
| Finished | Nov 22 01:53:04 PM PST 23 |
| Peak memory | 226208 kb |
| Host | smart-fd92ac7d-d6cd-4b2a-ba42-3a77f16a3cb2 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68236607659657386721049197 71602105333378179937330562633139218971448094600849 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_stress_all_with_rand_reset.68236607659657 38672104919771602105333378179937330562633139218971448094600849 |
| Directory | /workspace/44.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/44.uart_tx_ovrd.36111865074979886457444441634273781785288612108243734175007723165879687713248 |
| Short name | T663 |
| Test name | |
| Test status | |
| Simulation time | 485186362 ps |
| CPU time | 1.31 seconds |
| Started | Nov 22 01:45:39 PM PST 23 |
| Finished | Nov 22 01:45:42 PM PST 23 |
| Peak memory | 197920 kb |
| Host | smart-6b144767-60dd-4907-ac6a-f209b0d84aed |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=36111865074979886457444441634273781785288612108243734175007723165879687713248 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 44.uart_tx_ovrd.36111865074979886457444441634273781785288612108243734175007723165879687713248 |
| Directory | /workspace/44.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/44.uart_tx_rx.83077326069193992415213639938054048941120176033746543312365744353666429600015 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 57391945390 ps |
| CPU time | 63.21 seconds |
| Started | Nov 22 01:45:58 PM PST 23 |
| Finished | Nov 22 01:47:10 PM PST 23 |
| Peak memory | 200084 kb |
| Host | smart-09b897ba-145c-4a9f-b699-eae106743f1c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=83077326069193992415213639938054048941120176033746543312365744353666429600015 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 44.uart_tx_rx.83077326069193992415213639938054048941120176033746543312365744353666429600015 |
| Directory | /workspace/44.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/45.uart_alert_test.79071270675205169192924821467032375622772078710421552039705877365131339115034 |
| Short name | T761 |
| Test name | |
| Test status | |
| Simulation time | 16368684 ps |
| CPU time | 0.54 seconds |
| Started | Nov 22 01:45:09 PM PST 23 |
| Finished | Nov 22 01:45:11 PM PST 23 |
| Peak memory | 194608 kb |
| Host | smart-1852260e-90de-47c2-9e9b-1f252239bfb2 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79071270675205169192924821467032375622772078710421552039705877365131339115034 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 45.uart_alert_test.79071270675205169192924821467032375622772078710421552039705877365131339115034 |
| Directory | /workspace/45.uart_alert_test/latest |
| Test location | /workspace/coverage/default/45.uart_fifo_full.27763807327311939139994601735334195505692963150578135119625639661842855479231 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 61777160308 ps |
| CPU time | 60.52 seconds |
| Started | Nov 22 01:45:37 PM PST 23 |
| Finished | Nov 22 01:46:39 PM PST 23 |
| Peak memory | 200048 kb |
| Host | smart-c13ba8cf-88a4-4743-9dfb-19f6ddbe83d5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=27763807327311939139994601735334195505692963150578135119625639661842855479231 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 45.uart_fifo_full.27763807327311939139994601735334195505692963150578135119625639661842855479231 |
| Directory | /workspace/45.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/45.uart_fifo_overflow.101313068414201956811144162161685405504715428701761115347493679779569322729120 |
| Short name | T1020 |
| Test name | |
| Test status | |
| Simulation time | 58551936110 ps |
| CPU time | 54.4 seconds |
| Started | Nov 22 01:45:28 PM PST 23 |
| Finished | Nov 22 01:46:25 PM PST 23 |
| Peak memory | 199264 kb |
| Host | smart-39f057b7-eed1-43a1-ba15-1f3a5af808fb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=101313068414201956811144162161685405504715428701761115347493679779569322729120 -assert nopostproc +UVM_TESTNAME=uart_bas e_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 45.uart_fifo_overflow.101313068414201956811144162161685405504715428701761115347493679779569322729120 |
| Directory | /workspace/45.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/45.uart_fifo_reset.109775824329995580536671387318914074941068094061000739804228563548646181529682 |
| Short name | T1059 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 113 seconds |
| Started | Nov 22 01:45:13 PM PST 23 |
| Finished | Nov 22 01:47:08 PM PST 23 |
| Peak memory | 198900 kb |
| Host | smart-1d9a942e-3fa2-49de-b586-d0061e39c8fb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=109775824329995580536671387318914074941068094061000739804228563548646181529682 -assert nopostproc +UVM_TESTNAME=uart_bas e_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_reset.109775824329995580536671387318914074941068094061000739804228563548646181529682 |
| Directory | /workspace/45.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/45.uart_intr.76185139702901871056581393298883213290773106006083597105046798574716897756454 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 787145125175 ps |
| CPU time | 782.23 seconds |
| Started | Nov 22 01:45:30 PM PST 23 |
| Finished | Nov 22 01:58:34 PM PST 23 |
| Peak memory | 200032 kb |
| Host | smart-beeee926-0aae-4fa2-a9d3-b414cfe001d9 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76185139702901871056581393298883213290773106006083597105046798574716897756454 -assert nopost proc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 45.uart_intr.76185139702901871056581393298883213290773106006083597105046798574716897756454 |
| Directory | /workspace/45.uart_intr/latest |
| Test location | /workspace/coverage/default/45.uart_long_xfer_wo_dly.112319527131893999119053324825060366714565233081372080911383627712220413945937 |
| Short name | T737 |
| Test name | |
| Test status | |
| Simulation time | 93387746707 ps |
| CPU time | 357.13 seconds |
| Started | Nov 22 01:45:21 PM PST 23 |
| Finished | Nov 22 01:51:20 PM PST 23 |
| Peak memory | 200120 kb |
| Host | smart-98e6fa15-fecc-4f5a-b3ba-9e0b7a6eb48d |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=112319527131893999119053324825060366714565233081372080911383627712220413945937 -assert nopostproc +UVM_TE STNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 45.uart_long_xfer_wo_dly.112319527131893999119053324825060366714565233081372080911383627712220413945937 |
| Directory | /workspace/45.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/45.uart_loopback.11327173221111741801239541120982550223799884537376624425589147911018964862488 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 14572448663 ps |
| CPU time | 16.19 seconds |
| Started | Nov 22 01:45:27 PM PST 23 |
| Finished | Nov 22 01:45:45 PM PST 23 |
| Peak memory | 200020 kb |
| Host | smart-eca5e60f-d4cf-46f8-a6c1-a1ac90b8ac0c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=11327173221111741801239541120982550223799884537376624425589147911018964862488 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 45.uart_loopback.11327173221111741801239541120982550223799884537376624425589147911018964862488 |
| Directory | /workspace/45.uart_loopback/latest |
| Test location | /workspace/coverage/default/45.uart_noise_filter.114230191631548449305853369689809956375807458962576932696697387358558618377186 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 94501577082 ps |
| CPU time | 96.87 seconds |
| Started | Nov 22 01:45:37 PM PST 23 |
| Finished | Nov 22 01:47:15 PM PST 23 |
| Peak memory | 200232 kb |
| Host | smart-4635c604-6613-4c8e-b36e-8b13af139123 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=114230191631548449305853369689809956375807458962576932696697387358558618377186 -assert nopostproc +UVM_TESTNAME=uart_bas e_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 45.uart_noise_filter.114230191631548449305853369689809956375807458962576932696697387358558618377186 |
| Directory | /workspace/45.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/45.uart_perf.104557682898132344847772683370116039903287644794103355116731683915130144436389 |
| Short name | T1230 |
| Test name | |
| Test status | |
| Simulation time | 14098773881 ps |
| CPU time | 479.39 seconds |
| Started | Nov 22 01:45:24 PM PST 23 |
| Finished | Nov 22 01:53:24 PM PST 23 |
| Peak memory | 200168 kb |
| Host | smart-85d1a6b3-0398-4b3f-8003-af18d4f1a265 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=104557682898132344847772683370116039903287644794103355116731683915130144436389 -assert nopostproc +UVM_TE STNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 45.uart_perf.104557682898132344847772683370116039903287644794103355116731683915130144436389 |
| Directory | /workspace/45.uart_perf/latest |
| Test location | /workspace/coverage/default/45.uart_rx_oversample.99145162409697670486279132438343448545672409859064095101041637793340025287971 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 4370280281 ps |
| CPU time | 19.76 seconds |
| Started | Nov 22 01:45:40 PM PST 23 |
| Finished | Nov 22 01:46:01 PM PST 23 |
| Peak memory | 198992 kb |
| Host | smart-208aa741-5e4a-4dcd-8cbe-f301143e0093 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=99145162409697670486279132438343448545672409859064095101041637793340025287971 -assert nopostproc +UVM_TES TNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 45.uart_rx_oversample.99145162409697670486279132438343448545672409859064095101041637793340025287971 |
| Directory | /workspace/45.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/45.uart_rx_parity_err.70685523621971514706977434395057103020915969320725973592313195183005851164840 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 36616611594 ps |
| CPU time | 37.92 seconds |
| Started | Nov 22 01:45:27 PM PST 23 |
| Finished | Nov 22 01:46:06 PM PST 23 |
| Peak memory | 200096 kb |
| Host | smart-4e938f1d-785f-40a9-a469-6e0329500fc8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=70685523621971514706977434395057103020915969320725973592313195183005851164840 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 45.uart_rx_parity_err.70685523621971514706977434395057103020915969320725973592313195183005851164840 |
| Directory | /workspace/45.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/45.uart_rx_start_bit_filter.84774090775002812372373817328696992071874266729582672604010413070427400181032 |
| Short name | T1225 |
| Test name | |
| Test status | |
| Simulation time | 4267638245 ps |
| CPU time | 4.7 seconds |
| Started | Nov 22 01:45:37 PM PST 23 |
| Finished | Nov 22 01:45:42 PM PST 23 |
| Peak memory | 195884 kb |
| Host | smart-f021378e-0baf-4691-97cb-7cd3a2ded648 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=84774090775002812372373817328696992071874266729582672604010413070427400181032 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 45.uart_rx_start_bit_filter.84774090775002812372373817328696992071874266729582672604010413070427400181032 |
| Directory | /workspace/45.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/45.uart_smoke.28788286648377634093047559658357430632552484005055791925457898601949061194427 |
| Short name | T912 |
| Test name | |
| Test status | |
| Simulation time | 5759626309 ps |
| CPU time | 18.6 seconds |
| Started | Nov 22 01:45:26 PM PST 23 |
| Finished | Nov 22 01:45:46 PM PST 23 |
| Peak memory | 199616 kb |
| Host | smart-705f75c0-1604-4eda-9293-0aa297a9c3b9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=28788286648377634093047559658357430632552484005055791925457898601949061194427 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 45.uart_smoke.28788286648377634093047559658357430632552484005055791925457898601949061194427 |
| Directory | /workspace/45.uart_smoke/latest |
| Test location | /workspace/coverage/default/45.uart_stress_all.13568096938744303003474123987579464994899832524173835529429090306979130856560 |
| Short name | T682 |
| Test name | |
| Test status | |
| Simulation time | 43402307308 ps |
| CPU time | 56.66 seconds |
| Started | Nov 22 01:45:37 PM PST 23 |
| Finished | Nov 22 01:46:34 PM PST 23 |
| Peak memory | 200116 kb |
| Host | smart-25605571-6619-4778-8768-044658d84616 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13568096938744303003474123987579464994899832524173835529429090306979130856560 -assert nopos tproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 45.uart_stress_all.13568096938744303003474123987579464994899832524173835529429090306979130856560 |
| Directory | /workspace/45.uart_stress_all/latest |
| Test location | /workspace/coverage/default/45.uart_stress_all_with_rand_reset.29266767666628724879258067945003153721038497236959775031025838825320006414101 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 87476847566 ps |
| CPU time | 463.32 seconds |
| Started | Nov 22 01:45:29 PM PST 23 |
| Finished | Nov 22 01:53:14 PM PST 23 |
| Peak memory | 226252 kb |
| Host | smart-561a4bd7-5f07-4ac6-b2c8-94f7f6718cf1 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29266767666628724879258067 945003153721038497236959775031025838825320006414101 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_stress_all_with_rand_reset.2926676766662 8724879258067945003153721038497236959775031025838825320006414101 |
| Directory | /workspace/45.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/45.uart_tx_ovrd.58046452548650461634373085386387637024232785368359552693057365001188238897313 |
| Short name | T1026 |
| Test name | |
| Test status | |
| Simulation time | 485186362 ps |
| CPU time | 1.29 seconds |
| Started | Nov 22 01:45:32 PM PST 23 |
| Finished | Nov 22 01:45:35 PM PST 23 |
| Peak memory | 197928 kb |
| Host | smart-6325bade-10d4-457d-af10-bfde7bf334dd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=58046452548650461634373085386387637024232785368359552693057365001188238897313 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 45.uart_tx_ovrd.58046452548650461634373085386387637024232785368359552693057365001188238897313 |
| Directory | /workspace/45.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/45.uart_tx_rx.56405336770069025554722426002684984584683382208095623921745352957232528907561 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 57391945390 ps |
| CPU time | 63.39 seconds |
| Started | Nov 22 01:45:12 PM PST 23 |
| Finished | Nov 22 01:46:16 PM PST 23 |
| Peak memory | 200096 kb |
| Host | smart-6665a624-eb53-4202-8346-c97ccf3d5a51 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=56405336770069025554722426002684984584683382208095623921745352957232528907561 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 45.uart_tx_rx.56405336770069025554722426002684984584683382208095623921745352957232528907561 |
| Directory | /workspace/45.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/46.uart_alert_test.36011133627980739340810935849122251119717057920706095035449948695472675570085 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 16368684 ps |
| CPU time | 0.55 seconds |
| Started | Nov 22 01:45:23 PM PST 23 |
| Finished | Nov 22 01:45:25 PM PST 23 |
| Peak memory | 194608 kb |
| Host | smart-3dbe98c5-76b2-49a8-84ee-1b1021ea3f78 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36011133627980739340810935849122251119717057920706095035449948695472675570085 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 46.uart_alert_test.36011133627980739340810935849122251119717057920706095035449948695472675570085 |
| Directory | /workspace/46.uart_alert_test/latest |
| Test location | /workspace/coverage/default/46.uart_fifo_full.20595779605041293135649655959774518958784048723584492883683891086447116750205 |
| Short name | T719 |
| Test name | |
| Test status | |
| Simulation time | 61777160308 ps |
| CPU time | 60.06 seconds |
| Started | Nov 22 01:45:24 PM PST 23 |
| Finished | Nov 22 01:46:26 PM PST 23 |
| Peak memory | 200100 kb |
| Host | smart-984b55ae-2873-4dd7-8ef9-aa4761582613 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=20595779605041293135649655959774518958784048723584492883683891086447116750205 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 46.uart_fifo_full.20595779605041293135649655959774518958784048723584492883683891086447116750205 |
| Directory | /workspace/46.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/46.uart_fifo_overflow.4461502500066211907967115210415615646870302165590747013695479719253149211199 |
| Short name | T887 |
| Test name | |
| Test status | |
| Simulation time | 58551936110 ps |
| CPU time | 55.24 seconds |
| Started | Nov 22 01:45:20 PM PST 23 |
| Finished | Nov 22 01:46:16 PM PST 23 |
| Peak memory | 199760 kb |
| Host | smart-9511f184-c5c5-4396-b476-357f50395c48 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4461502500066211907967115210415615646870302165590747013695479719253149211199 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_overflow.4461502500066211907967115210415615646870302165590747013695479719253149211199 |
| Directory | /workspace/46.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/46.uart_fifo_reset.26820149573125492670579212960706984825169370941428206218387191775454774188742 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 112.52 seconds |
| Started | Nov 22 01:45:31 PM PST 23 |
| Finished | Nov 22 01:47:25 PM PST 23 |
| Peak memory | 198920 kb |
| Host | smart-07b641b5-dfb2-4fd3-a72b-6caab47cc483 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=26820149573125492670579212960706984825169370941428206218387191775454774188742 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 46.uart_fifo_reset.26820149573125492670579212960706984825169370941428206218387191775454774188742 |
| Directory | /workspace/46.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/46.uart_intr.96856601044420422733582634195208961088670098095692959935359303572031848980642 |
| Short name | T1049 |
| Test name | |
| Test status | |
| Simulation time | 787145125175 ps |
| CPU time | 778.57 seconds |
| Started | Nov 22 01:45:28 PM PST 23 |
| Finished | Nov 22 01:58:28 PM PST 23 |
| Peak memory | 200000 kb |
| Host | smart-9574fa97-d29e-4e1a-820f-33f4e7006774 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96856601044420422733582634195208961088670098095692959935359303572031848980642 -assert nopost proc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 46.uart_intr.96856601044420422733582634195208961088670098095692959935359303572031848980642 |
| Directory | /workspace/46.uart_intr/latest |
| Test location | /workspace/coverage/default/46.uart_long_xfer_wo_dly.99686668848467971879515726188678337824723959533284934339261107940779598780881 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 93387746707 ps |
| CPU time | 349.35 seconds |
| Started | Nov 22 01:45:27 PM PST 23 |
| Finished | Nov 22 01:51:18 PM PST 23 |
| Peak memory | 200096 kb |
| Host | smart-36f300eb-e058-4d55-8711-deb1918e8f44 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=99686668848467971879515726188678337824723959533284934339261107940779598780881 -assert nopostproc +UVM_TES TNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 46.uart_long_xfer_wo_dly.99686668848467971879515726188678337824723959533284934339261107940779598780881 |
| Directory | /workspace/46.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/46.uart_loopback.21367773325802791647814566266313486096044870355014954517613782316251032584844 |
| Short name | T915 |
| Test name | |
| Test status | |
| Simulation time | 14572448663 ps |
| CPU time | 16.06 seconds |
| Started | Nov 22 01:45:26 PM PST 23 |
| Finished | Nov 22 01:45:43 PM PST 23 |
| Peak memory | 200048 kb |
| Host | smart-bd35d732-4063-40c8-9a2e-98f3b0601fbf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=21367773325802791647814566266313486096044870355014954517613782316251032584844 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 46.uart_loopback.21367773325802791647814566266313486096044870355014954517613782316251032584844 |
| Directory | /workspace/46.uart_loopback/latest |
| Test location | /workspace/coverage/default/46.uart_noise_filter.115336504116138612092096907823756361625800986727369696021839903255942249708462 |
| Short name | T800 |
| Test name | |
| Test status | |
| Simulation time | 94501577082 ps |
| CPU time | 96.85 seconds |
| Started | Nov 22 01:45:24 PM PST 23 |
| Finished | Nov 22 01:47:03 PM PST 23 |
| Peak memory | 200232 kb |
| Host | smart-50d5042d-5610-44d2-8256-31f6486cf87e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=115336504116138612092096907823756361625800986727369696021839903255942249708462 -assert nopostproc +UVM_TESTNAME=uart_bas e_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 46.uart_noise_filter.115336504116138612092096907823756361625800986727369696021839903255942249708462 |
| Directory | /workspace/46.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/46.uart_perf.112965109103232902289211138921418622031689830199512476656463503591985653148826 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 14098773881 ps |
| CPU time | 463.8 seconds |
| Started | Nov 22 01:45:28 PM PST 23 |
| Finished | Nov 22 01:53:14 PM PST 23 |
| Peak memory | 199452 kb |
| Host | smart-99c28bbd-51e5-4064-9b1a-9a4dd9722fa6 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=112965109103232902289211138921418622031689830199512476656463503591985653148826 -assert nopostproc +UVM_TE STNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 46.uart_perf.112965109103232902289211138921418622031689830199512476656463503591985653148826 |
| Directory | /workspace/46.uart_perf/latest |
| Test location | /workspace/coverage/default/46.uart_rx_oversample.34401474651214007692546573664678867497970097601486217850707649863158923709955 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 4370280281 ps |
| CPU time | 20.2 seconds |
| Started | Nov 22 01:45:26 PM PST 23 |
| Finished | Nov 22 01:45:47 PM PST 23 |
| Peak memory | 198952 kb |
| Host | smart-81a08ce2-b2e0-43ad-af2a-036db0e056c1 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=34401474651214007692546573664678867497970097601486217850707649863158923709955 -assert nopostproc +UVM_TES TNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 46.uart_rx_oversample.34401474651214007692546573664678867497970097601486217850707649863158923709955 |
| Directory | /workspace/46.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/46.uart_rx_parity_err.88336859661067733323007751580714601976104072835180161706757954457449855603515 |
| Short name | T794 |
| Test name | |
| Test status | |
| Simulation time | 36616611594 ps |
| CPU time | 37.78 seconds |
| Started | Nov 22 01:45:40 PM PST 23 |
| Finished | Nov 22 01:46:19 PM PST 23 |
| Peak memory | 200152 kb |
| Host | smart-f92f2dda-8101-4bf7-be05-7e4c65abf32f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=88336859661067733323007751580714601976104072835180161706757954457449855603515 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 46.uart_rx_parity_err.88336859661067733323007751580714601976104072835180161706757954457449855603515 |
| Directory | /workspace/46.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/46.uart_rx_start_bit_filter.74819364161015681914578318331605650140584844994036141368602105804269999420093 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 4267638245 ps |
| CPU time | 4.65 seconds |
| Started | Nov 22 01:45:28 PM PST 23 |
| Finished | Nov 22 01:45:35 PM PST 23 |
| Peak memory | 196048 kb |
| Host | smart-1fbb6cf6-9695-4a25-82c9-258d01f96467 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=74819364161015681914578318331605650140584844994036141368602105804269999420093 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 46.uart_rx_start_bit_filter.74819364161015681914578318331605650140584844994036141368602105804269999420093 |
| Directory | /workspace/46.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/46.uart_smoke.98826828068317604616100664055606697341934433127399271589263493613342046976710 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 5759626309 ps |
| CPU time | 18.16 seconds |
| Started | Nov 22 01:45:22 PM PST 23 |
| Finished | Nov 22 01:45:41 PM PST 23 |
| Peak memory | 199536 kb |
| Host | smart-404d5126-b1ee-47ae-9c29-e183f0796802 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=98826828068317604616100664055606697341934433127399271589263493613342046976710 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 46.uart_smoke.98826828068317604616100664055606697341934433127399271589263493613342046976710 |
| Directory | /workspace/46.uart_smoke/latest |
| Test location | /workspace/coverage/default/46.uart_stress_all.54015684618877271288803956149271851203272578665569207786518429432687664487265 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 43402307308 ps |
| CPU time | 57.03 seconds |
| Started | Nov 22 01:45:23 PM PST 23 |
| Finished | Nov 22 01:46:21 PM PST 23 |
| Peak memory | 200064 kb |
| Host | smart-5ede7810-434a-46ac-91b4-864019af4882 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54015684618877271288803956149271851203272578665569207786518429432687664487265 -assert nopos tproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 46.uart_stress_all.54015684618877271288803956149271851203272578665569207786518429432687664487265 |
| Directory | /workspace/46.uart_stress_all/latest |
| Test location | /workspace/coverage/default/46.uart_stress_all_with_rand_reset.97738557802719678836061116099882384418201440562148198597536812385203517156431 |
| Short name | T716 |
| Test name | |
| Test status | |
| Simulation time | 87476847566 ps |
| CPU time | 462.22 seconds |
| Started | Nov 22 01:45:28 PM PST 23 |
| Finished | Nov 22 01:53:12 PM PST 23 |
| Peak memory | 226248 kb |
| Host | smart-b6e02f24-307c-4bd4-a7da-d42ff431deff |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97738557802719678836061116 099882384418201440562148198597536812385203517156431 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_stress_all_with_rand_reset.9773855780271 9678836061116099882384418201440562148198597536812385203517156431 |
| Directory | /workspace/46.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/46.uart_tx_ovrd.103812605940121239218802225131932682376379911284525430873251009220503492325710 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 485186362 ps |
| CPU time | 1.27 seconds |
| Started | Nov 22 01:45:40 PM PST 23 |
| Finished | Nov 22 01:45:43 PM PST 23 |
| Peak memory | 197928 kb |
| Host | smart-37b558f4-00d8-451d-bdf8-7f5546e305b7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=103812605940121239218802225131932682376379911284525430873251009220503492325710 -assert nopostproc +UVM_TESTNAME=uart_bas e_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 46.uart_tx_ovrd.103812605940121239218802225131932682376379911284525430873251009220503492325710 |
| Directory | /workspace/46.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/46.uart_tx_rx.113257128301319714717741875005562568717730380720409572168988111199511162094536 |
| Short name | T939 |
| Test name | |
| Test status | |
| Simulation time | 57391945390 ps |
| CPU time | 63.08 seconds |
| Started | Nov 22 01:45:40 PM PST 23 |
| Finished | Nov 22 01:46:45 PM PST 23 |
| Peak memory | 200096 kb |
| Host | smart-e0205963-7243-4668-b5d9-91743040dcad |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=113257128301319714717741875005562568717730380720409572168988111199511162094536 -assert nopostproc +UVM_TESTNAME=uart_bas e_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 46.uart_tx_rx.113257128301319714717741875005562568717730380720409572168988111199511162094536 |
| Directory | /workspace/46.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/47.uart_alert_test.66298126721979916946830723488650918947281440947405454872679391084940143877480 |
| Short name | T1016 |
| Test name | |
| Test status | |
| Simulation time | 16368684 ps |
| CPU time | 0.55 seconds |
| Started | Nov 22 01:45:57 PM PST 23 |
| Finished | Nov 22 01:46:04 PM PST 23 |
| Peak memory | 194560 kb |
| Host | smart-04e2ddde-f6ea-418b-8b90-287a306f66ce |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66298126721979916946830723488650918947281440947405454872679391084940143877480 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 47.uart_alert_test.66298126721979916946830723488650918947281440947405454872679391084940143877480 |
| Directory | /workspace/47.uart_alert_test/latest |
| Test location | /workspace/coverage/default/47.uart_fifo_full.75785816835563149156915806364054870213416119812375977166148586319126101332824 |
| Short name | T1033 |
| Test name | |
| Test status | |
| Simulation time | 61777160308 ps |
| CPU time | 60.79 seconds |
| Started | Nov 22 01:45:23 PM PST 23 |
| Finished | Nov 22 01:46:24 PM PST 23 |
| Peak memory | 199944 kb |
| Host | smart-75625de2-e719-45d8-aefc-1c90b8051992 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=75785816835563149156915806364054870213416119812375977166148586319126101332824 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 47.uart_fifo_full.75785816835563149156915806364054870213416119812375977166148586319126101332824 |
| Directory | /workspace/47.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/47.uart_fifo_overflow.88805695259207700525767758825461792492392487933158551685161172045701255192445 |
| Short name | T1271 |
| Test name | |
| Test status | |
| Simulation time | 58551936110 ps |
| CPU time | 54.28 seconds |
| Started | Nov 22 01:45:30 PM PST 23 |
| Finished | Nov 22 01:46:26 PM PST 23 |
| Peak memory | 199872 kb |
| Host | smart-9b6e85ee-5086-4c0a-b641-1119ef67dad7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=88805695259207700525767758825461792492392487933158551685161172045701255192445 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 47.uart_fifo_overflow.88805695259207700525767758825461792492392487933158551685161172045701255192445 |
| Directory | /workspace/47.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/47.uart_fifo_reset.41188209447817386541906310182760861332571226642734131408391077608639224091371 |
| Short name | T1004 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 113.39 seconds |
| Started | Nov 22 01:45:30 PM PST 23 |
| Finished | Nov 22 01:47:25 PM PST 23 |
| Peak memory | 198856 kb |
| Host | smart-1f3debcc-7abd-4413-939f-e7d52fcd70b2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=41188209447817386541906310182760861332571226642734131408391077608639224091371 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 47.uart_fifo_reset.41188209447817386541906310182760861332571226642734131408391077608639224091371 |
| Directory | /workspace/47.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/47.uart_intr.90633800106304415715525602995514907134058969874846007146724304423478658302870 |
| Short name | T784 |
| Test name | |
| Test status | |
| Simulation time | 787145125175 ps |
| CPU time | 784.18 seconds |
| Started | Nov 22 01:45:40 PM PST 23 |
| Finished | Nov 22 01:58:46 PM PST 23 |
| Peak memory | 200036 kb |
| Host | smart-12618bbf-30d5-483f-8f3a-0f5e280805e4 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90633800106304415715525602995514907134058969874846007146724304423478658302870 -assert nopost proc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 47.uart_intr.90633800106304415715525602995514907134058969874846007146724304423478658302870 |
| Directory | /workspace/47.uart_intr/latest |
| Test location | /workspace/coverage/default/47.uart_long_xfer_wo_dly.111870013731910888788547114995070454685956265231398976254585061467628077515105 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 93387746707 ps |
| CPU time | 352.54 seconds |
| Started | Nov 22 01:45:54 PM PST 23 |
| Finished | Nov 22 01:51:50 PM PST 23 |
| Peak memory | 200080 kb |
| Host | smart-73a367dd-b4f5-476e-b535-f376c93a66d1 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=111870013731910888788547114995070454685956265231398976254585061467628077515105 -assert nopostproc +UVM_TE STNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 47.uart_long_xfer_wo_dly.111870013731910888788547114995070454685956265231398976254585061467628077515105 |
| Directory | /workspace/47.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/47.uart_loopback.115301491406912868947965566172003436589444193971252514693735348445167197423003 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 14572448663 ps |
| CPU time | 16.24 seconds |
| Started | Nov 22 01:45:46 PM PST 23 |
| Finished | Nov 22 01:46:04 PM PST 23 |
| Peak memory | 199884 kb |
| Host | smart-52f475d4-c1d0-400d-8725-d7da9ab3dcfa |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=115301491406912868947965566172003436589444193971252514693735348445167197423003 -assert nopostproc +UVM_TESTNAME=uart_bas e_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 47.uart_loopback.115301491406912868947965566172003436589444193971252514693735348445167197423003 |
| Directory | /workspace/47.uart_loopback/latest |
| Test location | /workspace/coverage/default/47.uart_noise_filter.97371772486872727905647717902666553069968775966511344432843977135253886622426 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 94501577082 ps |
| CPU time | 96.62 seconds |
| Started | Nov 22 01:45:55 PM PST 23 |
| Finished | Nov 22 01:47:35 PM PST 23 |
| Peak memory | 200248 kb |
| Host | smart-5c31dc34-cb8c-4827-8251-c1e133679118 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=97371772486872727905647717902666553069968775966511344432843977135253886622426 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_noise_filter.97371772486872727905647717902666553069968775966511344432843977135253886622426 |
| Directory | /workspace/47.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/47.uart_perf.50572977005606565161109339406970161866248762106698469122676689965863493480306 |
| Short name | T1102 |
| Test name | |
| Test status | |
| Simulation time | 14098773881 ps |
| CPU time | 474.03 seconds |
| Started | Nov 22 01:45:42 PM PST 23 |
| Finished | Nov 22 01:53:38 PM PST 23 |
| Peak memory | 200164 kb |
| Host | smart-32ae97d8-2b07-4db7-aa50-340d8f010c6a |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=50572977005606565161109339406970161866248762106698469122676689965863493480306 -assert nopostproc +UVM_TES TNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 47.uart_perf.50572977005606565161109339406970161866248762106698469122676689965863493480306 |
| Directory | /workspace/47.uart_perf/latest |
| Test location | /workspace/coverage/default/47.uart_rx_oversample.84762244713642422168329011861809154029662354890040218891435236189663168447378 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 4370280281 ps |
| CPU time | 20.09 seconds |
| Started | Nov 22 01:45:46 PM PST 23 |
| Finished | Nov 22 01:46:09 PM PST 23 |
| Peak memory | 198940 kb |
| Host | smart-9e902efe-6d81-462a-a251-455f7a175b4f |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=84762244713642422168329011861809154029662354890040218891435236189663168447378 -assert nopostproc +UVM_TES TNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 47.uart_rx_oversample.84762244713642422168329011861809154029662354890040218891435236189663168447378 |
| Directory | /workspace/47.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/47.uart_rx_parity_err.93745121056626500891106829230142625183144019086889272705873625183684479197545 |
| Short name | T961 |
| Test name | |
| Test status | |
| Simulation time | 36616611594 ps |
| CPU time | 37.65 seconds |
| Started | Nov 22 01:45:28 PM PST 23 |
| Finished | Nov 22 01:46:08 PM PST 23 |
| Peak memory | 200120 kb |
| Host | smart-a476bd19-f1c4-4df6-b668-394ea4db735a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=93745121056626500891106829230142625183144019086889272705873625183684479197545 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 47.uart_rx_parity_err.93745121056626500891106829230142625183144019086889272705873625183684479197545 |
| Directory | /workspace/47.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/47.uart_rx_start_bit_filter.66490962988252116108948511723266909077647369705621384711914908980285624378964 |
| Short name | T665 |
| Test name | |
| Test status | |
| Simulation time | 4267638245 ps |
| CPU time | 4.66 seconds |
| Started | Nov 22 01:45:43 PM PST 23 |
| Finished | Nov 22 01:45:49 PM PST 23 |
| Peak memory | 195956 kb |
| Host | smart-204cc2d5-339d-418c-b058-5937c19dbc3c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=66490962988252116108948511723266909077647369705621384711914908980285624378964 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 47.uart_rx_start_bit_filter.66490962988252116108948511723266909077647369705621384711914908980285624378964 |
| Directory | /workspace/47.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/47.uart_smoke.111710718659715109369403575147517981434451300089282322219462049881860151586456 |
| Short name | T1218 |
| Test name | |
| Test status | |
| Simulation time | 5759626309 ps |
| CPU time | 18.21 seconds |
| Started | Nov 22 01:45:29 PM PST 23 |
| Finished | Nov 22 01:45:49 PM PST 23 |
| Peak memory | 199592 kb |
| Host | smart-5ec8bb1a-0362-4a41-bb58-8f30fc775da9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=111710718659715109369403575147517981434451300089282322219462049881860151586456 -assert nopostproc +UVM_TESTNAME=uart_bas e_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 47.uart_smoke.111710718659715109369403575147517981434451300089282322219462049881860151586456 |
| Directory | /workspace/47.uart_smoke/latest |
| Test location | /workspace/coverage/default/47.uart_stress_all.111055280246883776611227195818613997132497974651503947457157471222274893104470 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 43402307308 ps |
| CPU time | 57.76 seconds |
| Started | Nov 22 01:45:46 PM PST 23 |
| Finished | Nov 22 01:46:46 PM PST 23 |
| Peak memory | 200092 kb |
| Host | smart-a127fecd-5b62-42f3-bdb0-a9ebff057239 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111055280246883776611227195818613997132497974651503947457157471222274893104470 -assert nopo stproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 47.uart_stress_all.111055280246883776611227195818613997132497974651503947457157471222274893104470 |
| Directory | /workspace/47.uart_stress_all/latest |
| Test location | /workspace/coverage/default/47.uart_stress_all_with_rand_reset.40722963769766244947292801240056409911034114214022056265792852449061715363246 |
| Short name | T1106 |
| Test name | |
| Test status | |
| Simulation time | 87476847566 ps |
| CPU time | 465.18 seconds |
| Started | Nov 22 01:45:45 PM PST 23 |
| Finished | Nov 22 01:53:32 PM PST 23 |
| Peak memory | 226248 kb |
| Host | smart-897316b6-3a78-4939-bda7-6f842b26429f |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40722963769766244947292801 240056409911034114214022056265792852449061715363246 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_stress_all_with_rand_reset.4072296376976 6244947292801240056409911034114214022056265792852449061715363246 |
| Directory | /workspace/47.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/47.uart_tx_ovrd.109173168345049326700408826123324891659036565180422762033037624057543983003297 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 485186362 ps |
| CPU time | 1.32 seconds |
| Started | Nov 22 01:45:33 PM PST 23 |
| Finished | Nov 22 01:45:35 PM PST 23 |
| Peak memory | 197932 kb |
| Host | smart-c810759b-ecc7-4aef-b786-16d32b695f0e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=109173168345049326700408826123324891659036565180422762033037624057543983003297 -assert nopostproc +UVM_TESTNAME=uart_bas e_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 47.uart_tx_ovrd.109173168345049326700408826123324891659036565180422762033037624057543983003297 |
| Directory | /workspace/47.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/47.uart_tx_rx.98058167716978034383983266264310328497015653719692413042246646635808650726359 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 57391945390 ps |
| CPU time | 63.74 seconds |
| Started | Nov 22 01:45:25 PM PST 23 |
| Finished | Nov 22 01:46:30 PM PST 23 |
| Peak memory | 200012 kb |
| Host | smart-02f65cd8-1202-4595-9d6f-e8c8220b9cd5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=98058167716978034383983266264310328497015653719692413042246646635808650726359 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 47.uart_tx_rx.98058167716978034383983266264310328497015653719692413042246646635808650726359 |
| Directory | /workspace/47.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/48.uart_alert_test.48301351257731884407972439537413294592074255960320685049998458145573947213719 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 16368684 ps |
| CPU time | 0.55 seconds |
| Started | Nov 22 01:45:36 PM PST 23 |
| Finished | Nov 22 01:45:38 PM PST 23 |
| Peak memory | 194608 kb |
| Host | smart-142ed52a-dccb-47fe-ad4e-99c6e7d60906 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48301351257731884407972439537413294592074255960320685049998458145573947213719 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 48.uart_alert_test.48301351257731884407972439537413294592074255960320685049998458145573947213719 |
| Directory | /workspace/48.uart_alert_test/latest |
| Test location | /workspace/coverage/default/48.uart_fifo_full.32252427399546769301296036704389593397029890760031236867288651663396677136132 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 61777160308 ps |
| CPU time | 60.39 seconds |
| Started | Nov 22 01:45:47 PM PST 23 |
| Finished | Nov 22 01:46:49 PM PST 23 |
| Peak memory | 200024 kb |
| Host | smart-290a71db-0d4e-4399-8275-773ccd9b88e9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=32252427399546769301296036704389593397029890760031236867288651663396677136132 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 48.uart_fifo_full.32252427399546769301296036704389593397029890760031236867288651663396677136132 |
| Directory | /workspace/48.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/48.uart_fifo_overflow.9031121584799259911745708183707153695734360224146268460309268256859488194851 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 58551936110 ps |
| CPU time | 54.24 seconds |
| Started | Nov 22 01:46:10 PM PST 23 |
| Finished | Nov 22 01:47:09 PM PST 23 |
| Peak memory | 199796 kb |
| Host | smart-553e2c5b-a954-4a6d-8ad9-052e84001117 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=9031121584799259911745708183707153695734360224146268460309268256859488194851 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_overflow.9031121584799259911745708183707153695734360224146268460309268256859488194851 |
| Directory | /workspace/48.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/48.uart_fifo_reset.114552902572405377139996605564129294722243972885916832518400149571853677120027 |
| Short name | T885 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 112.31 seconds |
| Started | Nov 22 01:45:54 PM PST 23 |
| Finished | Nov 22 01:47:50 PM PST 23 |
| Peak memory | 198988 kb |
| Host | smart-ee37fd63-9acb-459d-b7ad-a282f01ee37a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=114552902572405377139996605564129294722243972885916832518400149571853677120027 -assert nopostproc +UVM_TESTNAME=uart_bas e_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_reset.114552902572405377139996605564129294722243972885916832518400149571853677120027 |
| Directory | /workspace/48.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/48.uart_intr.61354433771492494507038202317027942337875226123300797870390508666906753136352 |
| Short name | T1179 |
| Test name | |
| Test status | |
| Simulation time | 787145125175 ps |
| CPU time | 783.96 seconds |
| Started | Nov 22 01:46:10 PM PST 23 |
| Finished | Nov 22 01:59:19 PM PST 23 |
| Peak memory | 200040 kb |
| Host | smart-a86b554f-dd7c-433b-89b2-ad9f72d96873 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61354433771492494507038202317027942337875226123300797870390508666906753136352 -assert nopost proc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 48.uart_intr.61354433771492494507038202317027942337875226123300797870390508666906753136352 |
| Directory | /workspace/48.uart_intr/latest |
| Test location | /workspace/coverage/default/48.uart_long_xfer_wo_dly.1169639136968995399799734322518015240131800088005252440888811644343965695552 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 93387746707 ps |
| CPU time | 351.87 seconds |
| Started | Nov 22 01:45:36 PM PST 23 |
| Finished | Nov 22 01:51:28 PM PST 23 |
| Peak memory | 200088 kb |
| Host | smart-e30270b6-5402-4cf8-a465-5d77f210326f |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1169639136968995399799734322518015240131800088005252440888811644343965695552 -assert nopostproc +UVM_TEST NAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_long_xfer_wo_dly.1169639136968995399799734322518015240131800088005252440888811644343965695552 |
| Directory | /workspace/48.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/48.uart_loopback.56584729151474023954736186293188147304923031494385187194297648289895901905064 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 14572448663 ps |
| CPU time | 16.06 seconds |
| Started | Nov 22 01:46:12 PM PST 23 |
| Finished | Nov 22 01:46:32 PM PST 23 |
| Peak memory | 200000 kb |
| Host | smart-37d31ba9-92d1-4215-8d4c-b8e0cc923720 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=56584729151474023954736186293188147304923031494385187194297648289895901905064 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 48.uart_loopback.56584729151474023954736186293188147304923031494385187194297648289895901905064 |
| Directory | /workspace/48.uart_loopback/latest |
| Test location | /workspace/coverage/default/48.uart_noise_filter.82689351335590401695241810447380815001423374011154887704371530227343690893444 |
| Short name | T869 |
| Test name | |
| Test status | |
| Simulation time | 94501577082 ps |
| CPU time | 97.43 seconds |
| Started | Nov 22 01:45:46 PM PST 23 |
| Finished | Nov 22 01:47:26 PM PST 23 |
| Peak memory | 200264 kb |
| Host | smart-a3493c95-1202-4c15-be3a-64191d309346 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=82689351335590401695241810447380815001423374011154887704371530227343690893444 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_noise_filter.82689351335590401695241810447380815001423374011154887704371530227343690893444 |
| Directory | /workspace/48.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/48.uart_perf.60726984759752000919084854513884666874074582234589053226895330045980393603887 |
| Short name | T1257 |
| Test name | |
| Test status | |
| Simulation time | 14098773881 ps |
| CPU time | 465.86 seconds |
| Started | Nov 22 01:46:01 PM PST 23 |
| Finished | Nov 22 01:53:53 PM PST 23 |
| Peak memory | 200104 kb |
| Host | smart-1e933f76-7340-4671-ab9e-a1b69f44abac |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=60726984759752000919084854513884666874074582234589053226895330045980393603887 -assert nopostproc +UVM_TES TNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 48.uart_perf.60726984759752000919084854513884666874074582234589053226895330045980393603887 |
| Directory | /workspace/48.uart_perf/latest |
| Test location | /workspace/coverage/default/48.uart_rx_oversample.90359703358570228406370354578133574785709542230408663905637917903713079688406 |
| Short name | T752 |
| Test name | |
| Test status | |
| Simulation time | 4370280281 ps |
| CPU time | 19.62 seconds |
| Started | Nov 22 01:46:09 PM PST 23 |
| Finished | Nov 22 01:46:34 PM PST 23 |
| Peak memory | 198892 kb |
| Host | smart-345f1543-73db-4362-b5c9-15204c0a682f |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=90359703358570228406370354578133574785709542230408663905637917903713079688406 -assert nopostproc +UVM_TES TNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 48.uart_rx_oversample.90359703358570228406370354578133574785709542230408663905637917903713079688406 |
| Directory | /workspace/48.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/48.uart_rx_parity_err.4452777041528796522456744583718628353003794442181941295786537217812542533066 |
| Short name | T1086 |
| Test name | |
| Test status | |
| Simulation time | 36616611594 ps |
| CPU time | 37.47 seconds |
| Started | Nov 22 01:46:12 PM PST 23 |
| Finished | Nov 22 01:46:53 PM PST 23 |
| Peak memory | 200052 kb |
| Host | smart-b2381955-a4f5-43d6-aba0-3cee48882520 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4452777041528796522456744583718628353003794442181941295786537217812542533066 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_parity_err.4452777041528796522456744583718628353003794442181941295786537217812542533066 |
| Directory | /workspace/48.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/48.uart_rx_start_bit_filter.10467716025596411624160948179830006214634791606517388517442042002094837563774 |
| Short name | T1236 |
| Test name | |
| Test status | |
| Simulation time | 4267638245 ps |
| CPU time | 4.67 seconds |
| Started | Nov 22 01:46:03 PM PST 23 |
| Finished | Nov 22 01:46:14 PM PST 23 |
| Peak memory | 195836 kb |
| Host | smart-b4316d87-002c-4b0e-b003-88e132a85c2d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=10467716025596411624160948179830006214634791606517388517442042002094837563774 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 48.uart_rx_start_bit_filter.10467716025596411624160948179830006214634791606517388517442042002094837563774 |
| Directory | /workspace/48.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/48.uart_smoke.37874909074486289048096349289506051329716230393345947273992457509672688868877 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 5759626309 ps |
| CPU time | 18.18 seconds |
| Started | Nov 22 01:46:03 PM PST 23 |
| Finished | Nov 22 01:46:27 PM PST 23 |
| Peak memory | 199492 kb |
| Host | smart-b6bd809a-65a4-4620-9ea6-0ec3508b6b7a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=37874909074486289048096349289506051329716230393345947273992457509672688868877 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 48.uart_smoke.37874909074486289048096349289506051329716230393345947273992457509672688868877 |
| Directory | /workspace/48.uart_smoke/latest |
| Test location | /workspace/coverage/default/48.uart_stress_all.21067753814419122242735357240567328663175844137263591566767064193958752703486 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 43402307308 ps |
| CPU time | 56.14 seconds |
| Started | Nov 22 01:45:59 PM PST 23 |
| Finished | Nov 22 01:47:03 PM PST 23 |
| Peak memory | 200064 kb |
| Host | smart-d6448114-7a5c-43db-8b70-ce2fbc1f4afe |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21067753814419122242735357240567328663175844137263591566767064193958752703486 -assert nopos tproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 48.uart_stress_all.21067753814419122242735357240567328663175844137263591566767064193958752703486 |
| Directory | /workspace/48.uart_stress_all/latest |
| Test location | /workspace/coverage/default/48.uart_stress_all_with_rand_reset.26405237394847239429525490564257578901014037890104973513563925680659892694056 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 87476847566 ps |
| CPU time | 474.02 seconds |
| Started | Nov 22 01:45:38 PM PST 23 |
| Finished | Nov 22 01:53:33 PM PST 23 |
| Peak memory | 226228 kb |
| Host | smart-b516f706-74c4-40cd-99b2-921759d5d529 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26405237394847239429525490 564257578901014037890104973513563925680659892694056 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_stress_all_with_rand_reset.2640523739484 7239429525490564257578901014037890104973513563925680659892694056 |
| Directory | /workspace/48.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/48.uart_tx_ovrd.82470506139149195935521909623096505735613456065831799552606779566041619046217 |
| Short name | T976 |
| Test name | |
| Test status | |
| Simulation time | 485186362 ps |
| CPU time | 1.27 seconds |
| Started | Nov 22 01:46:06 PM PST 23 |
| Finished | Nov 22 01:46:14 PM PST 23 |
| Peak memory | 197880 kb |
| Host | smart-f5f9b725-6b70-4bd4-af2a-b167b1492c68 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=82470506139149195935521909623096505735613456065831799552606779566041619046217 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 48.uart_tx_ovrd.82470506139149195935521909623096505735613456065831799552606779566041619046217 |
| Directory | /workspace/48.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/48.uart_tx_rx.30667523040781436742104653681878765307556657668932955698397589092674267689605 |
| Short name | T662 |
| Test name | |
| Test status | |
| Simulation time | 57391945390 ps |
| CPU time | 64.18 seconds |
| Started | Nov 22 01:45:47 PM PST 23 |
| Finished | Nov 22 01:46:53 PM PST 23 |
| Peak memory | 200080 kb |
| Host | smart-5145b5c6-ecb2-4be0-b7e9-f9d8b705a846 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=30667523040781436742104653681878765307556657668932955698397589092674267689605 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 48.uart_tx_rx.30667523040781436742104653681878765307556657668932955698397589092674267689605 |
| Directory | /workspace/48.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/49.uart_alert_test.99101665981975643266177485072676944091821860178904010527622546633591515857168 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 16368684 ps |
| CPU time | 0.55 seconds |
| Started | Nov 22 01:45:30 PM PST 23 |
| Finished | Nov 22 01:45:32 PM PST 23 |
| Peak memory | 194624 kb |
| Host | smart-4dd093a4-1e27-42d7-9d2c-d648da499cf2 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99101665981975643266177485072676944091821860178904010527622546633591515857168 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 49.uart_alert_test.99101665981975643266177485072676944091821860178904010527622546633591515857168 |
| Directory | /workspace/49.uart_alert_test/latest |
| Test location | /workspace/coverage/default/49.uart_fifo_full.33256851262875170405828395444061388363721185249253719334131380888536879366053 |
| Short name | T1043 |
| Test name | |
| Test status | |
| Simulation time | 61777160308 ps |
| CPU time | 60.25 seconds |
| Started | Nov 22 01:45:43 PM PST 23 |
| Finished | Nov 22 01:46:44 PM PST 23 |
| Peak memory | 200072 kb |
| Host | smart-b10643dc-7910-44e2-a17e-c7b846caadb6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=33256851262875170405828395444061388363721185249253719334131380888536879366053 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 49.uart_fifo_full.33256851262875170405828395444061388363721185249253719334131380888536879366053 |
| Directory | /workspace/49.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/49.uart_fifo_overflow.28630778707289792945608387511318453040112071552038032601486620354810238311089 |
| Short name | T986 |
| Test name | |
| Test status | |
| Simulation time | 58551936110 ps |
| CPU time | 55.16 seconds |
| Started | Nov 22 01:45:30 PM PST 23 |
| Finished | Nov 22 01:46:27 PM PST 23 |
| Peak memory | 199848 kb |
| Host | smart-77eb5034-94e3-4cce-b7d5-590c699832ae |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=28630778707289792945608387511318453040112071552038032601486620354810238311089 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 49.uart_fifo_overflow.28630778707289792945608387511318453040112071552038032601486620354810238311089 |
| Directory | /workspace/49.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/49.uart_fifo_reset.90985557045578490821774521442537413950550808317071930309967503431966243929226 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 112.91 seconds |
| Started | Nov 22 01:45:39 PM PST 23 |
| Finished | Nov 22 01:47:32 PM PST 23 |
| Peak memory | 198840 kb |
| Host | smart-c4d7eaab-688c-4fb6-947c-be575b281abb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=90985557045578490821774521442537413950550808317071930309967503431966243929226 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 49.uart_fifo_reset.90985557045578490821774521442537413950550808317071930309967503431966243929226 |
| Directory | /workspace/49.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/49.uart_intr.19499729123296937286130652447033526574791202346659945000115319170577126234789 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 787145125175 ps |
| CPU time | 781.28 seconds |
| Started | Nov 22 01:45:30 PM PST 23 |
| Finished | Nov 22 01:58:33 PM PST 23 |
| Peak memory | 200024 kb |
| Host | smart-8e81b744-7622-4b4f-9b58-e7801499fb9f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19499729123296937286130652447033526574791202346659945000115319170577126234789 -assert nopost proc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 49.uart_intr.19499729123296937286130652447033526574791202346659945000115319170577126234789 |
| Directory | /workspace/49.uart_intr/latest |
| Test location | /workspace/coverage/default/49.uart_long_xfer_wo_dly.96223527418861451325563552068374435149710465725921950250745376813230236171264 |
| Short name | T1040 |
| Test name | |
| Test status | |
| Simulation time | 93387746707 ps |
| CPU time | 346.36 seconds |
| Started | Nov 22 01:45:29 PM PST 23 |
| Finished | Nov 22 01:51:18 PM PST 23 |
| Peak memory | 200040 kb |
| Host | smart-8f0d043b-8d33-4bd9-b69a-805938b6a58c |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=96223527418861451325563552068374435149710465725921950250745376813230236171264 -assert nopostproc +UVM_TES TNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 49.uart_long_xfer_wo_dly.96223527418861451325563552068374435149710465725921950250745376813230236171264 |
| Directory | /workspace/49.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/49.uart_loopback.44243416233543073336476454933683722895106837045739755470500609158510475754322 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 14572448663 ps |
| CPU time | 16.05 seconds |
| Started | Nov 22 01:45:44 PM PST 23 |
| Finished | Nov 22 01:46:02 PM PST 23 |
| Peak memory | 200044 kb |
| Host | smart-eba3b4da-fa57-4284-8812-cd428f994eb9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=44243416233543073336476454933683722895106837045739755470500609158510475754322 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 49.uart_loopback.44243416233543073336476454933683722895106837045739755470500609158510475754322 |
| Directory | /workspace/49.uart_loopback/latest |
| Test location | /workspace/coverage/default/49.uart_noise_filter.10013175936807971580770149111468512593562377489940013968754315744994952676490 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 94501577082 ps |
| CPU time | 96.71 seconds |
| Started | Nov 22 01:45:31 PM PST 23 |
| Finished | Nov 22 01:47:09 PM PST 23 |
| Peak memory | 200260 kb |
| Host | smart-d173a44f-2c68-4ce0-9e8d-59c4128312c2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=10013175936807971580770149111468512593562377489940013968754315744994952676490 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_noise_filter.10013175936807971580770149111468512593562377489940013968754315744994952676490 |
| Directory | /workspace/49.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/49.uart_perf.102833977645443194144426079522477574088256267149709882910780198423034013491617 |
| Short name | T1045 |
| Test name | |
| Test status | |
| Simulation time | 14098773881 ps |
| CPU time | 463.65 seconds |
| Started | Nov 22 01:45:41 PM PST 23 |
| Finished | Nov 22 01:53:27 PM PST 23 |
| Peak memory | 200168 kb |
| Host | smart-4e8e27e9-edb7-4bf6-b5c8-0a828075f1af |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=102833977645443194144426079522477574088256267149709882910780198423034013491617 -assert nopostproc +UVM_TE STNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 49.uart_perf.102833977645443194144426079522477574088256267149709882910780198423034013491617 |
| Directory | /workspace/49.uart_perf/latest |
| Test location | /workspace/coverage/default/49.uart_rx_oversample.22518182929694698416038252901001561689857230472718253816668980869290364111821 |
| Short name | T1212 |
| Test name | |
| Test status | |
| Simulation time | 4370280281 ps |
| CPU time | 19.7 seconds |
| Started | Nov 22 01:45:42 PM PST 23 |
| Finished | Nov 22 01:46:04 PM PST 23 |
| Peak memory | 198964 kb |
| Host | smart-c11668b0-3074-4413-b198-f413efbbadd1 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=22518182929694698416038252901001561689857230472718253816668980869290364111821 -assert nopostproc +UVM_TES TNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 49.uart_rx_oversample.22518182929694698416038252901001561689857230472718253816668980869290364111821 |
| Directory | /workspace/49.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/49.uart_rx_parity_err.28871449713163595355651844452178614670975553467228361842765417648598648882261 |
| Short name | T880 |
| Test name | |
| Test status | |
| Simulation time | 36616611594 ps |
| CPU time | 38.29 seconds |
| Started | Nov 22 01:45:46 PM PST 23 |
| Finished | Nov 22 01:46:27 PM PST 23 |
| Peak memory | 200004 kb |
| Host | smart-50098170-f42a-41cc-a48f-fba76b2c4da0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=28871449713163595355651844452178614670975553467228361842765417648598648882261 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 49.uart_rx_parity_err.28871449713163595355651844452178614670975553467228361842765417648598648882261 |
| Directory | /workspace/49.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/49.uart_rx_start_bit_filter.3989237683487973056475682720144520640813044135522149226873000906985344863711 |
| Short name | T879 |
| Test name | |
| Test status | |
| Simulation time | 4267638245 ps |
| CPU time | 4.62 seconds |
| Started | Nov 22 01:45:40 PM PST 23 |
| Finished | Nov 22 01:45:47 PM PST 23 |
| Peak memory | 195988 kb |
| Host | smart-7184541b-4acc-4257-93fa-8893efcde92f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3989237683487973056475682720144520640813044135522149226873000906985344863711 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 49.uart_rx_start_bit_filter.3989237683487973056475682720144520640813044135522149226873000906985344863711 |
| Directory | /workspace/49.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/49.uart_smoke.69389389731257470643554576491630284968026086776390723479815061927440300325142 |
| Short name | T1052 |
| Test name | |
| Test status | |
| Simulation time | 5759626309 ps |
| CPU time | 18.23 seconds |
| Started | Nov 22 01:45:28 PM PST 23 |
| Finished | Nov 22 01:45:48 PM PST 23 |
| Peak memory | 199504 kb |
| Host | smart-fe7ed50d-df88-42c0-8448-b477f8592cb7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=69389389731257470643554576491630284968026086776390723479815061927440300325142 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 49.uart_smoke.69389389731257470643554576491630284968026086776390723479815061927440300325142 |
| Directory | /workspace/49.uart_smoke/latest |
| Test location | /workspace/coverage/default/49.uart_stress_all.6078907591016135116170214984022001286170011297399911663917874436221099773259 |
| Short name | T1114 |
| Test name | |
| Test status | |
| Simulation time | 43402307308 ps |
| CPU time | 56.46 seconds |
| Started | Nov 22 01:45:40 PM PST 23 |
| Finished | Nov 22 01:46:39 PM PST 23 |
| Peak memory | 200004 kb |
| Host | smart-bf0bade1-dd3e-4dd4-8a2b-1a784b1892ce |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6078907591016135116170214984022001286170011297399911663917874436221099773259 -assert nopost proc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 49.uart_stress_all.6078907591016135116170214984022001286170011297399911663917874436221099773259 |
| Directory | /workspace/49.uart_stress_all/latest |
| Test location | /workspace/coverage/default/49.uart_stress_all_with_rand_reset.47196255498409990997054458972999887832254462636899050071745535623801450802602 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 87476847566 ps |
| CPU time | 463.63 seconds |
| Started | Nov 22 01:45:31 PM PST 23 |
| Finished | Nov 22 01:53:16 PM PST 23 |
| Peak memory | 226236 kb |
| Host | smart-52a2280f-9e44-4d4c-98cf-28894a7b65b2 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47196255498409990997054458 972999887832254462636899050071745535623801450802602 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_stress_all_with_rand_reset.4719625549840 9990997054458972999887832254462636899050071745535623801450802602 |
| Directory | /workspace/49.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/49.uart_tx_ovrd.18542855002497661190443888723520018377493378434693066338773807910907296567722 |
| Short name | T1116 |
| Test name | |
| Test status | |
| Simulation time | 485186362 ps |
| CPU time | 1.28 seconds |
| Started | Nov 22 01:45:30 PM PST 23 |
| Finished | Nov 22 01:45:33 PM PST 23 |
| Peak memory | 197896 kb |
| Host | smart-f41a686d-2a98-418b-a88c-3532848cc6a5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=18542855002497661190443888723520018377493378434693066338773807910907296567722 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 49.uart_tx_ovrd.18542855002497661190443888723520018377493378434693066338773807910907296567722 |
| Directory | /workspace/49.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/49.uart_tx_rx.111233809772525257202944427224748722521497501544148588251059597516020064432878 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 57391945390 ps |
| CPU time | 63.53 seconds |
| Started | Nov 22 01:45:29 PM PST 23 |
| Finished | Nov 22 01:46:35 PM PST 23 |
| Peak memory | 200100 kb |
| Host | smart-0c537f2f-c69a-4473-b6e5-6fe59fd817e5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=111233809772525257202944427224748722521497501544148588251059597516020064432878 -assert nopostproc +UVM_TESTNAME=uart_bas e_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 49.uart_tx_rx.111233809772525257202944427224748722521497501544148588251059597516020064432878 |
| Directory | /workspace/49.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/5.uart_alert_test.103949171912090266858849317376503988993261894172402444546770055032073237912965 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 16368684 ps |
| CPU time | 0.57 seconds |
| Started | Nov 22 01:44:00 PM PST 23 |
| Finished | Nov 22 01:44:04 PM PST 23 |
| Peak memory | 194624 kb |
| Host | smart-ff0af4e1-c49d-446e-8c59-6b4f0d3ff68c |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103949171912090266858849317376503988993261894172402444546770055032073237912965 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 5.uart_alert_test.103949171912090266858849317376503988993261894172402444546770055032073237912965 |
| Directory | /workspace/5.uart_alert_test/latest |
| Test location | /workspace/coverage/default/5.uart_fifo_full.5852444671754378163863652052579916004750510614062799945637843981081398751909 |
| Short name | T701 |
| Test name | |
| Test status | |
| Simulation time | 61777160308 ps |
| CPU time | 60.95 seconds |
| Started | Nov 22 01:44:05 PM PST 23 |
| Finished | Nov 22 01:45:12 PM PST 23 |
| Peak memory | 200072 kb |
| Host | smart-64b7ccea-866f-46e5-8770-9d48470e2f62 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=5852444671754378163863652052579916004750510614062799945637843981081398751909 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 5.uart_fifo_full.5852444671754378163863652052579916004750510614062799945637843981081398751909 |
| Directory | /workspace/5.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/5.uart_fifo_overflow.104162085354456315788661889723087020802667454185528154724019250533996903155499 |
| Short name | T787 |
| Test name | |
| Test status | |
| Simulation time | 58551936110 ps |
| CPU time | 54.78 seconds |
| Started | Nov 22 01:44:03 PM PST 23 |
| Finished | Nov 22 01:45:02 PM PST 23 |
| Peak memory | 199812 kb |
| Host | smart-69b73e98-b0ac-4552-96ce-e91b213af3b4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=104162085354456315788661889723087020802667454185528154724019250533996903155499 -assert nopostproc +UVM_TESTNAME=uart_bas e_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 5.uart_fifo_overflow.104162085354456315788661889723087020802667454185528154724019250533996903155499 |
| Directory | /workspace/5.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/5.uart_fifo_reset.78365255240731379851989373766212797635726709803695840938689194417381216176177 |
| Short name | T901 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 114.37 seconds |
| Started | Nov 22 01:43:44 PM PST 23 |
| Finished | Nov 22 01:45:40 PM PST 23 |
| Peak memory | 198940 kb |
| Host | smart-705ac831-d624-4b6d-a54b-6a154984d342 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=78365255240731379851989373766212797635726709803695840938689194417381216176177 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 5.uart_fifo_reset.78365255240731379851989373766212797635726709803695840938689194417381216176177 |
| Directory | /workspace/5.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/5.uart_intr.115063394806488510883481769609949610601388476081497622120369177728012694863612 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 787145125175 ps |
| CPU time | 783.33 seconds |
| Started | Nov 22 01:44:01 PM PST 23 |
| Finished | Nov 22 01:57:08 PM PST 23 |
| Peak memory | 200128 kb |
| Host | smart-411bdf49-7256-4f05-82fe-7b8e4e6ed364 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115063394806488510883481769609949610601388476081497622120369177728012694863612 -assert nopos tproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 5.uart_intr.115063394806488510883481769609949610601388476081497622120369177728012694863612 |
| Directory | /workspace/5.uart_intr/latest |
| Test location | /workspace/coverage/default/5.uart_long_xfer_wo_dly.91649388559332788315575256091078720030711576450066954784889871514639446270264 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 93387746707 ps |
| CPU time | 353.33 seconds |
| Started | Nov 22 01:44:03 PM PST 23 |
| Finished | Nov 22 01:50:01 PM PST 23 |
| Peak memory | 199956 kb |
| Host | smart-cc3d1aed-b45d-461a-84d8-cd4b2dfb8b35 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=91649388559332788315575256091078720030711576450066954784889871514639446270264 -assert nopostproc +UVM_TES TNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 5.uart_long_xfer_wo_dly.91649388559332788315575256091078720030711576450066954784889871514639446270264 |
| Directory | /workspace/5.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/5.uart_loopback.87705689015490545040252858155634356858095984080724899538887455909040766720162 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 14572448663 ps |
| CPU time | 16.3 seconds |
| Started | Nov 22 01:43:58 PM PST 23 |
| Finished | Nov 22 01:44:18 PM PST 23 |
| Peak memory | 200036 kb |
| Host | smart-18909e43-b676-49bf-9501-f30c6521b805 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=87705689015490545040252858155634356858095984080724899538887455909040766720162 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 5.uart_loopback.87705689015490545040252858155634356858095984080724899538887455909040766720162 |
| Directory | /workspace/5.uart_loopback/latest |
| Test location | /workspace/coverage/default/5.uart_noise_filter.29869766316872842842435435125913567841376839199049519150066358878927802274434 |
| Short name | T1032 |
| Test name | |
| Test status | |
| Simulation time | 94501577082 ps |
| CPU time | 98.11 seconds |
| Started | Nov 22 01:44:07 PM PST 23 |
| Finished | Nov 22 01:45:50 PM PST 23 |
| Peak memory | 200240 kb |
| Host | smart-ac188be6-afd2-4fa1-a8c9-2a0f7c86a452 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=29869766316872842842435435125913567841376839199049519150066358878927802274434 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_noise_filter.29869766316872842842435435125913567841376839199049519150066358878927802274434 |
| Directory | /workspace/5.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/5.uart_perf.26629029247004680824141409645589626670792863862864796084643809730200407675747 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 14098773881 ps |
| CPU time | 470.84 seconds |
| Started | Nov 22 01:44:09 PM PST 23 |
| Finished | Nov 22 01:52:04 PM PST 23 |
| Peak memory | 200156 kb |
| Host | smart-8af659fb-3de5-49c4-b1de-f7b4b393d8e5 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=26629029247004680824141409645589626670792863862864796084643809730200407675747 -assert nopostproc +UVM_TES TNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 5.uart_perf.26629029247004680824141409645589626670792863862864796084643809730200407675747 |
| Directory | /workspace/5.uart_perf/latest |
| Test location | /workspace/coverage/default/5.uart_rx_oversample.73704686751242043540173743924771965290192399505334467991624420526177109353292 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 4370280281 ps |
| CPU time | 20.15 seconds |
| Started | Nov 22 01:44:00 PM PST 23 |
| Finished | Nov 22 01:44:24 PM PST 23 |
| Peak memory | 198968 kb |
| Host | smart-959d912b-62b7-4f9d-b29d-e85bdaefc364 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=73704686751242043540173743924771965290192399505334467991624420526177109353292 -assert nopostproc +UVM_TES TNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 5.uart_rx_oversample.73704686751242043540173743924771965290192399505334467991624420526177109353292 |
| Directory | /workspace/5.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/5.uart_rx_parity_err.113090539865558667383453303188602190773134937562345319512079009201663322037522 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 36616611594 ps |
| CPU time | 37.93 seconds |
| Started | Nov 22 01:44:01 PM PST 23 |
| Finished | Nov 22 01:44:43 PM PST 23 |
| Peak memory | 200120 kb |
| Host | smart-e886a399-a0d7-455a-91cf-1b9ac05f5893 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=113090539865558667383453303188602190773134937562345319512079009201663322037522 -assert nopostproc +UVM_TESTNAME=uart_bas e_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 5.uart_rx_parity_err.113090539865558667383453303188602190773134937562345319512079009201663322037522 |
| Directory | /workspace/5.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/5.uart_rx_start_bit_filter.87444283063388991184228888644075701414760939816457267917752222289141934402331 |
| Short name | T714 |
| Test name | |
| Test status | |
| Simulation time | 4267638245 ps |
| CPU time | 4.7 seconds |
| Started | Nov 22 01:43:59 PM PST 23 |
| Finished | Nov 22 01:44:07 PM PST 23 |
| Peak memory | 196012 kb |
| Host | smart-d79a3660-d704-4f14-a784-23e5d09c4341 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=87444283063388991184228888644075701414760939816457267917752222289141934402331 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 5.uart_rx_start_bit_filter.87444283063388991184228888644075701414760939816457267917752222289141934402331 |
| Directory | /workspace/5.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/5.uart_smoke.3997516171486706418256757024253912280576177278713089046716852581236167828034 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 5759626309 ps |
| CPU time | 18.35 seconds |
| Started | Nov 22 01:43:57 PM PST 23 |
| Finished | Nov 22 01:44:19 PM PST 23 |
| Peak memory | 199584 kb |
| Host | smart-292a0514-9578-453d-b7e5-f98606d8dd55 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3997516171486706418256757024253912280576177278713089046716852581236167828034 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 5.uart_smoke.3997516171486706418256757024253912280576177278713089046716852581236167828034 |
| Directory | /workspace/5.uart_smoke/latest |
| Test location | /workspace/coverage/default/5.uart_stress_all.102259944699849249684355763105378473716015136883418559692582075653936776672172 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 43402307308 ps |
| CPU time | 57.68 seconds |
| Started | Nov 22 01:43:59 PM PST 23 |
| Finished | Nov 22 01:45:00 PM PST 23 |
| Peak memory | 200060 kb |
| Host | smart-78c8b49b-c721-4e48-a13e-132935bdb963 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102259944699849249684355763105378473716015136883418559692582075653936776672172 -assert nopo stproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 5.uart_stress_all.102259944699849249684355763105378473716015136883418559692582075653936776672172 |
| Directory | /workspace/5.uart_stress_all/latest |
| Test location | /workspace/coverage/default/5.uart_stress_all_with_rand_reset.114668704072154192405096669868462436528226374820598497194139487372821670381519 |
| Short name | T672 |
| Test name | |
| Test status | |
| Simulation time | 87476847566 ps |
| CPU time | 463.72 seconds |
| Started | Nov 22 01:44:18 PM PST 23 |
| Finished | Nov 22 01:52:05 PM PST 23 |
| Peak memory | 226112 kb |
| Host | smart-66718421-2b25-4cb6-8c98-110ecea3182d |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11466870407215419240509666 9868462436528226374820598497194139487372821670381519 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_stress_all_with_rand_reset.1146687040721 54192405096669868462436528226374820598497194139487372821670381519 |
| Directory | /workspace/5.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/5.uart_tx_ovrd.114251946499266824040755670859722091808115724777148759417011929369063908443247 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 485186362 ps |
| CPU time | 1.28 seconds |
| Started | Nov 22 01:43:38 PM PST 23 |
| Finished | Nov 22 01:43:41 PM PST 23 |
| Peak memory | 197912 kb |
| Host | smart-486cbf84-c389-43d2-a7f6-7124f0eee84a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=114251946499266824040755670859722091808115724777148759417011929369063908443247 -assert nopostproc +UVM_TESTNAME=uart_bas e_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 5.uart_tx_ovrd.114251946499266824040755670859722091808115724777148759417011929369063908443247 |
| Directory | /workspace/5.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/5.uart_tx_rx.110025571537656810728334697427194807576817678782101194745433582861527174415165 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 57391945390 ps |
| CPU time | 64.17 seconds |
| Started | Nov 22 01:43:43 PM PST 23 |
| Finished | Nov 22 01:44:48 PM PST 23 |
| Peak memory | 200060 kb |
| Host | smart-4b61d496-f152-4dbb-b643-28ca48479b60 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=110025571537656810728334697427194807576817678782101194745433582861527174415165 -assert nopostproc +UVM_TESTNAME=uart_bas e_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 5.uart_tx_rx.110025571537656810728334697427194807576817678782101194745433582861527174415165 |
| Directory | /workspace/5.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/50.uart_fifo_reset.85323552521192202104417321791449863383832987230816596080704290972430561746043 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 113.48 seconds |
| Started | Nov 22 01:45:30 PM PST 23 |
| Finished | Nov 22 01:47:25 PM PST 23 |
| Peak memory | 198924 kb |
| Host | smart-d817660d-de28-4c86-ab3b-60b3cdfbaa9c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=85323552521192202104417321791449863383832987230816596080704290972430561746043 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 50.uart_fifo_reset.85323552521192202104417321791449863383832987230816596080704290972430561746043 |
| Directory | /workspace/50.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/50.uart_stress_all_with_rand_reset.73483306979823131380440012683663749598346382991743663758956340752661267379341 |
| Short name | T693 |
| Test name | |
| Test status | |
| Simulation time | 87476847566 ps |
| CPU time | 462.77 seconds |
| Started | Nov 22 01:45:40 PM PST 23 |
| Finished | Nov 22 01:53:25 PM PST 23 |
| Peak memory | 226184 kb |
| Host | smart-1b138e23-43f8-4b0c-8640-f622d3f962dd |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73483306979823131380440012 683663749598346382991743663758956340752661267379341 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.uart_stress_all_with_rand_reset.7348330697982 3131380440012683663749598346382991743663758956340752661267379341 |
| Directory | /workspace/50.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/51.uart_fifo_reset.35071088157397563414938402502131371812503933023654873586599293343846669513164 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 113.66 seconds |
| Started | Nov 22 01:45:33 PM PST 23 |
| Finished | Nov 22 01:47:28 PM PST 23 |
| Peak memory | 198920 kb |
| Host | smart-a34bc847-cd94-4767-80af-04b6079323d5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=35071088157397563414938402502131371812503933023654873586599293343846669513164 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 51.uart_fifo_reset.35071088157397563414938402502131371812503933023654873586599293343846669513164 |
| Directory | /workspace/51.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/51.uart_stress_all_with_rand_reset.46905886211817266953030335844478819369984682501632856811358595466963204017887 |
| Short name | T1261 |
| Test name | |
| Test status | |
| Simulation time | 87476847566 ps |
| CPU time | 469.46 seconds |
| Started | Nov 22 01:45:28 PM PST 23 |
| Finished | Nov 22 01:53:19 PM PST 23 |
| Peak memory | 226240 kb |
| Host | smart-ba335d7c-76d4-467f-b833-878edff0c965 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46905886211817266953030335 844478819369984682501632856811358595466963204017887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.uart_stress_all_with_rand_reset.4690588621181 7266953030335844478819369984682501632856811358595466963204017887 |
| Directory | /workspace/51.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/52.uart_fifo_reset.33293189377250151054214998617222818168294742832086372840734645844793225508585 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 113.45 seconds |
| Started | Nov 22 01:45:40 PM PST 23 |
| Finished | Nov 22 01:47:36 PM PST 23 |
| Peak memory | 198804 kb |
| Host | smart-a07d47d9-3eff-4520-9df9-4a645a8b3a81 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=33293189377250151054214998617222818168294742832086372840734645844793225508585 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 52.uart_fifo_reset.33293189377250151054214998617222818168294742832086372840734645844793225508585 |
| Directory | /workspace/52.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/52.uart_stress_all_with_rand_reset.34488097205210554123873058439579689957201069213579443076300257412282271245491 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 87476847566 ps |
| CPU time | 480.47 seconds |
| Started | Nov 22 01:45:54 PM PST 23 |
| Finished | Nov 22 01:53:58 PM PST 23 |
| Peak memory | 226312 kb |
| Host | smart-317d3241-760a-4589-a598-aa331544d7c9 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34488097205210554123873058 439579689957201069213579443076300257412282271245491 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.uart_stress_all_with_rand_reset.3448809720521 0554123873058439579689957201069213579443076300257412282271245491 |
| Directory | /workspace/52.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/53.uart_fifo_reset.46339702878402629240661431600458597169694032095509395816911176097091498426491 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 113.63 seconds |
| Started | Nov 22 01:45:40 PM PST 23 |
| Finished | Nov 22 01:47:35 PM PST 23 |
| Peak memory | 198928 kb |
| Host | smart-5e79ba5f-1103-4a01-8a72-ca443eaac599 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=46339702878402629240661431600458597169694032095509395816911176097091498426491 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 53.uart_fifo_reset.46339702878402629240661431600458597169694032095509395816911176097091498426491 |
| Directory | /workspace/53.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/53.uart_stress_all_with_rand_reset.112743032954631274115747411071542099509734795196754364193138194099483064374939 |
| Short name | T957 |
| Test name | |
| Test status | |
| Simulation time | 87476847566 ps |
| CPU time | 469.29 seconds |
| Started | Nov 22 01:45:55 PM PST 23 |
| Finished | Nov 22 01:53:51 PM PST 23 |
| Peak memory | 226260 kb |
| Host | smart-b6113d6c-a811-4046-9add-32a68d4968bf |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11274303295463127411574741 1071542099509734795196754364193138194099483064374939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.uart_stress_all_with_rand_reset.112743032954 631274115747411071542099509734795196754364193138194099483064374939 |
| Directory | /workspace/53.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/54.uart_fifo_reset.24219431108913210776916091032049940993569186798014834922306942595133961143148 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 112.96 seconds |
| Started | Nov 22 01:45:57 PM PST 23 |
| Finished | Nov 22 01:47:57 PM PST 23 |
| Peak memory | 198936 kb |
| Host | smart-e2f8db37-f8b4-4ebf-9831-2a31afed2f01 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=24219431108913210776916091032049940993569186798014834922306942595133961143148 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 54.uart_fifo_reset.24219431108913210776916091032049940993569186798014834922306942595133961143148 |
| Directory | /workspace/54.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/54.uart_stress_all_with_rand_reset.2809179977236006580187485280007787511946795409120786049917676152142393876384 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 87476847566 ps |
| CPU time | 456.04 seconds |
| Started | Nov 22 01:45:46 PM PST 23 |
| Finished | Nov 22 01:53:24 PM PST 23 |
| Peak memory | 226220 kb |
| Host | smart-9fd018f4-fb9a-4564-8ff7-b4a7c8281768 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28091799772360065801874852 80007787511946795409120786049917676152142393876384 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.uart_stress_all_with_rand_reset.28091799772360 06580187485280007787511946795409120786049917676152142393876384 |
| Directory | /workspace/54.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/55.uart_fifo_reset.102604065954196255096987435297245858343183579155480328704414374267434453137434 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 112.87 seconds |
| Started | Nov 22 01:45:29 PM PST 23 |
| Finished | Nov 22 01:47:23 PM PST 23 |
| Peak memory | 198912 kb |
| Host | smart-3bae2337-7781-47aa-86a9-f90c30db097c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=102604065954196255096987435297245858343183579155480328704414374267434453137434 -assert nopostproc +UVM_TESTNAME=uart_bas e_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.uart_fifo_reset.102604065954196255096987435297245858343183579155480328704414374267434453137434 |
| Directory | /workspace/55.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/55.uart_stress_all_with_rand_reset.54263550423827455847491459424824411414456507954599499070525357992370488004328 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 87476847566 ps |
| CPU time | 469.01 seconds |
| Started | Nov 22 01:45:59 PM PST 23 |
| Finished | Nov 22 01:53:56 PM PST 23 |
| Peak memory | 226220 kb |
| Host | smart-4dd696e9-1d44-40c9-9e36-4b919ab00075 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54263550423827455847491459 424824411414456507954599499070525357992370488004328 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.uart_stress_all_with_rand_reset.5426355042382 7455847491459424824411414456507954599499070525357992370488004328 |
| Directory | /workspace/55.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/56.uart_fifo_reset.19510671236234743342813277570282624436848591731466921813735485693263368000723 |
| Short name | T1224 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 113.29 seconds |
| Started | Nov 22 01:45:51 PM PST 23 |
| Finished | Nov 22 01:47:46 PM PST 23 |
| Peak memory | 198956 kb |
| Host | smart-2d9e199f-9dbc-4a44-b86a-524302f7c566 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=19510671236234743342813277570282624436848591731466921813735485693263368000723 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 56.uart_fifo_reset.19510671236234743342813277570282624436848591731466921813735485693263368000723 |
| Directory | /workspace/56.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/56.uart_stress_all_with_rand_reset.5706082987308609394722253586500221510320293289628288223127777939836013021405 |
| Short name | T691 |
| Test name | |
| Test status | |
| Simulation time | 87476847566 ps |
| CPU time | 475.98 seconds |
| Started | Nov 22 01:45:40 PM PST 23 |
| Finished | Nov 22 01:53:38 PM PST 23 |
| Peak memory | 226272 kb |
| Host | smart-0cb59003-7d15-40fd-91ed-40ac8225353f |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57060829873086093947222535 86500221510320293289628288223127777939836013021405 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.uart_stress_all_with_rand_reset.57060829873086 09394722253586500221510320293289628288223127777939836013021405 |
| Directory | /workspace/56.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/57.uart_fifo_reset.17427784140654827883581939641016194243647754809845996509979508837459592495 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 113.86 seconds |
| Started | Nov 22 01:46:02 PM PST 23 |
| Finished | Nov 22 01:48:02 PM PST 23 |
| Peak memory | 198936 kb |
| Host | smart-dbdc21e9-83ff-4d79-a923-ab27c1a3bcb2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=17427784140654827883581939641016194243647754809845996509979508837459592495 -assert nopostproc +UVM_TESTNAME=uart_base_te st +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 57.uart_fifo_reset.17427784140654827883581939641016194243647754809845996509979508837459592495 |
| Directory | /workspace/57.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/57.uart_stress_all_with_rand_reset.110639531135420162267328391176216593704712194121866345919515428482242167702010 |
| Short name | T1110 |
| Test name | |
| Test status | |
| Simulation time | 87476847566 ps |
| CPU time | 458.58 seconds |
| Started | Nov 22 01:46:02 PM PST 23 |
| Finished | Nov 22 01:53:47 PM PST 23 |
| Peak memory | 226224 kb |
| Host | smart-2b5af1d1-9087-4442-ac04-cbdf2166f281 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11063953113542016226732839 1176216593704712194121866345919515428482242167702010 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.uart_stress_all_with_rand_reset.110639531135 420162267328391176216593704712194121866345919515428482242167702010 |
| Directory | /workspace/57.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/58.uart_fifo_reset.50973731055360578373763535272973842272900038921391313312578691871399651113150 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 113.67 seconds |
| Started | Nov 22 01:46:01 PM PST 23 |
| Finished | Nov 22 01:48:02 PM PST 23 |
| Peak memory | 198856 kb |
| Host | smart-bcd298c0-0213-4bc6-b743-f0dd07b626a3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=50973731055360578373763535272973842272900038921391313312578691871399651113150 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 58.uart_fifo_reset.50973731055360578373763535272973842272900038921391313312578691871399651113150 |
| Directory | /workspace/58.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/58.uart_stress_all_with_rand_reset.108114517991332592633461253363156139297296558917180554389263665433934440340538 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 87476847566 ps |
| CPU time | 477.18 seconds |
| Started | Nov 22 01:45:53 PM PST 23 |
| Finished | Nov 22 01:53:53 PM PST 23 |
| Peak memory | 226312 kb |
| Host | smart-46e769b2-fde9-4b6c-8406-b4432b697663 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10811451799133259263346125 3363156139297296558917180554389263665433934440340538 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.uart_stress_all_with_rand_reset.108114517991 332592633461253363156139297296558917180554389263665433934440340538 |
| Directory | /workspace/58.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/59.uart_fifo_reset.25014098682951166397705070513334360290743830632718776629748976980087315310746 |
| Short name | T1108 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 113.17 seconds |
| Started | Nov 22 01:45:46 PM PST 23 |
| Finished | Nov 22 01:47:42 PM PST 23 |
| Peak memory | 198956 kb |
| Host | smart-d564fa3e-c90e-4f7e-92d4-628d910045d0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=25014098682951166397705070513334360290743830632718776629748976980087315310746 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 59.uart_fifo_reset.25014098682951166397705070513334360290743830632718776629748976980087315310746 |
| Directory | /workspace/59.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/59.uart_stress_all_with_rand_reset.25077141315220657320325849888049623686909328961155538636407163781506182928383 |
| Short name | T774 |
| Test name | |
| Test status | |
| Simulation time | 87476847566 ps |
| CPU time | 468.94 seconds |
| Started | Nov 22 01:46:07 PM PST 23 |
| Finished | Nov 22 01:54:02 PM PST 23 |
| Peak memory | 226240 kb |
| Host | smart-de67ddb6-82da-4fb5-b878-4918aa2ac09e |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25077141315220657320325849 888049623686909328961155538636407163781506182928383 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.uart_stress_all_with_rand_reset.2507714131522 0657320325849888049623686909328961155538636407163781506182928383 |
| Directory | /workspace/59.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/6.uart_alert_test.79629727336417931773977491968028995249448913629463940167273415827485016651655 |
| Short name | T929 |
| Test name | |
| Test status | |
| Simulation time | 16368684 ps |
| CPU time | 0.54 seconds |
| Started | Nov 22 01:43:54 PM PST 23 |
| Finished | Nov 22 01:43:58 PM PST 23 |
| Peak memory | 194588 kb |
| Host | smart-23b032ce-1086-483b-9488-2add0573d604 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79629727336417931773977491968028995249448913629463940167273415827485016651655 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 6.uart_alert_test.79629727336417931773977491968028995249448913629463940167273415827485016651655 |
| Directory | /workspace/6.uart_alert_test/latest |
| Test location | /workspace/coverage/default/6.uart_fifo_full.74149626528321776606766808240223514405666975947788141572951939983851307866513 |
| Short name | T963 |
| Test name | |
| Test status | |
| Simulation time | 61777160308 ps |
| CPU time | 60.43 seconds |
| Started | Nov 22 01:44:05 PM PST 23 |
| Finished | Nov 22 01:45:11 PM PST 23 |
| Peak memory | 200124 kb |
| Host | smart-a39f7446-c3b6-4903-8915-30d303ff11a7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=74149626528321776606766808240223514405666975947788141572951939983851307866513 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 6.uart_fifo_full.74149626528321776606766808240223514405666975947788141572951939983851307866513 |
| Directory | /workspace/6.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/6.uart_fifo_overflow.41915830395107818801516642273134957555656151773329177100721265819446520727456 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 58551936110 ps |
| CPU time | 54.48 seconds |
| Started | Nov 22 01:44:03 PM PST 23 |
| Finished | Nov 22 01:45:02 PM PST 23 |
| Peak memory | 199884 kb |
| Host | smart-e58202e9-2a62-4df5-8c31-ff8a8058d921 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=41915830395107818801516642273134957555656151773329177100721265819446520727456 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 6.uart_fifo_overflow.41915830395107818801516642273134957555656151773329177100721265819446520727456 |
| Directory | /workspace/6.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/6.uart_fifo_reset.108394649096298024425142533327666165628655582584529827956963019511900917119959 |
| Short name | T1175 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 112.81 seconds |
| Started | Nov 22 01:43:52 PM PST 23 |
| Finished | Nov 22 01:45:48 PM PST 23 |
| Peak memory | 198920 kb |
| Host | smart-70f80269-5621-4c14-aeec-ef34f86f9760 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=108394649096298024425142533327666165628655582584529827956963019511900917119959 -assert nopostproc +UVM_TESTNAME=uart_bas e_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_reset.108394649096298024425142533327666165628655582584529827956963019511900917119959 |
| Directory | /workspace/6.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/6.uart_intr.30087311794084405411179842237927466994010806504849333937442370666288855624466 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 787145125175 ps |
| CPU time | 787.07 seconds |
| Started | Nov 22 01:44:01 PM PST 23 |
| Finished | Nov 22 01:57:12 PM PST 23 |
| Peak memory | 200160 kb |
| Host | smart-ecd4bcd8-ee7a-4989-bc7a-67ac62b23091 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30087311794084405411179842237927466994010806504849333937442370666288855624466 -assert nopost proc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 6.uart_intr.30087311794084405411179842237927466994010806504849333937442370666288855624466 |
| Directory | /workspace/6.uart_intr/latest |
| Test location | /workspace/coverage/default/6.uart_long_xfer_wo_dly.23328983918488964811181185596080690448319846768284609793204977285921261602646 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 93387746707 ps |
| CPU time | 354.11 seconds |
| Started | Nov 22 01:44:10 PM PST 23 |
| Finished | Nov 22 01:50:08 PM PST 23 |
| Peak memory | 200172 kb |
| Host | smart-e89433fb-8a12-43d6-b6d9-807ed9b2f8c6 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=23328983918488964811181185596080690448319846768284609793204977285921261602646 -assert nopostproc +UVM_TES TNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 6.uart_long_xfer_wo_dly.23328983918488964811181185596080690448319846768284609793204977285921261602646 |
| Directory | /workspace/6.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/6.uart_loopback.115156245187290939204333837708060075446706982883022410517561750887103719419119 |
| Short name | T694 |
| Test name | |
| Test status | |
| Simulation time | 14572448663 ps |
| CPU time | 16.18 seconds |
| Started | Nov 22 01:44:01 PM PST 23 |
| Finished | Nov 22 01:44:21 PM PST 23 |
| Peak memory | 200044 kb |
| Host | smart-163707c5-2a55-4183-a764-7c8ebdca6927 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=115156245187290939204333837708060075446706982883022410517561750887103719419119 -assert nopostproc +UVM_TESTNAME=uart_bas e_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 6.uart_loopback.115156245187290939204333837708060075446706982883022410517561750887103719419119 |
| Directory | /workspace/6.uart_loopback/latest |
| Test location | /workspace/coverage/default/6.uart_noise_filter.38219273071926993710938715402098077119845546303164482388179659105498508147891 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 94501577082 ps |
| CPU time | 97.16 seconds |
| Started | Nov 22 01:44:04 PM PST 23 |
| Finished | Nov 22 01:45:45 PM PST 23 |
| Peak memory | 200252 kb |
| Host | smart-a16457c8-0c51-4274-8288-4b1752a33041 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=38219273071926993710938715402098077119845546303164482388179659105498508147891 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_noise_filter.38219273071926993710938715402098077119845546303164482388179659105498508147891 |
| Directory | /workspace/6.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/6.uart_perf.94704833984362079821531185023839508983669855387161183097093125250266952940922 |
| Short name | T881 |
| Test name | |
| Test status | |
| Simulation time | 14098773881 ps |
| CPU time | 469.73 seconds |
| Started | Nov 22 01:44:06 PM PST 23 |
| Finished | Nov 22 01:52:01 PM PST 23 |
| Peak memory | 200108 kb |
| Host | smart-f7671768-aeca-4217-9240-1156c1c519f1 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=94704833984362079821531185023839508983669855387161183097093125250266952940922 -assert nopostproc +UVM_TES TNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 6.uart_perf.94704833984362079821531185023839508983669855387161183097093125250266952940922 |
| Directory | /workspace/6.uart_perf/latest |
| Test location | /workspace/coverage/default/6.uart_rx_oversample.102327126461938643469997334562786806308363622763685722267605632549221816225613 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 4370280281 ps |
| CPU time | 19.65 seconds |
| Started | Nov 22 01:43:55 PM PST 23 |
| Finished | Nov 22 01:44:18 PM PST 23 |
| Peak memory | 198864 kb |
| Host | smart-cd3f6027-95a7-4b85-aed3-8b8c0129b1fa |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=102327126461938643469997334562786806308363622763685722267605632549221816225613 -assert nopostproc +UVM_TE STNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_oversample.102327126461938643469997334562786806308363622763685722267605632549221816225613 |
| Directory | /workspace/6.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/6.uart_rx_parity_err.25934628719851388631095894859025952808355805008504467887108552329906041481105 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 36616611594 ps |
| CPU time | 37.84 seconds |
| Started | Nov 22 01:44:10 PM PST 23 |
| Finished | Nov 22 01:44:52 PM PST 23 |
| Peak memory | 200124 kb |
| Host | smart-cea51885-f585-4170-af40-0f0d4e496138 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=25934628719851388631095894859025952808355805008504467887108552329906041481105 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 6.uart_rx_parity_err.25934628719851388631095894859025952808355805008504467887108552329906041481105 |
| Directory | /workspace/6.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/6.uart_rx_start_bit_filter.97212524060598917386184430287985422616188775470974207697016106498804904009761 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 4267638245 ps |
| CPU time | 4.67 seconds |
| Started | Nov 22 01:43:46 PM PST 23 |
| Finished | Nov 22 01:43:52 PM PST 23 |
| Peak memory | 195832 kb |
| Host | smart-a6608e2a-07af-4d34-bf49-fdeba217c642 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=97212524060598917386184430287985422616188775470974207697016106498804904009761 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 6.uart_rx_start_bit_filter.97212524060598917386184430287985422616188775470974207697016106498804904009761 |
| Directory | /workspace/6.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/6.uart_smoke.33245974808179833470758026077375951068326519452245178500444073113285000730124 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 5759626309 ps |
| CPU time | 17.92 seconds |
| Started | Nov 22 01:44:14 PM PST 23 |
| Finished | Nov 22 01:44:35 PM PST 23 |
| Peak memory | 199544 kb |
| Host | smart-417453f2-85b0-44d5-9224-a9dbe361d581 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=33245974808179833470758026077375951068326519452245178500444073113285000730124 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 6.uart_smoke.33245974808179833470758026077375951068326519452245178500444073113285000730124 |
| Directory | /workspace/6.uart_smoke/latest |
| Test location | /workspace/coverage/default/6.uart_stress_all.58817594705159641875418424791602143567701585409701965587580732883258998324768 |
| Short name | T700 |
| Test name | |
| Test status | |
| Simulation time | 43402307308 ps |
| CPU time | 56.25 seconds |
| Started | Nov 22 01:43:59 PM PST 23 |
| Finished | Nov 22 01:44:59 PM PST 23 |
| Peak memory | 200104 kb |
| Host | smart-3e4121c1-8e55-4cff-b66b-253e3d030699 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58817594705159641875418424791602143567701585409701965587580732883258998324768 -assert nopos tproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 6.uart_stress_all.58817594705159641875418424791602143567701585409701965587580732883258998324768 |
| Directory | /workspace/6.uart_stress_all/latest |
| Test location | /workspace/coverage/default/6.uart_stress_all_with_rand_reset.8823486786980911703780532980079061141365059046094423533663403274866318792430 |
| Short name | T666 |
| Test name | |
| Test status | |
| Simulation time | 87476847566 ps |
| CPU time | 476.21 seconds |
| Started | Nov 22 01:44:02 PM PST 23 |
| Finished | Nov 22 01:52:03 PM PST 23 |
| Peak memory | 226240 kb |
| Host | smart-bad7737e-d291-43c6-b4e8-d8b175bfa163 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88234867869809117037805329 80079061141365059046094423533663403274866318792430 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_stress_all_with_rand_reset.882348678698091 1703780532980079061141365059046094423533663403274866318792430 |
| Directory | /workspace/6.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/6.uart_tx_ovrd.26138376958840815159649429357467816417167596189910480766117965495442223751327 |
| Short name | T872 |
| Test name | |
| Test status | |
| Simulation time | 485186362 ps |
| CPU time | 1.23 seconds |
| Started | Nov 22 01:44:17 PM PST 23 |
| Finished | Nov 22 01:44:22 PM PST 23 |
| Peak memory | 197788 kb |
| Host | smart-95fd8b1a-37df-4c49-8298-4f1444a2efa1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=26138376958840815159649429357467816417167596189910480766117965495442223751327 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 6.uart_tx_ovrd.26138376958840815159649429357467816417167596189910480766117965495442223751327 |
| Directory | /workspace/6.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/6.uart_tx_rx.100228394504520586605305546278637881114332119730968781374856918555321552012513 |
| Short name | T1219 |
| Test name | |
| Test status | |
| Simulation time | 57391945390 ps |
| CPU time | 62.83 seconds |
| Started | Nov 22 01:44:14 PM PST 23 |
| Finished | Nov 22 01:45:20 PM PST 23 |
| Peak memory | 200076 kb |
| Host | smart-0957fa9c-3544-42fa-94af-0e81c39bf7c3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=100228394504520586605305546278637881114332119730968781374856918555321552012513 -assert nopostproc +UVM_TESTNAME=uart_bas e_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 6.uart_tx_rx.100228394504520586605305546278637881114332119730968781374856918555321552012513 |
| Directory | /workspace/6.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/60.uart_fifo_reset.84115571043794491686403987594035495875645731195713432641730381666396837858999 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 113.11 seconds |
| Started | Nov 22 01:45:55 PM PST 23 |
| Finished | Nov 22 01:47:51 PM PST 23 |
| Peak memory | 198600 kb |
| Host | smart-2b2a54cb-6e8a-479e-8850-29fc7abf59c2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=84115571043794491686403987594035495875645731195713432641730381666396837858999 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 60.uart_fifo_reset.84115571043794491686403987594035495875645731195713432641730381666396837858999 |
| Directory | /workspace/60.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/60.uart_stress_all_with_rand_reset.40298788726335522101774200724890653820368279131825435313557548562069138834911 |
| Short name | T1123 |
| Test name | |
| Test status | |
| Simulation time | 87476847566 ps |
| CPU time | 465.02 seconds |
| Started | Nov 22 01:46:07 PM PST 23 |
| Finished | Nov 22 01:53:58 PM PST 23 |
| Peak memory | 226240 kb |
| Host | smart-4490b588-efc0-41ec-a80c-bbe95ded173f |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40298788726335522101774200 724890653820368279131825435313557548562069138834911 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.uart_stress_all_with_rand_reset.4029878872633 5522101774200724890653820368279131825435313557548562069138834911 |
| Directory | /workspace/60.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/61.uart_fifo_reset.13493704843495180608946912617492940259694543463447526190442569721736764541777 |
| Short name | T708 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 112.58 seconds |
| Started | Nov 22 01:45:57 PM PST 23 |
| Finished | Nov 22 01:47:58 PM PST 23 |
| Peak memory | 198792 kb |
| Host | smart-bbdaa9af-fc56-4b19-b926-be49bfd56c1e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=13493704843495180608946912617492940259694543463447526190442569721736764541777 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 61.uart_fifo_reset.13493704843495180608946912617492940259694543463447526190442569721736764541777 |
| Directory | /workspace/61.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/61.uart_stress_all_with_rand_reset.82447300322154529150033693429113910828464481941500251355887845416325634841255 |
| Short name | T1250 |
| Test name | |
| Test status | |
| Simulation time | 87476847566 ps |
| CPU time | 462.13 seconds |
| Started | Nov 22 01:46:04 PM PST 23 |
| Finished | Nov 22 01:53:51 PM PST 23 |
| Peak memory | 226220 kb |
| Host | smart-aeb320df-dd07-4427-81fe-d50e9ee6f188 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82447300322154529150033693 429113910828464481941500251355887845416325634841255 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.uart_stress_all_with_rand_reset.8244730032215 4529150033693429113910828464481941500251355887845416325634841255 |
| Directory | /workspace/61.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/62.uart_fifo_reset.115567333529995235887175017419604439772203848582815136092544411581591427021753 |
| Short name | T850 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 113.12 seconds |
| Started | Nov 22 01:46:24 PM PST 23 |
| Finished | Nov 22 01:48:19 PM PST 23 |
| Peak memory | 198888 kb |
| Host | smart-b5c3c4cf-7b2b-4cfc-b1af-6807f2d02231 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=115567333529995235887175017419604439772203848582815136092544411581591427021753 -assert nopostproc +UVM_TESTNAME=uart_bas e_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.uart_fifo_reset.115567333529995235887175017419604439772203848582815136092544411581591427021753 |
| Directory | /workspace/62.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/62.uart_stress_all_with_rand_reset.58553781865933917283644073392269355558695723167989372494487841423510583214619 |
| Short name | T841 |
| Test name | |
| Test status | |
| Simulation time | 87476847566 ps |
| CPU time | 451.01 seconds |
| Started | Nov 22 01:46:18 PM PST 23 |
| Finished | Nov 22 01:53:50 PM PST 23 |
| Peak memory | 226164 kb |
| Host | smart-4340b985-285f-496b-96b7-cfe64548c4c4 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58553781865933917283644073 392269355558695723167989372494487841423510583214619 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.uart_stress_all_with_rand_reset.5855378186593 3917283644073392269355558695723167989372494487841423510583214619 |
| Directory | /workspace/62.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/63.uart_fifo_reset.63160473761936836177120028421315410782303238542628452120179575111871008565039 |
| Short name | T899 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 113.58 seconds |
| Started | Nov 22 01:46:10 PM PST 23 |
| Finished | Nov 22 01:48:09 PM PST 23 |
| Peak memory | 198872 kb |
| Host | smart-2097debf-7e1d-4c0c-a12d-b615879358ad |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=63160473761936836177120028421315410782303238542628452120179575111871008565039 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 63.uart_fifo_reset.63160473761936836177120028421315410782303238542628452120179575111871008565039 |
| Directory | /workspace/63.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/63.uart_stress_all_with_rand_reset.61745937633678568048727446192192529175274051701429685858967511493222570559551 |
| Short name | T1178 |
| Test name | |
| Test status | |
| Simulation time | 87476847566 ps |
| CPU time | 468.7 seconds |
| Started | Nov 22 01:46:05 PM PST 23 |
| Finished | Nov 22 01:54:01 PM PST 23 |
| Peak memory | 226244 kb |
| Host | smart-e05bfa5c-9000-4b69-869b-4d2a8c2fdb7d |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61745937633678568048727446 192192529175274051701429685858967511493222570559551 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.uart_stress_all_with_rand_reset.6174593763367 8568048727446192192529175274051701429685858967511493222570559551 |
| Directory | /workspace/63.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/64.uart_fifo_reset.80832995571771748593791819029368585709393407608894186595736947710159017209501 |
| Short name | T1255 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 112.75 seconds |
| Started | Nov 22 01:46:15 PM PST 23 |
| Finished | Nov 22 01:48:10 PM PST 23 |
| Peak memory | 198760 kb |
| Host | smart-fa23adbb-a03e-49d3-962b-b65546a07990 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=80832995571771748593791819029368585709393407608894186595736947710159017209501 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 64.uart_fifo_reset.80832995571771748593791819029368585709393407608894186595736947710159017209501 |
| Directory | /workspace/64.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/64.uart_stress_all_with_rand_reset.38499817383994061634830418494069357023489434786938138563615252004399129163458 |
| Short name | T953 |
| Test name | |
| Test status | |
| Simulation time | 87476847566 ps |
| CPU time | 466.16 seconds |
| Started | Nov 22 01:45:59 PM PST 23 |
| Finished | Nov 22 01:53:53 PM PST 23 |
| Peak memory | 226100 kb |
| Host | smart-596b0169-1a6f-431b-948c-627aa848058b |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38499817383994061634830418 494069357023489434786938138563615252004399129163458 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.uart_stress_all_with_rand_reset.3849981738399 4061634830418494069357023489434786938138563615252004399129163458 |
| Directory | /workspace/64.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/65.uart_fifo_reset.100632193376800099573263139064445478321832914990093971858788839426275766865294 |
| Short name | T772 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 113.86 seconds |
| Started | Nov 22 01:46:05 PM PST 23 |
| Finished | Nov 22 01:48:06 PM PST 23 |
| Peak memory | 198908 kb |
| Host | smart-90fed63b-e914-420f-9454-281243dd35bf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=100632193376800099573263139064445478321832914990093971858788839426275766865294 -assert nopostproc +UVM_TESTNAME=uart_bas e_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.uart_fifo_reset.100632193376800099573263139064445478321832914990093971858788839426275766865294 |
| Directory | /workspace/65.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/65.uart_stress_all_with_rand_reset.5730000557335497873773612368983708461179491151399092561466423253533477032106 |
| Short name | T1243 |
| Test name | |
| Test status | |
| Simulation time | 87476847566 ps |
| CPU time | 467.51 seconds |
| Started | Nov 22 01:46:21 PM PST 23 |
| Finished | Nov 22 01:54:10 PM PST 23 |
| Peak memory | 226188 kb |
| Host | smart-ed6f5ec8-6530-4e22-9720-a96f1d474a74 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57300005573354978737736123 68983708461179491151399092561466423253533477032106 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.uart_stress_all_with_rand_reset.57300005573354 97873773612368983708461179491151399092561466423253533477032106 |
| Directory | /workspace/65.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/66.uart_fifo_reset.90024371717439566060727197847712495659060318830972213084127381940894292505990 |
| Short name | T1238 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 113.08 seconds |
| Started | Nov 22 01:46:16 PM PST 23 |
| Finished | Nov 22 01:48:11 PM PST 23 |
| Peak memory | 198860 kb |
| Host | smart-cd155d04-7922-4109-997a-f79a22c84e8b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=90024371717439566060727197847712495659060318830972213084127381940894292505990 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 66.uart_fifo_reset.90024371717439566060727197847712495659060318830972213084127381940894292505990 |
| Directory | /workspace/66.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/66.uart_stress_all_with_rand_reset.1905375237663208273515543272829776985681654630982937121685802655678975763164 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 87476847566 ps |
| CPU time | 452.69 seconds |
| Started | Nov 22 01:46:19 PM PST 23 |
| Finished | Nov 22 01:53:53 PM PST 23 |
| Peak memory | 226176 kb |
| Host | smart-3b7f136b-c738-4d04-b55c-71ae26321e62 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19053752376632082735155432 72829776985681654630982937121685802655678975763164 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.uart_stress_all_with_rand_reset.19053752376632 08273515543272829776985681654630982937121685802655678975763164 |
| Directory | /workspace/66.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/67.uart_fifo_reset.48930062300643825716475592344079341132688616223001572118720524664401423822485 |
| Short name | T776 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 114.54 seconds |
| Started | Nov 22 01:46:21 PM PST 23 |
| Finished | Nov 22 01:48:17 PM PST 23 |
| Peak memory | 198880 kb |
| Host | smart-b607d0ff-b522-458e-a3fb-23b80be749bb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=48930062300643825716475592344079341132688616223001572118720524664401423822485 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 67.uart_fifo_reset.48930062300643825716475592344079341132688616223001572118720524664401423822485 |
| Directory | /workspace/67.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/67.uart_stress_all_with_rand_reset.51903495574605849887975336685684151254598691461607581226504740197560233589890 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 87476847566 ps |
| CPU time | 446.75 seconds |
| Started | Nov 22 01:46:17 PM PST 23 |
| Finished | Nov 22 01:53:45 PM PST 23 |
| Peak memory | 226164 kb |
| Host | smart-018134dd-a9f3-4796-ada3-6036647272e9 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51903495574605849887975336 685684151254598691461607581226504740197560233589890 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.uart_stress_all_with_rand_reset.5190349557460 5849887975336685684151254598691461607581226504740197560233589890 |
| Directory | /workspace/67.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/68.uart_fifo_reset.79220053333800432122135508587259488049540804721922850748100920459456254025206 |
| Short name | T955 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 112.4 seconds |
| Started | Nov 22 01:45:54 PM PST 23 |
| Finished | Nov 22 01:47:50 PM PST 23 |
| Peak memory | 198900 kb |
| Host | smart-f35ecb7d-176e-439f-a1cb-13e6d88f35ce |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=79220053333800432122135508587259488049540804721922850748100920459456254025206 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 68.uart_fifo_reset.79220053333800432122135508587259488049540804721922850748100920459456254025206 |
| Directory | /workspace/68.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/68.uart_stress_all_with_rand_reset.8052885377995041989976892762802617759385908184497497070840565900655373137984 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 87476847566 ps |
| CPU time | 456.12 seconds |
| Started | Nov 22 01:45:42 PM PST 23 |
| Finished | Nov 22 01:53:20 PM PST 23 |
| Peak memory | 226192 kb |
| Host | smart-8cb31af4-abca-4c4a-aea9-fd7112863a40 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80528853779950419899768927 62802617759385908184497497070840565900655373137984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.uart_stress_all_with_rand_reset.80528853779950 41989976892762802617759385908184497497070840565900655373137984 |
| Directory | /workspace/68.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/69.uart_fifo_reset.94629838679404687207496692288826432280414442688432332737592793779305774046415 |
| Short name | T1234 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 113.21 seconds |
| Started | Nov 22 01:45:39 PM PST 23 |
| Finished | Nov 22 01:47:34 PM PST 23 |
| Peak memory | 198920 kb |
| Host | smart-27e8dc02-3771-4610-8243-632c486c18eb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=94629838679404687207496692288826432280414442688432332737592793779305774046415 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 69.uart_fifo_reset.94629838679404687207496692288826432280414442688432332737592793779305774046415 |
| Directory | /workspace/69.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/69.uart_stress_all_with_rand_reset.104546329765546649494760126324339749141846181064120139093083272737338134594733 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 87476847566 ps |
| CPU time | 458.24 seconds |
| Started | Nov 22 01:45:29 PM PST 23 |
| Finished | Nov 22 01:53:09 PM PST 23 |
| Peak memory | 226060 kb |
| Host | smart-cddaf77b-f8cd-4fa7-b640-c2da87bca62f |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10454632976554664949476012 6324339749141846181064120139093083272737338134594733 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.uart_stress_all_with_rand_reset.104546329765 546649494760126324339749141846181064120139093083272737338134594733 |
| Directory | /workspace/69.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/7.uart_alert_test.100509185128038482748795035991337571486865139326826963195666921785254090473916 |
| Short name | T968 |
| Test name | |
| Test status | |
| Simulation time | 16368684 ps |
| CPU time | 0.59 seconds |
| Started | Nov 22 01:44:15 PM PST 23 |
| Finished | Nov 22 01:44:19 PM PST 23 |
| Peak memory | 194580 kb |
| Host | smart-3c6723c3-73bd-4aa1-b7e8-6395a601481e |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100509185128038482748795035991337571486865139326826963195666921785254090473916 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 7.uart_alert_test.100509185128038482748795035991337571486865139326826963195666921785254090473916 |
| Directory | /workspace/7.uart_alert_test/latest |
| Test location | /workspace/coverage/default/7.uart_fifo_full.11588549142596045471680238486251350969208381305261438049278455365755243730407 |
| Short name | T1006 |
| Test name | |
| Test status | |
| Simulation time | 61777160308 ps |
| CPU time | 61.16 seconds |
| Started | Nov 22 01:44:02 PM PST 23 |
| Finished | Nov 22 01:45:07 PM PST 23 |
| Peak memory | 200024 kb |
| Host | smart-f93ee480-2a0e-4f4a-b151-205a0543315a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=11588549142596045471680238486251350969208381305261438049278455365755243730407 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 7.uart_fifo_full.11588549142596045471680238486251350969208381305261438049278455365755243730407 |
| Directory | /workspace/7.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/7.uart_fifo_overflow.37827822475828515988206252631481530044685421980930074214237103466453510352496 |
| Short name | T1217 |
| Test name | |
| Test status | |
| Simulation time | 58551936110 ps |
| CPU time | 54.42 seconds |
| Started | Nov 22 01:43:56 PM PST 23 |
| Finished | Nov 22 01:44:54 PM PST 23 |
| Peak memory | 199844 kb |
| Host | smart-2d49fa8b-d799-4a1b-807f-c1eaebd3a009 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=37827822475828515988206252631481530044685421980930074214237103466453510352496 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 7.uart_fifo_overflow.37827822475828515988206252631481530044685421980930074214237103466453510352496 |
| Directory | /workspace/7.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/7.uart_fifo_reset.27677399018150994828736264427086883473052316474782202302153742447952488596904 |
| Short name | T838 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 113.73 seconds |
| Started | Nov 22 01:43:58 PM PST 23 |
| Finished | Nov 22 01:45:56 PM PST 23 |
| Peak memory | 198944 kb |
| Host | smart-4cebf689-ae63-4247-889b-a6fee20d0e0e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=27677399018150994828736264427086883473052316474782202302153742447952488596904 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 7.uart_fifo_reset.27677399018150994828736264427086883473052316474782202302153742447952488596904 |
| Directory | /workspace/7.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/7.uart_intr.883712596434263236016052009183322129745539801217495616420013434594183680625 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 787145125175 ps |
| CPU time | 795.82 seconds |
| Started | Nov 22 01:44:21 PM PST 23 |
| Finished | Nov 22 01:57:43 PM PST 23 |
| Peak memory | 200068 kb |
| Host | smart-bdac95b7-304a-470d-a599-31c3814f3fd6 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883712596434263236016052009183322129745539801217495616420013434594183680625 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_intr.883712596434263236016052009183322129745539801217495616420013434594183680625 |
| Directory | /workspace/7.uart_intr/latest |
| Test location | /workspace/coverage/default/7.uart_long_xfer_wo_dly.108525121429259843608282818386954757943304919271523387318064625916298779703368 |
| Short name | T1207 |
| Test name | |
| Test status | |
| Simulation time | 93387746707 ps |
| CPU time | 354.43 seconds |
| Started | Nov 22 01:44:01 PM PST 23 |
| Finished | Nov 22 01:50:00 PM PST 23 |
| Peak memory | 200136 kb |
| Host | smart-6ad92f3b-6c1c-413a-945b-4fe0f699fc4c |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=108525121429259843608282818386954757943304919271523387318064625916298779703368 -assert nopostproc +UVM_TE STNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 7.uart_long_xfer_wo_dly.108525121429259843608282818386954757943304919271523387318064625916298779703368 |
| Directory | /workspace/7.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/7.uart_loopback.57485448477742010926087786530710982274089426805032518032798630904723941684875 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 14572448663 ps |
| CPU time | 16.12 seconds |
| Started | Nov 22 01:43:55 PM PST 23 |
| Finished | Nov 22 01:44:15 PM PST 23 |
| Peak memory | 200012 kb |
| Host | smart-7160a60a-5f5b-4920-b30f-350c46cb7f5a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=57485448477742010926087786530710982274089426805032518032798630904723941684875 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 7.uart_loopback.57485448477742010926087786530710982274089426805032518032798630904723941684875 |
| Directory | /workspace/7.uart_loopback/latest |
| Test location | /workspace/coverage/default/7.uart_noise_filter.104638756763118005671603512716877842868910031868050322602629606387092703057323 |
| Short name | T1012 |
| Test name | |
| Test status | |
| Simulation time | 94501577082 ps |
| CPU time | 97.54 seconds |
| Started | Nov 22 01:44:05 PM PST 23 |
| Finished | Nov 22 01:45:47 PM PST 23 |
| Peak memory | 200248 kb |
| Host | smart-7c0e0ecf-bfd2-4840-bdfd-1456b9e50f88 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=104638756763118005671603512716877842868910031868050322602629606387092703057323 -assert nopostproc +UVM_TESTNAME=uart_bas e_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 7.uart_noise_filter.104638756763118005671603512716877842868910031868050322602629606387092703057323 |
| Directory | /workspace/7.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/7.uart_rx_oversample.112922660681819487269985904736445787760845105371520241641596245117604955345424 |
| Short name | T882 |
| Test name | |
| Test status | |
| Simulation time | 4370280281 ps |
| CPU time | 19.22 seconds |
| Started | Nov 22 01:43:59 PM PST 23 |
| Finished | Nov 22 01:44:22 PM PST 23 |
| Peak memory | 198788 kb |
| Host | smart-95037b20-3388-48d2-9852-5f4863b0aa3e |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=112922660681819487269985904736445787760845105371520241641596245117604955345424 -assert nopostproc +UVM_TE STNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_oversample.112922660681819487269985904736445787760845105371520241641596245117604955345424 |
| Directory | /workspace/7.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/7.uart_rx_parity_err.16965553303815868580732082035469263030133885269128203703502634191155854173188 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 36616611594 ps |
| CPU time | 37.73 seconds |
| Started | Nov 22 01:44:02 PM PST 23 |
| Finished | Nov 22 01:44:44 PM PST 23 |
| Peak memory | 200120 kb |
| Host | smart-14d6eb15-495f-4290-b97d-06794b67d211 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=16965553303815868580732082035469263030133885269128203703502634191155854173188 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 7.uart_rx_parity_err.16965553303815868580732082035469263030133885269128203703502634191155854173188 |
| Directory | /workspace/7.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/7.uart_rx_start_bit_filter.17642676775617022004856380455008142128294853603700509357134360606170773204020 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 4267638245 ps |
| CPU time | 4.67 seconds |
| Started | Nov 22 01:43:46 PM PST 23 |
| Finished | Nov 22 01:43:52 PM PST 23 |
| Peak memory | 195876 kb |
| Host | smart-fb7b322b-8cf8-4375-95cb-7246f9612ddd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=17642676775617022004856380455008142128294853603700509357134360606170773204020 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 7.uart_rx_start_bit_filter.17642676775617022004856380455008142128294853603700509357134360606170773204020 |
| Directory | /workspace/7.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/7.uart_smoke.8487686729172255998149628353048203429102345146426650150450939018898686847776 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 5759626309 ps |
| CPU time | 17.69 seconds |
| Started | Nov 22 01:44:18 PM PST 23 |
| Finished | Nov 22 01:44:39 PM PST 23 |
| Peak memory | 199588 kb |
| Host | smart-3cc8a1a8-7809-4626-83d0-ef239d93c8a2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=8487686729172255998149628353048203429102345146426650150450939018898686847776 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 7.uart_smoke.8487686729172255998149628353048203429102345146426650150450939018898686847776 |
| Directory | /workspace/7.uart_smoke/latest |
| Test location | /workspace/coverage/default/7.uart_stress_all.92379482222129177017813691980759546974484820283996273096575434385821538727537 |
| Short name | T1078 |
| Test name | |
| Test status | |
| Simulation time | 43402307308 ps |
| CPU time | 57.68 seconds |
| Started | Nov 22 01:43:58 PM PST 23 |
| Finished | Nov 22 01:44:59 PM PST 23 |
| Peak memory | 200056 kb |
| Host | smart-769ed481-5c3f-4185-b477-56d4778512c7 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92379482222129177017813691980759546974484820283996273096575434385821538727537 -assert nopos tproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 7.uart_stress_all.92379482222129177017813691980759546974484820283996273096575434385821538727537 |
| Directory | /workspace/7.uart_stress_all/latest |
| Test location | /workspace/coverage/default/7.uart_stress_all_with_rand_reset.61695272519526688544134292245424632821402807231131877639616958444028427079412 |
| Short name | T1220 |
| Test name | |
| Test status | |
| Simulation time | 87476847566 ps |
| CPU time | 476.64 seconds |
| Started | Nov 22 01:44:02 PM PST 23 |
| Finished | Nov 22 01:52:03 PM PST 23 |
| Peak memory | 226216 kb |
| Host | smart-15b093d6-1370-4d61-b570-9f1bdd3a4593 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61695272519526688544134292 245424632821402807231131877639616958444028427079412 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_stress_all_with_rand_reset.61695272519526 688544134292245424632821402807231131877639616958444028427079412 |
| Directory | /workspace/7.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/7.uart_tx_ovrd.65819026776309061333276920063063715006674315892376793728466695786207574720630 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 485186362 ps |
| CPU time | 1.31 seconds |
| Started | Nov 22 01:43:57 PM PST 23 |
| Finished | Nov 22 01:44:02 PM PST 23 |
| Peak memory | 197900 kb |
| Host | smart-d8a38506-64be-4388-abc0-66fecbc45cb7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=65819026776309061333276920063063715006674315892376793728466695786207574720630 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 7.uart_tx_ovrd.65819026776309061333276920063063715006674315892376793728466695786207574720630 |
| Directory | /workspace/7.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/7.uart_tx_rx.102431715291772446562564940922131461745087890474657062574163091458014587437580 |
| Short name | T1017 |
| Test name | |
| Test status | |
| Simulation time | 57391945390 ps |
| CPU time | 63.46 seconds |
| Started | Nov 22 01:44:13 PM PST 23 |
| Finished | Nov 22 01:45:20 PM PST 23 |
| Peak memory | 199976 kb |
| Host | smart-6182b5f0-fc5e-43b2-bcf1-6e2b856ce5bf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=102431715291772446562564940922131461745087890474657062574163091458014587437580 -assert nopostproc +UVM_TESTNAME=uart_bas e_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 7.uart_tx_rx.102431715291772446562564940922131461745087890474657062574163091458014587437580 |
| Directory | /workspace/7.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/70.uart_fifo_reset.58801706360789993799750561039862318236735009675439284029696754350213845481830 |
| Short name | T1051 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 113.48 seconds |
| Started | Nov 22 01:45:55 PM PST 23 |
| Finished | Nov 22 01:47:55 PM PST 23 |
| Peak memory | 198940 kb |
| Host | smart-52da9aaa-f75e-47e7-907e-c2dbefdd88b2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=58801706360789993799750561039862318236735009675439284029696754350213845481830 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 70.uart_fifo_reset.58801706360789993799750561039862318236735009675439284029696754350213845481830 |
| Directory | /workspace/70.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/70.uart_stress_all_with_rand_reset.49584435281776506449504967840871086842506985664641208299966690968724911282216 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 87476847566 ps |
| CPU time | 469.31 seconds |
| Started | Nov 22 01:45:50 PM PST 23 |
| Finished | Nov 22 01:53:41 PM PST 23 |
| Peak memory | 226244 kb |
| Host | smart-8cd7bdc2-24f7-455d-84bf-7685b191ea30 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49584435281776506449504967 840871086842506985664641208299966690968724911282216 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.uart_stress_all_with_rand_reset.4958443528177 6506449504967840871086842506985664641208299966690968724911282216 |
| Directory | /workspace/70.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/71.uart_fifo_reset.23964181211618672344182182954459744323090969934384058397341463967128955733838 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 112.89 seconds |
| Started | Nov 22 01:45:44 PM PST 23 |
| Finished | Nov 22 01:47:39 PM PST 23 |
| Peak memory | 198932 kb |
| Host | smart-e7cfa110-5d2c-49de-920e-c0c0aa6855b4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=23964181211618672344182182954459744323090969934384058397341463967128955733838 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 71.uart_fifo_reset.23964181211618672344182182954459744323090969934384058397341463967128955733838 |
| Directory | /workspace/71.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/71.uart_stress_all_with_rand_reset.20061788681067714608883879789515318978349326831484537924608151476233069407481 |
| Short name | T771 |
| Test name | |
| Test status | |
| Simulation time | 87476847566 ps |
| CPU time | 463.55 seconds |
| Started | Nov 22 01:45:56 PM PST 23 |
| Finished | Nov 22 01:53:46 PM PST 23 |
| Peak memory | 226184 kb |
| Host | smart-a6620f19-ea7e-4e93-88ab-388eac15ebf0 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20061788681067714608883879 789515318978349326831484537924608151476233069407481 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.uart_stress_all_with_rand_reset.2006178868106 7714608883879789515318978349326831484537924608151476233069407481 |
| Directory | /workspace/71.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/72.uart_fifo_reset.77439063220820368705318283850389749484668197506665803350448124392022232769518 |
| Short name | T678 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 113.22 seconds |
| Started | Nov 22 01:45:51 PM PST 23 |
| Finished | Nov 22 01:47:46 PM PST 23 |
| Peak memory | 198932 kb |
| Host | smart-90a9ff15-a13f-4daf-9724-29e124fc6e57 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=77439063220820368705318283850389749484668197506665803350448124392022232769518 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 72.uart_fifo_reset.77439063220820368705318283850389749484668197506665803350448124392022232769518 |
| Directory | /workspace/72.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/72.uart_stress_all_with_rand_reset.97576522198409567671099702555855062841502471148693390560301664637737024168143 |
| Short name | T839 |
| Test name | |
| Test status | |
| Simulation time | 87476847566 ps |
| CPU time | 461.71 seconds |
| Started | Nov 22 01:45:44 PM PST 23 |
| Finished | Nov 22 01:53:28 PM PST 23 |
| Peak memory | 226248 kb |
| Host | smart-6ac1835f-f60f-4a0b-aca8-cea645167896 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97576522198409567671099702 555855062841502471148693390560301664637737024168143 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.uart_stress_all_with_rand_reset.9757652219840 9567671099702555855062841502471148693390560301664637737024168143 |
| Directory | /workspace/72.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/73.uart_fifo_reset.72565745750394415506917423111178584197322957530861778606661465858544959623472 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 113.37 seconds |
| Started | Nov 22 01:45:41 PM PST 23 |
| Finished | Nov 22 01:47:36 PM PST 23 |
| Peak memory | 198864 kb |
| Host | smart-de9251bd-410a-4b52-ba2d-d00bf5a3466f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=72565745750394415506917423111178584197322957530861778606661465858544959623472 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 73.uart_fifo_reset.72565745750394415506917423111178584197322957530861778606661465858544959623472 |
| Directory | /workspace/73.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/73.uart_stress_all_with_rand_reset.72202751032512120479541689470766515511349651480010265081988668334980407214787 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 87476847566 ps |
| CPU time | 472.18 seconds |
| Started | Nov 22 01:45:51 PM PST 23 |
| Finished | Nov 22 01:53:44 PM PST 23 |
| Peak memory | 226220 kb |
| Host | smart-92fc761c-edec-4c67-b40c-cb0fe61c79ef |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72202751032512120479541689 470766515511349651480010265081988668334980407214787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.uart_stress_all_with_rand_reset.7220275103251 2120479541689470766515511349651480010265081988668334980407214787 |
| Directory | /workspace/73.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/74.uart_fifo_reset.32425163482582537238045104113040771893920753642986168824389438694661527586105 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 113.05 seconds |
| Started | Nov 22 01:45:45 PM PST 23 |
| Finished | Nov 22 01:47:40 PM PST 23 |
| Peak memory | 198908 kb |
| Host | smart-ed2be553-28b6-41ea-9138-f0fcd08e3c4f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=32425163482582537238045104113040771893920753642986168824389438694661527586105 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 74.uart_fifo_reset.32425163482582537238045104113040771893920753642986168824389438694661527586105 |
| Directory | /workspace/74.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/74.uart_stress_all_with_rand_reset.73830087628374871233793770463323467878231860770860820235606694816570065671290 |
| Short name | T831 |
| Test name | |
| Test status | |
| Simulation time | 87476847566 ps |
| CPU time | 467.22 seconds |
| Started | Nov 22 01:45:40 PM PST 23 |
| Finished | Nov 22 01:53:29 PM PST 23 |
| Peak memory | 226120 kb |
| Host | smart-5146c6f7-beb5-4313-9f9f-913210e2663b |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73830087628374871233793770 463323467878231860770860820235606694816570065671290 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.uart_stress_all_with_rand_reset.7383008762837 4871233793770463323467878231860770860820235606694816570065671290 |
| Directory | /workspace/74.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/75.uart_fifo_reset.59563651853236058800347077527542934661067229092259192501173400235133057266230 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 112.63 seconds |
| Started | Nov 22 01:45:49 PM PST 23 |
| Finished | Nov 22 01:47:43 PM PST 23 |
| Peak memory | 198936 kb |
| Host | smart-d866803a-d8fd-4b2c-978d-617765e14251 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=59563651853236058800347077527542934661067229092259192501173400235133057266230 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 75.uart_fifo_reset.59563651853236058800347077527542934661067229092259192501173400235133057266230 |
| Directory | /workspace/75.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/75.uart_stress_all_with_rand_reset.9342251402376620256151259061416466071370346811522687960728857426398452568158 |
| Short name | T671 |
| Test name | |
| Test status | |
| Simulation time | 87476847566 ps |
| CPU time | 468.24 seconds |
| Started | Nov 22 01:45:40 PM PST 23 |
| Finished | Nov 22 01:53:29 PM PST 23 |
| Peak memory | 226188 kb |
| Host | smart-a64071fb-8f84-418c-aa4e-e5dbe16b2b27 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93422514023766202561512590 61416466071370346811522687960728857426398452568158 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.uart_stress_all_with_rand_reset.93422514023766 20256151259061416466071370346811522687960728857426398452568158 |
| Directory | /workspace/75.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/76.uart_fifo_reset.32499976448250704265386199411957699665585662800684563849529641078023894103097 |
| Short name | T847 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 114.19 seconds |
| Started | Nov 22 01:45:27 PM PST 23 |
| Finished | Nov 22 01:47:23 PM PST 23 |
| Peak memory | 198804 kb |
| Host | smart-feaab84b-c4cb-440a-983e-3a4c1d28318d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=32499976448250704265386199411957699665585662800684563849529641078023894103097 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 76.uart_fifo_reset.32499976448250704265386199411957699665585662800684563849529641078023894103097 |
| Directory | /workspace/76.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/76.uart_stress_all_with_rand_reset.99484129535479506506551209828996146285432981070643502723737116066375283290456 |
| Short name | T696 |
| Test name | |
| Test status | |
| Simulation time | 87476847566 ps |
| CPU time | 464.33 seconds |
| Started | Nov 22 01:45:47 PM PST 23 |
| Finished | Nov 22 01:53:33 PM PST 23 |
| Peak memory | 226236 kb |
| Host | smart-1535286a-9940-41f9-b988-cd00f2168181 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99484129535479506506551209 828996146285432981070643502723737116066375283290456 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.uart_stress_all_with_rand_reset.9948412953547 9506506551209828996146285432981070643502723737116066375283290456 |
| Directory | /workspace/76.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/77.uart_fifo_reset.12458207983236536089255777898536898796620583542386895144520871844082474064806 |
| Short name | T981 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 112.83 seconds |
| Started | Nov 22 01:45:44 PM PST 23 |
| Finished | Nov 22 01:47:39 PM PST 23 |
| Peak memory | 198932 kb |
| Host | smart-35f9a610-0793-4561-9b6e-53dce2ffeb43 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=12458207983236536089255777898536898796620583542386895144520871844082474064806 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 77.uart_fifo_reset.12458207983236536089255777898536898796620583542386895144520871844082474064806 |
| Directory | /workspace/77.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/77.uart_stress_all_with_rand_reset.60799578311705828047479546012334567743276773657460379915576969554760411366477 |
| Short name | T816 |
| Test name | |
| Test status | |
| Simulation time | 87476847566 ps |
| CPU time | 478.08 seconds |
| Started | Nov 22 01:45:57 PM PST 23 |
| Finished | Nov 22 01:54:02 PM PST 23 |
| Peak memory | 226256 kb |
| Host | smart-64ae5530-0dae-4bb8-93d0-856acdcba905 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60799578311705828047479546 012334567743276773657460379915576969554760411366477 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.uart_stress_all_with_rand_reset.6079957831170 5828047479546012334567743276773657460379915576969554760411366477 |
| Directory | /workspace/77.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/78.uart_fifo_reset.90013198430030000663948024749974571886489113699309245858527392600375869955456 |
| Short name | T765 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 113.13 seconds |
| Started | Nov 22 01:45:44 PM PST 23 |
| Finished | Nov 22 01:47:39 PM PST 23 |
| Peak memory | 198956 kb |
| Host | smart-3790a2b4-8cff-4def-90e6-52edb647ccee |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=90013198430030000663948024749974571886489113699309245858527392600375869955456 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 78.uart_fifo_reset.90013198430030000663948024749974571886489113699309245858527392600375869955456 |
| Directory | /workspace/78.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/78.uart_stress_all_with_rand_reset.8219411089538290215723662818373272674213900148322463393466115673185408939604 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 87476847566 ps |
| CPU time | 459.72 seconds |
| Started | Nov 22 01:45:45 PM PST 23 |
| Finished | Nov 22 01:53:27 PM PST 23 |
| Peak memory | 226208 kb |
| Host | smart-c7efec6a-6168-4ea9-be0a-06e64146d5d8 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82194110895382902157236628 18373272674213900148322463393466115673185408939604 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.uart_stress_all_with_rand_reset.82194110895382 90215723662818373272674213900148322463393466115673185408939604 |
| Directory | /workspace/78.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/79.uart_fifo_reset.60827595136391986222597090397405379091603719272798224298305167051394969030494 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 113.31 seconds |
| Started | Nov 22 01:45:40 PM PST 23 |
| Finished | Nov 22 01:47:35 PM PST 23 |
| Peak memory | 198860 kb |
| Host | smart-debd7df3-be55-4809-ab1f-eb852eabd563 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=60827595136391986222597090397405379091603719272798224298305167051394969030494 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 79.uart_fifo_reset.60827595136391986222597090397405379091603719272798224298305167051394969030494 |
| Directory | /workspace/79.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/79.uart_stress_all_with_rand_reset.48342854991905978815878795762314185622318906532818573930621824456018147779290 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 87476847566 ps |
| CPU time | 474.36 seconds |
| Started | Nov 22 01:45:42 PM PST 23 |
| Finished | Nov 22 01:53:38 PM PST 23 |
| Peak memory | 226236 kb |
| Host | smart-567ae4f4-ecbf-4a1c-9060-2199ff84d94c |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48342854991905978815878795 762314185622318906532818573930621824456018147779290 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.uart_stress_all_with_rand_reset.4834285499190 5978815878795762314185622318906532818573930621824456018147779290 |
| Directory | /workspace/79.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/8.uart_alert_test.99864036106782452335334059759529251456208666537247421759729698810550591744918 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 16368684 ps |
| CPU time | 0.54 seconds |
| Started | Nov 22 01:44:17 PM PST 23 |
| Finished | Nov 22 01:44:22 PM PST 23 |
| Peak memory | 194548 kb |
| Host | smart-87d1e63a-7087-4eb7-92d1-131a889faf17 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99864036106782452335334059759529251456208666537247421759729698810550591744918 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 8.uart_alert_test.99864036106782452335334059759529251456208666537247421759729698810550591744918 |
| Directory | /workspace/8.uart_alert_test/latest |
| Test location | /workspace/coverage/default/8.uart_fifo_full.31583702445369812700466578608644750964261750873805586003609402678999658972040 |
| Short name | T729 |
| Test name | |
| Test status | |
| Simulation time | 61777160308 ps |
| CPU time | 61.82 seconds |
| Started | Nov 22 01:44:03 PM PST 23 |
| Finished | Nov 22 01:45:10 PM PST 23 |
| Peak memory | 200072 kb |
| Host | smart-97a4fa1f-db79-4997-929b-9284380b856f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=31583702445369812700466578608644750964261750873805586003609402678999658972040 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 8.uart_fifo_full.31583702445369812700466578608644750964261750873805586003609402678999658972040 |
| Directory | /workspace/8.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/8.uart_fifo_overflow.90915120053008309252194016663574301233821697492067254119690982475750477271155 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 58551936110 ps |
| CPU time | 54.69 seconds |
| Started | Nov 22 01:43:59 PM PST 23 |
| Finished | Nov 22 01:44:57 PM PST 23 |
| Peak memory | 199788 kb |
| Host | smart-810d56b1-82ac-42ef-aa69-4b6e94f3bb55 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=90915120053008309252194016663574301233821697492067254119690982475750477271155 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 8.uart_fifo_overflow.90915120053008309252194016663574301233821697492067254119690982475750477271155 |
| Directory | /workspace/8.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/8.uart_fifo_reset.103199706240420650969719525026054558519229697910254733299335093650467033415619 |
| Short name | T866 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 113.1 seconds |
| Started | Nov 22 01:44:11 PM PST 23 |
| Finished | Nov 22 01:46:07 PM PST 23 |
| Peak memory | 198804 kb |
| Host | smart-b126549b-aa33-4f32-a110-23e53e4c2a87 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=103199706240420650969719525026054558519229697910254733299335093650467033415619 -assert nopostproc +UVM_TESTNAME=uart_bas e_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_reset.103199706240420650969719525026054558519229697910254733299335093650467033415619 |
| Directory | /workspace/8.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/8.uart_intr.56048167968737978598717736378686320722514867922533315862587376863971649727328 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 787145125175 ps |
| CPU time | 788.34 seconds |
| Started | Nov 22 01:44:02 PM PST 23 |
| Finished | Nov 22 01:57:14 PM PST 23 |
| Peak memory | 200024 kb |
| Host | smart-d6a5a1c0-0977-4f15-9f73-92a599dd44e1 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56048167968737978598717736378686320722514867922533315862587376863971649727328 -assert nopost proc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 8.uart_intr.56048167968737978598717736378686320722514867922533315862587376863971649727328 |
| Directory | /workspace/8.uart_intr/latest |
| Test location | /workspace/coverage/default/8.uart_long_xfer_wo_dly.69849828994711636111568449843694647341402952593506968355519473163639386605197 |
| Short name | T1023 |
| Test name | |
| Test status | |
| Simulation time | 93387746707 ps |
| CPU time | 351.2 seconds |
| Started | Nov 22 01:43:57 PM PST 23 |
| Finished | Nov 22 01:49:51 PM PST 23 |
| Peak memory | 200140 kb |
| Host | smart-f39b3f52-6e7e-44e3-aff5-27fdd98694f2 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=69849828994711636111568449843694647341402952593506968355519473163639386605197 -assert nopostproc +UVM_TES TNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 8.uart_long_xfer_wo_dly.69849828994711636111568449843694647341402952593506968355519473163639386605197 |
| Directory | /workspace/8.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/8.uart_loopback.18736572090037896371747288470171836026362398511860503502899436808569008732919 |
| Short name | T835 |
| Test name | |
| Test status | |
| Simulation time | 14572448663 ps |
| CPU time | 16.24 seconds |
| Started | Nov 22 01:44:04 PM PST 23 |
| Finished | Nov 22 01:44:25 PM PST 23 |
| Peak memory | 200048 kb |
| Host | smart-5db63a68-a7e6-4a6d-8c87-4ad24e6d8874 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=18736572090037896371747288470171836026362398511860503502899436808569008732919 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 8.uart_loopback.18736572090037896371747288470171836026362398511860503502899436808569008732919 |
| Directory | /workspace/8.uart_loopback/latest |
| Test location | /workspace/coverage/default/8.uart_noise_filter.38086051600404770346693488059637442804294228611595403549499594079675601740953 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 94501577082 ps |
| CPU time | 96.9 seconds |
| Started | Nov 22 01:44:02 PM PST 23 |
| Finished | Nov 22 01:45:44 PM PST 23 |
| Peak memory | 200248 kb |
| Host | smart-ae3bb511-ff1e-4e61-aa98-40899a49339a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=38086051600404770346693488059637442804294228611595403549499594079675601740953 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_noise_filter.38086051600404770346693488059637442804294228611595403549499594079675601740953 |
| Directory | /workspace/8.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/8.uart_perf.63281362176321815068375778609984685724219196872577301283983017423663434628081 |
| Short name | T920 |
| Test name | |
| Test status | |
| Simulation time | 14098773881 ps |
| CPU time | 476.54 seconds |
| Started | Nov 22 01:43:52 PM PST 23 |
| Finished | Nov 22 01:51:52 PM PST 23 |
| Peak memory | 200152 kb |
| Host | smart-7976f407-1933-4e1c-baca-4fc653a9e7c3 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=63281362176321815068375778609984685724219196872577301283983017423663434628081 -assert nopostproc +UVM_TES TNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 8.uart_perf.63281362176321815068375778609984685724219196872577301283983017423663434628081 |
| Directory | /workspace/8.uart_perf/latest |
| Test location | /workspace/coverage/default/8.uart_rx_oversample.39675683648940517268698996151164016721027077797358256338062446534992733582043 |
| Short name | T907 |
| Test name | |
| Test status | |
| Simulation time | 4370280281 ps |
| CPU time | 20.02 seconds |
| Started | Nov 22 01:43:57 PM PST 23 |
| Finished | Nov 22 01:44:20 PM PST 23 |
| Peak memory | 198960 kb |
| Host | smart-4b69ab21-70d1-48f3-953a-4fda10af4dfc |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=39675683648940517268698996151164016721027077797358256338062446534992733582043 -assert nopostproc +UVM_TES TNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 8.uart_rx_oversample.39675683648940517268698996151164016721027077797358256338062446534992733582043 |
| Directory | /workspace/8.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/8.uart_rx_parity_err.46674865886874105714290977544827663337441792770392833201684849066566956284650 |
| Short name | T1187 |
| Test name | |
| Test status | |
| Simulation time | 36616611594 ps |
| CPU time | 37.78 seconds |
| Started | Nov 22 01:44:07 PM PST 23 |
| Finished | Nov 22 01:44:50 PM PST 23 |
| Peak memory | 200116 kb |
| Host | smart-31193e7e-c78d-436a-9fa5-d79097a9fc0f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=46674865886874105714290977544827663337441792770392833201684849066566956284650 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 8.uart_rx_parity_err.46674865886874105714290977544827663337441792770392833201684849066566956284650 |
| Directory | /workspace/8.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/8.uart_rx_start_bit_filter.66233963305046783688425952445534315069370435825654245089148681315240256382479 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 4267638245 ps |
| CPU time | 4.68 seconds |
| Started | Nov 22 01:44:07 PM PST 23 |
| Finished | Nov 22 01:44:16 PM PST 23 |
| Peak memory | 195836 kb |
| Host | smart-d87c5f08-9801-44c4-9a21-fa6f93058e8c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=66233963305046783688425952445534315069370435825654245089148681315240256382479 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 8.uart_rx_start_bit_filter.66233963305046783688425952445534315069370435825654245089148681315240256382479 |
| Directory | /workspace/8.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/8.uart_smoke.107879988489119035963454099855970219833528930810127923804843252388999064632870 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 5759626309 ps |
| CPU time | 18.33 seconds |
| Started | Nov 22 01:44:07 PM PST 23 |
| Finished | Nov 22 01:44:30 PM PST 23 |
| Peak memory | 199596 kb |
| Host | smart-82784ae7-6a9c-4c6a-aed2-27068b507ee6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=107879988489119035963454099855970219833528930810127923804843252388999064632870 -assert nopostproc +UVM_TESTNAME=uart_bas e_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 8.uart_smoke.107879988489119035963454099855970219833528930810127923804843252388999064632870 |
| Directory | /workspace/8.uart_smoke/latest |
| Test location | /workspace/coverage/default/8.uart_stress_all.83517419493815140448974004674036259296232368830002335753197412684400715051792 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 43402307308 ps |
| CPU time | 56.29 seconds |
| Started | Nov 22 01:44:15 PM PST 23 |
| Finished | Nov 22 01:45:14 PM PST 23 |
| Peak memory | 200068 kb |
| Host | smart-03b50092-a771-4f60-88c3-e4ac425b60f8 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83517419493815140448974004674036259296232368830002335753197412684400715051792 -assert nopos tproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 8.uart_stress_all.83517419493815140448974004674036259296232368830002335753197412684400715051792 |
| Directory | /workspace/8.uart_stress_all/latest |
| Test location | /workspace/coverage/default/8.uart_stress_all_with_rand_reset.103835070250651530079980916830969409902812298724615959304458892378773886689827 |
| Short name | T886 |
| Test name | |
| Test status | |
| Simulation time | 87476847566 ps |
| CPU time | 468 seconds |
| Started | Nov 22 01:44:07 PM PST 23 |
| Finished | Nov 22 01:52:00 PM PST 23 |
| Peak memory | 226208 kb |
| Host | smart-0c9f63b8-1286-4e0d-83db-33d0429a8ecb |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10383507025065153007998091 6830969409902812298724615959304458892378773886689827 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_stress_all_with_rand_reset.1038350702506 51530079980916830969409902812298724615959304458892378773886689827 |
| Directory | /workspace/8.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/8.uart_tx_ovrd.3689709740238995700972072369752938029057374086196937291796122377667991717768 |
| Short name | T873 |
| Test name | |
| Test status | |
| Simulation time | 485186362 ps |
| CPU time | 1.25 seconds |
| Started | Nov 22 01:43:46 PM PST 23 |
| Finished | Nov 22 01:43:55 PM PST 23 |
| Peak memory | 197968 kb |
| Host | smart-2003a8b5-91a8-45f9-b868-a7d9fff174a1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3689709740238995700972072369752938029057374086196937291796122377667991717768 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 8.uart_tx_ovrd.3689709740238995700972072369752938029057374086196937291796122377667991717768 |
| Directory | /workspace/8.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/8.uart_tx_rx.61715059352994963969821575353018397967292950762110048069314926009887884693003 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 57391945390 ps |
| CPU time | 63.55 seconds |
| Started | Nov 22 01:44:11 PM PST 23 |
| Finished | Nov 22 01:45:18 PM PST 23 |
| Peak memory | 199988 kb |
| Host | smart-2f332dd2-3620-440b-a1e7-f29ec2fbfd65 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=61715059352994963969821575353018397967292950762110048069314926009887884693003 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 8.uart_tx_rx.61715059352994963969821575353018397967292950762110048069314926009887884693003 |
| Directory | /workspace/8.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/80.uart_fifo_reset.68704276794168530412665408526934218265931310168725725307256614146817017520996 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 112.96 seconds |
| Started | Nov 22 01:45:42 PM PST 23 |
| Finished | Nov 22 01:47:37 PM PST 23 |
| Peak memory | 198880 kb |
| Host | smart-f128551e-cc24-4267-9091-80b477538ced |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=68704276794168530412665408526934218265931310168725725307256614146817017520996 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 80.uart_fifo_reset.68704276794168530412665408526934218265931310168725725307256614146817017520996 |
| Directory | /workspace/80.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/80.uart_stress_all_with_rand_reset.32042529231748834553821782348938704312434241588922313308460297449153459746522 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 87476847566 ps |
| CPU time | 462.15 seconds |
| Started | Nov 22 01:45:42 PM PST 23 |
| Finished | Nov 22 01:53:26 PM PST 23 |
| Peak memory | 226272 kb |
| Host | smart-85788f25-0d30-48c6-b8fa-fc4731c8ff27 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32042529231748834553821782 348938704312434241588922313308460297449153459746522 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.uart_stress_all_with_rand_reset.3204252923174 8834553821782348938704312434241588922313308460297449153459746522 |
| Directory | /workspace/80.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/81.uart_fifo_reset.108896349037969136526222773588592821451092940206043010924240851839994005319787 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 112.82 seconds |
| Started | Nov 22 01:45:49 PM PST 23 |
| Finished | Nov 22 01:47:43 PM PST 23 |
| Peak memory | 198900 kb |
| Host | smart-75a9b7bd-1993-4a34-8247-1eae93dcf9f8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=108896349037969136526222773588592821451092940206043010924240851839994005319787 -assert nopostproc +UVM_TESTNAME=uart_bas e_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.uart_fifo_reset.108896349037969136526222773588592821451092940206043010924240851839994005319787 |
| Directory | /workspace/81.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/81.uart_stress_all_with_rand_reset.13269802478289571417061818241281681589777698946013630504178452916763855564275 |
| Short name | T1039 |
| Test name | |
| Test status | |
| Simulation time | 87476847566 ps |
| CPU time | 468.72 seconds |
| Started | Nov 22 01:45:38 PM PST 23 |
| Finished | Nov 22 01:53:28 PM PST 23 |
| Peak memory | 226260 kb |
| Host | smart-7a46ad74-634a-458b-8555-325a4166961a |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13269802478289571417061818 241281681589777698946013630504178452916763855564275 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.uart_stress_all_with_rand_reset.1326980247828 9571417061818241281681589777698946013630504178452916763855564275 |
| Directory | /workspace/81.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/82.uart_fifo_reset.65320466758723676028889867198711686027388788001473899016868598833519475172910 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 113.37 seconds |
| Started | Nov 22 01:45:59 PM PST 23 |
| Finished | Nov 22 01:48:01 PM PST 23 |
| Peak memory | 198808 kb |
| Host | smart-3194f1e2-3336-47cf-992a-04a61c1b9833 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=65320466758723676028889867198711686027388788001473899016868598833519475172910 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 82.uart_fifo_reset.65320466758723676028889867198711686027388788001473899016868598833519475172910 |
| Directory | /workspace/82.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/82.uart_stress_all_with_rand_reset.35037061527592089806418794774503522032044569516758160787854118343135870803395 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 87476847566 ps |
| CPU time | 456.85 seconds |
| Started | Nov 22 01:45:37 PM PST 23 |
| Finished | Nov 22 01:53:15 PM PST 23 |
| Peak memory | 226248 kb |
| Host | smart-daae9e24-d87e-4141-befe-eb9a8da103d3 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35037061527592089806418794 774503522032044569516758160787854118343135870803395 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.uart_stress_all_with_rand_reset.3503706152759 2089806418794774503522032044569516758160787854118343135870803395 |
| Directory | /workspace/82.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/83.uart_fifo_reset.2765259077795717289486376868192837751352862104711973733705695528123037131386 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 113.32 seconds |
| Started | Nov 22 01:45:59 PM PST 23 |
| Finished | Nov 22 01:48:01 PM PST 23 |
| Peak memory | 198892 kb |
| Host | smart-b30655c7-387b-45d9-a6a3-b9f7bf815a94 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2765259077795717289486376868192837751352862104711973733705695528123037131386 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 83.uart_fifo_reset.2765259077795717289486376868192837751352862104711973733705695528123037131386 |
| Directory | /workspace/83.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/83.uart_stress_all_with_rand_reset.48382907137157603671224775245594231248196581296446011956701767958135854816684 |
| Short name | T1275 |
| Test name | |
| Test status | |
| Simulation time | 87476847566 ps |
| CPU time | 446.36 seconds |
| Started | Nov 22 01:45:28 PM PST 23 |
| Finished | Nov 22 01:52:57 PM PST 23 |
| Peak memory | 226240 kb |
| Host | smart-94fad5c4-e599-4ef5-9cb2-7e3a3cda967a |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48382907137157603671224775 245594231248196581296446011956701767958135854816684 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.uart_stress_all_with_rand_reset.4838290713715 7603671224775245594231248196581296446011956701767958135854816684 |
| Directory | /workspace/83.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/84.uart_fifo_reset.70861567248493072823307647169766797119132149805953641099732955156740770046815 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 114.7 seconds |
| Started | Nov 22 01:45:46 PM PST 23 |
| Finished | Nov 22 01:47:43 PM PST 23 |
| Peak memory | 198880 kb |
| Host | smart-ccbab071-8190-4324-9a93-5fb0c24fb715 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=70861567248493072823307647169766797119132149805953641099732955156740770046815 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 84.uart_fifo_reset.70861567248493072823307647169766797119132149805953641099732955156740770046815 |
| Directory | /workspace/84.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/84.uart_stress_all_with_rand_reset.89074553535955519760437139570953547868901977133661440275579928348366120937539 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 87476847566 ps |
| CPU time | 463.4 seconds |
| Started | Nov 22 01:45:56 PM PST 23 |
| Finished | Nov 22 01:53:47 PM PST 23 |
| Peak memory | 226196 kb |
| Host | smart-11c2a8e5-cd05-4cfc-941d-29ba1d1d9f5b |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89074553535955519760437139 570953547868901977133661440275579928348366120937539 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.uart_stress_all_with_rand_reset.8907455353595 5519760437139570953547868901977133661440275579928348366120937539 |
| Directory | /workspace/84.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/85.uart_fifo_reset.113985508042478337720287576604418327966068686150501308079977879960048917351847 |
| Short name | T790 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 113.15 seconds |
| Started | Nov 22 01:45:42 PM PST 23 |
| Finished | Nov 22 01:47:36 PM PST 23 |
| Peak memory | 198948 kb |
| Host | smart-a86625af-a11f-49a1-9130-646d78fcefa1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=113985508042478337720287576604418327966068686150501308079977879960048917351847 -assert nopostproc +UVM_TESTNAME=uart_bas e_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.uart_fifo_reset.113985508042478337720287576604418327966068686150501308079977879960048917351847 |
| Directory | /workspace/85.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/85.uart_stress_all_with_rand_reset.91263348600692650609817694575000460178597736200756258013232014526279898691236 |
| Short name | T1208 |
| Test name | |
| Test status | |
| Simulation time | 87476847566 ps |
| CPU time | 454.69 seconds |
| Started | Nov 22 01:45:54 PM PST 23 |
| Finished | Nov 22 01:53:32 PM PST 23 |
| Peak memory | 226248 kb |
| Host | smart-1f697ca4-beb2-4e6a-88f9-6c911a4cf6ad |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91263348600692650609817694 575000460178597736200756258013232014526279898691236 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.uart_stress_all_with_rand_reset.9126334860069 2650609817694575000460178597736200756258013232014526279898691236 |
| Directory | /workspace/85.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/86.uart_fifo_reset.11797854918095206107246429580888950103026473696905532776240246469583868611994 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 112.61 seconds |
| Started | Nov 22 01:45:30 PM PST 23 |
| Finished | Nov 22 01:47:24 PM PST 23 |
| Peak memory | 199016 kb |
| Host | smart-d3788a5e-054f-4fe7-9181-9110063c6afb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=11797854918095206107246429580888950103026473696905532776240246469583868611994 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 86.uart_fifo_reset.11797854918095206107246429580888950103026473696905532776240246469583868611994 |
| Directory | /workspace/86.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/86.uart_stress_all_with_rand_reset.12250008604704751463791161294321945368398370995824859995707991009361849687826 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 87476847566 ps |
| CPU time | 465.49 seconds |
| Started | Nov 22 01:45:29 PM PST 23 |
| Finished | Nov 22 01:53:17 PM PST 23 |
| Peak memory | 226240 kb |
| Host | smart-4b4b308d-9053-4248-987c-fcd603bb40a6 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12250008604704751463791161 294321945368398370995824859995707991009361849687826 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.uart_stress_all_with_rand_reset.1225000860470 4751463791161294321945368398370995824859995707991009361849687826 |
| Directory | /workspace/86.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/87.uart_fifo_reset.50098298296796071335886342318203253133004497765172295535414088849863662613972 |
| Short name | T1134 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 112.57 seconds |
| Started | Nov 22 01:45:52 PM PST 23 |
| Finished | Nov 22 01:47:47 PM PST 23 |
| Peak memory | 198912 kb |
| Host | smart-d55a0130-1a66-4b1f-95d2-b0cadda0cd92 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=50098298296796071335886342318203253133004497765172295535414088849863662613972 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 87.uart_fifo_reset.50098298296796071335886342318203253133004497765172295535414088849863662613972 |
| Directory | /workspace/87.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/87.uart_stress_all_with_rand_reset.17031886597781077353728251729893236304706461783746748756983508307026961345082 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 87476847566 ps |
| CPU time | 481.89 seconds |
| Started | Nov 22 01:45:56 PM PST 23 |
| Finished | Nov 22 01:54:05 PM PST 23 |
| Peak memory | 226256 kb |
| Host | smart-f3ff67d6-2a61-4475-aa28-5e6cd2872305 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17031886597781077353728251 729893236304706461783746748756983508307026961345082 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.uart_stress_all_with_rand_reset.1703188659778 1077353728251729893236304706461783746748756983508307026961345082 |
| Directory | /workspace/87.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/88.uart_fifo_reset.46724113556306175387952994576109892302517332132612099389926044079268920763299 |
| Short name | T734 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 113.3 seconds |
| Started | Nov 22 01:45:36 PM PST 23 |
| Finished | Nov 22 01:47:30 PM PST 23 |
| Peak memory | 198932 kb |
| Host | smart-344f3be0-9469-421a-9ba2-f85dd4bd7377 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=46724113556306175387952994576109892302517332132612099389926044079268920763299 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 88.uart_fifo_reset.46724113556306175387952994576109892302517332132612099389926044079268920763299 |
| Directory | /workspace/88.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/88.uart_stress_all_with_rand_reset.83756587847123189569797020184652627497910426692439046957845110391181747511162 |
| Short name | T792 |
| Test name | |
| Test status | |
| Simulation time | 87476847566 ps |
| CPU time | 466.96 seconds |
| Started | Nov 22 01:45:30 PM PST 23 |
| Finished | Nov 22 01:53:18 PM PST 23 |
| Peak memory | 226076 kb |
| Host | smart-3350a0d1-3c71-48d9-aebc-5fc4a3c986c4 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83756587847123189569797020 184652627497910426692439046957845110391181747511162 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.uart_stress_all_with_rand_reset.8375658784712 3189569797020184652627497910426692439046957845110391181747511162 |
| Directory | /workspace/88.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/89.uart_fifo_reset.45422005172938997330199123897721298226935060089067493720741383577251629799544 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 112.49 seconds |
| Started | Nov 22 01:45:43 PM PST 23 |
| Finished | Nov 22 01:47:37 PM PST 23 |
| Peak memory | 198936 kb |
| Host | smart-fe730f4f-5e3a-41ec-a2aa-e36faabd9d7a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=45422005172938997330199123897721298226935060089067493720741383577251629799544 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 89.uart_fifo_reset.45422005172938997330199123897721298226935060089067493720741383577251629799544 |
| Directory | /workspace/89.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/89.uart_stress_all_with_rand_reset.84307083725923578415196181075779252804705771515058860060069915143699014901772 |
| Short name | T679 |
| Test name | |
| Test status | |
| Simulation time | 87476847566 ps |
| CPU time | 468.51 seconds |
| Started | Nov 22 01:45:54 PM PST 23 |
| Finished | Nov 22 01:53:46 PM PST 23 |
| Peak memory | 226260 kb |
| Host | smart-9876e496-0f24-4b82-8a7c-17cd42b7c224 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84307083725923578415196181 075779252804705771515058860060069915143699014901772 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.uart_stress_all_with_rand_reset.8430708372592 3578415196181075779252804705771515058860060069915143699014901772 |
| Directory | /workspace/89.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/9.uart_alert_test.69549762923473619499577598337890310952470547726617760303055191973308135015344 |
| Short name | T1041 |
| Test name | |
| Test status | |
| Simulation time | 16368684 ps |
| CPU time | 0.54 seconds |
| Started | Nov 22 01:44:16 PM PST 23 |
| Finished | Nov 22 01:44:20 PM PST 23 |
| Peak memory | 194672 kb |
| Host | smart-2f2a3a81-ce35-42a6-b9f9-0ac8632503af |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69549762923473619499577598337890310952470547726617760303055191973308135015344 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 9.uart_alert_test.69549762923473619499577598337890310952470547726617760303055191973308135015344 |
| Directory | /workspace/9.uart_alert_test/latest |
| Test location | /workspace/coverage/default/9.uart_fifo_full.43788496854139338885941420867062168900107984544268895146318781527115626696914 |
| Short name | T1254 |
| Test name | |
| Test status | |
| Simulation time | 61777160308 ps |
| CPU time | 61.38 seconds |
| Started | Nov 22 01:43:55 PM PST 23 |
| Finished | Nov 22 01:45:00 PM PST 23 |
| Peak memory | 199992 kb |
| Host | smart-7ae193c3-cfe2-47b4-a854-ac370467f0e1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=43788496854139338885941420867062168900107984544268895146318781527115626696914 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 9.uart_fifo_full.43788496854139338885941420867062168900107984544268895146318781527115626696914 |
| Directory | /workspace/9.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/9.uart_fifo_overflow.9561440259254482861403740386198523568987269079093957400345288904742475880979 |
| Short name | T849 |
| Test name | |
| Test status | |
| Simulation time | 58551936110 ps |
| CPU time | 54.72 seconds |
| Started | Nov 22 01:44:10 PM PST 23 |
| Finished | Nov 22 01:45:08 PM PST 23 |
| Peak memory | 199784 kb |
| Host | smart-9017eb1f-04fe-47b7-aa49-9c15a820c15e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=9561440259254482861403740386198523568987269079093957400345288904742475880979 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_overflow.9561440259254482861403740386198523568987269079093957400345288904742475880979 |
| Directory | /workspace/9.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/9.uart_fifo_reset.66236573024213090575782220365535598323181351476040797187195511216930996466878 |
| Short name | T722 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 114.44 seconds |
| Started | Nov 22 01:43:56 PM PST 23 |
| Finished | Nov 22 01:45:54 PM PST 23 |
| Peak memory | 198888 kb |
| Host | smart-206d9078-34da-42ef-8729-cbfc5479b3ed |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=66236573024213090575782220365535598323181351476040797187195511216930996466878 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 9.uart_fifo_reset.66236573024213090575782220365535598323181351476040797187195511216930996466878 |
| Directory | /workspace/9.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/9.uart_intr.62303684522989407086409225488253583867048292150191660053739884186417545265209 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 787145125175 ps |
| CPU time | 784.88 seconds |
| Started | Nov 22 01:43:58 PM PST 23 |
| Finished | Nov 22 01:57:07 PM PST 23 |
| Peak memory | 200044 kb |
| Host | smart-4b88dd3d-891b-4ee7-8d9a-b29d89ea99ed |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62303684522989407086409225488253583867048292150191660053739884186417545265209 -assert nopost proc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 9.uart_intr.62303684522989407086409225488253583867048292150191660053739884186417545265209 |
| Directory | /workspace/9.uart_intr/latest |
| Test location | /workspace/coverage/default/9.uart_long_xfer_wo_dly.36622381260734410474424931229771757508797400522740062163656329373965609098132 |
| Short name | T1200 |
| Test name | |
| Test status | |
| Simulation time | 93387746707 ps |
| CPU time | 348.19 seconds |
| Started | Nov 22 01:44:16 PM PST 23 |
| Finished | Nov 22 01:50:07 PM PST 23 |
| Peak memory | 200156 kb |
| Host | smart-bcded8e1-0042-4441-af54-44973186ac2b |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=36622381260734410474424931229771757508797400522740062163656329373965609098132 -assert nopostproc +UVM_TES TNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 9.uart_long_xfer_wo_dly.36622381260734410474424931229771757508797400522740062163656329373965609098132 |
| Directory | /workspace/9.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/9.uart_loopback.6924173934787544844972400692594689737156845798031332181669615426703645732174 |
| Short name | T1092 |
| Test name | |
| Test status | |
| Simulation time | 14572448663 ps |
| CPU time | 16.44 seconds |
| Started | Nov 22 01:43:55 PM PST 23 |
| Finished | Nov 22 01:44:15 PM PST 23 |
| Peak memory | 200072 kb |
| Host | smart-44cb6384-15c8-46ed-9e31-f31492404f1c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=6924173934787544844972400692594689737156845798031332181669615426703645732174 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 9.uart_loopback.6924173934787544844972400692594689737156845798031332181669615426703645732174 |
| Directory | /workspace/9.uart_loopback/latest |
| Test location | /workspace/coverage/default/9.uart_noise_filter.33769233039730790588218357460793570973117609140772895903412953376926871048571 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 94501577082 ps |
| CPU time | 95.97 seconds |
| Started | Nov 22 01:44:02 PM PST 23 |
| Finished | Nov 22 01:45:42 PM PST 23 |
| Peak memory | 200296 kb |
| Host | smart-f25dc3e6-d846-4579-afc7-7f6b2133fa23 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=33769233039730790588218357460793570973117609140772895903412953376926871048571 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_noise_filter.33769233039730790588218357460793570973117609140772895903412953376926871048571 |
| Directory | /workspace/9.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/9.uart_perf.82860696017759510837516285695751801453943279396818522660440903396643269355095 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 14098773881 ps |
| CPU time | 474.52 seconds |
| Started | Nov 22 01:44:07 PM PST 23 |
| Finished | Nov 22 01:52:06 PM PST 23 |
| Peak memory | 200108 kb |
| Host | smart-616f83a8-08db-4793-a966-adee86e9131c |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=82860696017759510837516285695751801453943279396818522660440903396643269355095 -assert nopostproc +UVM_TES TNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 9.uart_perf.82860696017759510837516285695751801453943279396818522660440903396643269355095 |
| Directory | /workspace/9.uart_perf/latest |
| Test location | /workspace/coverage/default/9.uart_rx_oversample.107425791406545167693894657192484241981026447931885777300478711149107019961442 |
| Short name | T908 |
| Test name | |
| Test status | |
| Simulation time | 4370280281 ps |
| CPU time | 19.53 seconds |
| Started | Nov 22 01:44:00 PM PST 23 |
| Finished | Nov 22 01:44:23 PM PST 23 |
| Peak memory | 198892 kb |
| Host | smart-3fc8d7a6-5ad6-4b94-8051-f33f1daa03b4 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=107425791406545167693894657192484241981026447931885777300478711149107019961442 -assert nopostproc +UVM_TE STNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_oversample.107425791406545167693894657192484241981026447931885777300478711149107019961442 |
| Directory | /workspace/9.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/9.uart_rx_parity_err.15924532230494811933122168238965727085459507792224806993487687856238376261165 |
| Short name | T971 |
| Test name | |
| Test status | |
| Simulation time | 36616611594 ps |
| CPU time | 38.08 seconds |
| Started | Nov 22 01:44:12 PM PST 23 |
| Finished | Nov 22 01:44:54 PM PST 23 |
| Peak memory | 200124 kb |
| Host | smart-9fcbe36e-984c-483f-a789-1ee3e18ebaba |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=15924532230494811933122168238965727085459507792224806993487687856238376261165 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 9.uart_rx_parity_err.15924532230494811933122168238965727085459507792224806993487687856238376261165 |
| Directory | /workspace/9.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/9.uart_rx_start_bit_filter.26430842182507982671059777080354781972454852274801154613761249193940060165425 |
| Short name | T1022 |
| Test name | |
| Test status | |
| Simulation time | 4267638245 ps |
| CPU time | 4.67 seconds |
| Started | Nov 22 01:43:48 PM PST 23 |
| Finished | Nov 22 01:43:55 PM PST 23 |
| Peak memory | 195932 kb |
| Host | smart-5b615c9f-df0a-45a4-9295-fef266280cdb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=26430842182507982671059777080354781972454852274801154613761249193940060165425 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 9.uart_rx_start_bit_filter.26430842182507982671059777080354781972454852274801154613761249193940060165425 |
| Directory | /workspace/9.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/9.uart_smoke.24119648038488484404402555702198316171923699015330647936027105544848665801949 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 5759626309 ps |
| CPU time | 18.2 seconds |
| Started | Nov 22 01:44:12 PM PST 23 |
| Finished | Nov 22 01:44:34 PM PST 23 |
| Peak memory | 199548 kb |
| Host | smart-e3122267-cebf-4372-9145-7c0db1deb876 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=24119648038488484404402555702198316171923699015330647936027105544848665801949 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 9.uart_smoke.24119648038488484404402555702198316171923699015330647936027105544848665801949 |
| Directory | /workspace/9.uart_smoke/latest |
| Test location | /workspace/coverage/default/9.uart_stress_all.74546482721050156881143669718513201732105883159124102658992351937908269986113 |
| Short name | T1149 |
| Test name | |
| Test status | |
| Simulation time | 43402307308 ps |
| CPU time | 55.65 seconds |
| Started | Nov 22 01:44:05 PM PST 23 |
| Finished | Nov 22 01:45:06 PM PST 23 |
| Peak memory | 199864 kb |
| Host | smart-9390487b-8e5d-41cc-a374-645e1bfcc274 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74546482721050156881143669718513201732105883159124102658992351937908269986113 -assert nopos tproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 9.uart_stress_all.74546482721050156881143669718513201732105883159124102658992351937908269986113 |
| Directory | /workspace/9.uart_stress_all/latest |
| Test location | /workspace/coverage/default/9.uart_stress_all_with_rand_reset.35622940892144984810613232493962251583273770076229239715820893336535365039142 |
| Short name | T1190 |
| Test name | |
| Test status | |
| Simulation time | 87476847566 ps |
| CPU time | 464.14 seconds |
| Started | Nov 22 01:44:13 PM PST 23 |
| Finished | Nov 22 01:52:00 PM PST 23 |
| Peak memory | 226228 kb |
| Host | smart-f0dcae75-f939-4543-af59-840e710195a4 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35622940892144984810613232 493962251583273770076229239715820893336535365039142 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_stress_all_with_rand_reset.35622940892144 984810613232493962251583273770076229239715820893336535365039142 |
| Directory | /workspace/9.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/9.uart_tx_ovrd.98367615135177423628477033658735215067166949460243459916113320121479220908150 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 485186362 ps |
| CPU time | 1.23 seconds |
| Started | Nov 22 01:44:22 PM PST 23 |
| Finished | Nov 22 01:44:30 PM PST 23 |
| Peak memory | 197912 kb |
| Host | smart-52fdcbe4-3b9e-404a-a4d7-a9fec6aaac4b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=98367615135177423628477033658735215067166949460243459916113320121479220908150 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 9.uart_tx_ovrd.98367615135177423628477033658735215067166949460243459916113320121479220908150 |
| Directory | /workspace/9.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/9.uart_tx_rx.108707429578431380093369362576990241849337937121523136745343628964462571201266 |
| Short name | T1072 |
| Test name | |
| Test status | |
| Simulation time | 57391945390 ps |
| CPU time | 63.67 seconds |
| Started | Nov 22 01:44:05 PM PST 23 |
| Finished | Nov 22 01:45:17 PM PST 23 |
| Peak memory | 199948 kb |
| Host | smart-eea266f7-c705-4f99-8c36-b352a5527d7a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=108707429578431380093369362576990241849337937121523136745343628964462571201266 -assert nopostproc +UVM_TESTNAME=uart_bas e_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 9.uart_tx_rx.108707429578431380093369362576990241849337937121523136745343628964462571201266 |
| Directory | /workspace/9.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/90.uart_fifo_reset.44304484913249720761410884209324961394963138325563113059943591588983788500903 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 113.7 seconds |
| Started | Nov 22 01:45:57 PM PST 23 |
| Finished | Nov 22 01:47:58 PM PST 23 |
| Peak memory | 198864 kb |
| Host | smart-387b7116-c4af-46fc-b4cc-9df66f0a1e48 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=44304484913249720761410884209324961394963138325563113059943591588983788500903 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 90.uart_fifo_reset.44304484913249720761410884209324961394963138325563113059943591588983788500903 |
| Directory | /workspace/90.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/90.uart_stress_all_with_rand_reset.10985024106683222206347198793446836588630563232612308560546396238189302922634 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 87476847566 ps |
| CPU time | 463.16 seconds |
| Started | Nov 22 01:45:45 PM PST 23 |
| Finished | Nov 22 01:53:30 PM PST 23 |
| Peak memory | 226248 kb |
| Host | smart-6b7bc32a-26a3-4a6f-9e37-c16a28db0615 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10985024106683222206347198 793446836588630563232612308560546396238189302922634 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.uart_stress_all_with_rand_reset.1098502410668 3222206347198793446836588630563232612308560546396238189302922634 |
| Directory | /workspace/90.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/91.uart_fifo_reset.30021785640864716183713817786166622418062070414086417359298208170011221502466 |
| Short name | T992 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 113.43 seconds |
| Started | Nov 22 01:45:52 PM PST 23 |
| Finished | Nov 22 01:47:49 PM PST 23 |
| Peak memory | 198828 kb |
| Host | smart-d8694ea0-a181-442f-bad1-74f7a3049a81 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=30021785640864716183713817786166622418062070414086417359298208170011221502466 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 91.uart_fifo_reset.30021785640864716183713817786166622418062070414086417359298208170011221502466 |
| Directory | /workspace/91.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/91.uart_stress_all_with_rand_reset.70906122579095858632420400408756650195670333044226052620280001286223013022347 |
| Short name | T1154 |
| Test name | |
| Test status | |
| Simulation time | 87476847566 ps |
| CPU time | 469.98 seconds |
| Started | Nov 22 01:45:44 PM PST 23 |
| Finished | Nov 22 01:53:35 PM PST 23 |
| Peak memory | 226256 kb |
| Host | smart-d9cba7df-7628-45f8-8bf7-18995b0d3dfd |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70906122579095858632420400 408756650195670333044226052620280001286223013022347 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.uart_stress_all_with_rand_reset.7090612257909 5858632420400408756650195670333044226052620280001286223013022347 |
| Directory | /workspace/91.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/92.uart_fifo_reset.87968535602295313303677948346012938745950747599366220463104746676457309475459 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 115.06 seconds |
| Started | Nov 22 01:45:58 PM PST 23 |
| Finished | Nov 22 01:48:01 PM PST 23 |
| Peak memory | 198900 kb |
| Host | smart-8e83122d-f6b7-46a1-93fb-67f4623783ec |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=87968535602295313303677948346012938745950747599366220463104746676457309475459 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 92.uart_fifo_reset.87968535602295313303677948346012938745950747599366220463104746676457309475459 |
| Directory | /workspace/92.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/92.uart_stress_all_with_rand_reset.94721432908502671835712767405091204218571854783289964673621837073800446931744 |
| Short name | T878 |
| Test name | |
| Test status | |
| Simulation time | 87476847566 ps |
| CPU time | 464.43 seconds |
| Started | Nov 22 01:45:44 PM PST 23 |
| Finished | Nov 22 01:53:30 PM PST 23 |
| Peak memory | 226300 kb |
| Host | smart-e71a021f-84c9-4532-bb1d-3a64a0d98b12 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94721432908502671835712767 405091204218571854783289964673621837073800446931744 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.uart_stress_all_with_rand_reset.9472143290850 2671835712767405091204218571854783289964673621837073800446931744 |
| Directory | /workspace/92.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/93.uart_fifo_reset.78544276738084213934060948029207533993405110164392629121433508991036433249593 |
| Short name | T828 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 113.3 seconds |
| Started | Nov 22 01:45:50 PM PST 23 |
| Finished | Nov 22 01:47:45 PM PST 23 |
| Peak memory | 198932 kb |
| Host | smart-8b02fc72-5450-4dc7-819a-edb4aaa3949d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=78544276738084213934060948029207533993405110164392629121433508991036433249593 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 93.uart_fifo_reset.78544276738084213934060948029207533993405110164392629121433508991036433249593 |
| Directory | /workspace/93.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/93.uart_stress_all_with_rand_reset.111824921461513992898370392837586558524146875577864591645521788267643437680673 |
| Short name | T670 |
| Test name | |
| Test status | |
| Simulation time | 87476847566 ps |
| CPU time | 474.23 seconds |
| Started | Nov 22 01:45:36 PM PST 23 |
| Finished | Nov 22 01:53:32 PM PST 23 |
| Peak memory | 226232 kb |
| Host | smart-e6ce2edd-993c-4c07-8802-124d89001ad8 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11182492146151399289837039 2837586558524146875577864591645521788267643437680673 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.uart_stress_all_with_rand_reset.111824921461 513992898370392837586558524146875577864591645521788267643437680673 |
| Directory | /workspace/93.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/94.uart_fifo_reset.9370137497781711752776831567436249842348953510160071478311052336395739678569 |
| Short name | T1181 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 113.6 seconds |
| Started | Nov 22 01:45:44 PM PST 23 |
| Finished | Nov 22 01:47:39 PM PST 23 |
| Peak memory | 198944 kb |
| Host | smart-432eb991-f630-4e0b-a88f-0558ef6a1863 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=9370137497781711752776831567436249842348953510160071478311052336395739678569 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 94.uart_fifo_reset.9370137497781711752776831567436249842348953510160071478311052336395739678569 |
| Directory | /workspace/94.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/94.uart_stress_all_with_rand_reset.95720936633766188925160032662296256937357779350362475618596972134298845033068 |
| Short name | T773 |
| Test name | |
| Test status | |
| Simulation time | 87476847566 ps |
| CPU time | 459.64 seconds |
| Started | Nov 22 01:46:00 PM PST 23 |
| Finished | Nov 22 01:53:47 PM PST 23 |
| Peak memory | 225896 kb |
| Host | smart-b4a1cd92-5978-4c89-ac43-5a5a484f8793 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95720936633766188925160032 662296256937357779350362475618596972134298845033068 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.uart_stress_all_with_rand_reset.9572093663376 6188925160032662296256937357779350362475618596972134298845033068 |
| Directory | /workspace/94.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/95.uart_fifo_reset.2135021186067322927751007800534029895495428176462206094496363534191800738538 |
| Short name | T798 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 113.01 seconds |
| Started | Nov 22 01:45:50 PM PST 23 |
| Finished | Nov 22 01:47:44 PM PST 23 |
| Peak memory | 198936 kb |
| Host | smart-a165b642-3b6b-46c2-9b73-bf8c8db8cf56 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2135021186067322927751007800534029895495428176462206094496363534191800738538 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 95.uart_fifo_reset.2135021186067322927751007800534029895495428176462206094496363534191800738538 |
| Directory | /workspace/95.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/95.uart_stress_all_with_rand_reset.35760099083126400235448356454892131687095564780213667492442027442176224403182 |
| Short name | T1037 |
| Test name | |
| Test status | |
| Simulation time | 87476847566 ps |
| CPU time | 462.41 seconds |
| Started | Nov 22 01:45:44 PM PST 23 |
| Finished | Nov 22 01:53:28 PM PST 23 |
| Peak memory | 226240 kb |
| Host | smart-867949bf-0073-4ccc-a20c-69dc1c3a164a |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35760099083126400235448356 454892131687095564780213667492442027442176224403182 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.uart_stress_all_with_rand_reset.3576009908312 6400235448356454892131687095564780213667492442027442176224403182 |
| Directory | /workspace/95.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/96.uart_fifo_reset.22136142262000330913704233916771959635450592398860195004138761467233846921582 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 113.08 seconds |
| Started | Nov 22 01:45:59 PM PST 23 |
| Finished | Nov 22 01:48:00 PM PST 23 |
| Peak memory | 198796 kb |
| Host | smart-17502012-e853-4c05-a6b9-b0389573b7ea |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=22136142262000330913704233916771959635450592398860195004138761467233846921582 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 96.uart_fifo_reset.22136142262000330913704233916771959635450592398860195004138761467233846921582 |
| Directory | /workspace/96.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/96.uart_stress_all_with_rand_reset.90152261261633255347308576110877287523054324715482586135391032251728690313467 |
| Short name | T948 |
| Test name | |
| Test status | |
| Simulation time | 87476847566 ps |
| CPU time | 464.18 seconds |
| Started | Nov 22 01:46:02 PM PST 23 |
| Finished | Nov 22 01:53:52 PM PST 23 |
| Peak memory | 226244 kb |
| Host | smart-275b0821-2a61-40e2-aae9-ccdd454724c3 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90152261261633255347308576 110877287523054324715482586135391032251728690313467 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.uart_stress_all_with_rand_reset.9015226126163 3255347308576110877287523054324715482586135391032251728690313467 |
| Directory | /workspace/96.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/97.uart_fifo_reset.99539913351361033641755383674970703970486169236082399229830035254352702442270 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 113.54 seconds |
| Started | Nov 22 01:45:59 PM PST 23 |
| Finished | Nov 22 01:48:01 PM PST 23 |
| Peak memory | 198816 kb |
| Host | smart-012b8f98-b29a-4470-bb1b-9103a7b8e675 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=99539913351361033641755383674970703970486169236082399229830035254352702442270 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 97.uart_fifo_reset.99539913351361033641755383674970703970486169236082399229830035254352702442270 |
| Directory | /workspace/97.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/97.uart_stress_all_with_rand_reset.73357712283695384766851443533927325944427586766599797984928819206937137449353 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 87476847566 ps |
| CPU time | 460.87 seconds |
| Started | Nov 22 01:46:14 PM PST 23 |
| Finished | Nov 22 01:53:58 PM PST 23 |
| Peak memory | 226272 kb |
| Host | smart-43e5ca30-9b7a-44b4-9155-a76ed844c671 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73357712283695384766851443 533927325944427586766599797984928819206937137449353 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.uart_stress_all_with_rand_reset.7335771228369 5384766851443533927325944427586766599797984928819206937137449353 |
| Directory | /workspace/97.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/98.uart_fifo_reset.6016999825010225523931138056195089934013219204766740022444627764831671682147 |
| Short name | T1103 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 113.18 seconds |
| Started | Nov 22 01:46:00 PM PST 23 |
| Finished | Nov 22 01:48:00 PM PST 23 |
| Peak memory | 198860 kb |
| Host | smart-9212931a-0796-42a0-9218-f9fd43ea0c6e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=6016999825010225523931138056195089934013219204766740022444627764831671682147 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 98.uart_fifo_reset.6016999825010225523931138056195089934013219204766740022444627764831671682147 |
| Directory | /workspace/98.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/98.uart_stress_all_with_rand_reset.16050991260560089533966276275310467596672749801229353651356363497009962323774 |
| Short name | T1185 |
| Test name | |
| Test status | |
| Simulation time | 87476847566 ps |
| CPU time | 459.51 seconds |
| Started | Nov 22 01:46:00 PM PST 23 |
| Finished | Nov 22 01:53:47 PM PST 23 |
| Peak memory | 226148 kb |
| Host | smart-7b445d79-2f65-47cd-a9ca-27dcfc1c137c |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16050991260560089533966276 275310467596672749801229353651356363497009962323774 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.uart_stress_all_with_rand_reset.1605099126056 0089533966276275310467596672749801229353651356363497009962323774 |
| Directory | /workspace/98.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/99.uart_fifo_reset.81399809271873141689542434466127928749428156736309169732624998403135641546283 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 123972198458 ps |
| CPU time | 112.45 seconds |
| Started | Nov 22 01:46:26 PM PST 23 |
| Finished | Nov 22 01:48:20 PM PST 23 |
| Peak memory | 198968 kb |
| Host | smart-3ebf7633-2b92-4cc5-b71d-4c1b439dd8d2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=81399809271873141689542434466127928749428156736309169732624998403135641546283 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 99.uart_fifo_reset.81399809271873141689542434466127928749428156736309169732624998403135641546283 |
| Directory | /workspace/99.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/99.uart_stress_all_with_rand_reset.31926019432117806371261060666599050018720404339465254842118911271641375622300 |
| Short name | T998 |
| Test name | |
| Test status | |
| Simulation time | 87476847566 ps |
| CPU time | 469.37 seconds |
| Started | Nov 22 01:46:20 PM PST 23 |
| Finished | Nov 22 01:54:11 PM PST 23 |
| Peak memory | 226220 kb |
| Host | smart-c99d056f-3ffc-4993-a813-dcc9fe8f3c73 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31926019432117806371261060 666599050018720404339465254842118911271641375622300 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.uart_stress_all_with_rand_reset.3192601943211 7806371261060666599050018720404339465254842118911271641375622300 |
| Directory | /workspace/99.uart_stress_all_with_rand_reset/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |