UART Simulation Results

Wednesday November 22 2023 20:02:38 UTC

GitHub Revision: 4002b28ec4

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 56541452733628775295814943325285397402671097056517970046183331126493552547969

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	19.480s	5.760ms	50	50	100.00
V1	csr_hw_reset	uart_csr_hw_reset	0.610s	22.529us	5	5	100.00
V1	csr_rw	uart_csr_rw	0.670s	21.815us	20	20	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.600s	306.241us	5	5	100.00
V1	csr_aliasing	uart_csr_aliasing	0.860s	42.368us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	0.860s	38.333us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.670s	21.815us	20	20	100.00
		uart_csr_aliasing	0.860s	42.368us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	base_random_seq	uart_tx_rx	1.078m	57.392ms	50	50	100.00
V2	parity	uart_smoke	19.480s	5.760ms	50	50	100.00
		uart_tx_rx	1.078m	57.392ms	50	50	100.00
V2	parity_error	uart_intr	13.264m	787.145ms	50	50	100.00
		uart_rx_parity_err	38.380s	36.617ms	50	50	100.00
V2	watermark	uart_tx_rx	1.078m	57.392ms	50	50	100.00
		uart_intr	13.264m	787.145ms	50	50	100.00
V2	fifo_full	uart_fifo_full	1.034m	61.777ms	50	50	100.00
V2	fifo_overflow	uart_fifo_overflow	55.540s	58.552ms	50	50	100.00
V2	fifo_reset	uart_fifo_reset	1.920m	123.972ms	300	300	100.00
V2	rx_frame_err	uart_intr	13.264m	787.145ms	50	50	100.00
V2	rx_break_err	uart_intr	13.264m	787.145ms	50	50	100.00
V2	rx_timeout	uart_intr	13.264m	787.145ms	50	50	100.00
V2	perf	uart_perf	8.014m	14.099ms	50	50	100.00
V2	sys_loopback	uart_loopback	16.600s	14.572ms	50	50	100.00
V2	line_loopback	uart_loopback	16.600s	14.572ms	50	50	100.00
V2	rx_noise_filter	uart_noise_filter	1.649m	94.502ms	50	50	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	5.100s	4.268ms	50	50	100.00
V2	tx_overide	uart_tx_ovrd	1.320s	485.186us	50	50	100.00
V2	rx_oversample	uart_rx_oversample	21.070s	4.370ms	50	50	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	6.099m	93.388ms	50	50	100.00
V2	stress_all	uart_stress_all	58.280s	43.402ms	50	50	100.00
V2	stress_all_with_reset	uart_stress_all_with_rand_reset	8.031m	87.477ms	100	100	100.00
V2	alert_test	uart_alert_test	0.620s	16.369us	50	50	100.00
V2	intr_test	uart_intr_test	0.680s	22.779us	50	50	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.140s	152.868us	20	20	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.140s	152.868us	20	20	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	0.610s	22.529us	5	5	100.00
		uart_csr_rw	0.670s	21.815us	20	20	100.00
		uart_csr_aliasing	0.860s	42.368us	5	5	100.00
		uart_same_csr_outstanding	0.830s	45.029us	20	20	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	0.610s	22.529us	5	5	100.00
		uart_csr_rw	0.670s	21.815us	20	20	100.00
		uart_csr_aliasing	0.860s	42.368us	5	5	100.00
		uart_same_csr_outstanding	0.830s	45.029us	20	20	100.00
V2		TOTAL			1190	1190	100.00
V2S	tl_intg_err	uart_sec_cm	0.900s	100.582us	5	5	100.00
		uart_tl_intg_err	1.410s	136.350us	20	20	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.410s	136.350us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3		TOTAL			0	0	--
		TOTAL			1320	1320	100.00

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	19	19	19	100.00
V2S	2	2	2	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
92.89	99.79	98.22	100.00	--	99.52	98.20	61.62

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