Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	67464180	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

33612197

1

T1

71

T2

72

T3

264

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	90160381	1			T1	208		T2	216		T3	71
values[0x0]	5153250	1			T1	52		T2	58		T3	99
values[0x1]	5762746	1			T1	47		T2	44		T3	108

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	47528387	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

53547990

1

T1

148

T2

153

T3

271

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	376716	1			T3	2		T4	2		T8	1
valid_sources[0x01]	363165	1			T7	1		T8	1		T9	5
valid_sources[0x02]	364247	1			T1	1		T4	3		T7	1
valid_sources[0x03]	408670	1			T9	11		T33	8		T43	2
valid_sources[0x04]	381100	1			T3	1		T4	2		T8	1
valid_sources[0x05]	370892	1			T1	3		T3	2		T4	5
valid_sources[0x06]	443350	1			T3	1		T4	1		T7	1
valid_sources[0x07]	400932	1			T3	2		T4	2		T9	5
valid_sources[0x08]	502998	1			T3	1		T5	1		T7	1
valid_sources[0x09]	429038	1			T1	1		T4	5		T7	1
valid_sources[0x0a]	388185	1			T3	1		T4	1		T7	1
valid_sources[0x0b]	408747	1			T10	4		T33	7		T37	2
valid_sources[0x0c]	383532	1			T1	1		T7	2		T9	3
valid_sources[0x0d]	367449	1			T1	2		T3	1		T7	1
valid_sources[0x0e]	404365	1			T1	1		T4	4		T7	1
valid_sources[0x0f]	454248	1			T9	4		T10	2		T33	7
valid_sources[0x10]	373785	1			T1	4		T4	1		T6	2
valid_sources[0x11]	379707	1			T1	2		T3	1		T4	2
valid_sources[0x12]	393856	1			T1	3		T3	1		T4	3
valid_sources[0x13]	376713	1			T4	1		T9	1		T10	3
valid_sources[0x14]	437434	1			T1	3		T3	1		T4	3
valid_sources[0x15]	408294	1			T3	2		T4	1		T7	2
valid_sources[0x16]	381059	1			T1	2		T3	1		T4	2
valid_sources[0x17]	400657	1			T3	1		T4	4		T7	3
valid_sources[0x18]	387130	1			T4	3		T7	1		T33	1
valid_sources[0x19]	406939	1			T1	1		T4	1		T9	6
valid_sources[0x1a]	382971	1			T1	2		T3	2		T4	8
valid_sources[0x1b]	398562	1			T1	1		T3	1		T4	1
valid_sources[0x1c]	470239	1			T3	2		T4	1		T10	4
valid_sources[0x1d]	376650	1			T3	1		T9	3		T10	2
valid_sources[0x1e]	391958	1			T1	1		T4	1		T9	4
valid_sources[0x1f]	403047	1			T3	1		T9	3		T10	4
valid_sources[0x20]	389514	1			T1	1		T3	2		T4	1
valid_sources[0x21]	388778	1			T1	4		T3	1		T4	1
valid_sources[0x22]	377987	1			T1	4		T4	3		T7	1
valid_sources[0x23]	440842	1			T1	2		T3	2		T4	3
valid_sources[0x24]	377130	1			T3	1		T4	3		T7	3
valid_sources[0x25]	381411	1			T1	1		T10	2		T47	19
valid_sources[0x26]	388983	1			T1	2		T3	1		T4	3
valid_sources[0x27]	380111	1			T4	1		T7	1		T9	1
valid_sources[0x28]	374272	1			T4	1		T9	4		T10	6
valid_sources[0x29]	355094	1			T3	2		T9	2		T10	4
valid_sources[0x2a]	399405	1			T4	2		T9	1		T10	2
valid_sources[0x2b]	387376	1			T1	2		T3	1		T4	1
valid_sources[0x2c]	423338	1			T1	1		T3	3		T4	6
valid_sources[0x2d]	407277	1			T4	3		T7	1		T10	3
valid_sources[0x2e]	400433	1			T4	1		T7	1		T9	2
valid_sources[0x2f]	369108	1			T1	3		T2	24		T3	1
valid_sources[0x30]	401080	1			T4	4		T7	3		T9	2
valid_sources[0x31]	368647	1			T3	2		T7	4		T8	1
valid_sources[0x32]	399190	1			T1	1		T7	2		T10	1
valid_sources[0x33]	376960	1			T1	1		T3	1		T4	3
valid_sources[0x34]	364297	1			T1	2		T3	1		T4	5
valid_sources[0x35]	403812	1			T4	2		T5	1		T10	1
valid_sources[0x36]	432652	1			T1	5		T3	2		T4	1
valid_sources[0x37]	386917	1			T1	1		T3	1		T5	1
valid_sources[0x38]	397356	1			T3	1		T4	3		T9	1
valid_sources[0x39]	364612	1			T1	3		T3	3		T4	1
valid_sources[0x3a]	372634	1			T1	7		T2	8		T4	5
valid_sources[0x3b]	384177	1			T1	1		T4	4		T5	1
valid_sources[0x3c]	359590	1			T1	2		T10	1		T33	5
valid_sources[0x3d]	377476	1			T1	1		T3	1		T4	2
valid_sources[0x3e]	396934	1			T1	3		T7	1		T9	7
valid_sources[0x3f]	390056	1			T1	3		T4	1		T10	3
valid_sources[0x40]	383028	1			T1	1		T2	47		T4	1
valid_sources[0x41]	390694	1			T1	1		T4	3		T7	3
valid_sources[0x42]	483040	1			T3	1		T9	5		T33	3
valid_sources[0x43]	389687	1			T3	1		T4	1		T7	1
valid_sources[0x44]	461515	1			T3	1		T4	8		T9	1
valid_sources[0x45]	373692	1			T1	2		T4	4		T9	2
valid_sources[0x46]	405384	1			T3	2		T4	1		T7	1
valid_sources[0x47]	394163	1			T3	1		T9	6		T10	2
valid_sources[0x48]	388989	1			T1	3		T9	1		T10	5
valid_sources[0x49]	393391	1			T4	4		T7	2		T9	2
valid_sources[0x4a]	382723	1			T1	1		T4	2		T7	1
valid_sources[0x4b]	388423	1			T1	1		T3	1		T4	4
valid_sources[0x4c]	367969	1			T1	3		T3	2		T4	5
valid_sources[0x4d]	423943	1			T4	1		T9	6		T10	1
valid_sources[0x4e]	380666	1			T3	1		T4	1		T9	3
valid_sources[0x4f]	370668	1			T1	1		T3	4		T4	1
valid_sources[0x50]	375900	1			T4	2		T7	1		T10	1
valid_sources[0x51]	371689	1			T1	2		T3	1		T4	1
valid_sources[0x52]	399848	1			T3	2		T4	1		T9	1
valid_sources[0x53]	369024	1			T1	1		T4	5		T9	1
valid_sources[0x54]	371170	1			T4	1		T7	1		T8	2
valid_sources[0x55]	400535	1			T1	1		T3	1		T4	1
valid_sources[0x56]	397732	1			T1	1		T4	10		T7	1
valid_sources[0x57]	378798	1			T3	1		T4	1		T10	5
valid_sources[0x58]	370799	1			T1	1		T9	1		T10	2
valid_sources[0x59]	381161	1			T1	1		T3	3		T4	1
valid_sources[0x5a]	508518	1			T1	1		T5	1		T7	1
valid_sources[0x5b]	416170	1			T4	4		T10	3		T33	10
valid_sources[0x5c]	381317	1			T3	3		T4	2		T7	1
valid_sources[0x5d]	392085	1			T3	4		T7	3		T9	4
valid_sources[0x5e]	359386	1			T4	5		T9	4		T10	2
valid_sources[0x5f]	459700	1			T1	2		T2	50		T3	2
valid_sources[0x60]	398926	1			T3	1		T10	4		T47	15
valid_sources[0x61]	382453	1			T4	4		T9	2		T10	5
valid_sources[0x62]	403692	1			T1	2		T2	3		T4	2
valid_sources[0x63]	381585	1			T1	2		T3	1		T4	3
valid_sources[0x64]	434214	1			T1	2		T3	3		T7	1
valid_sources[0x65]	393998	1			T1	4		T4	2		T9	2
valid_sources[0x66]	405794	1			T3	2		T4	1		T7	1
valid_sources[0x67]	421645	1			T10	2		T33	5		T43	2
valid_sources[0x68]	469837	1			T3	3		T4	2		T10	2
valid_sources[0x69]	447441	1			T3	2		T4	1		T8	1
valid_sources[0x6a]	365434	1			T1	2		T2	43		T8	1
valid_sources[0x6b]	381837	1			T3	1		T4	1		T7	1
valid_sources[0x6c]	382263	1			T1	1		T3	1		T4	1
valid_sources[0x6d]	372106	1			T1	10		T4	3		T7	2
valid_sources[0x6e]	370251	1			T3	1		T4	5		T9	2
valid_sources[0x6f]	388919	1			T1	1		T3	5		T4	3
valid_sources[0x70]	371430	1			T3	1		T4	1		T9	7
valid_sources[0x71]	373355	1			T1	1		T4	3		T7	1
valid_sources[0x72]	368089	1			T1	2		T7	4		T9	4
valid_sources[0x73]	396138	1			T1	3		T3	1		T4	2
valid_sources[0x74]	425407	1			T1	2		T2	10		T3	1
valid_sources[0x75]	368211	1			T3	2		T4	4		T8	1
valid_sources[0x76]	380796	1			T1	2		T3	1		T4	3
valid_sources[0x77]	441033	1			T1	4		T4	2		T9	3
valid_sources[0x78]	366157	1			T3	3		T4	2		T7	1
valid_sources[0x79]	389189	1			T1	4		T9	5		T10	1
valid_sources[0x7a]	364256	1			T4	3		T7	1		T9	5
valid_sources[0x7b]	379255	1			T1	3		T4	2		T7	1
valid_sources[0x7c]	381449	1			T3	6		T9	9		T10	3
valid_sources[0x7d]	399789	1			T1	3		T4	6		T10	1
valid_sources[0x7e]	376381	1			T7	2		T9	8		T10	2
valid_sources[0x7f]	515343	1			T1	3		T3	3		T4	7
valid_sources[0x80]	405819	1			T4	3		T9	3		T10	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

23927298

1

T1

25

T2

24

T3

67

values[0x0]

all_enables

biggest_size

4872059

1

T1

29

T2

30

T3

99

values[0x1]

all_enables

biggest_size

4812840

1

T1

17

T2

18

T3

98