Unified Coverage Report :: Module :: uart_csr_assert_fpv

Module : uart_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_uart_csr_assert_0/uart_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.uart_csr_assert	100.00						100.00

---

Module Instance : tb.dut.uart_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : uart_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	16150524	0	0
ctrl_rd_A	2147483647	216318	0	0
intr_enable_rd_A	2147483647	192214	0	0
ovrd_rd_A	2147483647	215427	0	0
timeout_ctrl_rd_A	2147483647	215042	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	16150524	0	0
T1	3257	1	0	0
T2	3694	1	0	0
T3	2833	371	0	0
T4	8630	539	0	0
T5	1289	0	0	0
T6	1217	0	0	0
T7	2074	0	0	0
T8	1525	89	0	0
T9	7429	4	0	0
T10	8943	3	0	0
T43	0	3	0	0
T44	0	403	0	0
T51	0	1	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	216318	0	0
T10	8943	295	0	0
T33	3239	0	0	0
T37	1417	0	0	0
T38	1173	0	0	0
T43	3937	0	0	0
T47	1169	0	0	0
T51	1419	0	0	0
T52	1317	0	0	0
T53	865	0	0	0
T54	1000	0	0	0
T57	0	16	0	0
T58	0	66	0	0
T67	0	32	0	0
T71	0	6	0	0
T114	0	66	0	0
T115	0	19	0	0
T116	0	25	0	0
T117	0	61	0	0
T118	0	18	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	192214	0	0
T5	1289	12	0	0
T6	1217	10	0	0
T7	2074	0	0	0
T8	1525	0	0	0
T9	7429	0	0	0
T10	8943	388	0	0
T33	3239	0	0	0
T37	1417	18	0	0
T38	0	9	0	0
T47	1169	0	0	0
T51	1419	0	0	0
T52	0	24	0	0
T57	0	12	0	0
T58	0	60	0	0
T71	0	22	0	0
T72	0	27	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	215427	0	0
T10	8943	111	0	0
T33	3239	0	0	0
T37	1417	0	0	0
T38	1173	0	0	0
T43	3937	0	0	0
T47	1169	0	0	0
T51	1419	8	0	0
T52	1317	0	0	0
T53	865	0	0	0
T54	1000	0	0	0
T58	0	14	0	0
T67	0	5	0	0
T71	0	7	0	0
T114	0	24	0	0
T115	0	53	0	0
T116	0	9	0	0
T117	0	15	0	0
T118	0	10	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	215042	0	0
T10	8943	124	0	0
T33	3239	0	0	0
T37	1417	0	0	0
T38	1173	0	0	0
T43	3937	0	0	0
T47	1169	0	0	0
T51	1419	14	0	0
T52	1317	0	0	0
T53	865	0	0	0
T54	1000	0	0	0
T57	0	5	0	0
T58	0	12	0	0
T67	0	8	0	0
T71	0	4	0	0
T114	0	42	0	0
T115	0	30	0	0
T116	0	29	0	0
T117	0	34	0	0