Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	67374435	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

35090869

1

T1

212

T2

201

T3

8

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	92185728	1			T1	116		T2	44		T3	11
values[0x0]	4858872	1			T1	50		T2	86		T3	7
values[0x1]	5420704	1			T1	46		T2	86		T3	4

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	47763315	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

54701989

1

T1

212

T2

209

T3

9

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	375786	1			T6	3		T9	6		T39	2
valid_sources[0x01]	482932	1			T2	4		T9	8		T10	1
valid_sources[0x02]	973722	1			T2	1		T9	13		T10	1
valid_sources[0x03]	375221	1			T2	1		T7	5		T9	16
valid_sources[0x04]	381608	1			T2	1		T9	14		T10	3
valid_sources[0x05]	372193	1			T5	16		T9	7		T10	1
valid_sources[0x06]	395006	1			T2	2		T9	8		T10	3
valid_sources[0x07]	382012	1			T2	2		T5	1		T9	11
valid_sources[0x08]	413877	1			T1	7		T2	1		T5	2
valid_sources[0x09]	490286	1			T2	7		T5	2		T9	12
valid_sources[0x0a]	401123	1			T9	13		T10	4		T52	1
valid_sources[0x0b]	401154	1			T2	1		T9	8		T10	1
valid_sources[0x0c]	392089	1			T9	12		T10	2		T39	1
valid_sources[0x0d]	374204	1			T4	1		T9	7		T10	1
valid_sources[0x0e]	401347	1			T2	1		T5	8		T9	12
valid_sources[0x0f]	383274	1			T9	9		T40	1		T42	1
valid_sources[0x10]	405340	1			T2	6		T9	6		T10	2
valid_sources[0x11]	551638	1			T5	5		T9	9		T39	1
valid_sources[0x12]	393352	1			T9	5		T10	2		T46	1
valid_sources[0x13]	475400	1			T2	1		T5	1		T9	10
valid_sources[0x14]	372261	1			T9	1		T42	1		T49	2
valid_sources[0x15]	384340	1			T6	15		T9	9		T10	2
valid_sources[0x16]	426196	1			T9	8		T10	1		T39	2
valid_sources[0x17]	369440	1			T9	6		T32	1		T68	3
valid_sources[0x18]	400227	1			T2	1		T9	4		T10	1
valid_sources[0x19]	427009	1			T9	12		T39	1		T46	12
valid_sources[0x1a]	367638	1			T2	1		T5	9		T9	10
valid_sources[0x1b]	391203	1			T2	4		T9	13		T10	1
valid_sources[0x1c]	363346	1			T5	2		T9	5		T10	1
valid_sources[0x1d]	372804	1			T9	5		T10	1		T42	2
valid_sources[0x1e]	392196	1			T2	1		T9	6		T10	3
valid_sources[0x1f]	403888	1			T5	3		T9	6		T10	1
valid_sources[0x20]	385470	1			T2	2		T9	10		T10	1
valid_sources[0x21]	396991	1			T2	4		T5	2		T9	14
valid_sources[0x22]	382833	1			T6	1		T7	2		T9	10
valid_sources[0x23]	434607	1			T9	4		T39	1		T35	2
valid_sources[0x24]	359722	1			T5	2		T9	9		T42	2
valid_sources[0x25]	440815	1			T9	8		T10	1		T39	2
valid_sources[0x26]	407675	1			T2	6		T9	6		T42	2
valid_sources[0x27]	396033	1			T2	2		T5	27		T9	11
valid_sources[0x28]	369715	1			T5	6		T8	22		T9	7
valid_sources[0x29]	452741	1			T9	3		T10	1		T39	1
valid_sources[0x2a]	392939	1			T9	6		T39	2		T42	3
valid_sources[0x2b]	399097	1			T9	2		T10	1		T52	1
valid_sources[0x2c]	434591	1			T9	6		T39	1		T42	1
valid_sources[0x2d]	393033	1			T9	6		T39	2		T35	3
valid_sources[0x2e]	394126	1			T9	6		T52	1		T35	1
valid_sources[0x2f]	391592	1			T9	14		T10	1		T35	3
valid_sources[0x30]	361139	1			T2	4		T6	5		T9	10
valid_sources[0x31]	419835	1			T2	6		T4	1		T5	1
valid_sources[0x32]	366572	1			T9	7		T10	1		T46	12
valid_sources[0x33]	402727	1			T6	7		T9	8		T10	1
valid_sources[0x34]	422061	1			T5	1		T9	14		T10	1
valid_sources[0x35]	395138	1			T1	2		T2	1		T5	4
valid_sources[0x36]	413739	1			T6	4		T9	11		T10	1
valid_sources[0x37]	374322	1			T5	12		T7	1		T9	13
valid_sources[0x38]	378959	1			T2	4		T9	16		T10	1
valid_sources[0x39]	368469	1			T5	5		T9	8		T10	1
valid_sources[0x3a]	398253	1			T9	9		T10	1		T39	1
valid_sources[0x3b]	398791	1			T2	3		T5	26		T9	9
valid_sources[0x3c]	352416	1			T1	12		T2	2		T9	9
valid_sources[0x3d]	372980	1			T2	1		T9	10		T10	2
valid_sources[0x3e]	405336	1			T9	6		T35	2		T410	3
valid_sources[0x3f]	389919	1			T9	5		T10	2		T39	3
valid_sources[0x40]	383168	1			T5	1		T9	11		T10	2
valid_sources[0x41]	406287	1			T9	12		T49	2		T43	1
valid_sources[0x42]	395101	1			T2	4		T9	6		T10	2
valid_sources[0x43]	397199	1			T2	4		T9	6		T10	1
valid_sources[0x44]	371286	1			T2	1		T4	7		T9	11
valid_sources[0x45]	422088	1			T1	11		T9	8		T39	1
valid_sources[0x46]	398145	1			T2	2		T5	1		T9	11
valid_sources[0x47]	363286	1			T9	9		T10	4		T53	1
valid_sources[0x48]	385088	1			T2	2		T9	7		T39	1
valid_sources[0x49]	469596	1			T5	1		T9	6		T35	3
valid_sources[0x4a]	396853	1			T2	4		T9	6		T10	1
valid_sources[0x4b]	393693	1			T4	9		T5	14		T9	10
valid_sources[0x4c]	380062	1			T6	1		T9	12		T10	2
valid_sources[0x4d]	387496	1			T2	1		T9	19		T10	2
valid_sources[0x4e]	400919	1			T2	1		T5	8		T6	2
valid_sources[0x4f]	395472	1			T9	13		T35	1		T49	3
valid_sources[0x50]	377947	1			T5	4		T9	7		T10	1
valid_sources[0x51]	381421	1			T9	8		T10	1		T46	12
valid_sources[0x52]	397481	1			T2	4		T9	7		T10	2
valid_sources[0x53]	384648	1			T7	3		T9	13		T10	3
valid_sources[0x54]	390148	1			T2	2		T7	5		T9	10
valid_sources[0x55]	371367	1			T5	7		T9	11		T10	1
valid_sources[0x56]	374955	1			T2	2		T5	4		T9	5
valid_sources[0x57]	406067	1			T6	1		T9	5		T10	1
valid_sources[0x58]	402168	1			T9	9		T35	1		T42	2
valid_sources[0x59]	374278	1			T9	15		T35	2		T42	1
valid_sources[0x5a]	368924	1			T6	1		T9	5		T10	2
valid_sources[0x5b]	394997	1			T2	7		T9	9		T10	1
valid_sources[0x5c]	412859	1			T1	17		T2	1		T5	13
valid_sources[0x5d]	385608	1			T2	2		T9	9		T10	1
valid_sources[0x5e]	534788	1			T5	3		T6	2		T9	7
valid_sources[0x5f]	387445	1			T2	1		T9	6		T42	1
valid_sources[0x60]	390211	1			T5	4		T9	6		T10	1
valid_sources[0x61]	382083	1			T9	5		T10	1		T42	3
valid_sources[0x62]	390698	1			T9	11		T10	1		T39	1
valid_sources[0x63]	388471	1			T2	1		T7	2		T9	6
valid_sources[0x64]	396636	1			T1	11		T2	1		T9	13
valid_sources[0x65]	386905	1			T1	1		T2	1		T9	5
valid_sources[0x66]	378669	1			T2	5		T9	8		T10	1
valid_sources[0x67]	382630	1			T9	14		T10	2		T49	1
valid_sources[0x68]	410501	1			T9	2		T10	1		T42	1
valid_sources[0x69]	372526	1			T6	2		T9	4		T35	1
valid_sources[0x6a]	376587	1			T9	14		T10	1		T52	1
valid_sources[0x6b]	380750	1			T1	5		T5	4		T9	9
valid_sources[0x6c]	415098	1			T5	2		T9	15		T10	2
valid_sources[0x6d]	396739	1			T2	4		T5	9		T9	12
valid_sources[0x6e]	411838	1			T2	3		T5	11		T9	10
valid_sources[0x6f]	379830	1			T1	12		T9	13		T10	4
valid_sources[0x70]	385636	1			T5	6		T9	7		T10	2
valid_sources[0x71]	393054	1			T9	7		T10	2		T39	1
valid_sources[0x72]	379805	1			T3	22		T6	5		T9	9
valid_sources[0x73]	389073	1			T6	4		T9	7		T52	1
valid_sources[0x74]	463977	1			T1	12		T2	3		T9	8
valid_sources[0x75]	387403	1			T9	11		T10	1		T53	2
valid_sources[0x76]	383293	1			T9	12		T53	2		T43	3
valid_sources[0x77]	419330	1			T5	12		T9	5		T39	1
valid_sources[0x78]	414516	1			T6	5		T9	8		T10	1
valid_sources[0x79]	378858	1			T9	6		T39	1		T52	1
valid_sources[0x7a]	411968	1			T9	4		T52	1		T35	2
valid_sources[0x7b]	378342	1			T9	15		T10	4		T35	1
valid_sources[0x7c]	437510	1			T5	1		T6	10		T9	15
valid_sources[0x7d]	387137	1			T5	2		T9	8		T10	2
valid_sources[0x7e]	376260	1			T9	5		T35	2		T408	1
valid_sources[0x7f]	445922	1			T1	1		T5	3		T9	8
valid_sources[0x80]	371000	1			T9	6		T49	3		T43	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

25995606

1

T1

116

T2

41

T3

5

values[0x0]

all_enables

biggest_size

4578546

1

T1

50

T2

86

T3

2

values[0x1]

all_enables

biggest_size

4516717

1

T1

46

T2

74

T3

1