Unified Coverage Report :: Module :: uart_csr_assert_fpv

Module : uart_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_uart_csr_assert_0/uart_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.uart_csr_assert	100.00						100.00

---

Module Instance : tb.dut.uart_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : uart_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	15046393	0	0
ctrl_rd_A	2147483647	274394	0	0
intr_enable_rd_A	2147483647	241038	0	0
ovrd_rd_A	2147483647	273064	0	0
timeout_ctrl_rd_A	2147483647	269699	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	15046393	0	0
T2	2291	189	0	0
T3	1028	0	0	0
T4	1085	0	0	0
T5	14425	779	0	0
T6	1108	0	0	0
T7	1804	0	0	0
T8	1463	0	0	0
T9	5942	0	0	0
T10	11156	620	0	0
T35	0	36	0	0
T39	6899	501	0	0
T40	0	132	0	0
T41	0	57	0	0
T42	0	62	0	0
T43	0	229	0	0
T44	0	282	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	274394	0	0
T5	14425	47	0	0
T6	1108	0	0	0
T7	1804	9	0	0
T8	1463	0	0	0
T9	5942	0	0	0
T10	11156	33	0	0
T33	1188	0	0	0
T35	2583	0	0	0
T39	6899	0	0	0
T44	0	50	0	0
T46	0	28	0	0
T47	0	13	0	0
T48	0	37	0	0
T52	1435	0	0	0
T60	0	467	0	0
T98	0	2	0	0
T99	0	32	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	241038	0	0
T5	14425	39	0	0
T6	1108	0	0	0
T7	1804	1	0	0
T8	1463	0	0	0
T9	5942	0	0	0
T10	11156	36	0	0
T33	1188	9	0	0
T35	2583	0	0	0
T39	6899	0	0	0
T44	0	25	0	0
T46	0	42	0	0
T48	0	2	0	0
T52	1435	0	0	0
T60	0	426	0	0
T98	0	1	0	0
T100	0	13	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	273064	0	0
T5	14425	54	0	0
T6	1108	0	0	0
T7	1804	7	0	0
T8	1463	0	0	0
T9	5942	0	0	0
T10	11156	38	0	0
T33	1188	0	0	0
T35	2583	0	0	0
T39	6899	0	0	0
T44	0	25	0	0
T46	0	27	0	0
T47	0	5	0	0
T48	0	5	0	0
T52	1435	0	0	0
T60	0	392	0	0
T98	0	7	0	0
T101	0	2	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	269699	0	0
T5	14425	42	0	0
T6	1108	0	0	0
T7	1804	12	0	0
T8	1463	0	0	0
T9	5942	0	0	0
T10	11156	34	0	0
T33	1188	0	0	0
T35	2583	0	0	0
T39	6899	0	0	0
T44	0	17	0	0
T46	0	30	0	0
T47	0	11	0	0
T48	0	1	0	0
T52	1435	0	0	0
T60	0	457	0	0
T98	0	7	0	0
T101	0	10	0	0