Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	67892101	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

33055562

1

T1

578

T2

6

T3

18

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	89285068	1			T1	574		T2	11		T3	20
values[0x0]	5504762	1			T1	288		T2	3		T3	11
values[0x1]	6157833	1			T1	285		T2	8		T3	9

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	47547087	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

53400576

1

T1

680

T2

7

T3

20

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	379445	1			T1	3		T4	3		T5	1
valid_sources[0x01]	379917	1			T1	5		T4	3		T5	1
valid_sources[0x02]	402649	1			T1	8		T3	1		T4	3
valid_sources[0x03]	360977	1			T1	8		T4	2		T9	1
valid_sources[0x04]	407029	1			T1	10		T4	1		T9	1
valid_sources[0x05]	460910	1			T1	2		T3	2		T4	3
valid_sources[0x06]	395048	1			T1	6		T6	1		T8	8
valid_sources[0x07]	410830	1			T1	7		T4	1		T9	2
valid_sources[0x08]	366536	1			T1	7		T2	1		T6	1
valid_sources[0x09]	370716	1			T1	7		T7	1		T8	27
valid_sources[0x0a]	382804	1			T1	1		T4	1		T9	1
valid_sources[0x0b]	374496	1			T1	5		T6	1		T9	1
valid_sources[0x0c]	372602	1			T1	5		T9	2		T47	29
valid_sources[0x0d]	365293	1			T1	5		T4	1		T9	1
valid_sources[0x0e]	370893	1			T1	5		T9	1		T30	3
valid_sources[0x0f]	370775	1			T1	4		T9	1		T47	13
valid_sources[0x10]	357300	1			T1	1		T4	1		T7	7
valid_sources[0x11]	370565	1			T1	4		T4	1		T8	17
valid_sources[0x12]	369510	1			T1	5		T2	3		T4	2
valid_sources[0x13]	426040	1			T3	1		T4	2		T9	3
valid_sources[0x14]	516200	1			T1	3		T3	1		T4	1
valid_sources[0x15]	361131	1			T1	7		T4	1		T7	21
valid_sources[0x16]	377476	1			T1	5		T9	2		T30	1
valid_sources[0x17]	376328	1			T1	4		T6	1		T30	2
valid_sources[0x18]	364835	1			T1	5		T4	1		T8	8
valid_sources[0x19]	376063	1			T1	5		T4	1		T5	1
valid_sources[0x1a]	369656	1			T1	1		T47	5		T42	2
valid_sources[0x1b]	380111	1			T1	5		T9	2		T30	1
valid_sources[0x1c]	366204	1			T1	4		T7	1		T30	2
valid_sources[0x1d]	362298	1			T1	9		T4	2		T30	2
valid_sources[0x1e]	386976	1			T1	5		T9	4		T30	1
valid_sources[0x1f]	371554	1			T1	8		T4	3		T9	1
valid_sources[0x20]	394372	1			T1	5		T4	2		T9	1
valid_sources[0x21]	369988	1			T1	4		T4	2		T30	3
valid_sources[0x22]	368682	1			T1	6		T4	2		T5	1
valid_sources[0x23]	393201	1			T1	4		T30	3		T31	4
valid_sources[0x24]	361223	1			T1	2		T4	2		T5	1
valid_sources[0x25]	385163	1			T1	2		T4	1		T9	2
valid_sources[0x26]	358817	1			T1	6		T7	7		T47	11
valid_sources[0x27]	510698	1			T1	6		T4	1		T9	2
valid_sources[0x28]	394188	1			T1	2		T4	1		T7	1
valid_sources[0x29]	355638	1			T1	3		T4	3		T30	1
valid_sources[0x2a]	410010	1			T1	2		T47	11		T33	2
valid_sources[0x2b]	374462	1			T1	2		T4	1		T30	6
valid_sources[0x2c]	406516	1			T1	4		T4	3		T6	1
valid_sources[0x2d]	411464	1			T1	5		T4	2		T10	3
valid_sources[0x2e]	387271	1			T1	3		T4	4		T30	1
valid_sources[0x2f]	412760	1			T1	6		T5	1		T10	31
valid_sources[0x30]	450996	1			T1	3		T4	1		T9	1
valid_sources[0x31]	381103	1			T1	5		T9	1		T30	3
valid_sources[0x32]	370244	1			T1	3		T6	1		T8	12
valid_sources[0x33]	375664	1			T1	3		T4	2		T9	1
valid_sources[0x34]	388098	1			T30	1		T47	5		T32	1
valid_sources[0x35]	392267	1			T1	5		T4	1		T7	1
valid_sources[0x36]	377642	1			T1	1		T30	2		T47	6
valid_sources[0x37]	371496	1			T1	4		T9	1		T30	1
valid_sources[0x38]	397550	1			T1	3		T3	1		T4	1
valid_sources[0x39]	394514	1			T1	1		T47	7		T48	2
valid_sources[0x3a]	430397	1			T1	8		T4	3		T30	1
valid_sources[0x3b]	370854	1			T1	2		T9	2		T30	3
valid_sources[0x3c]	373340	1			T1	4		T4	1		T9	4
valid_sources[0x3d]	401551	1			T1	7		T2	3		T4	3
valid_sources[0x3e]	414414	1			T1	4		T6	1		T30	2
valid_sources[0x3f]	372925	1			T1	3		T4	1		T6	1
valid_sources[0x40]	423384	1			T1	5		T3	1		T30	2
valid_sources[0x41]	368728	1			T1	7		T30	2		T47	13
valid_sources[0x42]	376692	1			T1	1		T8	1		T10	5
valid_sources[0x43]	384170	1			T1	5		T3	1		T30	2
valid_sources[0x44]	371692	1			T1	5		T9	1		T30	2
valid_sources[0x45]	386096	1			T1	4		T3	3		T4	2
valid_sources[0x46]	378699	1			T1	5		T8	7		T30	2
valid_sources[0x47]	362349	1			T1	1		T4	2		T47	2
valid_sources[0x48]	379260	1			T1	2		T4	3		T7	1
valid_sources[0x49]	352999	1			T1	4		T4	4		T9	2
valid_sources[0x4a]	362857	1			T1	3		T4	1		T5	2
valid_sources[0x4b]	374675	1			T1	5		T4	1		T9	1
valid_sources[0x4c]	382123	1			T1	5		T9	2		T47	9
valid_sources[0x4d]	368186	1			T1	2		T4	1		T30	1
valid_sources[0x4e]	419841	1			T1	4		T4	2		T9	1
valid_sources[0x4f]	394345	1			T1	7		T9	1		T47	8
valid_sources[0x50]	382076	1			T1	3		T8	21		T9	1
valid_sources[0x51]	376631	1			T1	3		T4	1		T9	1
valid_sources[0x52]	368085	1			T1	7		T9	1		T47	25
valid_sources[0x53]	403721	1			T1	6		T4	2		T9	1
valid_sources[0x54]	349255	1			T1	1		T4	4		T30	2
valid_sources[0x55]	361524	1			T1	7		T4	1		T9	1
valid_sources[0x56]	377146	1			T1	5		T6	2		T47	10
valid_sources[0x57]	435825	1			T1	8		T4	1		T6	1
valid_sources[0x58]	426475	1			T1	4		T4	1		T30	1
valid_sources[0x59]	362564	1			T1	3		T4	1		T9	1
valid_sources[0x5a]	389256	1			T1	1		T4	1		T9	1
valid_sources[0x5b]	377879	1			T1	7		T3	1		T4	1
valid_sources[0x5c]	409450	1			T1	8		T4	1		T9	1
valid_sources[0x5d]	384906	1			T1	6		T4	1		T9	2
valid_sources[0x5e]	378544	1			T1	2		T9	1		T30	3
valid_sources[0x5f]	355853	1			T1	5		T4	2		T30	1
valid_sources[0x60]	405727	1			T1	4		T4	1		T9	2
valid_sources[0x61]	374106	1			T1	5		T4	1		T30	2
valid_sources[0x62]	377808	1			T1	5		T4	2		T5	1
valid_sources[0x63]	411943	1			T1	2		T30	2		T47	1
valid_sources[0x64]	409765	1			T1	4		T9	1		T47	3
valid_sources[0x65]	370918	1			T1	1		T4	1		T9	2
valid_sources[0x66]	399590	1			T1	4		T9	1		T30	1
valid_sources[0x67]	477403	1			T1	8		T9	1		T30	2
valid_sources[0x68]	375477	1			T1	5		T4	1		T8	9
valid_sources[0x69]	373320	1			T1	3		T4	2		T9	1
valid_sources[0x6a]	399310	1			T1	5		T4	2		T30	1
valid_sources[0x6b]	390326	1			T1	5		T2	3		T4	1
valid_sources[0x6c]	368732	1			T1	4		T4	2		T9	1
valid_sources[0x6d]	373589	1			T1	6		T4	1		T31	2
valid_sources[0x6e]	371768	1			T1	3		T4	3		T30	1
valid_sources[0x6f]	389675	1			T1	7		T3	4		T4	2
valid_sources[0x70]	471217	1			T1	6		T4	1		T9	1
valid_sources[0x71]	393342	1			T1	8		T4	2		T30	4
valid_sources[0x72]	359072	1			T1	7		T4	1		T9	3
valid_sources[0x73]	390413	1			T1	2		T30	2		T31	3
valid_sources[0x74]	376401	1			T1	5		T4	2		T8	32
valid_sources[0x75]	397279	1			T1	7		T4	1		T30	2
valid_sources[0x76]	415250	1			T1	4		T7	12		T9	1
valid_sources[0x77]	380631	1			T1	1		T4	2		T10	2
valid_sources[0x78]	527227	1			T1	5		T9	2		T30	2
valid_sources[0x79]	354333	1			T1	5		T9	2		T30	4
valid_sources[0x7a]	368181	1			T1	6		T9	1		T30	2
valid_sources[0x7b]	367081	1			T1	3		T9	1		T30	1
valid_sources[0x7c]	361695	1			T1	5		T30	2		T47	12
valid_sources[0x7d]	370339	1			T1	5		T4	1		T6	3
valid_sources[0x7e]	352423	1			T1	5		T31	4		T47	4
valid_sources[0x7f]	377525	1			T1	2		T9	1		T30	2
valid_sources[0x80]	371457	1			T1	1		T9	2		T30	5

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

22651211

1

T1

296

T2

5

T3

12

values[0x0]

all_enables

biggest_size

5230970

1

T1

174

T2

1

T3

4

values[0x1]

all_enables

biggest_size

5173381

1

T1

108

T3

2

T4

58