Unified Coverage Report :: Module :: uart_csr_assert_fpv

Module : uart_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_uart_csr_assert_0/uart_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.uart_csr_assert	100.00						100.00

---

Module Instance : tb.dut.uart_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : uart_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	17370062	0	0
ctrl_rd_A	2147483647	248655	0	0
intr_enable_rd_A	2147483647	220934	0	0
ovrd_rd_A	2147483647	246592	0	0
timeout_ctrl_rd_A	2147483647	246167	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	17370062	0	0
T30	1952	157	0	0
T31	4098	0	0	0
T32	1270	1	0	0
T33	9616	4	0	0
T34	5338	205	0	0
T38	1375	0	0	0
T39	0	4	0	0
T42	0	111	0	0
T43	0	425	0	0
T47	25298	0	0	0
T48	1045	0	0	0
T49	990	0	0	0
T50	2418	0	0	0
T88	0	3	0	0
T108	0	2	0	0
T109	0	15	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	248655	0	0
T9	2795	83	0	0
T10	1169	0	0	0
T30	1952	0	0	0
T31	4098	0	0	0
T32	1270	0	0	0
T33	9616	334	0	0
T34	0	15	0	0
T38	1375	0	0	0
T39	0	372	0	0
T43	0	32	0	0
T47	25298	448	0	0
T48	1045	0	0	0
T49	990	0	0	0
T50	0	54	0	0
T57	0	41	0	0
T108	0	20	0	0
T110	0	47	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	220934	0	0
T9	2795	92	0	0
T10	1169	0	0	0
T30	1952	0	0	0
T31	4098	0	0	0
T32	1270	0	0	0
T33	9616	396	0	0
T34	0	14	0	0
T38	1375	0	0	0
T39	0	240	0	0
T47	25298	434	0	0
T48	1045	0	0	0
T49	990	0	0	0
T50	0	34	0	0
T97	0	10	0	0
T108	0	15	0	0
T111	0	15	0	0
T112	0	23	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	246592	0	0
T9	2795	98	0	0
T10	1169	0	0	0
T30	1952	0	0	0
T31	4098	0	0	0
T32	1270	0	0	0
T33	9616	116	0	0
T34	0	21	0	0
T38	1375	0	0	0
T39	0	117	0	0
T43	0	61	0	0
T47	25298	422	0	0
T48	1045	0	0	0
T49	990	0	0	0
T50	0	15	0	0
T57	0	5	0	0
T108	0	19	0	0
T110	0	32	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	246167	0	0
T9	2795	48	0	0
T10	1169	0	0	0
T30	1952	0	0	0
T31	4098	0	0	0
T32	1270	0	0	0
T33	9616	124	0	0
T34	0	17	0	0
T38	1375	0	0	0
T39	0	96	0	0
T43	0	11	0	0
T47	25298	499	0	0
T48	1045	0	0	0
T49	990	0	0	0
T50	0	25	0	0
T57	0	5	0	0
T108	0	14	0	0
T110	0	20	0	0