Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	66863341	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

31932047

1

T1

13

T2

15

T3

16

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	89105464	1			T1	11		T2	20		T3	20
values[0x0]	4577261	1			T1	3		T2	9		T3	11
values[0x1]	5112663	1			T1	8		T2	11		T3	9

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	47143228	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

51652160

1

T1

14

T2

20

T3

18

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	369845	1			T7	1		T10	5		T52	1
valid_sources[0x01]	622529	1			T10	1		T50	2		T51	1
valid_sources[0x02]	403787	1			T2	1		T7	1		T10	2
valid_sources[0x03]	384709	1			T5	1		T7	3		T9	8
valid_sources[0x04]	356939	1			T10	5		T49	8		T50	1
valid_sources[0x05]	395895	1			T10	3		T50	1		T56	1
valid_sources[0x06]	371247	1			T10	2		T31	48		T51	1
valid_sources[0x07]	444467	1			T7	1		T9	4		T10	6
valid_sources[0x08]	391688	1			T50	1		T56	1		T34	1
valid_sources[0x09]	387399	1			T8	1		T10	1		T31	2
valid_sources[0x0a]	381284	1			T7	3		T10	2		T56	1
valid_sources[0x0b]	363838	1			T10	5		T50	1		T51	1
valid_sources[0x0c]	397081	1			T10	8		T48	1		T34	5
valid_sources[0x0d]	367061	1			T10	5		T48	1		T35	1
valid_sources[0x0e]	348830	1			T10	4		T31	74		T55	1
valid_sources[0x0f]	403014	1			T10	5		T31	6		T49	2
valid_sources[0x10]	385252	1			T10	4		T50	1		T55	1
valid_sources[0x11]	356233	1			T7	1		T10	8		T50	2
valid_sources[0x12]	379361	1			T50	1		T52	1		T56	5
valid_sources[0x13]	363191	1			T8	2		T10	5		T50	1
valid_sources[0x14]	368781	1			T50	1		T55	2		T56	1
valid_sources[0x15]	447563	1			T10	4		T48	1		T50	2
valid_sources[0x16]	390847	1			T10	2		T50	2		T33	5
valid_sources[0x17]	379016	1			T8	2		T10	6		T48	1
valid_sources[0x18]	394495	1			T7	2		T10	4		T50	1
valid_sources[0x19]	499613	1			T10	7		T50	2		T33	2
valid_sources[0x1a]	416146	1			T9	2		T55	1		T34	1
valid_sources[0x1b]	365908	1			T10	3		T50	3		T52	1
valid_sources[0x1c]	374961	1			T10	4		T50	2		T52	1
valid_sources[0x1d]	359722	1			T2	1		T10	4		T50	2
valid_sources[0x1e]	366461	1			T2	2		T10	2		T50	3
valid_sources[0x1f]	379218	1			T10	7		T49	1		T50	1
valid_sources[0x20]	400597	1			T8	1		T10	1		T50	1
valid_sources[0x21]	360594	1			T7	3		T9	3		T10	8
valid_sources[0x22]	413952	1			T5	1		T10	2		T50	2
valid_sources[0x23]	392138	1			T10	1		T49	3		T57	5
valid_sources[0x24]	404324	1			T7	6		T10	2		T50	1
valid_sources[0x25]	360451	1			T1	2		T5	1		T50	1
valid_sources[0x26]	386383	1			T9	5		T10	1		T34	1
valid_sources[0x27]	380824	1			T10	2		T56	1		T34	4
valid_sources[0x28]	379804	1			T7	2		T10	1		T31	22
valid_sources[0x29]	372520	1			T10	2		T49	2		T50	3
valid_sources[0x2a]	378588	1			T50	2		T33	15		T57	4
valid_sources[0x2b]	354198	1			T6	19		T7	1		T10	1
valid_sources[0x2c]	350936	1			T7	1		T10	2		T50	1
valid_sources[0x2d]	380823	1			T10	1		T48	1		T55	1
valid_sources[0x2e]	387412	1			T10	1		T50	2		T34	2
valid_sources[0x2f]	407791	1			T10	3		T31	2		T50	2
valid_sources[0x30]	381804	1			T3	40		T10	1		T48	1
valid_sources[0x31]	389530	1			T2	1		T51	1		T34	3
valid_sources[0x32]	357086	1			T7	3		T10	2		T55	1
valid_sources[0x33]	368214	1			T7	1		T10	3		T50	1
valid_sources[0x34]	376650	1			T10	2		T31	1		T52	1
valid_sources[0x35]	387030	1			T31	6		T52	2		T55	2
valid_sources[0x36]	391739	1			T2	1		T7	2		T8	1
valid_sources[0x37]	369516	1			T8	4		T10	6		T50	2
valid_sources[0x38]	384484	1			T2	1		T7	3		T10	4
valid_sources[0x39]	426344	1			T34	1		T33	13		T57	4
valid_sources[0x3a]	388338	1			T9	22		T10	3		T48	1
valid_sources[0x3b]	375905	1			T10	1		T56	4		T34	4
valid_sources[0x3c]	403242	1			T2	1		T7	2		T10	2
valid_sources[0x3d]	388300	1			T10	10		T51	1		T55	2
valid_sources[0x3e]	388877	1			T2	1		T48	1		T49	8
valid_sources[0x3f]	368900	1			T4	2		T51	1		T55	1
valid_sources[0x40]	398640	1			T7	2		T50	1		T51	1
valid_sources[0x41]	376218	1			T7	3		T9	6		T10	8
valid_sources[0x42]	363137	1			T6	17		T9	5		T10	2
valid_sources[0x43]	380832	1			T10	5		T50	2		T34	1
valid_sources[0x44]	380866	1			T2	1		T8	1		T10	8
valid_sources[0x45]	353612	1			T10	5		T50	1		T52	3
valid_sources[0x46]	377607	1			T10	1		T50	1		T55	1
valid_sources[0x47]	367246	1			T7	1		T8	1		T10	1
valid_sources[0x48]	389999	1			T2	1		T10	2		T50	1
valid_sources[0x49]	431849	1			T10	2		T34	3		T33	1
valid_sources[0x4a]	371791	1			T10	10		T50	3		T52	1
valid_sources[0x4b]	365211	1			T9	5		T10	3		T31	58
valid_sources[0x4c]	414703	1			T10	1		T49	7		T50	1
valid_sources[0x4d]	375621	1			T7	2		T10	3		T49	4
valid_sources[0x4e]	365107	1			T7	2		T10	4		T31	3
valid_sources[0x4f]	387309	1			T49	3		T51	2		T52	2
valid_sources[0x50]	357382	1			T2	1		T7	2		T10	2
valid_sources[0x51]	395982	1			T8	1		T10	5		T50	1
valid_sources[0x52]	375901	1			T50	1		T55	1		T34	4
valid_sources[0x53]	382575	1			T10	1		T50	1		T34	4
valid_sources[0x54]	362794	1			T10	9		T50	2		T55	1
valid_sources[0x55]	382671	1			T10	4		T31	2		T50	1
valid_sources[0x56]	433008	1			T51	1		T55	1		T56	3
valid_sources[0x57]	442001	1			T10	3		T55	1		T56	1
valid_sources[0x58]	395100	1			T10	6		T51	1		T52	1
valid_sources[0x59]	386914	1			T2	1		T10	4		T50	2
valid_sources[0x5a]	429756	1			T10	3		T34	2		T33	2
valid_sources[0x5b]	365688	1			T8	1		T31	2		T49	2
valid_sources[0x5c]	376797	1			T7	4		T10	10		T50	1
valid_sources[0x5d]	403932	1			T4	3		T10	4		T34	2
valid_sources[0x5e]	358501	1			T10	5		T49	3		T50	2
valid_sources[0x5f]	388165	1			T5	1		T10	3		T34	2
valid_sources[0x60]	372153	1			T8	2		T10	2		T31	2
valid_sources[0x61]	369570	1			T9	7		T50	2		T56	3
valid_sources[0x62]	393979	1			T10	2		T50	2		T52	1
valid_sources[0x63]	364996	1			T2	1		T10	4		T55	1
valid_sources[0x64]	380777	1			T10	6		T31	5		T49	1
valid_sources[0x65]	361969	1			T10	3		T50	1		T51	1
valid_sources[0x66]	371986	1			T1	14		T10	1		T31	2
valid_sources[0x67]	354065	1			T8	1		T10	2		T31	16
valid_sources[0x68]	356123	1			T10	8		T48	1		T50	1
valid_sources[0x69]	357648	1			T8	1		T52	4		T34	1
valid_sources[0x6a]	383029	1			T4	4		T10	3		T31	4
valid_sources[0x6b]	452114	1			T10	2		T48	1		T34	3
valid_sources[0x6c]	552768	1			T8	1		T10	3		T48	1
valid_sources[0x6d]	396368	1			T5	3		T10	3		T50	1
valid_sources[0x6e]	380472	1			T8	1		T10	3		T31	18
valid_sources[0x6f]	445084	1			T10	1		T50	2		T52	1
valid_sources[0x70]	375941	1			T2	1		T55	2		T56	1
valid_sources[0x71]	401630	1			T7	3		T8	1		T9	7
valid_sources[0x72]	348980	1			T7	4		T10	2		T51	1
valid_sources[0x73]	380943	1			T10	6		T49	13		T50	1
valid_sources[0x74]	446405	1			T7	7		T10	1		T50	1
valid_sources[0x75]	396972	1			T50	1		T52	3		T35	2
valid_sources[0x76]	344772	1			T10	2		T52	2		T34	1
valid_sources[0x77]	367595	1			T7	1		T10	2		T51	2
valid_sources[0x78]	372285	1			T10	2		T50	3		T33	2
valid_sources[0x79]	380079	1			T10	3		T31	16		T48	1
valid_sources[0x7a]	358099	1			T10	2		T31	1		T49	2
valid_sources[0x7b]	339121	1			T9	34		T10	1		T31	5
valid_sources[0x7c]	366390	1			T10	5		T49	1		T50	2
valid_sources[0x7d]	360992	1			T10	5		T34	4		T57	3
valid_sources[0x7e]	363736	1			T8	1		T9	3		T10	1
valid_sources[0x7f]	346075	1			T2	1		T4	1		T10	3
valid_sources[0x80]	375456	1			T8	2		T10	3		T34	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

23383202

1

T1

7

T2

10

T3

9

values[0x0]

all_enables

biggest_size

4303646

1

T1

1

T2

5

T3

3

values[0x1]

all_enables

biggest_size

4245199

1

T1

5

T3

4

T4

1