Unified Coverage Report :: Module :: uart_core

Module : uart_core

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.59	100.00	99.06			96.72

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_uart_0.1/rtl/uart_core.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.uart_core	99.13	100.00	99.06			98.33

---

Module Instance : tb.dut.uart_core

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.13	100.00	99.06			98.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.07	100.00	96.96			99.32	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
intr_hw_rx_break_err	100.00	100.00	100.00			100.00	100.00
intr_hw_rx_frame_err	100.00	100.00	100.00			100.00	100.00
intr_hw_rx_overflow	100.00	100.00	100.00			100.00	100.00
intr_hw_rx_parity_err	100.00	100.00	100.00			100.00	100.00
intr_hw_rx_timeout	100.00	100.00	100.00			100.00	100.00
intr_hw_rx_watermark	100.00	100.00	100.00			100.00	100.00
intr_hw_tx_empty	100.00	100.00	100.00			100.00	100.00
intr_hw_tx_watermark	100.00	100.00	100.00			100.00	100.00
sync_rx	100.00	100.00				100.00
u_uart_rxfifo	96.15	100.00	84.62			100.00	100.00
u_uart_txfifo	96.15	100.00	84.62			100.00	100.00
uart_rx	100.00	100.00	100.00			100.00
uart_tx	100.00	100.00	100.00			100.00

Line Coverage for Module : uart_core

	Line No.	Total	Covered	Percent
TOTAL		105	105	100.00
CONT_ASSIGN	73	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	77	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
CONT_ASSIGN	95	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	105	4	4	100.00
ALWAYS	113	4	4	100.00
ALWAYS	122	7	7	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	142	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	152	1	1	100.00
ALWAYS	166	4	4	100.00
CONT_ASSIGN	173	1	1	100.00
CONT_ASSIGN	179	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
ALWAYS	215	7	7	100.00
ALWAYS	246	5	5	100.00
CONT_ASSIGN	255	1	1	100.00
CONT_ASSIGN	258	1	1	100.00
CONT_ASSIGN	260	1	1	100.00
CONT_ASSIGN	280	1	1	100.00
ALWAYS	302	4	4	100.00
ALWAYS	311	7	7	100.00
CONT_ASSIGN	322	1	1	100.00
CONT_ASSIGN	334	1	1	100.00
ALWAYS	337	7	7	100.00
ALWAYS	349	9	9	100.00
CONT_ASSIGN	362	1	1	100.00
CONT_ASSIGN	365	1	1	100.00
CONT_ASSIGN	366	1	1	100.00
CONT_ASSIGN	368	1	1	100.00
CONT_ASSIGN	370	1	1	100.00
CONT_ASSIGN	388	1	1	100.00
ALWAYS	391	5	5	100.00
CONT_ASSIGN	400	1	1	100.00
CONT_ASSIGN	401	1	1	100.00
CONT_ASSIGN	511	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_uart_0.1/rtl/uart_core.sv' or '../src/lowrisc_ip_uart_0.1/rtl/uart_core.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
73	1	1
74	1	1
75	1	1
76	1	1
77	1	1
79	1	1
80	1	1
81	1	1
82	1	1
84	1	1
85	1	1
94	1	1
95	1	1
98	1	1
105	2	2
106	2	2
			MISSING_ELSE
113	1	1
114	1	1
115	1	1
116	1	1
122	2	2
124	1	1
126	2	2
			MISSING_ELSE
130	2	2
			MISSING_ELSE
140	1	1
142	1	1
144	1	1
145	1	1
146	1	1
147	1	1
148	1	1
149	1	1
151	1	1
152	1	1
166	1	1
167	1	1
168	1	1
169	1	1
			MISSING_ELSE
173	1	1
179	1	1
213	1	1
215	1	1
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
222	1	1
246	1	1
247	1	1
248	1	1
250	1	1
251	1	1
255	1	1
258	1	1
260	1	1
280	1	1
302	2	2
303	2	2
			MISSING_ELSE
311	1	1
312	1	1
313	1	1
314	1	1
315	1	1
316	1	1
317	1	1
322	1	1
334	1	1
337	1	1
338	1	1
339	1	1
340	1	1
342	1	1
343	1	1
344	1	1
349	1	1
350	1	1
351	1	1
352	1	1
353	1	1
354	1	1
355	1	1
356	1	1
357	1	1
362	1	1
365	1	1
366	1	1
368	1	1
370	1	1
388	1	1
391	1	1
392	1	1
393	1	1
395	1	1
396	1	1
400	1	1
401	1	1
511	1	1

---

Cond Coverage for Module : uart_core

	Total	Covered	Percent
Conditions	106	105	99.06
Logical	106	105	99.06
Non-Logical	0	0
Event	0	0

 LINE       79
 EXPRESSION (reg2hw.fifo_ctrl.rxrst.q & reg2hw.fifo_ctrl.rxrst.qe)
             ------------1-----------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T13,T14,T15
1	1	Covered	T13,T14,T15

 LINE       80
 EXPRESSION (reg2hw.fifo_ctrl.txrst.q & reg2hw.fifo_ctrl.txrst.qe)
             ------------1-----------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T12,T13
1	1	Covered	T11,T12,T13

 LINE       94
 EXPRESSION (rx_valid & (((~event_rx_frame_err)) | (rx_fifo_data != 8'b0)))
             ----1---   -------------------------2------------------------

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T14,T26,T27
1	1	Covered	T11,T12,T13

 LINE       94
 SUB-EXPRESSION (((~event_rx_frame_err)) | (rx_fifo_data != 8'b0))
                 -----------1-----------   -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T14,T26,T27
0	1	Covered	T14,T15,T26
1	0	Covered	T11,T12,T13

 LINE       94
 SUB-EXPRESSION (rx_fifo_data != 8'b0)
                -----------1----------

-1-	Status	Tests
0	Covered	T11,T12,T13
1	Covered	T11,T12,T13

 LINE       95
 EXPRESSION (event_rx_frame_err & (rx_fifo_data == 8'b0))
             ---------1--------   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T14,T15,T26
1	1	Covered	T14,T26,T27

 LINE       95
 SUB-EXPRESSION (rx_fifo_data == 8'b0)
                -----------1----------

-1-	Status	Tests
0	Covered	T11,T12,T13
1	Covered	T11,T12,T13

 LINE       98
 EXPRESSION (((break_st_q == BRK_WAIT) || not_allzero_char) ? 5'b0 : (allzero_err ? ((allzero_cnt_q + 5'b1)) : allzero_cnt_q))
             -----------------------1----------------------

-1-	Status	Tests
0	Covered	T11,T12,T13
1	Covered	T11,T12,T13

 LINE       98
 SUB-EXPRESSION ((break_st_q == BRK_WAIT) || not_allzero_char)
                 ------------1-----------    --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T11,T12,T13
0	1	Covered	T11,T12,T13
1	0	Covered	T14,T26,T27

 LINE       98
 SUB-EXPRESSION (break_st_q == BRK_WAIT)
                ------------1-----------

-1-	Status	Tests
0	Covered	T11,T12,T13
1	Covered	T14,T26,T27

 LINE       98
 SUB-EXPRESSION (allzero_err ? ((allzero_cnt_q + 5'b1)) : allzero_cnt_q)
                 -----1-----

-1-	Status	Tests
0	Covered	T11,T12,T13
1	Covered	T14,T26,T27

 LINE       146
 EXPRESSION (tx_uart_idle & ((~tx_fifo_rvalid)))
             ------1-----   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T12,T13
1	1	Covered	T11,T12,T13

 LINE       168
 EXPRESSION (tx_enable || rx_enable)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T11,T12,T13
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T13,T16

 LINE       179
 EXPRESSION (tx_uart_idle & tx_fifo_rvalid & tx_enable)
             ------1-----   -------2------   ----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T11,T12,T13
1	0	1	Covered	T11,T12,T13
1	1	0	Covered	T11,T12,T13
1	1	1	Covered	T11,T12,T13

 LINE       200
 EXPRESSION (((^tx_fifo_data)) ^ reg2hw.ctrl.parity_odd.q)
             --------1--------   ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T11,T12,T13
0	1	Covered	T11,T13,T14
1	0	Covered	T11,T12,T13
1	1	Covered	T12,T13,T16

 LINE       213
 EXPRESSION (line_loopback ? rx : tx_out_q)
             ------1------

-1-	Status	Tests
0	Covered	T11,T12,T13
1	Covered	T19,T21,T28

 LINE       255
 EXPRESSION ((rx_sync & rx_sync_q1) | (rx_sync & rx_sync_q2) | (rx_sync_q1 & rx_sync_q2))
             -----------1----------   -----------2----------   ------------3------------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T11,T12,T13
0	0	1	Covered	T11,T12,T13
0	1	0	Covered	T11,T12,T13
1	0	0	Covered	T11,T12,T13

 LINE       255
 SUB-EXPRESSION (rx_sync & rx_sync_q1)
                 ---1---   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T12,T13
1	1	Covered	T11,T12,T13

 LINE       255
 SUB-EXPRESSION (rx_sync & rx_sync_q2)
                 ---1---   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T12,T13
1	1	Covered	T11,T12,T13

 LINE       255
 SUB-EXPRESSION (rx_sync_q1 & rx_sync_q2)
                 -----1----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T12,T13
1	1	Covered	T11,T12,T13

 LINE       258
 EXPRESSION (rxnf_enable ? rx_in_maj : rx_sync)
             -----1-----

-1-	Status	Tests
0	Covered	T11,T12,T13
1	Covered	T11,T12,T13

 LINE       260
 EXPRESSION (sys_loopback ? tx_out : (line_loopback ? 1'b1 : rx_in_mx))
             ------1-----

-1-	Status	Tests
0	Covered	T11,T12,T13
1	Covered	T19,T21,T28

 LINE       260
 SUB-EXPRESSION (line_loopback ? 1'b1 : rx_in_mx)
                 ------1------

-1-	Status	Tests
0	Covered	T11,T12,T13
1	Covered	T19,T21,T28

 LINE       280
 EXPRESSION (rx_valid & ((~event_rx_frame_err)) & ((~event_rx_parity_err)))
             ----1---   -----------2-----------   ------------3-----------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T11,T12,T13
1	0	1	Covered	T14,T15,T26
1	1	0	Covered	T11,T12,T14
1	1	1	Covered	T11,T12,T13

 LINE       322
 EXPRESSION (tx_watermark_d & ((~tx_watermark_prev_q)))
             -------1------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T12,T13
1	1	Covered	T11,T12,T13

 LINE       334
 EXPRESSION (((~tx_fifo_rvalid)) & ((~tx_uart_idle_q)) & tx_uart_idle)
             ---------1---------   ---------2---------   ------3-----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T11,T12,T13
1	0	1	Covered	T11,T12,T13
1	1	0	Covered	T11,T12,T13
1	1	1	Covered	T11,T12,T13

 LINE       362
 EXPRESSION (rx_watermark_d & ((~rx_watermark_prev_q)))
             -------1------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T12,T13
1	1	Covered	T11,T12,T13

 LINE       368
 EXPRESSION (rx_fifo_depth != rx_fifo_depth_prev_q)
            -------------------1-------------------

-1-	Status	Tests
0	Covered	T11,T12,T13
1	Covered	T11,T12,T13

 LINE       370
 EXPRESSION 
 Number  Term
      1  (uart_rxto_en == 1'b0) ? 24'b0 : (event_rx_timeout ? 24'b0 : (rx_fifo_depth_changed ? 24'b0 : ((rx_fifo_depth == '0) ? 24'b0 : (rx_tick_baud ? ((rx_timeout_count_q + 24'b1)) : rx_timeout_count_q)))))

-1-	Status	Tests
0	Covered	T11,T12,T13
1	Covered	T11,T12,T13

 LINE       370
 SUB-EXPRESSION (uart_rxto_en == 1'b0)
                -----------1----------

-1-	Status	Tests
0	Covered	T11,T12,T13
1	Covered	T11,T12,T13

 LINE       370
 SUB-EXPRESSION 
 Number  Term
      1  event_rx_timeout ? 24'b0 : (rx_fifo_depth_changed ? 24'b0 : ((rx_fifo_depth == '0) ? 24'b0 : (rx_tick_baud ? ((rx_timeout_count_q + 24'b1)) : rx_timeout_count_q))))

-1-	Status	Tests
0	Covered	T11,T12,T13
1	Covered	T11,T14,T16

 LINE       370
 SUB-EXPRESSION (rx_fifo_depth_changed ? 24'b0 : ((rx_fifo_depth == '0) ? 24'b0 : (rx_tick_baud ? ((rx_timeout_count_q + 24'b1)) : rx_timeout_count_q)))
                 ----------1----------

-1-	Status	Tests
0	Covered	T11,T12,T13
1	Covered	T11,T12,T13

 LINE       370
 SUB-EXPRESSION ((rx_fifo_depth == '0) ? 24'b0 : (rx_tick_baud ? ((rx_timeout_count_q + 24'b1)) : rx_timeout_count_q))
                 ----------1----------

-1-	Status	Tests
0	Covered	T11,T12,T13
1	Covered	T11,T12,T13

 LINE       370
 SUB-EXPRESSION (rx_fifo_depth == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T11,T12,T13
1	Covered	T11,T12,T13

 LINE       370
 SUB-EXPRESSION (rx_tick_baud ? ((rx_timeout_count_q + 24'b1)) : rx_timeout_count_q)
                 ------1-----

-1-	Status	Tests
0	Covered	T11,T12,T13
1	Covered	T11,T12,T13

 LINE       388
 EXPRESSION ((rx_timeout_count_q == uart_rxto_val) & uart_rxto_en)
             ------------------1------------------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T12,T13
1	1	Covered	T11,T14,T16

 LINE       388
 SUB-EXPRESSION (rx_timeout_count_q == uart_rxto_val)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T11,T12,T13
1	Covered	T11,T12,T13

 LINE       400
 EXPRESSION (rx_fifo_wvalid & ((~rx_fifo_wready)))
             -------1------   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T12,T13
1	1	Covered	T14,T15,T25

 LINE       401
 EXPRESSION (break_err & (break_st_q == BRK_CHK))
             ----1----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Not Covered
1	1	Covered	T14,T26,T27

 LINE       401
 SUB-EXPRESSION (break_st_q == BRK_CHK)
                -----------1-----------

-1-	Status	Tests
0	Covered	T11,T12,T13
1	Covered	T11,T12,T13

---

Branch Coverage for Module : uart_core

	Line No.	Total	Covered	Percent
Branches		61	59	96.72
TERNARY	98	3	3	100.00
TERNARY	213	2	2	100.00
TERNARY	258	2	2	100.00
TERNARY	260	3	3	100.00
TERNARY	370	6	6	100.00
IF	105	3	3	100.00
CASE	113	4	4	100.00
IF	122	6	5	83.33
IF	166	3	3	100.00
IF	215	4	4	100.00
IF	246	2	2	100.00
IF	302	3	3	100.00
CASE	311	7	7	100.00
IF	337	2	2	100.00
CASE	349	9	8	88.89
IF	391	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_uart_0.1/rtl/uart_core.sv' or '../src/lowrisc_ip_uart_0.1/rtl/uart_core.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	98	(((break_st_q == BRK_WAIT) || not_allzero_char)) ? 
-2-:	98	(allzero_err) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T11,T12,T13
0	1	Covered	T14,T26,T27
0	0	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	213	(line_loopback) ? 

Branches:

-1-	Status	Tests
1	Covered	T19,T21,T28
0	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	258	(rxnf_enable) ? 

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	260	(sys_loopback) ? 
-2-:	260	(line_loopback) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T19,T21,T28
0	1	Covered	T19,T21,T28
0	0	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	370	((uart_rxto_en == 1'b0)) ? 
-2-:	370	(event_rx_timeout) ? 
-3-:	370	(rx_fifo_depth_changed) ? 
-4-:	370	((rx_fifo_depth == '0)) ? 
-5-:	370	(rx_tick_baud) ? 

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T11,T12,T13
0	1	-	-	-	Covered	T11,T14,T16
0	0	1	-	-	Covered	T11,T12,T13
0	0	0	1	-	Covered	T11,T12,T13
0	0	0	0	1	Covered	T11,T12,T13
0	0	0	0	0	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	105	if ((!rst_ni))
-2-:	106	if (rx_enable)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T11,T12,T13
0	1	Covered	T11,T12,T13
0	0	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	113	case (reg2hw.ctrl.rxblvl.q)

Branches:

-1-	Status	Tests
2'h0	Covered	T11,T12,T13
2'h1	Covered	T11,T12,T13
2'h2	Covered	T11,T12,T13
default	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	122	if ((!rst_ni))
-2-:	124	case (break_st_q)
-3-:	126	if (event_rx_break_err)
-4-:	130	if (rx_in)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T11,T12,T13
0	BRK_CHK	1	-	Covered	T14,T26,T27
0	BRK_CHK	0	-	Covered	T11,T12,T13
0	BRK_WAIT	-	1	Covered	T14,T26,T27
0	BRK_WAIT	-	0	Covered	T14,T26,T27
0	default	-	-	Not Covered

	LineNo.	Expression
-1-:	166	if ((!rst_ni))
-2-:	168	if ((tx_enable || rx_enable))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T11,T12,T13
0	1	Covered	T11,T12,T13
0	0	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	215	if ((!rst_ni))
-2-:	217	if (ovrd_tx_en)
-3-:	219	if (sys_loopback)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T11,T12,T13
0	1	-	Covered	T22,T29,T30
0	0	1	Covered	T19,T21,T28
0	0	0	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	246	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	302	if ((!rst_ni))
-2-:	303	if (tick_baud_x16)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T11,T12,T13
0	1	Covered	T11,T12,T13
0	0	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	311	case (uart_fifo_txilvl)

Branches:

-1-	Status	Tests
3'h0	Covered	T11,T12,T13
3'h1	Covered	T12,T13,T14
3'h2	Covered	T11,T12,T17
3'h3	Covered	T11,T14,T16
3'h4	Covered	T11,T13,T19
3'h5	Covered	T11,T12,T14
default	Covered	T13,T14,T16

	LineNo.	Expression
-1-:	337	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	349	case (uart_fifo_rxilvl)

Branches:

-1-	Status	Tests
3'h0	Covered	T11,T12,T13
3'h1	Covered	T11,T12,T13
3'h2	Covered	T11,T12,T13
3'h3	Covered	T12,T13,T14
3'h4	Covered	T12,T17,T19
3'h5	Covered	T11,T13,T16
3'h6	Covered	T13,T14,T16
3'h7	Covered	T11,T12,T15
default	Not Covered

	LineNo.	Expression
-1-:	391	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T11,T12,T13

Line Coverage for Instance : tb.dut.uart_core

	Line No.	Total	Covered	Percent
TOTAL		105	105	100.00
CONT_ASSIGN	73	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	77	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
CONT_ASSIGN	95	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	105	4	4	100.00
ALWAYS	113	4	4	100.00
ALWAYS	122	7	7	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	142	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	152	1	1	100.00
ALWAYS	166	4	4	100.00
CONT_ASSIGN	173	1	1	100.00
CONT_ASSIGN	179	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
ALWAYS	215	7	7	100.00
ALWAYS	246	5	5	100.00
CONT_ASSIGN	255	1	1	100.00
CONT_ASSIGN	258	1	1	100.00
CONT_ASSIGN	260	1	1	100.00
CONT_ASSIGN	280	1	1	100.00
ALWAYS	302	4	4	100.00
ALWAYS	311	7	7	100.00
CONT_ASSIGN	322	1	1	100.00
CONT_ASSIGN	334	1	1	100.00
ALWAYS	337	7	7	100.00
ALWAYS	349	9	9	100.00
CONT_ASSIGN	362	1	1	100.00
CONT_ASSIGN	365	1	1	100.00
CONT_ASSIGN	366	1	1	100.00
CONT_ASSIGN	368	1	1	100.00
CONT_ASSIGN	370	1	1	100.00
CONT_ASSIGN	388	1	1	100.00
ALWAYS	391	5	5	100.00
CONT_ASSIGN	400	1	1	100.00
CONT_ASSIGN	401	1	1	100.00
CONT_ASSIGN	511	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_uart_0.1/rtl/uart_core.sv' or '../src/lowrisc_ip_uart_0.1/rtl/uart_core.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
73	1	1
74	1	1
75	1	1
76	1	1
77	1	1
79	1	1
80	1	1
81	1	1
82	1	1
84	1	1
85	1	1
94	1	1
95	1	1
98	1	1
105	2	2
106	2	2
			MISSING_ELSE
113	1	1
114	1	1
115	1	1
116	1	1
122	2	2
124	1	1
126	2	2
			MISSING_ELSE
130	2	2
			MISSING_ELSE
140	1	1
142	1	1
144	1	1
145	1	1
146	1	1
147	1	1
148	1	1
149	1	1
151	1	1
152	1	1
166	1	1
167	1	1
168	1	1
169	1	1
			MISSING_ELSE
173	1	1
179	1	1
213	1	1
215	1	1
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
222	1	1
246	1	1
247	1	1
248	1	1
250	1	1
251	1	1
255	1	1
258	1	1
260	1	1
280	1	1
302	2	2
303	2	2
			MISSING_ELSE
311	1	1
312	1	1
313	1	1
314	1	1
315	1	1
316	1	1
317	1	1
322	1	1
334	1	1
337	1	1
338	1	1
339	1	1
340	1	1
342	1	1
343	1	1
344	1	1
349	1	1
350	1	1
351	1	1
352	1	1
353	1	1
354	1	1
355	1	1
356	1	1
357	1	1
362	1	1
365	1	1
366	1	1
368	1	1
370	1	1
388	1	1
391	1	1
392	1	1
393	1	1
395	1	1
396	1	1
400	1	1
401	1	1
511	1	1

---

Cond Coverage for Instance : tb.dut.uart_core

	Total	Covered	Percent
Conditions	106	105	99.06
Logical	106	105	99.06
Non-Logical	0	0
Event	0	0

 LINE       79
 EXPRESSION (reg2hw.fifo_ctrl.rxrst.q & reg2hw.fifo_ctrl.rxrst.qe)
             ------------1-----------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T13,T14,T15
1	1	Covered	T13,T14,T15

 LINE       80
 EXPRESSION (reg2hw.fifo_ctrl.txrst.q & reg2hw.fifo_ctrl.txrst.qe)
             ------------1-----------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T12,T13
1	1	Covered	T11,T12,T13

 LINE       94
 EXPRESSION (rx_valid & (((~event_rx_frame_err)) | (rx_fifo_data != 8'b0)))
             ----1---   -------------------------2------------------------

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T14,T26,T27
1	1	Covered	T11,T12,T13

 LINE       94
 SUB-EXPRESSION (((~event_rx_frame_err)) | (rx_fifo_data != 8'b0))
                 -----------1-----------   -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T14,T26,T27
0	1	Covered	T14,T15,T26
1	0	Covered	T11,T12,T13

 LINE       94
 SUB-EXPRESSION (rx_fifo_data != 8'b0)
                -----------1----------

-1-	Status	Tests
0	Covered	T11,T12,T13
1	Covered	T11,T12,T13

 LINE       95
 EXPRESSION (event_rx_frame_err & (rx_fifo_data == 8'b0))
             ---------1--------   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T14,T15,T26
1	1	Covered	T14,T26,T27

 LINE       95
 SUB-EXPRESSION (rx_fifo_data == 8'b0)
                -----------1----------

-1-	Status	Tests
0	Covered	T11,T12,T13
1	Covered	T11,T12,T13

 LINE       98
 EXPRESSION (((break_st_q == BRK_WAIT) || not_allzero_char) ? 5'b0 : (allzero_err ? ((allzero_cnt_q + 5'b1)) : allzero_cnt_q))
             -----------------------1----------------------

-1-	Status	Tests
0	Covered	T11,T12,T13
1	Covered	T11,T12,T13

 LINE       98
 SUB-EXPRESSION ((break_st_q == BRK_WAIT) || not_allzero_char)
                 ------------1-----------    --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T11,T12,T13
0	1	Covered	T11,T12,T13
1	0	Covered	T14,T26,T27

 LINE       98
 SUB-EXPRESSION (break_st_q == BRK_WAIT)
                ------------1-----------

-1-	Status	Tests
0	Covered	T11,T12,T13
1	Covered	T14,T26,T27

 LINE       98
 SUB-EXPRESSION (allzero_err ? ((allzero_cnt_q + 5'b1)) : allzero_cnt_q)
                 -----1-----

-1-	Status	Tests
0	Covered	T11,T12,T13
1	Covered	T14,T26,T27

 LINE       146
 EXPRESSION (tx_uart_idle & ((~tx_fifo_rvalid)))
             ------1-----   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T12,T13
1	1	Covered	T11,T12,T13

 LINE       168
 EXPRESSION (tx_enable || rx_enable)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T11,T12,T13
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T13,T16

 LINE       179
 EXPRESSION (tx_uart_idle & tx_fifo_rvalid & tx_enable)
             ------1-----   -------2------   ----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T11,T12,T13
1	0	1	Covered	T11,T12,T13
1	1	0	Covered	T11,T12,T13
1	1	1	Covered	T11,T12,T13

 LINE       200
 EXPRESSION (((^tx_fifo_data)) ^ reg2hw.ctrl.parity_odd.q)
             --------1--------   ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T11,T12,T13
0	1	Covered	T11,T13,T14
1	0	Covered	T11,T12,T13
1	1	Covered	T12,T13,T16

 LINE       213
 EXPRESSION (line_loopback ? rx : tx_out_q)
             ------1------

-1-	Status	Tests
0	Covered	T11,T12,T13
1	Covered	T19,T21,T28

 LINE       255
 EXPRESSION ((rx_sync & rx_sync_q1) | (rx_sync & rx_sync_q2) | (rx_sync_q1 & rx_sync_q2))
             -----------1----------   -----------2----------   ------------3------------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T11,T12,T13
0	0	1	Covered	T11,T12,T13
0	1	0	Covered	T11,T12,T13
1	0	0	Covered	T11,T12,T13

 LINE       255
 SUB-EXPRESSION (rx_sync & rx_sync_q1)
                 ---1---   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T12,T13
1	1	Covered	T11,T12,T13

 LINE       255
 SUB-EXPRESSION (rx_sync & rx_sync_q2)
                 ---1---   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T12,T13
1	1	Covered	T11,T12,T13

 LINE       255
 SUB-EXPRESSION (rx_sync_q1 & rx_sync_q2)
                 -----1----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T12,T13
1	1	Covered	T11,T12,T13

 LINE       258
 EXPRESSION (rxnf_enable ? rx_in_maj : rx_sync)
             -----1-----

-1-	Status	Tests
0	Covered	T11,T12,T13
1	Covered	T11,T12,T13

 LINE       260
 EXPRESSION (sys_loopback ? tx_out : (line_loopback ? 1'b1 : rx_in_mx))
             ------1-----

-1-	Status	Tests
0	Covered	T11,T12,T13
1	Covered	T19,T21,T28

 LINE       260
 SUB-EXPRESSION (line_loopback ? 1'b1 : rx_in_mx)
                 ------1------

-1-	Status	Tests
0	Covered	T11,T12,T13
1	Covered	T19,T21,T28

 LINE       280
 EXPRESSION (rx_valid & ((~event_rx_frame_err)) & ((~event_rx_parity_err)))
             ----1---   -----------2-----------   ------------3-----------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T11,T12,T13
1	0	1	Covered	T14,T15,T26
1	1	0	Covered	T11,T12,T14
1	1	1	Covered	T11,T12,T13

 LINE       322
 EXPRESSION (tx_watermark_d & ((~tx_watermark_prev_q)))
             -------1------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T12,T13
1	1	Covered	T11,T12,T13

 LINE       334
 EXPRESSION (((~tx_fifo_rvalid)) & ((~tx_uart_idle_q)) & tx_uart_idle)
             ---------1---------   ---------2---------   ------3-----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T11,T12,T13
1	0	1	Covered	T11,T12,T13
1	1	0	Covered	T11,T12,T13
1	1	1	Covered	T11,T12,T13

 LINE       362
 EXPRESSION (rx_watermark_d & ((~rx_watermark_prev_q)))
             -------1------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T12,T13
1	1	Covered	T11,T12,T13

 LINE       368
 EXPRESSION (rx_fifo_depth != rx_fifo_depth_prev_q)
            -------------------1-------------------

-1-	Status	Tests
0	Covered	T11,T12,T13
1	Covered	T11,T12,T13

 LINE       370
 EXPRESSION 
 Number  Term
      1  (uart_rxto_en == 1'b0) ? 24'b0 : (event_rx_timeout ? 24'b0 : (rx_fifo_depth_changed ? 24'b0 : ((rx_fifo_depth == '0) ? 24'b0 : (rx_tick_baud ? ((rx_timeout_count_q + 24'b1)) : rx_timeout_count_q)))))

-1-	Status	Tests
0	Covered	T11,T12,T13
1	Covered	T11,T12,T13

 LINE       370
 SUB-EXPRESSION (uart_rxto_en == 1'b0)
                -----------1----------

-1-	Status	Tests
0	Covered	T11,T12,T13
1	Covered	T11,T12,T13

 LINE       370
 SUB-EXPRESSION 
 Number  Term
      1  event_rx_timeout ? 24'b0 : (rx_fifo_depth_changed ? 24'b0 : ((rx_fifo_depth == '0) ? 24'b0 : (rx_tick_baud ? ((rx_timeout_count_q + 24'b1)) : rx_timeout_count_q))))

-1-	Status	Tests
0	Covered	T11,T12,T13
1	Covered	T11,T14,T16

 LINE       370
 SUB-EXPRESSION (rx_fifo_depth_changed ? 24'b0 : ((rx_fifo_depth == '0) ? 24'b0 : (rx_tick_baud ? ((rx_timeout_count_q + 24'b1)) : rx_timeout_count_q)))
                 ----------1----------

-1-	Status	Tests
0	Covered	T11,T12,T13
1	Covered	T11,T12,T13

 LINE       370
 SUB-EXPRESSION ((rx_fifo_depth == '0) ? 24'b0 : (rx_tick_baud ? ((rx_timeout_count_q + 24'b1)) : rx_timeout_count_q))
                 ----------1----------

-1-	Status	Tests
0	Covered	T11,T12,T13
1	Covered	T11,T12,T13

 LINE       370
 SUB-EXPRESSION (rx_fifo_depth == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T11,T12,T13
1	Covered	T11,T12,T13

 LINE       370
 SUB-EXPRESSION (rx_tick_baud ? ((rx_timeout_count_q + 24'b1)) : rx_timeout_count_q)
                 ------1-----

-1-	Status	Tests
0	Covered	T11,T12,T13
1	Covered	T11,T12,T13

 LINE       388
 EXPRESSION ((rx_timeout_count_q == uart_rxto_val) & uart_rxto_en)
             ------------------1------------------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T12,T13
1	1	Covered	T11,T14,T16

 LINE       388
 SUB-EXPRESSION (rx_timeout_count_q == uart_rxto_val)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T11,T12,T13
1	Covered	T11,T12,T13

 LINE       400
 EXPRESSION (rx_fifo_wvalid & ((~rx_fifo_wready)))
             -------1------   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T12,T13
1	1	Covered	T14,T15,T25

 LINE       401
 EXPRESSION (break_err & (break_st_q == BRK_CHK))
             ----1----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Not Covered
1	1	Covered	T14,T26,T27

 LINE       401
 SUB-EXPRESSION (break_st_q == BRK_CHK)
                -----------1-----------

-1-	Status	Tests
0	Covered	T11,T12,T13
1	Covered	T11,T12,T13

---

Branch Coverage for Instance : tb.dut.uart_core

	Line No.	Total	Covered	Percent
Branches		60	59	98.33
TERNARY	98	3	3	100.00
TERNARY	213	2	2	100.00
TERNARY	258	2	2	100.00
TERNARY	260	3	3	100.00
TERNARY	370	6	6	100.00
IF	105	3	3	100.00
CASE	113	4	4	100.00
IF	122	5	5	100.00
IF	166	3	3	100.00
IF	215	4	4	100.00
IF	246	2	2	100.00
IF	302	3	3	100.00
CASE	311	7	7	100.00
IF	337	2	2	100.00
CASE	349	9	8	88.89
IF	391	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_uart_0.1/rtl/uart_core.sv' or '../src/lowrisc_ip_uart_0.1/rtl/uart_core.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	98	(((break_st_q == BRK_WAIT) || not_allzero_char)) ? 
-2-:	98	(allzero_err) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T11,T12,T13
0	1	Covered	T14,T26,T27
0	0	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	213	(line_loopback) ? 

Branches:

-1-	Status	Tests
1	Covered	T19,T21,T28
0	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	258	(rxnf_enable) ? 

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	260	(sys_loopback) ? 
-2-:	260	(line_loopback) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T19,T21,T28
0	1	Covered	T19,T21,T28
0	0	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	370	((uart_rxto_en == 1'b0)) ? 
-2-:	370	(event_rx_timeout) ? 
-3-:	370	(rx_fifo_depth_changed) ? 
-4-:	370	((rx_fifo_depth == '0)) ? 
-5-:	370	(rx_tick_baud) ? 

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T11,T12,T13
0	1	-	-	-	Covered	T11,T14,T16
0	0	1	-	-	Covered	T11,T12,T13
0	0	0	1	-	Covered	T11,T12,T13
0	0	0	0	1	Covered	T11,T12,T13
0	0	0	0	0	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	105	if ((!rst_ni))
-2-:	106	if (rx_enable)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T11,T12,T13
0	1	Covered	T11,T12,T13
0	0	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	113	case (reg2hw.ctrl.rxblvl.q)

Branches:

-1-	Status	Tests
2'h0	Covered	T11,T12,T13
2'h1	Covered	T11,T12,T13
2'h2	Covered	T11,T12,T13
default	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	122	if ((!rst_ni))
-2-:	124	case (break_st_q)
-3-:	126	if (event_rx_break_err)
-4-:	130	if (rx_in)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T11,T12,T13
0	BRK_CHK	1	-	Covered	T14,T26,T27
0	BRK_CHK	0	-	Covered	T11,T12,T13
0	BRK_WAIT	-	1	Covered	T14,T26,T27
0	BRK_WAIT	-	0	Covered	T14,T26,T27
0	default	-	-	Excluded

	LineNo.	Expression
-1-:	166	if ((!rst_ni))
-2-:	168	if ((tx_enable || rx_enable))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T11,T12,T13
0	1	Covered	T11,T12,T13
0	0	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	215	if ((!rst_ni))
-2-:	217	if (ovrd_tx_en)
-3-:	219	if (sys_loopback)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T11,T12,T13
0	1	-	Covered	T22,T29,T30
0	0	1	Covered	T19,T21,T28
0	0	0	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	246	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	302	if ((!rst_ni))
-2-:	303	if (tick_baud_x16)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T11,T12,T13
0	1	Covered	T11,T12,T13
0	0	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	311	case (uart_fifo_txilvl)

Branches:

-1-	Status	Tests
3'h0	Covered	T11,T12,T13
3'h1	Covered	T12,T13,T14
3'h2	Covered	T11,T12,T17
3'h3	Covered	T11,T14,T16
3'h4	Covered	T11,T13,T19
3'h5	Covered	T11,T12,T14
default	Covered	T13,T14,T16

	LineNo.	Expression
-1-:	337	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	349	case (uart_fifo_rxilvl)

Branches:

-1-	Status	Tests
3'h0	Covered	T11,T12,T13
3'h1	Covered	T11,T12,T13
3'h2	Covered	T11,T12,T13
3'h3	Covered	T12,T13,T14
3'h4	Covered	T12,T17,T19
3'h5	Covered	T11,T13,T16
3'h6	Covered	T13,T14,T16
3'h7	Covered	T11,T12,T15
default	Not Covered

	LineNo.	Expression
-1-:	391	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T11,T12,T13