Unified Coverage Report :: Module :: uart_csr_assert_fpv

Module : uart_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_uart_csr_assert_0/uart_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.uart_csr_assert	100.00						100.00

---

Module Instance : tb.dut.uart_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : uart_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	14256362	0	0
ctrl_rd_A	2147483647	190262	0	0
intr_enable_rd_A	2147483647	167935	0	0
ovrd_rd_A	2147483647	187219	0	0
timeout_ctrl_rd_A	2147483647	185766	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	14256362	0	0
T10	10634	587	0	0
T31	25267	6	0	0
T32	1294	54	0	0
T33	0	691	0	0
T34	0	7	0	0
T35	1230	0	0	0
T38	0	1	0	0
T39	0	341	0	0
T47	860	0	0	0
T48	885	0	0	0
T49	1403	0	0	0
T50	1266	0	0	0
T51	807	0	0	0
T52	1739	0	0	0
T53	0	3	0	0
T65	0	8	0	0
T105	0	5	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	190262	0	0
T9	2943	19	0	0
T10	10634	0	0	0
T31	25267	385	0	0
T32	1294	0	0	0
T34	0	173	0	0
T47	860	0	0	0
T48	885	0	0	0
T49	1403	0	0	0
T50	1266	0	0	0
T51	807	0	0	0
T52	1739	29	0	0
T55	0	8	0	0
T57	0	222	0	0
T58	0	31	0	0
T65	0	12	0	0
T77	0	26	0	0
T79	0	59	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	167935	0	0
T1	1153	3	0	0
T2	1015	0	0	0
T3	777	0	0	0
T4	1296	0	0	0
T5	688	0	0	0
T6	818	0	0	0
T7	1672	0	0	0
T8	1116	0	0	0
T9	2943	48	0	0
T10	10634	0	0	0
T31	0	271	0	0
T34	0	163	0	0
T52	0	54	0	0
T55	0	26	0	0
T57	0	200	0	0
T63	0	13	0	0
T64	0	23	0	0
T65	0	6	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	187219	0	0
T9	2943	43	0	0
T10	10634	0	0	0
T31	25267	97	0	0
T32	1294	0	0	0
T34	0	54	0	0
T47	860	0	0	0
T48	885	0	0	0
T49	1403	0	0	0
T50	1266	0	0	0
T51	807	0	0	0
T52	1739	27	0	0
T55	0	33	0	0
T57	0	200	0	0
T58	0	4	0	0
T65	0	6	0	0
T79	0	23	0	0
T105	0	19	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	185766	0	0
T9	2943	17	0	0
T10	10634	0	0	0
T31	25267	131	0	0
T32	1294	0	0	0
T34	0	62	0	0
T47	860	0	0	0
T48	885	0	0	0
T49	1403	0	0	0
T50	1266	0	0	0
T51	807	0	0	0
T52	1739	36	0	0
T55	0	14	0	0
T57	0	225	0	0
T58	0	2	0	0
T65	0	6	0	0
T77	0	4	0	0
T79	0	24	0	0