Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	61246390	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

25553442

1

T1

694

T2

48

T3

252

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	79462085	1			T1	1296		T2	16		T3	498
values[0x0]	3470630	1			T1	227		T2	73		T3	114
values[0x1]	3867117	1			T1	228		T2	68		T3	132

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	42937495	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

43862337

1

T1

888

T2

61

T3

359

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	311337	1			T1	8		T4	2		T5	14
valid_sources[0x01]	375053	1			T1	4		T3	3		T4	2
valid_sources[0x02]	325974	1			T1	5		T3	2		T5	17
valid_sources[0x03]	349607	1			T1	8		T3	3		T5	24
valid_sources[0x04]	384953	1			T3	2		T5	12		T7	3
valid_sources[0x05]	325663	1			T1	9		T3	5		T4	3
valid_sources[0x06]	409807	1			T1	3		T3	8		T4	1
valid_sources[0x07]	320966	1			T1	6		T3	5		T4	2
valid_sources[0x08]	324430	1			T1	12		T3	2		T5	26
valid_sources[0x09]	327354	1			T1	5		T3	5		T4	1
valid_sources[0x0a]	323025	1			T1	5		T3	2		T4	1
valid_sources[0x0b]	338430	1			T1	8		T3	6		T5	16
valid_sources[0x0c]	318088	1			T1	8		T3	2		T4	5
valid_sources[0x0d]	316785	1			T1	2		T3	2		T5	18
valid_sources[0x0e]	323626	1			T1	7		T3	2		T4	1
valid_sources[0x0f]	390558	1			T1	5		T3	6		T4	7
valid_sources[0x10]	316343	1			T1	4		T3	3		T5	27
valid_sources[0x11]	348043	1			T1	7		T3	10		T5	17
valid_sources[0x12]	330612	1			T1	2		T3	3		T4	2
valid_sources[0x13]	392352	1			T1	10		T3	2		T4	1
valid_sources[0x14]	344769	1			T1	2		T3	3		T4	3
valid_sources[0x15]	320367	1			T1	9		T4	8		T5	18
valid_sources[0x16]	326541	1			T1	6		T3	4		T4	3
valid_sources[0x17]	359966	1			T1	3		T3	2		T4	3
valid_sources[0x18]	338179	1			T1	4		T3	2		T4	7
valid_sources[0x19]	334853	1			T1	12		T3	3		T5	19
valid_sources[0x1a]	355693	1			T1	9		T3	5		T5	17
valid_sources[0x1b]	324575	1			T1	8		T3	1		T5	19
valid_sources[0x1c]	359065	1			T1	5		T3	4		T5	10
valid_sources[0x1d]	337437	1			T1	6		T3	8		T5	24
valid_sources[0x1e]	307407	1			T1	8		T3	3		T5	14
valid_sources[0x1f]	320684	1			T1	6		T3	4		T5	13
valid_sources[0x20]	331428	1			T1	6		T3	6		T5	12
valid_sources[0x21]	311839	1			T1	9		T3	1		T5	21
valid_sources[0x22]	314817	1			T1	10		T3	2		T4	2
valid_sources[0x23]	352241	1			T1	4		T4	9		T5	15
valid_sources[0x24]	342367	1			T1	10		T3	4		T4	3
valid_sources[0x25]	305997	1			T1	3		T3	2		T5	16
valid_sources[0x26]	531867	1			T1	8		T3	2		T4	1
valid_sources[0x27]	320504	1			T1	4		T3	3		T4	2
valid_sources[0x28]	306888	1			T1	1		T3	4		T4	6
valid_sources[0x29]	324315	1			T1	11		T3	4		T5	19
valid_sources[0x2a]	318306	1			T1	13		T3	2		T5	21
valid_sources[0x2b]	354724	1			T1	5		T3	4		T5	21
valid_sources[0x2c]	325992	1			T1	9		T3	5		T4	1
valid_sources[0x2d]	326059	1			T1	5		T3	6		T4	2
valid_sources[0x2e]	321907	1			T1	2		T3	5		T5	27
valid_sources[0x2f]	308739	1			T1	4		T3	2		T4	4
valid_sources[0x30]	315670	1			T1	7		T3	2		T4	9
valid_sources[0x31]	321466	1			T1	9		T3	6		T5	25
valid_sources[0x32]	342495	1			T1	9		T3	6		T4	5
valid_sources[0x33]	330862	1			T1	7		T4	2		T5	12
valid_sources[0x34]	366073	1			T1	14		T3	1		T4	5
valid_sources[0x35]	311863	1			T1	1		T3	1		T4	4
valid_sources[0x36]	317305	1			T1	5		T3	5		T5	13
valid_sources[0x37]	361087	1			T1	7		T3	4		T4	1
valid_sources[0x38]	552366	1			T1	4		T3	4		T4	4
valid_sources[0x39]	334586	1			T1	5		T3	4		T4	2
valid_sources[0x3a]	325124	1			T1	5		T4	10		T5	24
valid_sources[0x3b]	373573	1			T1	5		T3	2		T5	21
valid_sources[0x3c]	348268	1			T1	10		T3	4		T4	1
valid_sources[0x3d]	584448	1			T1	5		T3	2		T4	1
valid_sources[0x3e]	356357	1			T1	3		T3	2		T4	9
valid_sources[0x3f]	329348	1			T1	5		T5	23		T6	12
valid_sources[0x40]	343007	1			T1	9		T3	7		T4	2
valid_sources[0x41]	330508	1			T1	10		T3	1		T5	24
valid_sources[0x42]	325036	1			T1	4		T3	6		T5	25
valid_sources[0x43]	310869	1			T1	8		T3	3		T5	12
valid_sources[0x44]	380277	1			T1	6		T3	8		T4	1
valid_sources[0x45]	338700	1			T1	8		T2	157		T3	1
valid_sources[0x46]	330938	1			T1	3		T3	7		T4	5
valid_sources[0x47]	321762	1			T1	8		T3	6		T5	14
valid_sources[0x48]	350289	1			T1	13		T3	6		T5	22
valid_sources[0x49]	314031	1			T1	13		T3	2		T5	14
valid_sources[0x4a]	311565	1			T1	9		T3	5		T5	19
valid_sources[0x4b]	316253	1			T1	5		T5	25		T8	8
valid_sources[0x4c]	309491	1			T1	5		T3	3		T4	1
valid_sources[0x4d]	344309	1			T1	8		T3	3		T5	20
valid_sources[0x4e]	308179	1			T1	4		T3	1		T5	20
valid_sources[0x4f]	308469	1			T1	11		T3	1		T4	3
valid_sources[0x50]	325996	1			T1	10		T3	3		T4	9
valid_sources[0x51]	318594	1			T1	7		T3	1		T4	1
valid_sources[0x52]	308385	1			T1	2		T3	3		T4	3
valid_sources[0x53]	343982	1			T1	6		T3	2		T5	16
valid_sources[0x54]	315141	1			T1	1		T5	22		T6	14
valid_sources[0x55]	319370	1			T1	8		T4	2		T5	13
valid_sources[0x56]	443430	1			T1	6		T3	3		T5	16
valid_sources[0x57]	334280	1			T1	7		T3	1		T4	2
valid_sources[0x58]	355500	1			T1	8		T3	3		T4	7
valid_sources[0x59]	333817	1			T1	7		T5	24		T6	5
valid_sources[0x5a]	324012	1			T1	4		T3	4		T5	18
valid_sources[0x5b]	335190	1			T1	11		T3	4		T5	20
valid_sources[0x5c]	344716	1			T1	6		T3	2		T5	17
valid_sources[0x5d]	309133	1			T1	17		T3	2		T5	11
valid_sources[0x5e]	328967	1			T1	8		T3	5		T4	1
valid_sources[0x5f]	323816	1			T1	6		T3	2		T5	7
valid_sources[0x60]	325636	1			T1	4		T3	2		T4	3
valid_sources[0x61]	327474	1			T3	4		T5	24		T6	6
valid_sources[0x62]	397351	1			T1	1		T3	3		T4	4
valid_sources[0x63]	325403	1			T1	10		T3	1		T4	1
valid_sources[0x64]	323937	1			T1	7		T3	1		T4	2
valid_sources[0x65]	335522	1			T1	13		T3	3		T5	19
valid_sources[0x66]	316059	1			T1	2		T3	1		T5	18
valid_sources[0x67]	319198	1			T1	4		T3	3		T5	23
valid_sources[0x68]	371174	1			T1	5		T3	3		T5	17
valid_sources[0x69]	335597	1			T1	10		T3	3		T4	2
valid_sources[0x6a]	321361	1			T1	13		T3	1		T4	3
valid_sources[0x6b]	319665	1			T1	10		T3	2		T4	2
valid_sources[0x6c]	304074	1			T1	3		T3	3		T4	9
valid_sources[0x6d]	326296	1			T1	9		T3	7		T4	1
valid_sources[0x6e]	315187	1			T1	11		T3	5		T4	3
valid_sources[0x6f]	316501	1			T1	2		T3	3		T5	12
valid_sources[0x70]	318363	1			T1	9		T3	6		T4	1
valid_sources[0x71]	351929	1			T1	7		T3	1		T4	1
valid_sources[0x72]	343122	1			T1	4		T3	3		T4	2
valid_sources[0x73]	360931	1			T1	5		T3	5		T4	1
valid_sources[0x74]	540459	1			T1	4		T3	5		T5	18
valid_sources[0x75]	318812	1			T1	5		T3	6		T4	1
valid_sources[0x76]	332948	1			T1	8		T3	2		T5	16
valid_sources[0x77]	332111	1			T1	12		T3	2		T5	18
valid_sources[0x78]	305748	1			T1	8		T3	5		T5	17
valid_sources[0x79]	324743	1			T1	10		T3	2		T5	18
valid_sources[0x7a]	337091	1			T1	12		T3	3		T5	22
valid_sources[0x7b]	327272	1			T1	6		T3	3		T5	20
valid_sources[0x7c]	318549	1			T1	4		T5	10		T6	1
valid_sources[0x7d]	330578	1			T1	3		T3	2		T5	14
valid_sources[0x7e]	481647	1			T1	9		T3	5		T4	8
valid_sources[0x7f]	308079	1			T1	3		T3	2		T4	2
valid_sources[0x80]	307192	1			T1	6		T3	5		T5	25

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

19108117

1

T1

579

T2

5

T3

179

values[0x0]

all_enables

biggest_size

3246564

1

T1

74

T2

27

T3

41

values[0x1]

all_enables

biggest_size

3198761

1

T1

41

T2

16

T3

32