Unified Coverage Report :: Module :: uart_csr_assert_fpv

Module : uart_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_uart_csr_assert_0/uart_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.uart_csr_assert	100.00						100.00

---

Module Instance : tb.dut.uart_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : uart_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	10540293	0	0
ctrl_rd_A	2147483647	239879	0	0
intr_enable_rd_A	2147483647	212144	0	0
ovrd_rd_A	2147483647	237041	0	0
timeout_ctrl_rd_A	2147483647	239119	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	10540293	0	0
T11	628068	160969	0	0
T12	213495	84894	0	0
T13	326609	132055	0	0
T14	863852	0	0	0
T17	609065	0	0	0
T19	0	165809	0	0
T20	0	57082	0	0
T22	125315	0	0	0
T23	983	0	0	0
T24	1359	0	0	0
T29	155072	0	0	0
T30	271735	0	0	0
T31	0	279884	0	0
T32	0	110238	0	0
T33	0	222005	0	0
T34	0	175004	0	0
T35	0	348159	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	239879	0	0
T11	628068	17732	0	0
T12	213495	0	0	0
T14	863852	0	0	0
T16	881516	0	0	0
T17	609065	0	0	0
T18	29834	0	0	0
T20	170502	2645	0	0
T21	32825	0	0	0
T32	0	12423	0	0
T34	0	20132	0	0
T35	0	17873	0	0
T37	619819	0	0	0
T43	0	84	0	0
T44	0	7	0	0
T58	0	21	0	0
T92	0	5	0	0
T93	0	7	0	0
T94	998550	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	212144	0	0
T11	628068	15710	0	0
T12	213495	0	0	0
T14	863852	0	0	0
T16	881516	0	0	0
T17	609065	0	0	0
T18	29834	0	0	0
T20	170502	2275	0	0
T21	32825	0	0	0
T32	0	11003	0	0
T34	0	17171	0	0
T35	0	16292	0	0
T37	619819	0	0	0
T43	0	71	0	0
T44	0	10	0	0
T58	0	1	0	0
T62	0	4	0	0
T93	0	43	0	0
T94	998550	0	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	237041	0	0
T11	628068	18332	0	0
T12	213495	0	0	0
T14	863852	0	0	0
T16	881516	0	0	0
T17	609065	0	0	0
T18	29834	0	0	0
T20	170502	2483	0	0
T21	32825	0	0	0
T32	0	12265	0	0
T34	0	19407	0	0
T35	0	17275	0	0
T37	619819	0	0	0
T43	0	69	0	0
T58	0	9	0	0
T62	0	8	0	0
T92	0	2	0	0
T93	0	6	0	0
T94	998550	0	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	239119	0	0
T11	628068	18165	0	0
T12	213495	0	0	0
T14	863852	0	0	0
T16	881516	0	0	0
T17	609065	0	0	0
T18	29834	0	0	0
T20	170502	2543	0	0
T21	32825	0	0	0
T32	0	12439	0	0
T34	0	19963	0	0
T35	0	18045	0	0
T37	619819	0	0	0
T43	0	88	0	0
T58	0	3	0	0
T62	0	4	0	0
T92	0	9	0	0
T93	0	12	0	0
T94	998550	0	0	0