Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	341	1			T13	1		T5	1		T7	8
all_values[1]	341	1			T13	1		T5	1		T7	8
all_values[2]	341	1			T13	1		T5	1		T7	8
all_values[3]	341	1			T13	1		T5	1		T7	8
all_values[4]	341	1			T13	1		T5	1		T7	8
all_values[5]	341	1			T13	1		T5	1		T7	8
all_values[6]	341	1			T13	1		T5	1		T7	8
all_values[7]	341	1			T13	1		T5	1		T7	8

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1435

1

T13

8

T5

8

T7

32

auto[1]

1293

1

T7

32

T8

24

T9

32

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1799

1

T13

8

T5

8

T7

38

auto[1]

929

1

T7

26

T8

23

T9

23

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	140	1			T13	1		T5	1		T7	3
all_values[0]	auto[0]	auto[1]	65	1			T8	1		T9	1		T11	1
all_values[0]	auto[1]	auto[0]	85	1			T7	1		T8	1		T9	4
all_values[0]	auto[1]	auto[1]	51	1			T7	4		T8	2		T9	3
all_values[1]	auto[0]	auto[0]	123	1			T13	1		T5	1		T7	1
all_values[1]	auto[0]	auto[1]	53	1			T9	1		T11	1		T41	2
all_values[1]	auto[1]	auto[0]	114	1			T7	5		T8	1		T9	1
all_values[1]	auto[1]	auto[1]	51	1			T7	2		T8	3		T9	1
all_values[2]	auto[0]	auto[0]	116	1			T13	1		T5	1		T7	2
all_values[2]	auto[0]	auto[1]	62	1			T7	2		T8	3		T9	1
all_values[2]	auto[1]	auto[0]	105	1			T7	4		T9	1		T11	2
all_values[2]	auto[1]	auto[1]	58	1			T8	1		T9	4		T30	2
all_values[3]	auto[0]	auto[0]	107	1			T13	1		T5	1		T7	3
all_values[3]	auto[0]	auto[1]	52	1			T7	3		T30	1		T41	2
all_values[3]	auto[1]	auto[0]	133	1			T7	2		T8	1		T9	3
all_values[3]	auto[1]	auto[1]	49	1			T8	4		T41	2		T71	1
all_values[4]	auto[0]	auto[0]	119	1			T13	1		T5	1		T7	3
all_values[4]	auto[0]	auto[1]	51	1			T7	1		T8	1		T30	4
all_values[4]	auto[1]	auto[0]	106	1			T7	3		T9	5		T11	4
all_values[4]	auto[1]	auto[1]	65	1			T7	1		T9	1		T30	1
all_values[5]	auto[0]	auto[0]	135	1			T13	1		T5	1		T7	3
all_values[5]	auto[0]	auto[1]	55	1			T7	3		T9	1		T41	3
all_values[5]	auto[1]	auto[0]	85	1			T7	1		T8	2		T9	1
all_values[5]	auto[1]	auto[1]	66	1			T7	1		T8	3		T9	1
all_values[6]	auto[0]	auto[0]	121	1			T13	1		T5	1		T7	1
all_values[6]	auto[0]	auto[1]	70	1			T7	2		T8	2		T9	2
all_values[6]	auto[1]	auto[0]	82	1			T7	3		T9	2		T11	1
all_values[6]	auto[1]	auto[1]	68	1			T7	2		T8	1		T9	2
all_values[7]	auto[0]	auto[0]	122	1			T13	1		T5	1		T7	2
all_values[7]	auto[0]	auto[1]	44	1			T7	3		T9	2		T30	2
all_values[7]	auto[1]	auto[0]	106	1			T7	1		T8	3		T11	4
all_values[7]	auto[1]	auto[1]	69	1			T7	2		T8	2		T9	3