Unified Coverage Report

Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
65.90	64.36	63.61	96.46		63.57	100.00	7.39

Total tests in report: 165

Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE		LINE		COND		TOGGLE		FSM		BRANCH		ASSERT		GROUP
TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	NAME
60.73	60.73	61.47	61.47	53.75	53.75	94.50	94.50			58.81	58.81	94.06	94.06	1.81	1.81	/workspace/coverage/cover_reg_top/0.uart_tl_intg_err.2888236358
63.86	3.13	64.05	2.58	60.64	6.90	96.60	2.09			62.62	3.81	94.72	0.66	4.53	2.73	/workspace/coverage/cover_reg_top/11.uart_intr_test.192031573
65.16	1.30	64.26	0.21	62.31	1.66	99.48	2.88			62.86	0.24	96.04	1.32	6.05	1.51	/workspace/coverage/cover_reg_top/17.uart_tl_errors.2624853207
65.84	0.68	64.36	0.10	62.90	0.59	99.48	0.00			63.57	0.71	98.68	2.64	6.05	0.00	/workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.3964010630
66.01	0.17	64.36	0.00	62.90	0.00	99.48	0.00			63.57	0.00	99.34	0.66	6.42	0.38	/workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.2609566157
66.12	0.11	64.36	0.00	62.90	0.00	99.48	0.00			63.57	0.00	100.00	0.66	6.42	0.00	/workspace/coverage/cover_reg_top/13.uart_csr_rw.2305023799
66.21	0.08	64.36	0.00	63.26	0.36	99.48	0.00			63.57	0.00	100.00	0.00	6.57	0.15	/workspace/coverage/cover_reg_top/17.uart_tl_intg_err.490274788
66.27	0.07	64.36	0.00	63.26	0.00	99.48	0.00			63.57	0.00	100.00	0.00	6.97	0.40	/workspace/coverage/cover_reg_top/49.uart_intr_test.1447861851
66.33	0.06	64.36	0.00	63.26	0.00	99.74	0.26			63.57	0.00	100.00	0.00	7.05	0.08	/workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.3368755736
66.38	0.05	64.36	0.00	63.50	0.24	99.74	0.00			63.57	0.00	100.00	0.00	7.12	0.06	/workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.3894612213
66.41	0.03	64.36	0.00	63.61	0.12	99.74	0.00			63.57	0.00	100.00	0.00	7.16	0.04	/workspace/coverage/cover_reg_top/8.uart_tl_intg_err.2816253512
66.43	0.02	64.36	0.00	63.61	0.00	99.74	0.00			63.57	0.00	100.00	0.00	7.31	0.15	/workspace/coverage/cover_reg_top/3.uart_intr_test.4255622561
66.44	0.01	64.36	0.00	63.61	0.00	99.74	0.00			63.57	0.00	100.00	0.00	7.37	0.06	/workspace/coverage/cover_reg_top/28.uart_intr_test.248701634
66.45	0.01	64.36	0.00	63.61	0.00	99.74	0.00			63.57	0.00	100.00	0.00	7.39	0.02	/workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.2240625710

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.uart_csr_aliasing.1755264517
/workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.3363646986
/workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.3359168942
/workspace/coverage/cover_reg_top/0.uart_csr_rw.1917998642
/workspace/coverage/cover_reg_top/0.uart_intr_test.2968136033
/workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.3264164562
/workspace/coverage/cover_reg_top/0.uart_tl_errors.1556386876
/workspace/coverage/cover_reg_top/1.uart_csr_aliasing.2501005806
/workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.2316641806
/workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.2522402948
/workspace/coverage/cover_reg_top/1.uart_csr_rw.1139992669
/workspace/coverage/cover_reg_top/1.uart_intr_test.3661585711
/workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.2585798953
/workspace/coverage/cover_reg_top/1.uart_tl_errors.966962594
/workspace/coverage/cover_reg_top/1.uart_tl_intg_err.3398462379
/workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.4002256369
/workspace/coverage/cover_reg_top/10.uart_csr_rw.1289375152
/workspace/coverage/cover_reg_top/10.uart_intr_test.3428855786
/workspace/coverage/cover_reg_top/10.uart_tl_errors.4085458796
/workspace/coverage/cover_reg_top/10.uart_tl_intg_err.2973220313
/workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.1743946032
/workspace/coverage/cover_reg_top/11.uart_csr_rw.1557449498
/workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.4136216988
/workspace/coverage/cover_reg_top/11.uart_tl_errors.2212962433
/workspace/coverage/cover_reg_top/11.uart_tl_intg_err.3226640059
/workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.3131730354
/workspace/coverage/cover_reg_top/12.uart_csr_rw.3629701904
/workspace/coverage/cover_reg_top/12.uart_intr_test.1827240983
/workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.132627393
/workspace/coverage/cover_reg_top/12.uart_tl_errors.1942980212
/workspace/coverage/cover_reg_top/12.uart_tl_intg_err.481484430
/workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.1156401434
/workspace/coverage/cover_reg_top/13.uart_intr_test.3511038914
/workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.2902707342
/workspace/coverage/cover_reg_top/13.uart_tl_errors.864688629
/workspace/coverage/cover_reg_top/13.uart_tl_intg_err.138236353
/workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.1078935077
/workspace/coverage/cover_reg_top/14.uart_csr_rw.3783657654
/workspace/coverage/cover_reg_top/14.uart_intr_test.3209969336
/workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.3062064442
/workspace/coverage/cover_reg_top/14.uart_tl_errors.3247003068
/workspace/coverage/cover_reg_top/14.uart_tl_intg_err.2418900665
/workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.2768857090
/workspace/coverage/cover_reg_top/15.uart_csr_rw.1354170536
/workspace/coverage/cover_reg_top/15.uart_intr_test.4196355327
/workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.447591287
/workspace/coverage/cover_reg_top/15.uart_tl_errors.306943811
/workspace/coverage/cover_reg_top/15.uart_tl_intg_err.2304772039
/workspace/coverage/cover_reg_top/16.uart_csr_rw.2358172845
/workspace/coverage/cover_reg_top/16.uart_intr_test.4100799639
/workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.2538932833
/workspace/coverage/cover_reg_top/16.uart_tl_errors.2073507321
/workspace/coverage/cover_reg_top/16.uart_tl_intg_err.2867336341
/workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.2043455097
/workspace/coverage/cover_reg_top/17.uart_csr_rw.776844797
/workspace/coverage/cover_reg_top/17.uart_intr_test.2720145694
/workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.3437660493
/workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.2457856994
/workspace/coverage/cover_reg_top/18.uart_csr_rw.3469128840
/workspace/coverage/cover_reg_top/18.uart_intr_test.1789070623
/workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.3603828774
/workspace/coverage/cover_reg_top/18.uart_tl_errors.3355794139
/workspace/coverage/cover_reg_top/18.uart_tl_intg_err.2731356418
/workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.2929350088
/workspace/coverage/cover_reg_top/19.uart_csr_rw.4248188258
/workspace/coverage/cover_reg_top/19.uart_intr_test.950634193
/workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.148719565
/workspace/coverage/cover_reg_top/19.uart_tl_errors.1693717170
/workspace/coverage/cover_reg_top/19.uart_tl_intg_err.4133387029
/workspace/coverage/cover_reg_top/2.uart_csr_aliasing.2757068552
/workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.108499
/workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.261018994
/workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.445165642
/workspace/coverage/cover_reg_top/2.uart_csr_rw.548114246
/workspace/coverage/cover_reg_top/2.uart_intr_test.2621440725
/workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.4059336026
/workspace/coverage/cover_reg_top/2.uart_tl_errors.2960248748
/workspace/coverage/cover_reg_top/2.uart_tl_intg_err.1911884383
/workspace/coverage/cover_reg_top/20.uart_intr_test.2406557959
/workspace/coverage/cover_reg_top/21.uart_intr_test.2740469157
/workspace/coverage/cover_reg_top/22.uart_intr_test.1539995746
/workspace/coverage/cover_reg_top/23.uart_intr_test.501988042
/workspace/coverage/cover_reg_top/24.uart_intr_test.1970405708
/workspace/coverage/cover_reg_top/25.uart_intr_test.1128244041
/workspace/coverage/cover_reg_top/26.uart_intr_test.2792608992
/workspace/coverage/cover_reg_top/27.uart_intr_test.2734828629
/workspace/coverage/cover_reg_top/29.uart_intr_test.117861765
/workspace/coverage/cover_reg_top/3.uart_csr_aliasing.1794430092
/workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.993128001
/workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.4090903298
/workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.3136231304
/workspace/coverage/cover_reg_top/3.uart_csr_rw.3868311997
/workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.3805476921
/workspace/coverage/cover_reg_top/3.uart_tl_errors.4019640598
/workspace/coverage/cover_reg_top/3.uart_tl_intg_err.3304253601
/workspace/coverage/cover_reg_top/30.uart_intr_test.3124601750
/workspace/coverage/cover_reg_top/31.uart_intr_test.498245320
/workspace/coverage/cover_reg_top/32.uart_intr_test.94897176
/workspace/coverage/cover_reg_top/33.uart_intr_test.86963421
/workspace/coverage/cover_reg_top/34.uart_intr_test.882345153
/workspace/coverage/cover_reg_top/35.uart_intr_test.2256039502
/workspace/coverage/cover_reg_top/36.uart_intr_test.2092661316
/workspace/coverage/cover_reg_top/37.uart_intr_test.3294980193
/workspace/coverage/cover_reg_top/38.uart_intr_test.2147718427
/workspace/coverage/cover_reg_top/39.uart_intr_test.3388597381
/workspace/coverage/cover_reg_top/4.uart_csr_aliasing.3935301422
/workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.1406847704
/workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.935359832
/workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.1832434951
/workspace/coverage/cover_reg_top/4.uart_csr_rw.3437588118
/workspace/coverage/cover_reg_top/4.uart_intr_test.1753812484
/workspace/coverage/cover_reg_top/4.uart_tl_errors.3418494453
/workspace/coverage/cover_reg_top/4.uart_tl_intg_err.275422727
/workspace/coverage/cover_reg_top/40.uart_intr_test.956317334
/workspace/coverage/cover_reg_top/41.uart_intr_test.75179185
/workspace/coverage/cover_reg_top/42.uart_intr_test.2960624242
/workspace/coverage/cover_reg_top/43.uart_intr_test.1566510374
/workspace/coverage/cover_reg_top/44.uart_intr_test.3150298793
/workspace/coverage/cover_reg_top/45.uart_intr_test.722325921
/workspace/coverage/cover_reg_top/46.uart_intr_test.1879131222
/workspace/coverage/cover_reg_top/47.uart_intr_test.2703463185
/workspace/coverage/cover_reg_top/48.uart_intr_test.3128263002
/workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.3212534880
/workspace/coverage/cover_reg_top/5.uart_csr_rw.2546544459
/workspace/coverage/cover_reg_top/5.uart_intr_test.2507678027
/workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.3319642597
/workspace/coverage/cover_reg_top/5.uart_tl_errors.3216574741
/workspace/coverage/cover_reg_top/5.uart_tl_intg_err.1595783725
/workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.247858723
/workspace/coverage/cover_reg_top/6.uart_csr_rw.567591586
/workspace/coverage/cover_reg_top/6.uart_intr_test.3398035272
/workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.822319444
/workspace/coverage/cover_reg_top/6.uart_tl_errors.427782579
/workspace/coverage/cover_reg_top/6.uart_tl_intg_err.4030041827
/workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.2029991926
/workspace/coverage/cover_reg_top/7.uart_csr_rw.351607893
/workspace/coverage/cover_reg_top/7.uart_intr_test.3273107234
/workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.2078842457
/workspace/coverage/cover_reg_top/7.uart_tl_errors.1896922259
/workspace/coverage/cover_reg_top/7.uart_tl_intg_err.3501567476
/workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.3509970366
/workspace/coverage/cover_reg_top/8.uart_csr_rw.975005599
/workspace/coverage/cover_reg_top/8.uart_intr_test.3662104649
/workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.1002745991
/workspace/coverage/cover_reg_top/8.uart_tl_errors.2019315998
/workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.1522921432
/workspace/coverage/cover_reg_top/9.uart_csr_rw.734101869
/workspace/coverage/cover_reg_top/9.uart_intr_test.1534037587
/workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.1799278787
/workspace/coverage/cover_reg_top/9.uart_tl_errors.61771110
/workspace/coverage/cover_reg_top/9.uart_tl_intg_err.3568858566

Total test records in report: 165

tests.html | tests1.html | tests2.html

TEST NO	TEST LOCATION	STARTED	FINISHED	SIMULATION TIME
T1	/workspace/coverage/cover_reg_top/0.uart_tl_intg_err.2888236358	Jan 14 12:18:14 PM PST 24	Jan 14 12:18:15 PM PST 24	1104117948 ps
T2	/workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.2240625710	Jan 14 12:19:09 PM PST 24	Jan 14 12:19:14 PM PST 24	78065677 ps
T3	/workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.2029991926	Jan 14 12:20:13 PM PST 24	Jan 14 12:20:14 PM PST 24	27272987 ps
T4	/workspace/coverage/cover_reg_top/17.uart_tl_intg_err.490274788	Jan 14 12:22:14 PM PST 24	Jan 14 12:22:16 PM PST 24	291847292 ps
T13	/workspace/coverage/cover_reg_top/3.uart_tl_errors.4019640598	Jan 14 12:22:08 PM PST 24	Jan 14 12:22:09 PM PST 24	48919319 ps
T5	/workspace/coverage/cover_reg_top/17.uart_tl_errors.2624853207	Jan 14 12:22:37 PM PST 24	Jan 14 12:22:40 PM PST 24	97033443 ps
T14	/workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.3212534880	Jan 14 12:17:14 PM PST 24	Jan 14 12:17:17 PM PST 24	21984414 ps
T12	/workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.1406847704	Jan 14 12:19:14 PM PST 24	Jan 14 12:19:18 PM PST 24	360539039 ps
T15	/workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.148719565	Jan 14 12:20:36 PM PST 24	Jan 14 12:20:37 PM PST 24	41875865 ps
T7	/workspace/coverage/cover_reg_top/23.uart_intr_test.501988042	Jan 14 12:19:44 PM PST 24	Jan 14 12:19:45 PM PST 24	15574662 ps
T22	/workspace/coverage/cover_reg_top/14.uart_csr_rw.3783657654	Jan 14 12:23:43 PM PST 24	Jan 14 12:23:44 PM PST 24	14114390 ps
T23	/workspace/coverage/cover_reg_top/2.uart_csr_rw.548114246	Jan 14 12:23:19 PM PST 24	Jan 14 12:23:25 PM PST 24	27254081 ps
T8	/workspace/coverage/cover_reg_top/22.uart_intr_test.1539995746	Jan 14 12:22:27 PM PST 24	Jan 14 12:22:29 PM PST 24	20306506 ps
T24	/workspace/coverage/cover_reg_top/6.uart_tl_intg_err.4030041827	Jan 14 12:19:56 PM PST 24	Jan 14 12:19:57 PM PST 24	189243121 ps
T9	/workspace/coverage/cover_reg_top/11.uart_intr_test.192031573	Jan 14 12:18:31 PM PST 24	Jan 14 12:18:32 PM PST 24	15086204 ps
T16	/workspace/coverage/cover_reg_top/18.uart_tl_errors.3355794139	Jan 14 12:18:15 PM PST 24	Jan 14 12:18:17 PM PST 24	80072065 ps
T56	/workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.1002745991	Jan 14 12:19:07 PM PST 24	Jan 14 12:19:10 PM PST 24	56543749 ps
T57	/workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.2609566157	Jan 14 12:23:10 PM PST 24	Jan 14 12:23:16 PM PST 24	19139435 ps
T26	/workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.2585798953	Jan 14 12:20:20 PM PST 24	Jan 14 12:20:22 PM PST 24	38384247 ps
T27	/workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.247858723	Jan 14 12:20:19 PM PST 24	Jan 14 12:20:21 PM PST 24	41496796 ps
T28	/workspace/coverage/cover_reg_top/9.uart_csr_rw.734101869	Jan 14 12:17:44 PM PST 24	Jan 14 12:17:45 PM PST 24	16990037 ps
T10	/workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.4090903298	Jan 14 12:23:00 PM PST 24	Jan 14 12:23:01 PM PST 24	14945094 ps
T11	/workspace/coverage/cover_reg_top/16.uart_intr_test.4100799639	Jan 14 12:22:34 PM PST 24	Jan 14 12:22:35 PM PST 24	47501469 ps
T29	/workspace/coverage/cover_reg_top/16.uart_csr_rw.2358172845	Jan 14 12:22:37 PM PST 24	Jan 14 12:22:38 PM PST 24	216279898 ps
T30	/workspace/coverage/cover_reg_top/34.uart_intr_test.882345153	Jan 14 12:19:49 PM PST 24	Jan 14 12:19:50 PM PST 24	42007593 ps
T31	/workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.3805476921	Jan 14 12:20:25 PM PST 24	Jan 14 12:20:26 PM PST 24	13197857 ps
T32	/workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.2043455097	Jan 14 12:22:12 PM PST 24	Jan 14 12:22:14 PM PST 24	88775753 ps
T17	/workspace/coverage/cover_reg_top/19.uart_tl_errors.1693717170	Jan 14 12:22:50 PM PST 24	Jan 14 12:22:54 PM PST 24	132284721 ps
T40	/workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.4136216988	Jan 14 12:20:25 PM PST 24	Jan 14 12:20:26 PM PST 24	125914535 ps
T41	/workspace/coverage/cover_reg_top/7.uart_intr_test.3273107234	Jan 14 12:22:36 PM PST 24	Jan 14 12:22:37 PM PST 24	52730996 ps
T79	/workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.1156401434	Jan 14 12:23:42 PM PST 24	Jan 14 12:23:44 PM PST 24	24977427 ps
T72	/workspace/coverage/cover_reg_top/15.uart_intr_test.4196355327	Jan 14 12:22:01 PM PST 24	Jan 14 12:22:02 PM PST 24	35907155 ps
T78	/workspace/coverage/cover_reg_top/3.uart_csr_aliasing.1794430092	Jan 14 12:19:09 PM PST 24	Jan 14 12:19:10 PM PST 24	44038891 ps
T64	/workspace/coverage/cover_reg_top/38.uart_intr_test.2147718427	Jan 14 12:19:14 PM PST 24	Jan 14 12:19:16 PM PST 24	13302170 ps
T18	/workspace/coverage/cover_reg_top/8.uart_tl_errors.2019315998	Jan 14 12:17:05 PM PST 24	Jan 14 12:17:08 PM PST 24	500072623 ps
T71	/workspace/coverage/cover_reg_top/49.uart_intr_test.1447861851	Jan 14 12:19:14 PM PST 24	Jan 14 12:19:16 PM PST 24	14250374 ps
T19	/workspace/coverage/cover_reg_top/10.uart_tl_errors.4085458796	Jan 14 12:23:10 PM PST 24	Jan 14 12:23:17 PM PST 24	1005837513 ps
T33	/workspace/coverage/cover_reg_top/0.uart_csr_rw.1917998642	Jan 14 12:23:12 PM PST 24	Jan 14 12:23:21 PM PST 24	52738741 ps
T65	/workspace/coverage/cover_reg_top/43.uart_intr_test.1566510374	Jan 14 12:19:14 PM PST 24	Jan 14 12:19:16 PM PST 24	105870907 ps
T20	/workspace/coverage/cover_reg_top/11.uart_tl_intg_err.3226640059	Jan 14 12:23:31 PM PST 24	Jan 14 12:23:33 PM PST 24	75158898 ps
T74	/workspace/coverage/cover_reg_top/19.uart_intr_test.950634193	Jan 14 12:19:31 PM PST 24	Jan 14 12:19:32 PM PST 24	82906928 ps
T80	/workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.2538932833	Jan 14 12:22:54 PM PST 24	Jan 14 12:22:56 PM PST 24	101291583 ps
T76	/workspace/coverage/cover_reg_top/25.uart_intr_test.1128244041	Jan 14 12:22:14 PM PST 24	Jan 14 12:22:16 PM PST 24	35794642 ps
T6	/workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.3368755736	Jan 14 12:23:01 PM PST 24	Jan 14 12:23:03 PM PST 24	1043944455 ps
T21	/workspace/coverage/cover_reg_top/9.uart_tl_errors.61771110	Jan 14 12:23:12 PM PST 24	Jan 14 12:23:21 PM PST 24	30987474 ps
T61	/workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.3509970366	Jan 14 12:23:08 PM PST 24	Jan 14 12:23:11 PM PST 24	27524369 ps
T25	/workspace/coverage/cover_reg_top/1.uart_tl_errors.966962594	Jan 14 12:22:25 PM PST 24	Jan 14 12:22:28 PM PST 24	181583897 ps
T81	/workspace/coverage/cover_reg_top/14.uart_intr_test.3209969336	Jan 14 12:19:35 PM PST 24	Jan 14 12:19:36 PM PST 24	20309776 ps
T82	/workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.3894612213	Jan 14 12:20:28 PM PST 24	Jan 14 12:20:29 PM PST 24	88147827 ps
T83	/workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.822319444	Jan 14 12:19:56 PM PST 24	Jan 14 12:19:57 PM PST 24	108795796 ps
T66	/workspace/coverage/cover_reg_top/47.uart_intr_test.2703463185	Jan 14 12:22:25 PM PST 24	Jan 14 12:22:27 PM PST 24	58248574 ps
T84	/workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.1832434951	Jan 14 12:23:10 PM PST 24	Jan 14 12:23:16 PM PST 24	105060713 ps
T77	/workspace/coverage/cover_reg_top/13.uart_intr_test.3511038914	Jan 14 12:19:06 PM PST 24	Jan 14 12:19:07 PM PST 24	53497663 ps
T85	/workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.445165642	Jan 14 12:18:01 PM PST 24	Jan 14 12:18:03 PM PST 24	73840199 ps
T86	/workspace/coverage/cover_reg_top/20.uart_intr_test.2406557959	Jan 14 12:22:50 PM PST 24	Jan 14 12:22:53 PM PST 24	46546832 ps
T87	/workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.1522921432	Jan 14 12:23:10 PM PST 24	Jan 14 12:23:16 PM PST 24	39940056 ps
T62	/workspace/coverage/cover_reg_top/7.uart_csr_rw.351607893	Jan 14 12:20:13 PM PST 24	Jan 14 12:20:14 PM PST 24	28651219 ps
T34	/workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.447591287	Jan 14 12:22:59 PM PST 24	Jan 14 12:23:01 PM PST 24	16388286 ps
T63	/workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.2522402948	Jan 14 12:23:19 PM PST 24	Jan 14 12:23:25 PM PST 24	36038108 ps
T35	/workspace/coverage/cover_reg_top/4.uart_csr_rw.3437588118	Jan 14 12:22:44 PM PST 24	Jan 14 12:22:46 PM PST 24	12131485 ps
T67	/workspace/coverage/cover_reg_top/14.uart_tl_intg_err.2418900665	Jan 14 12:23:42 PM PST 24	Jan 14 12:23:44 PM PST 24	116738800 ps
T88	/workspace/coverage/cover_reg_top/1.uart_csr_rw.1139992669	Jan 14 12:23:01 PM PST 24	Jan 14 12:23:03 PM PST 24	12354823 ps
T89	/workspace/coverage/cover_reg_top/11.uart_tl_errors.2212962433	Jan 14 12:23:08 PM PST 24	Jan 14 12:23:13 PM PST 24	290259004 ps
T90	/workspace/coverage/cover_reg_top/4.uart_tl_errors.3418494453	Jan 14 12:18:44 PM PST 24	Jan 14 12:18:49 PM PST 24	168066085 ps
T75	/workspace/coverage/cover_reg_top/28.uart_intr_test.248701634	Jan 14 12:22:01 PM PST 24	Jan 14 12:22:02 PM PST 24	13765960 ps
T59	/workspace/coverage/cover_reg_top/19.uart_tl_intg_err.4133387029	Jan 14 12:22:01 PM PST 24	Jan 14 12:22:03 PM PST 24	87221280 ps
T36	/workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.3964010630	Jan 14 12:23:12 PM PST 24	Jan 14 12:23:21 PM PST 24	18343361 ps
T73	/workspace/coverage/cover_reg_top/3.uart_intr_test.4255622561	Jan 14 12:19:46 PM PST 24	Jan 14 12:19:48 PM PST 24	22466806 ps
T91	/workspace/coverage/cover_reg_top/42.uart_intr_test.2960624242	Jan 14 12:23:04 PM PST 24	Jan 14 12:23:06 PM PST 24	24552222 ps
T92	/workspace/coverage/cover_reg_top/12.uart_csr_rw.3629701904	Jan 14 12:22:59 PM PST 24	Jan 14 12:23:00 PM PST 24	50516092 ps
T37	/workspace/coverage/cover_reg_top/13.uart_csr_rw.2305023799	Jan 14 12:23:02 PM PST 24	Jan 14 12:23:04 PM PST 24	31379959 ps
T48	/workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.2316641806	Jan 14 12:22:58 PM PST 24	Jan 14 12:23:01 PM PST 24	220027586 ps
T49	/workspace/coverage/cover_reg_top/41.uart_intr_test.75179185	Jan 14 12:20:46 PM PST 24	Jan 14 12:20:47 PM PST 24	117201051 ps
T50	/workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.3359168942	Jan 14 12:22:25 PM PST 24	Jan 14 12:22:26 PM PST 24	20527087 ps
T51	/workspace/coverage/cover_reg_top/36.uart_intr_test.2092661316	Jan 14 12:22:09 PM PST 24	Jan 14 12:22:10 PM PST 24	40129416 ps
T38	/workspace/coverage/cover_reg_top/17.uart_csr_rw.776844797	Jan 14 12:20:28 PM PST 24	Jan 14 12:20:29 PM PST 24	43257191 ps
T52	/workspace/coverage/cover_reg_top/12.uart_intr_test.1827240983	Jan 14 12:18:41 PM PST 24	Jan 14 12:18:43 PM PST 24	30568621 ps
T53	/workspace/coverage/cover_reg_top/18.uart_tl_intg_err.2731356418	Jan 14 12:22:37 PM PST 24	Jan 14 12:22:38 PM PST 24	471181772 ps
T54	/workspace/coverage/cover_reg_top/10.uart_csr_rw.1289375152	Jan 14 12:23:12 PM PST 24	Jan 14 12:23:21 PM PST 24	19966491 ps
T55	/workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.261018994	Jan 14 12:22:59 PM PST 24	Jan 14 12:23:00 PM PST 24	47332020 ps
T93	/workspace/coverage/cover_reg_top/35.uart_intr_test.2256039502	Jan 14 12:22:37 PM PST 24	Jan 14 12:22:38 PM PST 24	42369702 ps
T94	/workspace/coverage/cover_reg_top/30.uart_intr_test.3124601750	Jan 14 12:23:27 PM PST 24	Jan 14 12:23:29 PM PST 24	14566975 ps
T95	/workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.1799278787	Jan 14 12:23:10 PM PST 24	Jan 14 12:23:15 PM PST 24	31145941 ps
T96	/workspace/coverage/cover_reg_top/14.uart_tl_errors.3247003068	Jan 14 12:21:46 PM PST 24	Jan 14 12:21:48 PM PST 24	140791607 ps
T97	/workspace/coverage/cover_reg_top/5.uart_intr_test.2507678027	Jan 14 12:17:14 PM PST 24	Jan 14 12:17:17 PM PST 24	11395703 ps
T98	/workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.3264164562	Jan 14 12:19:30 PM PST 24	Jan 14 12:19:31 PM PST 24	89051080 ps
T39	/workspace/coverage/cover_reg_top/4.uart_csr_aliasing.3935301422	Jan 14 12:23:31 PM PST 24	Jan 14 12:23:32 PM PST 24	48714036 ps
T99	/workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.3131730354	Jan 14 12:23:12 PM PST 24	Jan 14 12:23:21 PM PST 24	28344939 ps
T100	/workspace/coverage/cover_reg_top/39.uart_intr_test.3388597381	Jan 14 12:22:37 PM PST 24	Jan 14 12:22:38 PM PST 24	52064823 ps
T101	/workspace/coverage/cover_reg_top/15.uart_csr_rw.1354170536	Jan 14 12:17:58 PM PST 24	Jan 14 12:17:59 PM PST 24	36254096 ps
T102	/workspace/coverage/cover_reg_top/21.uart_intr_test.2740469157	Jan 14 12:22:14 PM PST 24	Jan 14 12:22:16 PM PST 24	139190244 ps
T68	/workspace/coverage/cover_reg_top/16.uart_tl_intg_err.2867336341	Jan 14 12:22:59 PM PST 24	Jan 14 12:23:01 PM PST 24	349434529 ps
T103	/workspace/coverage/cover_reg_top/44.uart_intr_test.3150298793	Jan 14 12:22:12 PM PST 24	Jan 14 12:22:14 PM PST 24	27677121 ps
T104	/workspace/coverage/cover_reg_top/11.uart_csr_rw.1557449498	Jan 14 12:19:30 PM PST 24	Jan 14 12:19:31 PM PST 24	28397831 ps
T105	/workspace/coverage/cover_reg_top/0.uart_csr_aliasing.1755264517	Jan 14 12:22:47 PM PST 24	Jan 14 12:22:48 PM PST 24	23618249 ps
T106	/workspace/coverage/cover_reg_top/33.uart_intr_test.86963421	Jan 14 12:23:27 PM PST 24	Jan 14 12:23:29 PM PST 24	35998941 ps
T107	/workspace/coverage/cover_reg_top/18.uart_intr_test.1789070623	Jan 14 12:22:34 PM PST 24	Jan 14 12:22:35 PM PST 24	12480070 ps
T60	/workspace/coverage/cover_reg_top/13.uart_tl_intg_err.138236353	Jan 14 12:18:03 PM PST 24	Jan 14 12:18:05 PM PST 24	592237533 ps
T108	/workspace/coverage/cover_reg_top/4.uart_intr_test.1753812484	Jan 14 12:19:14 PM PST 24	Jan 14 12:19:16 PM PST 24	12638861 ps
T109	/workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.2929350088	Jan 14 12:20:20 PM PST 24	Jan 14 12:20:21 PM PST 24	17732763 ps
T58	/workspace/coverage/cover_reg_top/15.uart_tl_intg_err.2304772039	Jan 14 12:22:25 PM PST 24	Jan 14 12:22:27 PM PST 24	380889991 ps
T110	/workspace/coverage/cover_reg_top/2.uart_tl_errors.2960248748	Jan 14 12:19:04 PM PST 24	Jan 14 12:19:06 PM PST 24	78951895 ps
T69	/workspace/coverage/cover_reg_top/7.uart_tl_intg_err.3501567476	Jan 14 12:17:05 PM PST 24	Jan 14 12:17:07 PM PST 24	76156881 ps
T111	/workspace/coverage/cover_reg_top/7.uart_tl_errors.1896922259	Jan 14 12:23:00 PM PST 24	Jan 14 12:23:03 PM PST 24	475282418 ps
T112	/workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.4002256369	Jan 14 12:23:07 PM PST 24	Jan 14 12:23:11 PM PST 24	257220775 ps
T113	/workspace/coverage/cover_reg_top/18.uart_csr_rw.3469128840	Jan 14 12:22:34 PM PST 24	Jan 14 12:22:35 PM PST 24	12377863 ps
T114	/workspace/coverage/cover_reg_top/16.uart_tl_errors.2073507321	Jan 14 12:22:59 PM PST 24	Jan 14 12:23:02 PM PST 24	763339134 ps
T115	/workspace/coverage/cover_reg_top/2.uart_intr_test.2621440725	Jan 14 12:16:47 PM PST 24	Jan 14 12:16:48 PM PST 24	40027896 ps
T116	/workspace/coverage/cover_reg_top/8.uart_intr_test.3662104649	Jan 14 12:18:15 PM PST 24	Jan 14 12:18:16 PM PST 24	44456771 ps
T70	/workspace/coverage/cover_reg_top/8.uart_tl_intg_err.2816253512	Jan 14 12:20:13 PM PST 24	Jan 14 12:20:14 PM PST 24	163075164 ps
T117	/workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.1743946032	Jan 14 12:19:10 PM PST 24	Jan 14 12:19:16 PM PST 24	59621402 ps
T118	/workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.2768857090	Jan 14 12:19:46 PM PST 24	Jan 14 12:19:47 PM PST 24	106996825 ps
T119	/workspace/coverage/cover_reg_top/31.uart_intr_test.498245320	Jan 14 12:22:37 PM PST 24	Jan 14 12:22:38 PM PST 24	15181014 ps
T120	/workspace/coverage/cover_reg_top/9.uart_tl_intg_err.3568858566	Jan 14 12:18:27 PM PST 24	Jan 14 12:18:29 PM PST 24	147124423 ps
T121	/workspace/coverage/cover_reg_top/6.uart_tl_errors.427782579	Jan 14 12:19:14 PM PST 24	Jan 14 12:19:17 PM PST 24	136197146 ps
T42	/workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.935359832	Jan 14 12:22:44 PM PST 24	Jan 14 12:22:46 PM PST 24	26913160 ps
T46	/workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.108499	Jan 14 12:20:36 PM PST 24	Jan 14 12:20:38 PM PST 24	93171449 ps
T122	/workspace/coverage/cover_reg_top/5.uart_tl_intg_err.1595783725	Jan 14 12:18:03 PM PST 24	Jan 14 12:18:05 PM PST 24	102604013 ps
T43	/workspace/coverage/cover_reg_top/3.uart_csr_rw.3868311997	Jan 14 12:17:52 PM PST 24	Jan 14 12:17:53 PM PST 24	48251669 ps
T123	/workspace/coverage/cover_reg_top/2.uart_tl_intg_err.1911884383	Jan 14 12:17:28 PM PST 24	Jan 14 12:17:30 PM PST 24	549811229 ps
T124	/workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.2078842457	Jan 14 12:22:41 PM PST 24	Jan 14 12:22:42 PM PST 24	19746383 ps
T125	/workspace/coverage/cover_reg_top/26.uart_intr_test.2792608992	Jan 14 12:22:50 PM PST 24	Jan 14 12:22:53 PM PST 24	47601457 ps
T126	/workspace/coverage/cover_reg_top/29.uart_intr_test.117861765	Jan 14 12:22:28 PM PST 24	Jan 14 12:22:29 PM PST 24	13591786 ps
T127	/workspace/coverage/cover_reg_top/3.uart_tl_intg_err.3304253601	Jan 14 12:22:59 PM PST 24	Jan 14 12:23:01 PM PST 24	82320079 ps
T128	/workspace/coverage/cover_reg_top/0.uart_tl_errors.1556386876	Jan 14 12:22:47 PM PST 24	Jan 14 12:22:53 PM PST 24	31936936 ps
T129	/workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.3062064442	Jan 14 12:23:42 PM PST 24	Jan 14 12:23:44 PM PST 24	37466582 ps
T130	/workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.4059336026	Jan 14 12:22:59 PM PST 24	Jan 14 12:23:00 PM PST 24	49455630 ps
T131	/workspace/coverage/cover_reg_top/12.uart_tl_errors.1942980212	Jan 14 12:18:28 PM PST 24	Jan 14 12:18:30 PM PST 24	122753636 ps
T132	/workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.3437660493	Jan 14 12:22:37 PM PST 24	Jan 14 12:22:38 PM PST 24	59789654 ps
T133	/workspace/coverage/cover_reg_top/4.uart_tl_intg_err.275422727	Jan 14 12:19:14 PM PST 24	Jan 14 12:19:16 PM PST 24	182241906 ps
T134	/workspace/coverage/cover_reg_top/10.uart_intr_test.3428855786	Jan 14 12:18:28 PM PST 24	Jan 14 12:18:29 PM PST 24	51282312 ps
T47	/workspace/coverage/cover_reg_top/19.uart_csr_rw.4248188258	Jan 14 12:20:43 PM PST 24	Jan 14 12:20:44 PM PST 24	16796686 ps
T135	/workspace/coverage/cover_reg_top/48.uart_intr_test.3128263002	Jan 14 12:22:13 PM PST 24	Jan 14 12:22:14 PM PST 24	16171255 ps
T136	/workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.2902707342	Jan 14 12:23:15 PM PST 24	Jan 14 12:23:21 PM PST 24	55682372 ps
T137	/workspace/coverage/cover_reg_top/0.uart_intr_test.2968136033	Jan 14 12:23:41 PM PST 24	Jan 14 12:23:42 PM PST 24	50294568 ps
T138	/workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.3363646986	Jan 14 12:23:27 PM PST 24	Jan 14 12:23:31 PM PST 24	2745780990 ps
T139	/workspace/coverage/cover_reg_top/46.uart_intr_test.1879131222	Jan 14 12:18:36 PM PST 24	Jan 14 12:18:37 PM PST 24	21536027 ps
T140	/workspace/coverage/cover_reg_top/13.uart_tl_errors.864688629	Jan 14 12:23:12 PM PST 24	Jan 14 12:23:21 PM PST 24	73397599 ps
T141	/workspace/coverage/cover_reg_top/15.uart_tl_errors.306943811	Jan 14 12:22:59 PM PST 24	Jan 14 12:23:02 PM PST 24	154877272 ps
T142	/workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.3603828774	Jan 14 12:22:01 PM PST 24	Jan 14 12:22:02 PM PST 24	57936976 ps
T143	/workspace/coverage/cover_reg_top/9.uart_intr_test.1534037587	Jan 14 12:23:10 PM PST 24	Jan 14 12:23:15 PM PST 24	33424815 ps
T144	/workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.132627393	Jan 14 12:18:35 PM PST 24	Jan 14 12:18:36 PM PST 24	24275113 ps
T145	/workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.993128001	Jan 14 12:22:43 PM PST 24	Jan 14 12:22:46 PM PST 24	36725505 ps
T146	/workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.2457856994	Jan 14 12:20:31 PM PST 24	Jan 14 12:20:32 PM PST 24	18682073 ps
T44	/workspace/coverage/cover_reg_top/2.uart_csr_aliasing.2757068552	Jan 14 12:23:19 PM PST 24	Jan 14 12:23:25 PM PST 24	29916222 ps
T147	/workspace/coverage/cover_reg_top/5.uart_tl_errors.3216574741	Jan 14 12:19:31 PM PST 24	Jan 14 12:19:34 PM PST 24	131607474 ps
T148	/workspace/coverage/cover_reg_top/27.uart_intr_test.2734828629	Jan 14 12:22:01 PM PST 24	Jan 14 12:22:02 PM PST 24	21112006 ps
T149	/workspace/coverage/cover_reg_top/6.uart_intr_test.3398035272	Jan 14 12:20:19 PM PST 24	Jan 14 12:20:20 PM PST 24	22806012 ps
T150	/workspace/coverage/cover_reg_top/17.uart_intr_test.2720145694	Jan 14 12:22:37 PM PST 24	Jan 14 12:22:38 PM PST 24	39869805 ps
T151	/workspace/coverage/cover_reg_top/1.uart_tl_intg_err.3398462379	Jan 14 12:23:04 PM PST 24	Jan 14 12:23:07 PM PST 24	121396733 ps
T152	/workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.3319642597	Jan 14 12:22:59 PM PST 24	Jan 14 12:23:00 PM PST 24	22581045 ps
T153	/workspace/coverage/cover_reg_top/1.uart_csr_aliasing.2501005806	Jan 14 12:23:19 PM PST 24	Jan 14 12:23:25 PM PST 24	21711333 ps
T154	/workspace/coverage/cover_reg_top/10.uart_tl_intg_err.2973220313	Jan 14 12:22:45 PM PST 24	Jan 14 12:22:48 PM PST 24	333659562 ps
T45	/workspace/coverage/cover_reg_top/8.uart_csr_rw.975005599	Jan 14 12:22:40 PM PST 24	Jan 14 12:22:42 PM PST 24	17485491 ps
T155	/workspace/coverage/cover_reg_top/6.uart_csr_rw.567591586	Jan 14 12:17:43 PM PST 24	Jan 14 12:17:44 PM PST 24	13054544 ps
T156	/workspace/coverage/cover_reg_top/24.uart_intr_test.1970405708	Jan 14 12:22:27 PM PST 24	Jan 14 12:22:29 PM PST 24	13240423 ps
T157	/workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.1078935077	Jan 14 12:18:03 PM PST 24	Jan 14 12:18:05 PM PST 24	68010858 ps
T158	/workspace/coverage/cover_reg_top/12.uart_tl_intg_err.481484430	Jan 14 12:18:40 PM PST 24	Jan 14 12:18:43 PM PST 24	344601309 ps
T159	/workspace/coverage/cover_reg_top/32.uart_intr_test.94897176	Jan 14 12:18:31 PM PST 24	Jan 14 12:18:32 PM PST 24	14846290 ps
T160	/workspace/coverage/cover_reg_top/1.uart_intr_test.3661585711	Jan 14 12:19:33 PM PST 24	Jan 14 12:19:34 PM PST 24	41592237 ps
T161	/workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.3136231304	Jan 14 12:23:10 PM PST 24	Jan 14 12:23:15 PM PST 24	39125772 ps
T162	/workspace/coverage/cover_reg_top/37.uart_intr_test.3294980193	Jan 14 12:19:46 PM PST 24	Jan 14 12:19:47 PM PST 24	13117889 ps
T163	/workspace/coverage/cover_reg_top/40.uart_intr_test.956317334	Jan 14 12:22:13 PM PST 24	Jan 14 12:22:14 PM PST 24	24182752 ps
T164	/workspace/coverage/cover_reg_top/45.uart_intr_test.722325921	Jan 14 12:22:13 PM PST 24	Jan 14 12:22:14 PM PST 24	40072005 ps
T165	/workspace/coverage/cover_reg_top/5.uart_csr_rw.2546544459	Jan 14 12:20:04 PM PST 24	Jan 14 12:20:05 PM PST 24	17869501 ps

Test location	/workspace/coverage/cover_reg_top/0.uart_tl_intg_err.2888236358
Short name	T1
Test name
Test status
Simulation time	1104117948 ps
CPU time	1.04 seconds
Started	Jan 14 12:18:14 PM PST 24
Finished	Jan 14 12:18:15 PM PST 24
Peak memory	198956 kb
Host	smart-79b07386-e881-469b-9876-2e0517487eaa
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888236358 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_intg_err.2888236358
Directory	/workspace/0.uart_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/11.uart_intr_test.192031573
Short name	T9
Test name
Test status
Simulation time	15086204 ps
CPU time	0.6 seconds
Started	Jan 14 12:18:31 PM PST 24
Finished	Jan 14 12:18:32 PM PST 24
Peak memory	185164 kb
Host	smart-c27f387b-8ca0-46d7-b8ab-3f081fbdcf8d
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192031573 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_intr_test.192031573
Directory	/workspace/11.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/17.uart_tl_errors.2624853207
Short name	T5
Test name
Test status
Simulation time	97033443 ps
CPU time	2.04 seconds
Started	Jan 14 12:22:37 PM PST 24
Finished	Jan 14 12:22:40 PM PST 24
Peak memory	199804 kb
Host	smart-89bd7d08-ec80-4ada-b46c-c75539d41f12
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624853207 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_errors.2624853207
Directory	/workspace/17.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.3964010630
Short name	T36
Test name
Test status
Simulation time	18343361 ps
CPU time	0.68 seconds
Started	Jan 14 12:23:12 PM PST 24
Finished	Jan 14 12:23:21 PM PST 24
Peak memory	193632 kb
Host	smart-7fe0ce95-a9b8-4b99-8a87-bb364be8c41b
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964010630 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_hw_reset.3964010630
Directory	/workspace/0.uart_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.2609566157
Short name	T57
Test name
Test status
Simulation time	19139435 ps
CPU time	0.87 seconds
Started	Jan 14 12:23:10 PM PST 24
Finished	Jan 14 12:23:16 PM PST 24
Peak memory	196756 kb
Host	smart-653763c5-b8ca-471b-b043-a2c2819f285f
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609566157 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_same_csr _outstanding.2609566157
Directory	/workspace/4.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/13.uart_csr_rw.2305023799
Short name	T37
Test name
Test status
Simulation time	31379959 ps
CPU time	0.65 seconds
Started	Jan 14 12:23:02 PM PST 24
Finished	Jan 14 12:23:04 PM PST 24
Peak memory	194752 kb
Host	smart-89999fdd-e76b-4559-9062-dd311a2a551b
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305023799 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_csr_rw.2305023799
Directory	/workspace/13.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/17.uart_tl_intg_err.490274788
Short name	T4
Test name
Test status
Simulation time	291847292 ps
CPU time	0.98 seconds
Started	Jan 14 12:22:14 PM PST 24
Finished	Jan 14 12:22:16 PM PST 24
Peak memory	197424 kb
Host	smart-6c5a7f17-66e0-4c04-b2c5-74773d479357
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490274788 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_intg_err.490274788
Directory	/workspace/17.uart_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/49.uart_intr_test.1447861851
Short name	T71
Test name
Test status
Simulation time	14250374 ps
CPU time	0.56 seconds
Started	Jan 14 12:19:14 PM PST 24
Finished	Jan 14 12:19:16 PM PST 24
Peak memory	184808 kb
Host	smart-f33937b0-ec3a-486f-b363-b831cac51487
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447861851 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.uart_intr_test.1447861851
Directory	/workspace/49.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.3368755736
Short name	T6
Test name
Test status
Simulation time	1043944455 ps
CPU time	1.15 seconds
Started	Jan 14 12:23:01 PM PST 24
Finished	Jan 14 12:23:03 PM PST 24
Peak memory	195332 kb
Host	smart-a6c4205d-db26-4724-b941-9d60e3e07d9c
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368755736 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_hw_reset.3368755736
Directory	/workspace/1.uart_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.3894612213
Short name	T82
Test name
Test status
Simulation time	88147827 ps
CPU time	1.23 seconds
Started	Jan 14 12:20:28 PM PST 24
Finished	Jan 14 12:20:29 PM PST 24
Peak memory	199956 kb
Host	smart-425a74fc-969b-4a2c-a985-19c11e3f9dc4
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894612213 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_csr_mem_rw_with_rand_reset.3894612213
Directory	/workspace/16.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/8.uart_tl_intg_err.2816253512
Short name	T70
Test name
Test status
Simulation time	163075164 ps
CPU time	1.25 seconds
Started	Jan 14 12:20:13 PM PST 24
Finished	Jan 14 12:20:14 PM PST 24
Peak memory	199188 kb
Host	smart-33738494-6b53-4244-b349-b9f66ec86c69
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816253512 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_intg_err.2816253512
Directory	/workspace/8.uart_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/3.uart_intr_test.4255622561
Short name	T73
Test name
Test status
Simulation time	22466806 ps
CPU time	0.67 seconds
Started	Jan 14 12:19:46 PM PST 24
Finished	Jan 14 12:19:48 PM PST 24
Peak memory	185040 kb
Host	smart-2c449554-6656-40c2-8f57-ab8780c983be
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255622561 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_intr_test.4255622561
Directory	/workspace/3.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/28.uart_intr_test.248701634
Short name	T75
Test name
Test status
Simulation time	13765960 ps
CPU time	0.64 seconds
Started	Jan 14 12:22:01 PM PST 24
Finished	Jan 14 12:22:02 PM PST 24
Peak memory	182888 kb
Host	smart-09b8b91e-c52b-4a33-bffb-bcb751e6534a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248701634 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.uart_intr_test.248701634
Directory	/workspace/28.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.2240625710
Short name	T2
Test name
Test status
Simulation time	78065677 ps
CPU time	0.66 seconds
Started	Jan 14 12:19:09 PM PST 24
Finished	Jan 14 12:19:14 PM PST 24
Peak memory	195792 kb
Host	smart-bb132730-6ecc-40d2-92bd-6572d7a56cb5
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240625710 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_same_cs r_outstanding.2240625710
Directory	/workspace/10.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/0.uart_csr_aliasing.1755264517
Short name	T105
Test name
Test status
Simulation time	23618249 ps
CPU time	0.63 seconds
Started	Jan 14 12:22:47 PM PST 24
Finished	Jan 14 12:22:48 PM PST 24
Peak memory	195352 kb
Host	smart-83470157-91ba-4709-b5fd-2ddadeb351a1
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755264517 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_aliasing.1755264517
Directory	/workspace/0.uart_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.3363646986
Short name	T138
Test name
Test status
Simulation time	2745780990 ps
CPU time	2.51 seconds
Started	Jan 14 12:23:27 PM PST 24
Finished	Jan 14 12:23:31 PM PST 24
Peak memory	197756 kb
Host	smart-ec6488db-63de-419b-b3e9-556fadcdae72
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363646986 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_bit_bash.3363646986
Directory	/workspace/0.uart_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.3359168942
Short name	T50
Test name
Test status
Simulation time	20527087 ps
CPU time	0.8 seconds
Started	Jan 14 12:22:25 PM PST 24
Finished	Jan 14 12:22:26 PM PST 24
Peak memory	197152 kb
Host	smart-b4320d8b-edb1-4283-a4e9-ed7b71e8e25e
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359168942 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_mem_rw_with_rand_reset.3359168942
Directory	/workspace/0.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.uart_csr_rw.1917998642
Short name	T33
Test name
Test status
Simulation time	52738741 ps
CPU time	0.69 seconds
Started	Jan 14 12:23:12 PM PST 24
Finished	Jan 14 12:23:21 PM PST 24
Peak memory	193504 kb
Host	smart-b5b11982-fc30-4a7e-b59d-540529363ff3
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917998642 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_rw.1917998642
Directory	/workspace/0.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/0.uart_intr_test.2968136033
Short name	T137
Test name
Test status
Simulation time	50294568 ps
CPU time	0.56 seconds
Started	Jan 14 12:23:41 PM PST 24
Finished	Jan 14 12:23:42 PM PST 24
Peak memory	185056 kb
Host	smart-43a019a6-d95c-4e7d-b707-542769b5b5e5
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968136033 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_intr_test.2968136033
Directory	/workspace/0.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.3264164562
Short name	T98
Test name
Test status
Simulation time	89051080 ps
CPU time	0.8 seconds
Started	Jan 14 12:19:30 PM PST 24
Finished	Jan 14 12:19:31 PM PST 24
Peak memory	197000 kb
Host	smart-230c38df-4054-4ca4-ac86-84fc5206ab25
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264164562 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_same_csr _outstanding.3264164562
Directory	/workspace/0.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/0.uart_tl_errors.1556386876
Short name	T128
Test name
Test status
Simulation time	31936936 ps
CPU time	1.64 seconds
Started	Jan 14 12:22:47 PM PST 24
Finished	Jan 14 12:22:53 PM PST 24
Peak memory	199908 kb
Host	smart-43487202-a92b-4c95-8d80-b95209390d3b
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556386876 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_errors.1556386876
Directory	/workspace/0.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/1.uart_csr_aliasing.2501005806
Short name	T153
Test name
Test status
Simulation time	21711333 ps
CPU time	0.65 seconds
Started	Jan 14 12:23:19 PM PST 24
Finished	Jan 14 12:23:25 PM PST 24
Peak memory	194928 kb
Host	smart-ef28f8de-da66-440f-9e7a-d43f708f0c6c
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501005806 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_aliasing.2501005806
Directory	/workspace/1.uart_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.2316641806
Short name	T48
Test name
Test status
Simulation time	220027586 ps
CPU time	2.2 seconds
Started	Jan 14 12:22:58 PM PST 24
Finished	Jan 14 12:23:01 PM PST 24
Peak memory	196872 kb
Host	smart-a0ff8601-dc81-47de-8b0d-596b0b6868b9
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316641806 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_bit_bash.2316641806
Directory	/workspace/1.uart_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.2522402948
Short name	T63
Test name
Test status
Simulation time	36038108 ps
CPU time	0.82 seconds
Started	Jan 14 12:23:19 PM PST 24
Finished	Jan 14 12:23:25 PM PST 24
Peak memory	195404 kb
Host	smart-390f2234-fe0f-4e3e-afb3-c67d2c888ca9
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522402948 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_mem_rw_with_rand_reset.2522402948
Directory	/workspace/1.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.uart_csr_rw.1139992669
Short name	T88
Test name
Test status
Simulation time	12354823 ps
CPU time	0.56 seconds
Started	Jan 14 12:23:01 PM PST 24
Finished	Jan 14 12:23:03 PM PST 24
Peak memory	195344 kb
Host	smart-438571d3-6768-485a-8bf0-4eda7c6433bd
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139992669 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_rw.1139992669
Directory	/workspace/1.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/1.uart_intr_test.3661585711
Short name	T160
Test name
Test status
Simulation time	41592237 ps
CPU time	0.58 seconds
Started	Jan 14 12:19:33 PM PST 24
Finished	Jan 14 12:19:34 PM PST 24
Peak memory	194376 kb
Host	smart-a26bbdd2-8e7a-4204-bafd-33a392935df0
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661585711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_intr_test.3661585711
Directory	/workspace/1.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.2585798953
Short name	T26
Test name
Test status
Simulation time	38384247 ps
CPU time	0.63 seconds
Started	Jan 14 12:20:20 PM PST 24
Finished	Jan 14 12:20:22 PM PST 24
Peak memory	195540 kb
Host	smart-577cf626-0dea-4faf-9d24-5b452931d54b
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585798953 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_same_csr _outstanding.2585798953
Directory	/workspace/1.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/1.uart_tl_errors.966962594
Short name	T25
Test name
Test status
Simulation time	181583897 ps
CPU time	2.21 seconds
Started	Jan 14 12:22:25 PM PST 24
Finished	Jan 14 12:22:28 PM PST 24
Peak memory	198600 kb
Host	smart-32f4fe1b-ba22-4ed0-875d-d9eb726d2e10
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966962594 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_errors.966962594
Directory	/workspace/1.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/1.uart_tl_intg_err.3398462379
Short name	T151
Test name
Test status
Simulation time	121396733 ps
CPU time	1.41 seconds
Started	Jan 14 12:23:04 PM PST 24
Finished	Jan 14 12:23:07 PM PST 24
Peak memory	198444 kb
Host	smart-9dbb7101-46ed-4cfc-aa56-cec5088195cf
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398462379 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_intg_err.3398462379
Directory	/workspace/1.uart_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.4002256369
Short name	T112
Test name
Test status
Simulation time	257220775 ps
CPU time	1.08 seconds
Started	Jan 14 12:23:07 PM PST 24
Finished	Jan 14 12:23:11 PM PST 24
Peak memory	199920 kb
Host	smart-38642f90-a560-4399-bd5c-f691cecd8a4e
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002256369 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_csr_mem_rw_with_rand_reset.4002256369
Directory	/workspace/10.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/10.uart_csr_rw.1289375152
Short name	T54
Test name
Test status
Simulation time	19966491 ps
CPU time	0.65 seconds
Started	Jan 14 12:23:12 PM PST 24
Finished	Jan 14 12:23:21 PM PST 24
Peak memory	195376 kb
Host	smart-01e52f71-4943-4ffd-b67a-a158d4410b64
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289375152 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_csr_rw.1289375152
Directory	/workspace/10.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/10.uart_intr_test.3428855786
Short name	T134
Test name
Test status
Simulation time	51282312 ps
CPU time	0.61 seconds
Started	Jan 14 12:18:28 PM PST 24
Finished	Jan 14 12:18:29 PM PST 24
Peak memory	194252 kb
Host	smart-2ceb8ffb-4ef2-4cbc-b6c1-f727e9b5d524
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428855786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_intr_test.3428855786
Directory	/workspace/10.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/10.uart_tl_errors.4085458796
Short name	T19
Test name
Test status
Simulation time	1005837513 ps
CPU time	2.28 seconds
Started	Jan 14 12:23:10 PM PST 24
Finished	Jan 14 12:23:17 PM PST 24
Peak memory	198840 kb
Host	smart-b67011d7-ed4e-4705-8332-f3c06621a3f5
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085458796 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_errors.4085458796
Directory	/workspace/10.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/10.uart_tl_intg_err.2973220313
Short name	T154
Test name
Test status
Simulation time	333659562 ps
CPU time	1.42 seconds
Started	Jan 14 12:22:45 PM PST 24
Finished	Jan 14 12:22:48 PM PST 24
Peak memory	197884 kb
Host	smart-0cd73bd5-12fb-4042-9111-09a64db0d0a7
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973220313 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_intg_err.2973220313
Directory	/workspace/10.uart_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.1743946032
Short name	T117
Test name
Test status
Simulation time	59621402 ps
CPU time	1.42 seconds
Started	Jan 14 12:19:10 PM PST 24
Finished	Jan 14 12:19:16 PM PST 24
Peak memory	200088 kb
Host	smart-a3260f22-2821-4414-abe4-b82beaeb8b3a
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743946032 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_csr_mem_rw_with_rand_reset.1743946032
Directory	/workspace/11.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/11.uart_csr_rw.1557449498
Short name	T104
Test name
Test status
Simulation time	28397831 ps
CPU time	0.67 seconds
Started	Jan 14 12:19:30 PM PST 24
Finished	Jan 14 12:19:31 PM PST 24
Peak memory	195660 kb
Host	smart-9b36bf56-7c4a-4373-8a1e-20d2ad5d278f
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557449498 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_csr_rw.1557449498
Directory	/workspace/11.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.4136216988
Short name	T40
Test name
Test status
Simulation time	125914535 ps
CPU time	0.76 seconds
Started	Jan 14 12:20:25 PM PST 24
Finished	Jan 14 12:20:26 PM PST 24
Peak memory	196896 kb
Host	smart-5028fd7b-d32c-4e83-83ed-f4fb8fa02904
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136216988 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_same_cs r_outstanding.4136216988
Directory	/workspace/11.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/11.uart_tl_errors.2212962433
Short name	T89
Test name
Test status
Simulation time	290259004 ps
CPU time	1.96 seconds
Started	Jan 14 12:23:08 PM PST 24
Finished	Jan 14 12:23:13 PM PST 24
Peak memory	199904 kb
Host	smart-6505d624-2525-47df-8ba7-22d95694bb8b
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212962433 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_errors.2212962433
Directory	/workspace/11.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/11.uart_tl_intg_err.3226640059
Short name	T20
Test name
Test status
Simulation time	75158898 ps
CPU time	1.02 seconds
Started	Jan 14 12:23:31 PM PST 24
Finished	Jan 14 12:23:33 PM PST 24
Peak memory	197796 kb
Host	smart-c1e74727-f787-4a91-805a-a0498c2baa45
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226640059 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_intg_err.3226640059
Directory	/workspace/11.uart_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.3131730354
Short name	T99
Test name
Test status
Simulation time	28344939 ps
CPU time	0.76 seconds
Started	Jan 14 12:23:12 PM PST 24
Finished	Jan 14 12:23:21 PM PST 24
Peak memory	197436 kb
Host	smart-246d8f76-5d6e-45d4-953c-0fa74bff678b
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131730354 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_csr_mem_rw_with_rand_reset.3131730354
Directory	/workspace/12.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/12.uart_csr_rw.3629701904
Short name	T92
Test name
Test status
Simulation time	50516092 ps
CPU time	0.69 seconds
Started	Jan 14 12:22:59 PM PST 24
Finished	Jan 14 12:23:00 PM PST 24
Peak memory	195352 kb
Host	smart-bcdc1954-9134-4e3f-b9bb-1a967b2cca4e
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629701904 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_csr_rw.3629701904
Directory	/workspace/12.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/12.uart_intr_test.1827240983
Short name	T52
Test name
Test status
Simulation time	30568621 ps
CPU time	0.57 seconds
Started	Jan 14 12:18:41 PM PST 24
Finished	Jan 14 12:18:43 PM PST 24
Peak memory	185180 kb
Host	smart-80ba6e21-2cf7-44d8-ba5b-207ff6206185
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827240983 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_intr_test.1827240983
Directory	/workspace/12.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.132627393
Short name	T144
Test name
Test status
Simulation time	24275113 ps
CPU time	0.65 seconds
Started	Jan 14 12:18:35 PM PST 24
Finished	Jan 14 12:18:36 PM PST 24
Peak memory	195728 kb
Host	smart-69188259-a30a-4272-8daf-a265717693e1
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132627393 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_same_csr _outstanding.132627393
Directory	/workspace/12.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/12.uart_tl_errors.1942980212
Short name	T131
Test name
Test status
Simulation time	122753636 ps
CPU time	1.55 seconds
Started	Jan 14 12:18:28 PM PST 24
Finished	Jan 14 12:18:30 PM PST 24
Peak memory	199872 kb
Host	smart-cd8b9681-a346-4549-894d-dd72c3ec4023
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942980212 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_errors.1942980212
Directory	/workspace/12.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/12.uart_tl_intg_err.481484430
Short name	T158
Test name
Test status
Simulation time	344601309 ps
CPU time	1.37 seconds
Started	Jan 14 12:18:40 PM PST 24
Finished	Jan 14 12:18:43 PM PST 24
Peak memory	199300 kb
Host	smart-75d74b6e-0c81-4550-be62-070146443f1f
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481484430 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_intg_err.481484430
Directory	/workspace/12.uart_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.1156401434
Short name	T79
Test name
Test status
Simulation time	24977427 ps
CPU time	0.79 seconds
Started	Jan 14 12:23:42 PM PST 24
Finished	Jan 14 12:23:44 PM PST 24
Peak memory	199464 kb
Host	smart-b40010eb-08a2-4c9c-b189-a20937f17fb9
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156401434 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_csr_mem_rw_with_rand_reset.1156401434
Directory	/workspace/13.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/13.uart_intr_test.3511038914
Short name	T77
Test name
Test status
Simulation time	53497663 ps
CPU time	0.56 seconds
Started	Jan 14 12:19:06 PM PST 24
Finished	Jan 14 12:19:07 PM PST 24
Peak memory	185068 kb
Host	smart-72769603-af32-4949-b1a4-81d9a0f4910e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511038914 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_intr_test.3511038914
Directory	/workspace/13.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.2902707342
Short name	T136
Test name
Test status
Simulation time	55682372 ps
CPU time	0.68 seconds
Started	Jan 14 12:23:15 PM PST 24
Finished	Jan 14 12:23:21 PM PST 24
Peak memory	194700 kb
Host	smart-9aab4614-498b-4328-ab5c-13949dfa6f79
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902707342 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_same_cs r_outstanding.2902707342
Directory	/workspace/13.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/13.uart_tl_errors.864688629
Short name	T140
Test name
Test status
Simulation time	73397599 ps
CPU time	1.13 seconds
Started	Jan 14 12:23:12 PM PST 24
Finished	Jan 14 12:23:21 PM PST 24
Peak memory	199508 kb
Host	smart-b28c1562-b9f1-42b3-8ef2-94e614787d4e
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864688629 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_errors.864688629
Directory	/workspace/13.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/13.uart_tl_intg_err.138236353
Short name	T60
Test name
Test status
Simulation time	592237533 ps
CPU time	1.34 seconds
Started	Jan 14 12:18:03 PM PST 24
Finished	Jan 14 12:18:05 PM PST 24
Peak memory	199036 kb
Host	smart-673723d3-1ebe-460d-a5cc-33aa1a9dbeb6
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138236353 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_intg_err.138236353
Directory	/workspace/13.uart_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.1078935077
Short name	T157
Test name
Test status
Simulation time	68010858 ps
CPU time	0.99 seconds
Started	Jan 14 12:18:03 PM PST 24
Finished	Jan 14 12:18:05 PM PST 24
Peak memory	199768 kb
Host	smart-f153981c-f5e2-4bf3-ae49-63dcdc2fe16e
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078935077 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_csr_mem_rw_with_rand_reset.1078935077
Directory	/workspace/14.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/14.uart_csr_rw.3783657654
Short name	T22
Test name
Test status
Simulation time	14114390 ps
CPU time	0.64 seconds
Started	Jan 14 12:23:43 PM PST 24
Finished	Jan 14 12:23:44 PM PST 24
Peak memory	195280 kb
Host	smart-38a51686-a16a-4d15-84b4-118741b2ed41
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783657654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_csr_rw.3783657654
Directory	/workspace/14.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/14.uart_intr_test.3209969336
Short name	T81
Test name
Test status
Simulation time	20309776 ps
CPU time	0.56 seconds
Started	Jan 14 12:19:35 PM PST 24
Finished	Jan 14 12:19:36 PM PST 24
Peak memory	185060 kb
Host	smart-cd724777-09d7-4349-ba84-24e70816048e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209969336 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_intr_test.3209969336
Directory	/workspace/14.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.3062064442
Short name	T129
Test name
Test status
Simulation time	37466582 ps
CPU time	0.61 seconds
Started	Jan 14 12:23:42 PM PST 24
Finished	Jan 14 12:23:44 PM PST 24
Peak memory	195612 kb
Host	smart-ed1de475-1246-4521-99ed-25089b9abef3
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062064442 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_same_cs r_outstanding.3062064442
Directory	/workspace/14.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/14.uart_tl_errors.3247003068
Short name	T96
Test name
Test status
Simulation time	140791607 ps
CPU time	1.25 seconds
Started	Jan 14 12:21:46 PM PST 24
Finished	Jan 14 12:21:48 PM PST 24
Peak memory	199156 kb
Host	smart-64d2822c-98fa-44ae-a24f-fc12c4d5b801
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247003068 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_errors.3247003068
Directory	/workspace/14.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/14.uart_tl_intg_err.2418900665
Short name	T67
Test name
Test status
Simulation time	116738800 ps
CPU time	0.98 seconds
Started	Jan 14 12:23:42 PM PST 24
Finished	Jan 14 12:23:44 PM PST 24
Peak memory	198808 kb
Host	smart-582569e1-40cd-48ac-95e4-acf93626e008
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418900665 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_intg_err.2418900665
Directory	/workspace/14.uart_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.2768857090
Short name	T118
Test name
Test status
Simulation time	106996825 ps
CPU time	0.67 seconds
Started	Jan 14 12:19:46 PM PST 24
Finished	Jan 14 12:19:47 PM PST 24
Peak memory	196832 kb
Host	smart-08bb4888-f693-4868-8dc0-bbf8e9d3b246
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768857090 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_csr_mem_rw_with_rand_reset.2768857090
Directory	/workspace/15.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/15.uart_csr_rw.1354170536
Short name	T101
Test name
Test status
Simulation time	36254096 ps
CPU time	0.57 seconds
Started	Jan 14 12:17:58 PM PST 24
Finished	Jan 14 12:17:59 PM PST 24
Peak memory	195360 kb
Host	smart-a2f59133-8fd5-4da5-bfcd-0baace533af8
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354170536 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_csr_rw.1354170536
Directory	/workspace/15.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/15.uart_intr_test.4196355327
Short name	T72
Test name
Test status
Simulation time	35907155 ps
CPU time	0.56 seconds
Started	Jan 14 12:22:01 PM PST 24
Finished	Jan 14 12:22:02 PM PST 24
Peak memory	184144 kb
Host	smart-b1ed71f6-79be-4269-a86c-e3f77e54ebdd
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196355327 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_intr_test.4196355327
Directory	/workspace/15.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.447591287
Short name	T34
Test name
Test status
Simulation time	16388286 ps
CPU time	0.75 seconds
Started	Jan 14 12:22:59 PM PST 24
Finished	Jan 14 12:23:01 PM PST 24
Peak memory	193656 kb
Host	smart-d3fd4358-18a2-4511-8937-8863c54d97e0
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447591287 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_same_csr _outstanding.447591287
Directory	/workspace/15.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/15.uart_tl_errors.306943811
Short name	T141
Test name
Test status
Simulation time	154877272 ps
CPU time	1.93 seconds
Started	Jan 14 12:22:59 PM PST 24
Finished	Jan 14 12:23:02 PM PST 24
Peak memory	197860 kb
Host	smart-813193f6-b2b8-48f7-96a1-7131c41ab783
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306943811 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_errors.306943811
Directory	/workspace/15.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/15.uart_tl_intg_err.2304772039
Short name	T58
Test name
Test status
Simulation time	380889991 ps
CPU time	1.22 seconds
Started	Jan 14 12:22:25 PM PST 24
Finished	Jan 14 12:22:27 PM PST 24
Peak memory	197696 kb
Host	smart-142d555e-70b6-44ef-bf70-3483306e4b94
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304772039 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_intg_err.2304772039
Directory	/workspace/15.uart_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/16.uart_csr_rw.2358172845
Short name	T29
Test name
Test status
Simulation time	216279898 ps
CPU time	0.57 seconds
Started	Jan 14 12:22:37 PM PST 24
Finished	Jan 14 12:22:38 PM PST 24
Peak memory	195256 kb
Host	smart-949b2c75-777b-409c-bd9c-725c07e96975
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358172845 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_csr_rw.2358172845
Directory	/workspace/16.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/16.uart_intr_test.4100799639
Short name	T11
Test name
Test status
Simulation time	47501469 ps
CPU time	0.58 seconds
Started	Jan 14 12:22:34 PM PST 24
Finished	Jan 14 12:22:35 PM PST 24
Peak memory	183540 kb
Host	smart-aebdb891-1184-4259-8a8f-ad306360cb21
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100799639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_intr_test.4100799639
Directory	/workspace/16.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.2538932833
Short name	T80
Test name
Test status
Simulation time	101291583 ps
CPU time	0.82 seconds
Started	Jan 14 12:22:54 PM PST 24
Finished	Jan 14 12:22:56 PM PST 24
Peak memory	197564 kb
Host	smart-d6b3de6b-0e02-42f3-953c-4d7a113e3f40
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538932833 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_same_cs r_outstanding.2538932833
Directory	/workspace/16.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/16.uart_tl_errors.2073507321
Short name	T114
Test name
Test status
Simulation time	763339134 ps
CPU time	2.26 seconds
Started	Jan 14 12:22:59 PM PST 24
Finished	Jan 14 12:23:02 PM PST 24
Peak memory	197980 kb
Host	smart-111ec16a-1953-4a88-a0b4-f2723345ac12
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073507321 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_errors.2073507321
Directory	/workspace/16.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/16.uart_tl_intg_err.2867336341
Short name	T68
Test name
Test status
Simulation time	349434529 ps
CPU time	1.37 seconds
Started	Jan 14 12:22:59 PM PST 24
Finished	Jan 14 12:23:01 PM PST 24
Peak memory	197504 kb
Host	smart-66841317-1921-4120-a7a8-20cfbcb4ec05
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867336341 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_intg_err.2867336341
Directory	/workspace/16.uart_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.2043455097
Short name	T32
Test name
Test status
Simulation time	88775753 ps
CPU time	0.7 seconds
Started	Jan 14 12:22:12 PM PST 24
Finished	Jan 14 12:22:14 PM PST 24
Peak memory	196456 kb
Host	smart-0060311d-b494-4ff3-acb2-25fa24b78a9c
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043455097 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_csr_mem_rw_with_rand_reset.2043455097
Directory	/workspace/17.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/17.uart_csr_rw.776844797
Short name	T38
Test name
Test status
Simulation time	43257191 ps
CPU time	0.58 seconds
Started	Jan 14 12:20:28 PM PST 24
Finished	Jan 14 12:20:29 PM PST 24
Peak memory	195396 kb
Host	smart-d50e45b9-05a9-49a5-b55e-0a9c012ab730
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776844797 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_csr_rw.776844797
Directory	/workspace/17.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/17.uart_intr_test.2720145694
Short name	T150
Test name
Test status
Simulation time	39869805 ps
CPU time	0.58 seconds
Started	Jan 14 12:22:37 PM PST 24
Finished	Jan 14 12:22:38 PM PST 24
Peak memory	194196 kb
Host	smart-e9a48a5f-3fc4-4a11-a787-cf28fb60bfda
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720145694 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_intr_test.2720145694
Directory	/workspace/17.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.3437660493
Short name	T132
Test name
Test status
Simulation time	59789654 ps
CPU time	0.76 seconds
Started	Jan 14 12:22:37 PM PST 24
Finished	Jan 14 12:22:38 PM PST 24
Peak memory	196748 kb
Host	smart-0a7da6d5-1c87-456c-82f6-d8a37b691703
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437660493 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_same_cs r_outstanding.3437660493
Directory	/workspace/17.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.2457856994
Short name	T146
Test name
Test status
Simulation time	18682073 ps
CPU time	0.85 seconds
Started	Jan 14 12:20:31 PM PST 24
Finished	Jan 14 12:20:32 PM PST 24
Peak memory	199564 kb
Host	smart-d95febe6-0f08-469d-bc24-daf5bc65827a
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457856994 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_csr_mem_rw_with_rand_reset.2457856994
Directory	/workspace/18.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/18.uart_csr_rw.3469128840
Short name	T113
Test name
Test status
Simulation time	12377863 ps
CPU time	0.59 seconds
Started	Jan 14 12:22:34 PM PST 24
Finished	Jan 14 12:22:35 PM PST 24
Peak memory	193732 kb
Host	smart-ec8500bb-d7e3-4b18-8cf1-5be069648dbc
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469128840 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_csr_rw.3469128840
Directory	/workspace/18.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/18.uart_intr_test.1789070623
Short name	T107
Test name
Test status
Simulation time	12480070 ps
CPU time	0.57 seconds
Started	Jan 14 12:22:34 PM PST 24
Finished	Jan 14 12:22:35 PM PST 24
Peak memory	183164 kb
Host	smart-5b290e62-aa92-4acb-ad63-b29b07eaa73b
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789070623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_intr_test.1789070623
Directory	/workspace/18.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.3603828774
Short name	T142
Test name
Test status
Simulation time	57936976 ps
CPU time	0.84 seconds
Started	Jan 14 12:22:01 PM PST 24
Finished	Jan 14 12:22:02 PM PST 24
Peak memory	194060 kb
Host	smart-d61cb5e2-ff2b-4c0e-9c84-5969fef3dc94
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603828774 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_same_cs r_outstanding.3603828774
Directory	/workspace/18.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/18.uart_tl_errors.3355794139
Short name	T16
Test name
Test status
Simulation time	80072065 ps
CPU time	2.19 seconds
Started	Jan 14 12:18:15 PM PST 24
Finished	Jan 14 12:18:17 PM PST 24
Peak memory	200136 kb
Host	smart-12befdb1-5843-4e6b-a595-9cab24644a06
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355794139 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_errors.3355794139
Directory	/workspace/18.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/18.uart_tl_intg_err.2731356418
Short name	T53
Test name
Test status
Simulation time	471181772 ps
CPU time	0.93 seconds
Started	Jan 14 12:22:37 PM PST 24
Finished	Jan 14 12:22:38 PM PST 24
Peak memory	198416 kb
Host	smart-9a93fc03-6287-4de9-b0a7-b0b087c1127e
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731356418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_intg_err.2731356418
Directory	/workspace/18.uart_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.2929350088
Short name	T109
Test name
Test status
Simulation time	17732763 ps
CPU time	0.74 seconds
Started	Jan 14 12:20:20 PM PST 24
Finished	Jan 14 12:20:21 PM PST 24
Peak memory	198728 kb
Host	smart-4e9c5572-5459-4cf9-a753-171bea9d4b4a
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929350088 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_csr_mem_rw_with_rand_reset.2929350088
Directory	/workspace/19.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/19.uart_csr_rw.4248188258
Short name	T47
Test name
Test status
Simulation time	16796686 ps
CPU time	0.64 seconds
Started	Jan 14 12:20:43 PM PST 24
Finished	Jan 14 12:20:44 PM PST 24
Peak memory	195464 kb
Host	smart-62074b38-a354-4a89-b337-9a8769b88ce9
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248188258 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_csr_rw.4248188258
Directory	/workspace/19.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/19.uart_intr_test.950634193
Short name	T74
Test name
Test status
Simulation time	82906928 ps
CPU time	0.56 seconds
Started	Jan 14 12:19:31 PM PST 24
Finished	Jan 14 12:19:32 PM PST 24
Peak memory	185064 kb
Host	smart-e78b6a06-5b76-4ad4-9c4d-b7b446ffaf35
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950634193 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_intr_test.950634193
Directory	/workspace/19.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.148719565
Short name	T15
Test name
Test status
Simulation time	41875865 ps
CPU time	0.65 seconds
Started	Jan 14 12:20:36 PM PST 24
Finished	Jan 14 12:20:37 PM PST 24
Peak memory	195500 kb
Host	smart-4bdf79d5-d37a-4b97-a88d-d2579d46ab9f
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148719565 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_same_csr _outstanding.148719565
Directory	/workspace/19.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/19.uart_tl_errors.1693717170
Short name	T17
Test name
Test status
Simulation time	132284721 ps
CPU time	2.17 seconds
Started	Jan 14 12:22:50 PM PST 24
Finished	Jan 14 12:22:54 PM PST 24
Peak memory	199188 kb
Host	smart-b00a7cf3-c02f-49b2-bd4f-fa15ece8d298
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693717170 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_errors.1693717170
Directory	/workspace/19.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/19.uart_tl_intg_err.4133387029
Short name	T59
Test name
Test status
Simulation time	87221280 ps
CPU time	1.33 seconds
Started	Jan 14 12:22:01 PM PST 24
Finished	Jan 14 12:22:03 PM PST 24
Peak memory	197408 kb
Host	smart-3a79a380-bad1-409b-971e-8bf51d7a548b
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133387029 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_intg_err.4133387029
Directory	/workspace/19.uart_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/2.uart_csr_aliasing.2757068552
Short name	T44
Test name
Test status
Simulation time	29916222 ps
CPU time	0.88 seconds
Started	Jan 14 12:23:19 PM PST 24
Finished	Jan 14 12:23:25 PM PST 24
Peak memory	195188 kb
Host	smart-ada839ab-e77b-486d-baf9-955d23537458
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757068552 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_aliasing.2757068552
Directory	/workspace/2.uart_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.108499
Short name	T46
Test name
Test status
Simulation time	93171449 ps
CPU time	1.47 seconds
Started	Jan 14 12:20:36 PM PST 24
Finished	Jan 14 12:20:38 PM PST 24
Peak memory	197720 kb
Host	smart-ec636483-6cd3-4131-9a1d-be019a4ba278
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108499 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_bit_bash.108499
Directory	/workspace/2.uart_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.261018994
Short name	T55
Test name
Test status
Simulation time	47332020 ps
CPU time	0.66 seconds
Started	Jan 14 12:22:59 PM PST 24
Finished	Jan 14 12:23:00 PM PST 24
Peak memory	195244 kb
Host	smart-fa299879-60fd-494b-98db-9946d4760d54
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261018994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_hw_reset.261018994
Directory	/workspace/2.uart_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.445165642
Short name	T85
Test name
Test status
Simulation time	73840199 ps
CPU time	1.08 seconds
Started	Jan 14 12:18:01 PM PST 24
Finished	Jan 14 12:18:03 PM PST 24
Peak memory	200060 kb
Host	smart-63a22953-503e-4076-b66d-20c812fdd570
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445165642 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_mem_rw_with_rand_reset.445165642
Directory	/workspace/2.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.uart_csr_rw.548114246
Short name	T23
Test name
Test status
Simulation time	27254081 ps
CPU time	0.68 seconds
Started	Jan 14 12:23:19 PM PST 24
Finished	Jan 14 12:23:25 PM PST 24
Peak memory	193724 kb
Host	smart-05143008-3cfd-43cb-b6cf-e14a146700b5
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548114246 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_rw.548114246
Directory	/workspace/2.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/2.uart_intr_test.2621440725
Short name	T115
Test name
Test status
Simulation time	40027896 ps
CPU time	0.59 seconds
Started	Jan 14 12:16:47 PM PST 24
Finished	Jan 14 12:16:48 PM PST 24
Peak memory	184812 kb
Host	smart-6504ac79-da93-49fc-aaf0-46c0854e3f51
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621440725 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_intr_test.2621440725
Directory	/workspace/2.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.4059336026
Short name	T130
Test name
Test status
Simulation time	49455630 ps
CPU time	0.76 seconds
Started	Jan 14 12:22:59 PM PST 24
Finished	Jan 14 12:23:00 PM PST 24
Peak memory	196608 kb
Host	smart-a410ba8b-1682-4c20-a7d1-ab0b7c9aaa6a
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059336026 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_same_csr _outstanding.4059336026
Directory	/workspace/2.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/2.uart_tl_errors.2960248748
Short name	T110
Test name
Test status
Simulation time	78951895 ps
CPU time	1.73 seconds
Started	Jan 14 12:19:04 PM PST 24
Finished	Jan 14 12:19:06 PM PST 24
Peak memory	199940 kb
Host	smart-943d5b37-d9e1-489d-84e2-064dc84e8a2c
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960248748 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_errors.2960248748
Directory	/workspace/2.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/2.uart_tl_intg_err.1911884383
Short name	T123
Test name
Test status
Simulation time	549811229 ps
CPU time	1.24 seconds
Started	Jan 14 12:17:28 PM PST 24
Finished	Jan 14 12:17:30 PM PST 24
Peak memory	199120 kb
Host	smart-ec8bfd54-3c36-4bdd-9e0b-c75d704e80cf
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911884383 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_intg_err.1911884383
Directory	/workspace/2.uart_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/20.uart_intr_test.2406557959
Short name	T86
Test name
Test status
Simulation time	46546832 ps
CPU time	0.57 seconds
Started	Jan 14 12:22:50 PM PST 24
Finished	Jan 14 12:22:53 PM PST 24
Peak memory	184548 kb
Host	smart-90d45840-7611-4663-be3a-8d7e78834101
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406557959 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.uart_intr_test.2406557959
Directory	/workspace/20.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/21.uart_intr_test.2740469157
Short name	T102
Test name
Test status
Simulation time	139190244 ps
CPU time	0.54 seconds
Started	Jan 14 12:22:14 PM PST 24
Finished	Jan 14 12:22:16 PM PST 24
Peak memory	194296 kb
Host	smart-9e925c04-692d-477a-a48a-ef3e6acba873
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740469157 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.uart_intr_test.2740469157
Directory	/workspace/21.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/22.uart_intr_test.1539995746
Short name	T8
Test name
Test status
Simulation time	20306506 ps
CPU time	0.61 seconds
Started	Jan 14 12:22:27 PM PST 24
Finished	Jan 14 12:22:29 PM PST 24
Peak memory	183728 kb
Host	smart-f823dc6d-5b45-43c2-bf50-51e8d84a1a86
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539995746 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.uart_intr_test.1539995746
Directory	/workspace/22.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/23.uart_intr_test.501988042
Short name	T7
Test name
Test status
Simulation time	15574662 ps
CPU time	0.58 seconds
Started	Jan 14 12:19:44 PM PST 24
Finished	Jan 14 12:19:45 PM PST 24
Peak memory	185072 kb
Host	smart-0f3fe3ec-136a-4c2b-a58c-dfbaa2303023
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501988042 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.uart_intr_test.501988042
Directory	/workspace/23.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/24.uart_intr_test.1970405708
Short name	T156
Test name
Test status
Simulation time	13240423 ps
CPU time	0.6 seconds
Started	Jan 14 12:22:27 PM PST 24
Finished	Jan 14 12:22:29 PM PST 24
Peak memory	193052 kb
Host	smart-464ff763-514b-4842-bd51-c01d104ad0bb
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970405708 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.uart_intr_test.1970405708
Directory	/workspace/24.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/25.uart_intr_test.1128244041
Short name	T76
Test name
Test status
Simulation time	35794642 ps
CPU time	0.59 seconds
Started	Jan 14 12:22:14 PM PST 24
Finished	Jan 14 12:22:16 PM PST 24
Peak memory	194292 kb
Host	smart-2ff7c1c3-d21c-4371-b8c2-7999342a9644
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128244041 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.uart_intr_test.1128244041
Directory	/workspace/25.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/26.uart_intr_test.2792608992
Short name	T125
Test name
Test status
Simulation time	47601457 ps
CPU time	0.55 seconds
Started	Jan 14 12:22:50 PM PST 24
Finished	Jan 14 12:22:53 PM PST 24
Peak memory	184940 kb
Host	smart-eed467fb-d4a9-4aae-a0fb-cf413f25b989
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792608992 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.uart_intr_test.2792608992
Directory	/workspace/26.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/27.uart_intr_test.2734828629
Short name	T148
Test name
Test status
Simulation time	21112006 ps
CPU time	0.62 seconds
Started	Jan 14 12:22:01 PM PST 24
Finished	Jan 14 12:22:02 PM PST 24
Peak memory	192192 kb
Host	smart-8cbb4262-cde8-46b0-8c9b-a2415aa72d17
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734828629 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.uart_intr_test.2734828629
Directory	/workspace/27.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/29.uart_intr_test.117861765
Short name	T126
Test name
Test status
Simulation time	13591786 ps
CPU time	0.54 seconds
Started	Jan 14 12:22:28 PM PST 24
Finished	Jan 14 12:22:29 PM PST 24
Peak memory	184060 kb
Host	smart-b3b30e3e-4bed-4506-956d-619832d3b4cb
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117861765 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.uart_intr_test.117861765
Directory	/workspace/29.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/3.uart_csr_aliasing.1794430092
Short name	T78
Test name
Test status
Simulation time	44038891 ps
CPU time	0.83 seconds
Started	Jan 14 12:19:09 PM PST 24
Finished	Jan 14 12:19:10 PM PST 24
Peak memory	196284 kb
Host	smart-386d5534-0b6b-4901-b2f8-1709ba8caf7c
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794430092 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_aliasing.1794430092
Directory	/workspace/3.uart_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.993128001
Short name	T145
Test name
Test status
Simulation time	36725505 ps
CPU time	1.41 seconds
Started	Jan 14 12:22:43 PM PST 24
Finished	Jan 14 12:22:46 PM PST 24
Peak memory	197016 kb
Host	smart-0d8e7e87-602b-40c8-b415-7558e337a829
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993128001 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_bit_bash.993128001
Directory	/workspace/3.uart_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.4090903298
Short name	T10
Test name
Test status
Simulation time	14945094 ps
CPU time	0.56 seconds
Started	Jan 14 12:23:00 PM PST 24
Finished	Jan 14 12:23:01 PM PST 24
Peak memory	195208 kb
Host	smart-c36d8845-b272-47da-bb87-c1ffe0ad4e33
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090903298 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_hw_reset.4090903298
Directory	/workspace/3.uart_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.3136231304
Short name	T161
Test name
Test status
Simulation time	39125772 ps
CPU time	0.84 seconds
Started	Jan 14 12:23:10 PM PST 24
Finished	Jan 14 12:23:15 PM PST 24
Peak memory	199072 kb
Host	smart-4692d4ba-e088-4a7c-ad7c-5c88e15d5257
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136231304 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_mem_rw_with_rand_reset.3136231304
Directory	/workspace/3.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.uart_csr_rw.3868311997
Short name	T43
Test name
Test status
Simulation time	48251669 ps
CPU time	0.6 seconds
Started	Jan 14 12:17:52 PM PST 24
Finished	Jan 14 12:17:53 PM PST 24
Peak memory	195476 kb
Host	smart-c92c66dd-2b3e-48cd-8886-e9fc591ce9be
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868311997 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_rw.3868311997
Directory	/workspace/3.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.3805476921
Short name	T31
Test name
Test status
Simulation time	13197857 ps
CPU time	0.71 seconds
Started	Jan 14 12:20:25 PM PST 24
Finished	Jan 14 12:20:26 PM PST 24
Peak memory	195644 kb
Host	smart-31044cf7-7a94-49d8-b949-f2ea083e794a
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805476921 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_same_csr _outstanding.3805476921
Directory	/workspace/3.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/3.uart_tl_errors.4019640598
Short name	T13
Test name
Test status
Simulation time	48919319 ps
CPU time	1.18 seconds
Started	Jan 14 12:22:08 PM PST 24
Finished	Jan 14 12:22:09 PM PST 24
Peak memory	198476 kb
Host	smart-0dff01b0-74c1-4027-9ea1-67d2ee7852b3
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019640598 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_errors.4019640598
Directory	/workspace/3.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/3.uart_tl_intg_err.3304253601
Short name	T127
Test name
Test status
Simulation time	82320079 ps
CPU time	0.91 seconds
Started	Jan 14 12:22:59 PM PST 24
Finished	Jan 14 12:23:01 PM PST 24
Peak memory	198468 kb
Host	smart-0b6fa99c-7cd4-4a08-9a10-6ae5e4609928
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304253601 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_intg_err.3304253601
Directory	/workspace/3.uart_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/30.uart_intr_test.3124601750
Short name	T94
Test name
Test status
Simulation time	14566975 ps
CPU time	0.57 seconds
Started	Jan 14 12:23:27 PM PST 24
Finished	Jan 14 12:23:29 PM PST 24
Peak memory	194204 kb
Host	smart-89a84276-9d51-4de0-92e1-4bebc8796d43
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124601750 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.uart_intr_test.3124601750
Directory	/workspace/30.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/31.uart_intr_test.498245320
Short name	T119
Test name
Test status
Simulation time	15181014 ps
CPU time	0.59 seconds
Started	Jan 14 12:22:37 PM PST 24
Finished	Jan 14 12:22:38 PM PST 24
Peak memory	194164 kb
Host	smart-bd41de88-a8a6-4ab3-81f5-e3ee03493a38
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498245320 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.uart_intr_test.498245320
Directory	/workspace/31.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/32.uart_intr_test.94897176
Short name	T159
Test name
Test status
Simulation time	14846290 ps
CPU time	0.6 seconds
Started	Jan 14 12:18:31 PM PST 24
Finished	Jan 14 12:18:32 PM PST 24
Peak memory	185164 kb
Host	smart-243a8847-04af-46cb-9636-643cfde7ba90
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94897176 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.uart_intr_test.94897176
Directory	/workspace/32.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/33.uart_intr_test.86963421
Short name	T106
Test name
Test status
Simulation time	35998941 ps
CPU time	0.55 seconds
Started	Jan 14 12:23:27 PM PST 24
Finished	Jan 14 12:23:29 PM PST 24
Peak memory	184736 kb
Host	smart-5941c367-b4bd-40d5-b7e8-5ca187079aa7
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86963421 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.uart_intr_test.86963421
Directory	/workspace/33.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/34.uart_intr_test.882345153
Short name	T30
Test name
Test status
Simulation time	42007593 ps
CPU time	0.61 seconds
Started	Jan 14 12:19:49 PM PST 24
Finished	Jan 14 12:19:50 PM PST 24
Peak memory	185164 kb
Host	smart-ed9ce047-9993-4a73-9c39-455b9a6cdb2d
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882345153 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.uart_intr_test.882345153
Directory	/workspace/34.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/35.uart_intr_test.2256039502
Short name	T93
Test name
Test status
Simulation time	42369702 ps
CPU time	0.59 seconds
Started	Jan 14 12:22:37 PM PST 24
Finished	Jan 14 12:22:38 PM PST 24
Peak memory	184932 kb
Host	smart-9319dc83-1d37-4f54-b740-be1cf1053b6c
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256039502 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.uart_intr_test.2256039502
Directory	/workspace/35.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/36.uart_intr_test.2092661316
Short name	T51
Test name
Test status
Simulation time	40129416 ps
CPU time	0.64 seconds
Started	Jan 14 12:22:09 PM PST 24
Finished	Jan 14 12:22:10 PM PST 24
Peak memory	183984 kb
Host	smart-904950e6-ea95-4774-a22c-5eda77d53a55
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092661316 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.uart_intr_test.2092661316
Directory	/workspace/36.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/37.uart_intr_test.3294980193
Short name	T162
Test name
Test status
Simulation time	13117889 ps
CPU time	0.58 seconds
Started	Jan 14 12:19:46 PM PST 24
Finished	Jan 14 12:19:47 PM PST 24
Peak memory	194140 kb
Host	smart-39b7cb33-fe9e-41bc-aa8b-f2274c1bc295
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294980193 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.uart_intr_test.3294980193
Directory	/workspace/37.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/38.uart_intr_test.2147718427
Short name	T64
Test name
Test status
Simulation time	13302170 ps
CPU time	0.57 seconds
Started	Jan 14 12:19:14 PM PST 24
Finished	Jan 14 12:19:16 PM PST 24
Peak memory	194280 kb
Host	smart-c2bbb491-3597-4c3a-a7f4-32242b2adea0
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147718427 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.uart_intr_test.2147718427
Directory	/workspace/38.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/39.uart_intr_test.3388597381
Short name	T100
Test name
Test status
Simulation time	52064823 ps
CPU time	0.58 seconds
Started	Jan 14 12:22:37 PM PST 24
Finished	Jan 14 12:22:38 PM PST 24
Peak memory	184936 kb
Host	smart-00afe67e-69bf-4a0a-b1ef-5bbc44903d34
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388597381 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.uart_intr_test.3388597381
Directory	/workspace/39.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/4.uart_csr_aliasing.3935301422
Short name	T39
Test name
Test status
Simulation time	48714036 ps
CPU time	0.81 seconds
Started	Jan 14 12:23:31 PM PST 24
Finished	Jan 14 12:23:32 PM PST 24
Peak memory	195096 kb
Host	smart-c6148c52-af2b-4f94-8b0b-da8c077edcbd
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935301422 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_aliasing.3935301422
Directory	/workspace/4.uart_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.1406847704
Short name	T12
Test name
Test status
Simulation time	360539039 ps
CPU time	2.36 seconds
Started	Jan 14 12:19:14 PM PST 24
Finished	Jan 14 12:19:18 PM PST 24
Peak memory	197076 kb
Host	smart-618d35e3-b859-4d16-bb6b-b6e6057c3652
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406847704 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_bit_bash.1406847704
Directory	/workspace/4.uart_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.935359832
Short name	T42
Test name
Test status
Simulation time	26913160 ps
CPU time	0.62 seconds
Started	Jan 14 12:22:44 PM PST 24
Finished	Jan 14 12:22:46 PM PST 24
Peak memory	193736 kb
Host	smart-789ba032-ef9e-4333-bac3-8c3c4017213c
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935359832 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_hw_reset.935359832
Directory	/workspace/4.uart_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.1832434951
Short name	T84
Test name
Test status
Simulation time	105060713 ps
CPU time	0.98 seconds
Started	Jan 14 12:23:10 PM PST 24
Finished	Jan 14 12:23:16 PM PST 24
Peak memory	198868 kb
Host	smart-d325408c-6804-46b8-a34c-a8463368d966
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832434951 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_mem_rw_with_rand_reset.1832434951
Directory	/workspace/4.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.uart_csr_rw.3437588118
Short name	T35
Test name
Test status
Simulation time	12131485 ps
CPU time	0.63 seconds
Started	Jan 14 12:22:44 PM PST 24
Finished	Jan 14 12:22:46 PM PST 24
Peak memory	193932 kb
Host	smart-b52a5a9c-0a41-4ab6-b4a0-4b9237757044
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437588118 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_rw.3437588118
Directory	/workspace/4.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/4.uart_intr_test.1753812484
Short name	T108
Test name
Test status
Simulation time	12638861 ps
CPU time	0.54 seconds
Started	Jan 14 12:19:14 PM PST 24
Finished	Jan 14 12:19:16 PM PST 24
Peak memory	185044 kb
Host	smart-a7df6f61-b195-4d51-94df-4f4c449f51df
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753812484 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_intr_test.1753812484
Directory	/workspace/4.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/4.uart_tl_errors.3418494453
Short name	T90
Test name
Test status
Simulation time	168066085 ps
CPU time	2.2 seconds
Started	Jan 14 12:18:44 PM PST 24
Finished	Jan 14 12:18:49 PM PST 24
Peak memory	199972 kb
Host	smart-15646163-812b-4dac-a076-3b482b32d09a
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418494453 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_errors.3418494453
Directory	/workspace/4.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/4.uart_tl_intg_err.275422727
Short name	T133
Test name
Test status
Simulation time	182241906 ps
CPU time	1.01 seconds
Started	Jan 14 12:19:14 PM PST 24
Finished	Jan 14 12:19:16 PM PST 24
Peak memory	198956 kb
Host	smart-16acb590-cade-4cc6-825c-0294a4e1692d
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275422727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_intg_err.275422727
Directory	/workspace/4.uart_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/40.uart_intr_test.956317334
Short name	T163
Test name
Test status
Simulation time	24182752 ps
CPU time	0.64 seconds
Started	Jan 14 12:22:13 PM PST 24
Finished	Jan 14 12:22:14 PM PST 24
Peak memory	183396 kb
Host	smart-00e4547c-4153-492a-a667-1f06a0dfdbaa
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956317334 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.uart_intr_test.956317334
Directory	/workspace/40.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/41.uart_intr_test.75179185
Short name	T49
Test name
Test status
Simulation time	117201051 ps
CPU time	0.54 seconds
Started	Jan 14 12:20:46 PM PST 24
Finished	Jan 14 12:20:47 PM PST 24
Peak memory	194272 kb
Host	smart-a0bf7dd1-6067-4480-ba2e-e5895ef0fc05
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75179185 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.uart_intr_test.75179185
Directory	/workspace/41.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/42.uart_intr_test.2960624242
Short name	T91
Test name
Test status
Simulation time	24552222 ps
CPU time	0.63 seconds
Started	Jan 14 12:23:04 PM PST 24
Finished	Jan 14 12:23:06 PM PST 24
Peak memory	183792 kb
Host	smart-d6b6f256-8203-4c76-90ee-e5da4b397618
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960624242 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.uart_intr_test.2960624242
Directory	/workspace/42.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/43.uart_intr_test.1566510374
Short name	T65
Test name
Test status
Simulation time	105870907 ps
CPU time	0.56 seconds
Started	Jan 14 12:19:14 PM PST 24
Finished	Jan 14 12:19:16 PM PST 24
Peak memory	184824 kb
Host	smart-cbad90f3-4078-46f5-9e63-2c85a81ca79a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566510374 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.uart_intr_test.1566510374
Directory	/workspace/43.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/44.uart_intr_test.3150298793
Short name	T103
Test name
Test status
Simulation time	27677121 ps
CPU time	0.59 seconds
Started	Jan 14 12:22:12 PM PST 24
Finished	Jan 14 12:22:14 PM PST 24
Peak memory	183500 kb
Host	smart-56240dde-b09c-4685-bdf5-9886365dce6a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150298793 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.uart_intr_test.3150298793
Directory	/workspace/44.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/45.uart_intr_test.722325921
Short name	T164
Test name
Test status
Simulation time	40072005 ps
CPU time	0.64 seconds
Started	Jan 14 12:22:13 PM PST 24
Finished	Jan 14 12:22:14 PM PST 24
Peak memory	192604 kb
Host	smart-79a800c1-a429-4cbd-ba8a-5a3fea5faa6e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722325921 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.uart_intr_test.722325921
Directory	/workspace/45.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/46.uart_intr_test.1879131222
Short name	T139
Test name
Test status
Simulation time	21536027 ps
CPU time	0.56 seconds
Started	Jan 14 12:18:36 PM PST 24
Finished	Jan 14 12:18:37 PM PST 24
Peak memory	194228 kb
Host	smart-0f065cc3-9651-4619-a2f2-052dbd41748b
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879131222 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.uart_intr_test.1879131222
Directory	/workspace/46.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/47.uart_intr_test.2703463185
Short name	T66
Test name
Test status
Simulation time	58248574 ps
CPU time	0.61 seconds
Started	Jan 14 12:22:25 PM PST 24
Finished	Jan 14 12:22:27 PM PST 24
Peak memory	183876 kb
Host	smart-cad0fa7f-a8b3-46eb-84bf-0ef2b5e07761
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703463185 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.uart_intr_test.2703463185
Directory	/workspace/47.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/48.uart_intr_test.3128263002
Short name	T135
Test name
Test status
Simulation time	16171255 ps
CPU time	0.55 seconds
Started	Jan 14 12:22:13 PM PST 24
Finished	Jan 14 12:22:14 PM PST 24
Peak memory	184700 kb
Host	smart-1f844417-3c4e-41ae-b654-f46b7430628e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128263002 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.uart_intr_test.3128263002
Directory	/workspace/48.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.3212534880
Short name	T14
Test name
Test status
Simulation time	21984414 ps
CPU time	1.15 seconds
Started	Jan 14 12:17:14 PM PST 24
Finished	Jan 14 12:17:17 PM PST 24
Peak memory	199588 kb
Host	smart-f93f1931-aadd-4e9c-bc4e-d2fd586a876e
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212534880 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_csr_mem_rw_with_rand_reset.3212534880
Directory	/workspace/5.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/5.uart_csr_rw.2546544459
Short name	T165
Test name
Test status
Simulation time	17869501 ps
CPU time	0.72 seconds
Started	Jan 14 12:20:04 PM PST 24
Finished	Jan 14 12:20:05 PM PST 24
Peak memory	195564 kb
Host	smart-6857c2b2-780c-4679-a6f4-9ff1fd0f490d
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546544459 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_csr_rw.2546544459
Directory	/workspace/5.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/5.uart_intr_test.2507678027
Short name	T97
Test name
Test status
Simulation time	11395703 ps
CPU time	0.55 seconds
Started	Jan 14 12:17:14 PM PST 24
Finished	Jan 14 12:17:17 PM PST 24
Peak memory	193856 kb
Host	smart-facf42a4-2ef0-44c3-b97d-638c9e9943a0
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507678027 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_intr_test.2507678027
Directory	/workspace/5.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.3319642597
Short name	T152
Test name
Test status
Simulation time	22581045 ps
CPU time	0.69 seconds
Started	Jan 14 12:22:59 PM PST 24
Finished	Jan 14 12:23:00 PM PST 24
Peak memory	193952 kb
Host	smart-26d547ed-7175-47d3-8566-e057490e86b1
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319642597 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_same_csr _outstanding.3319642597
Directory	/workspace/5.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/5.uart_tl_errors.3216574741
Short name	T147
Test name
Test status
Simulation time	131607474 ps
CPU time	2.33 seconds
Started	Jan 14 12:19:31 PM PST 24
Finished	Jan 14 12:19:34 PM PST 24
Peak memory	200040 kb
Host	smart-dd8da27a-2a3b-4642-a996-9af8aa646745
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216574741 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_errors.3216574741
Directory	/workspace/5.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/5.uart_tl_intg_err.1595783725
Short name	T122
Test name
Test status
Simulation time	102604013 ps
CPU time	1.4 seconds
Started	Jan 14 12:18:03 PM PST 24
Finished	Jan 14 12:18:05 PM PST 24
Peak memory	199168 kb
Host	smart-5f381481-efd5-458d-80f7-4fcacbd540cd
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595783725 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_intg_err.1595783725
Directory	/workspace/5.uart_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.247858723
Short name	T27
Test name
Test status
Simulation time	41496796 ps
CPU time	0.78 seconds
Started	Jan 14 12:20:19 PM PST 24
Finished	Jan 14 12:20:21 PM PST 24
Peak memory	199772 kb
Host	smart-ebb9370c-c445-4d50-b630-c2ed4b86504c
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247858723 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_csr_mem_rw_with_rand_reset.247858723
Directory	/workspace/6.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/6.uart_csr_rw.567591586
Short name	T155
Test name
Test status
Simulation time	13054544 ps
CPU time	0.58 seconds
Started	Jan 14 12:17:43 PM PST 24
Finished	Jan 14 12:17:44 PM PST 24
Peak memory	195332 kb
Host	smart-1ab6f98b-c73a-4336-be2a-96991cf687eb
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567591586 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_csr_rw.567591586
Directory	/workspace/6.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/6.uart_intr_test.3398035272
Short name	T149
Test name
Test status
Simulation time	22806012 ps
CPU time	0.57 seconds
Started	Jan 14 12:20:19 PM PST 24
Finished	Jan 14 12:20:20 PM PST 24
Peak memory	194448 kb
Host	smart-d9a92efa-b21e-4c4d-a48a-ad397bafd537
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398035272 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_intr_test.3398035272
Directory	/workspace/6.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.822319444
Short name	T83
Test name
Test status
Simulation time	108795796 ps
CPU time	0.8 seconds
Started	Jan 14 12:19:56 PM PST 24
Finished	Jan 14 12:19:57 PM PST 24
Peak memory	197676 kb
Host	smart-f369d736-c3d0-45a9-afe0-0688b5cf8e82
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822319444 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_same_csr_ outstanding.822319444
Directory	/workspace/6.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/6.uart_tl_errors.427782579
Short name	T121
Test name
Test status
Simulation time	136197146 ps
CPU time	1.75 seconds
Started	Jan 14 12:19:14 PM PST 24
Finished	Jan 14 12:19:17 PM PST 24
Peak memory	199956 kb
Host	smart-307c9722-fa5c-4890-934d-99617b0ed5f3
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427782579 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_errors.427782579
Directory	/workspace/6.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/6.uart_tl_intg_err.4030041827
Short name	T24
Test name
Test status
Simulation time	189243121 ps
CPU time	0.95 seconds
Started	Jan 14 12:19:56 PM PST 24
Finished	Jan 14 12:19:57 PM PST 24
Peak memory	198988 kb
Host	smart-cbc8d5fb-fa2b-462e-92ac-96c2d26e820f
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030041827 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_intg_err.4030041827
Directory	/workspace/6.uart_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.2029991926
Short name	T3
Test name
Test status
Simulation time	27272987 ps
CPU time	0.88 seconds
Started	Jan 14 12:20:13 PM PST 24
Finished	Jan 14 12:20:14 PM PST 24
Peak memory	199780 kb
Host	smart-c2e34fbe-4a70-437d-88d9-0ff3cc18f294
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029991926 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_csr_mem_rw_with_rand_reset.2029991926
Directory	/workspace/7.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/7.uart_csr_rw.351607893
Short name	T62
Test name
Test status
Simulation time	28651219 ps
CPU time	0.62 seconds
Started	Jan 14 12:20:13 PM PST 24
Finished	Jan 14 12:20:14 PM PST 24
Peak memory	195420 kb
Host	smart-2f70b3b5-d8a1-440c-bd41-9475def2e6d5
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351607893 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_csr_rw.351607893
Directory	/workspace/7.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/7.uart_intr_test.3273107234
Short name	T41
Test name
Test status
Simulation time	52730996 ps
CPU time	0.55 seconds
Started	Jan 14 12:22:36 PM PST 24
Finished	Jan 14 12:22:37 PM PST 24
Peak memory	185056 kb
Host	smart-00dd2f77-8290-4727-b645-09bd145c9583
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273107234 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_intr_test.3273107234
Directory	/workspace/7.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.2078842457
Short name	T124
Test name
Test status
Simulation time	19746383 ps
CPU time	0.73 seconds
Started	Jan 14 12:22:41 PM PST 24
Finished	Jan 14 12:22:42 PM PST 24
Peak memory	196076 kb
Host	smart-ee8657a7-7600-4d0f-a25d-ab4d46fbb890
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078842457 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_same_csr _outstanding.2078842457
Directory	/workspace/7.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/7.uart_tl_errors.1896922259
Short name	T111
Test name
Test status
Simulation time	475282418 ps
CPU time	2.39 seconds
Started	Jan 14 12:23:00 PM PST 24
Finished	Jan 14 12:23:03 PM PST 24
Peak memory	199768 kb
Host	smart-ba64a7d5-fcd5-4c05-9033-3cddde6ab571
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896922259 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_errors.1896922259
Directory	/workspace/7.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/7.uart_tl_intg_err.3501567476
Short name	T69
Test name
Test status
Simulation time	76156881 ps
CPU time	1.29 seconds
Started	Jan 14 12:17:05 PM PST 24
Finished	Jan 14 12:17:07 PM PST 24
Peak memory	197532 kb
Host	smart-6147b884-7966-49d1-aaa0-f914ad965877
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501567476 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_intg_err.3501567476
Directory	/workspace/7.uart_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.3509970366
Short name	T61
Test name
Test status
Simulation time	27524369 ps
CPU time	0.75 seconds
Started	Jan 14 12:23:08 PM PST 24
Finished	Jan 14 12:23:11 PM PST 24
Peak memory	198408 kb
Host	smart-514403e2-04bd-4bd8-ab13-824b8300aad3
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509970366 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_csr_mem_rw_with_rand_reset.3509970366
Directory	/workspace/8.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/8.uart_csr_rw.975005599
Short name	T45
Test name
Test status
Simulation time	17485491 ps
CPU time	0.63 seconds
Started	Jan 14 12:22:40 PM PST 24
Finished	Jan 14 12:22:42 PM PST 24
Peak memory	194080 kb
Host	smart-b15ae995-6ffc-4b94-9bf5-d81631f4a14f
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975005599 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_csr_rw.975005599
Directory	/workspace/8.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/8.uart_intr_test.3662104649
Short name	T116
Test name
Test status
Simulation time	44456771 ps
CPU time	0.59 seconds
Started	Jan 14 12:18:15 PM PST 24
Finished	Jan 14 12:18:16 PM PST 24
Peak memory	194296 kb
Host	smart-c4828f42-57f7-4ef1-b44c-51ca2280a2b6
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662104649 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_intr_test.3662104649
Directory	/workspace/8.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.1002745991
Short name	T56
Test name
Test status
Simulation time	56543749 ps
CPU time	0.69 seconds
Started	Jan 14 12:19:07 PM PST 24
Finished	Jan 14 12:19:10 PM PST 24
Peak memory	196900 kb
Host	smart-ea584910-475b-420d-8626-6a9558d38dbe
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002745991 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_same_csr _outstanding.1002745991
Directory	/workspace/8.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/8.uart_tl_errors.2019315998
Short name	T18
Test name
Test status
Simulation time	500072623 ps
CPU time	2.4 seconds
Started	Jan 14 12:17:05 PM PST 24
Finished	Jan 14 12:17:08 PM PST 24
Peak memory	198508 kb
Host	smart-afdeb73e-c1e5-456a-bad1-9fb1197f5274
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019315998 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_errors.2019315998
Directory	/workspace/8.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.1522921432
Short name	T87
Test name
Test status
Simulation time	39940056 ps
CPU time	1.2 seconds
Started	Jan 14 12:23:10 PM PST 24
Finished	Jan 14 12:23:16 PM PST 24
Peak memory	199880 kb
Host	smart-ffb98d2b-20b7-4a23-b90b-ce2bb4b03323
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522921432 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_csr_mem_rw_with_rand_reset.1522921432
Directory	/workspace/9.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/9.uart_csr_rw.734101869
Short name	T28
Test name
Test status
Simulation time	16990037 ps
CPU time	0.62 seconds
Started	Jan 14 12:17:44 PM PST 24
Finished	Jan 14 12:17:45 PM PST 24
Peak memory	195504 kb
Host	smart-d7b09afa-b3c8-4062-85d7-1b3b5387284d
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734101869 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_csr_rw.734101869
Directory	/workspace/9.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/9.uart_intr_test.1534037587
Short name	T143
Test name
Test status
Simulation time	33424815 ps
CPU time	0.64 seconds
Started	Jan 14 12:23:10 PM PST 24
Finished	Jan 14 12:23:15 PM PST 24
Peak memory	194016 kb
Host	smart-d9a77449-a5a6-4d7f-98f7-0810ff5caa62
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534037587 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_intr_test.1534037587
Directory	/workspace/9.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.1799278787
Short name	T95
Test name
Test status
Simulation time	31145941 ps
CPU time	0.71 seconds
Started	Jan 14 12:23:10 PM PST 24
Finished	Jan 14 12:23:15 PM PST 24
Peak memory	195472 kb
Host	smart-f025ed29-59d3-45a4-92a9-1c2d7e48be03
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799278787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_same_csr _outstanding.1799278787
Directory	/workspace/9.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/9.uart_tl_errors.61771110
Short name	T21
Test name
Test status
Simulation time	30987474 ps
CPU time	1.41 seconds
Started	Jan 14 12:23:12 PM PST 24
Finished	Jan 14 12:23:21 PM PST 24
Peak memory	199860 kb
Host	smart-53ef5baa-8663-48d1-96b1-e2c9159d96c1
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61771110 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_errors.61771110
Directory	/workspace/9.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/9.uart_tl_intg_err.3568858566
Short name	T120
Test name
Test status
Simulation time	147124423 ps
CPU time	1.2 seconds
Started	Jan 14 12:18:27 PM PST 24
Finished	Jan 14 12:18:29 PM PST 24
Peak memory	199036 kb
Host	smart-8e683754-3f07-4924-aca4-a2726a7d067b
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568858566 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_intg_err.3568858566
Directory	/workspace/9.uart_tl_intg_err/latest