Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	341	1			T13	1		T5	1		T7	8
all_pins[1]	341	1			T13	1		T5	1		T7	8
all_pins[2]	341	1			T13	1		T5	1		T7	8
all_pins[3]	341	1			T13	1		T5	1		T7	8
all_pins[4]	341	1			T13	1		T5	1		T7	8
all_pins[5]	341	1			T13	1		T5	1		T7	8
all_pins[6]	341	1			T13	1		T5	1		T7	8
all_pins[7]	341	1			T13	1		T5	1		T7	8

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	2251	1			T13	8		T5	8		T7	52
values[0x1]	477	1			T7	12		T8	16		T9	15
transitions[0x0=>0x1]	346	1			T7	7		T8	11		T9	9
transitions[0x1=>0x0]	357	1			T7	7		T8	11		T9	10

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	290	1			T13	1		T5	1		T7	4
all_pins[0]	values[0x1]	51	1			T7	4		T8	2		T9	3
all_pins[0]	transitions[0x0=>0x1]	41	1			T7	2		T9	2		T11	1
all_pins[0]	transitions[0x1=>0x0]	41	1			T8	1		T11	2		T30	1
all_pins[1]	values[0x0]	290	1			T13	1		T5	1		T7	6
all_pins[1]	values[0x1]	51	1			T7	2		T8	3		T9	1
all_pins[1]	transitions[0x0=>0x1]	40	1			T7	2		T8	3		T11	2
all_pins[1]	transitions[0x1=>0x0]	47	1			T8	1		T9	3		T30	1
all_pins[2]	values[0x0]	283	1			T13	1		T5	1		T7	8
all_pins[2]	values[0x1]	58	1			T8	1		T9	4		T30	2
all_pins[2]	transitions[0x0=>0x1]	45	1			T9	4		T30	2		T72	1
all_pins[2]	transitions[0x1=>0x0]	36	1			T8	3		T41	2		T73	2
all_pins[3]	values[0x0]	292	1			T13	1		T5	1		T7	8
all_pins[3]	values[0x1]	49	1			T8	4		T41	2		T71	1
all_pins[3]	transitions[0x0=>0x1]	37	1			T8	4		T65	2		T74	1
all_pins[3]	transitions[0x1=>0x0]	53	1			T7	1		T9	1		T30	1
all_pins[4]	values[0x0]	276	1			T13	1		T5	1		T7	7
all_pins[4]	values[0x1]	65	1			T7	1		T9	1		T30	1
all_pins[4]	transitions[0x0=>0x1]	43	1			T7	1		T41	2		T64	3
all_pins[4]	transitions[0x1=>0x0]	44	1			T7	1		T8	3		T30	4
all_pins[5]	values[0x0]	275	1			T13	1		T5	1		T7	7
all_pins[5]	values[0x1]	66	1			T7	1		T8	3		T9	1
all_pins[5]	transitions[0x0=>0x1]	44	1			T8	2		T30	2		T41	3
all_pins[5]	transitions[0x1=>0x0]	46	1			T7	1		T9	1		T11	2
all_pins[6]	values[0x0]	273	1			T13	1		T5	1		T7	6
all_pins[6]	values[0x1]	68	1			T7	2		T8	1		T9	2
all_pins[6]	transitions[0x0=>0x1]	49	1			T7	1		T8	1		T9	1
all_pins[6]	transitions[0x1=>0x0]	50	1			T7	1		T8	2		T9	2
all_pins[7]	values[0x0]	272	1			T13	1		T5	1		T7	6
all_pins[7]	values[0x1]	69	1			T7	2		T8	2		T9	3
all_pins[7]	transitions[0x0=>0x1]	47	1			T7	1		T8	1		T9	2
all_pins[7]	transitions[0x1=>0x0]	40	1			T7	3		T8	1		T9	3