Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	0	48	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	0	48	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	272	1			T7	7		T8	4		T9	7
all_values[1]	272	1			T7	7		T8	4		T9	7
all_values[2]	272	1			T7	7		T8	4		T9	7
all_values[3]	272	1			T7	7		T8	4		T9	7
all_values[4]	272	1			T7	7		T8	4		T9	7
all_values[5]	272	1			T7	7		T8	4		T9	7
all_values[6]	272	1			T7	7		T8	4		T9	7
all_values[7]	272	1			T7	7		T8	4		T9	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1178

1

T7

29

T8

17

T9

22

auto[1]

998

1

T7

27

T8

15

T9

34

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

895

1

T7

21

T8

6

T9

23

auto[1]

1281

1

T7

35

T8

26

T9

33

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1298

1

T7

32

T8

15

T9

33

auto[1]

878

1

T7

24

T8

17

T9

23

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	70	1			T7	2		T8	1		T30	4
all_values[0]	auto[0]	auto[0]	auto[1]	25	1			T72	1		T64	1		T71	1
all_values[0]	auto[0]	auto[1]	auto[0]	41	1			T7	1		T9	2		T11	1
all_values[0]	auto[0]	auto[1]	auto[1]	26	1			T7	2		T8	2		T9	2
all_values[0]	auto[1]	auto[0]	auto[1]	57	1			T8	1		T11	1		T30	2
all_values[0]	auto[1]	auto[1]	auto[1]	53	1			T7	2		T9	3		T11	1
all_values[1]	auto[0]	auto[0]	auto[0]	72	1			T7	1		T8	1		T9	2
all_values[1]	auto[0]	auto[0]	auto[1]	22	1			T11	1		T64	1		T71	1
all_values[1]	auto[0]	auto[1]	auto[0]	52	1			T7	4		T9	1		T30	3
all_values[1]	auto[0]	auto[1]	auto[1]	19	1			T8	1		T9	1		T11	1
all_values[1]	auto[1]	auto[0]	auto[1]	59	1			T7	1		T9	2		T11	1
all_values[1]	auto[1]	auto[1]	auto[1]	48	1			T7	1		T8	2		T9	1
all_values[2]	auto[0]	auto[0]	auto[0]	53	1			T9	1		T11	1		T41	3
all_values[2]	auto[0]	auto[0]	auto[1]	29	1			T7	1		T8	1		T30	2
all_values[2]	auto[0]	auto[1]	auto[0]	54	1			T7	2		T11	2		T41	3
all_values[2]	auto[0]	auto[1]	auto[1]	23	1			T9	2		T30	2		T72	1
all_values[2]	auto[1]	auto[0]	auto[1]	56	1			T7	3		T8	3		T9	1
all_values[2]	auto[1]	auto[1]	auto[1]	57	1			T7	1		T9	3		T30	2
all_values[3]	auto[0]	auto[0]	auto[0]	56	1			T7	1		T9	3		T30	1
all_values[3]	auto[0]	auto[0]	auto[1]	21	1			T7	1		T41	1		T64	1
all_values[3]	auto[0]	auto[1]	auto[0]	69	1			T7	2		T9	3		T11	4
all_values[3]	auto[0]	auto[1]	auto[1]	22	1			T8	2		T41	1		T65	1
all_values[3]	auto[1]	auto[0]	auto[1]	58	1			T7	3		T8	1		T30	1
all_values[3]	auto[1]	auto[1]	auto[1]	46	1			T8	1		T9	1		T30	1
all_values[4]	auto[0]	auto[0]	auto[0]	63	1			T7	3		T8	2		T9	2
all_values[4]	auto[0]	auto[0]	auto[1]	23	1			T30	3		T74	1		T75	1
all_values[4]	auto[0]	auto[1]	auto[0]	47	1			T9	2		T11	2		T74	1
all_values[4]	auto[0]	auto[1]	auto[1]	25	1			T41	1		T64	1		T71	1
all_values[4]	auto[1]	auto[0]	auto[1]	55	1			T7	1		T8	2		T11	1
all_values[4]	auto[1]	auto[1]	auto[1]	59	1			T7	3		T9	3		T11	1
all_values[5]	auto[0]	auto[0]	auto[0]	80	1			T7	2		T9	4		T11	2
all_values[5]	auto[0]	auto[0]	auto[1]	22	1			T7	1		T76	1		T77	1
all_values[5]	auto[0]	auto[1]	auto[0]	33	1			T11	2		T30	1		T41	1
all_values[5]	auto[0]	auto[1]	auto[1]	30	1			T7	1		T8	1		T9	1
all_values[5]	auto[1]	auto[0]	auto[1]	59	1			T7	2		T8	1		T9	1
all_values[5]	auto[1]	auto[1]	auto[1]	48	1			T7	1		T8	2		T9	1
all_values[6]	auto[0]	auto[0]	auto[0]	62	1			T11	1		T72	4		T64	4
all_values[6]	auto[0]	auto[0]	auto[1]	30	1			T7	1		T8	1		T9	1
all_values[6]	auto[0]	auto[1]	auto[0]	32	1			T7	2		T9	2		T41	2
all_values[6]	auto[0]	auto[1]	auto[1]	32	1			T7	1		T9	1		T11	1
all_values[6]	auto[1]	auto[0]	auto[1]	67	1			T7	3		T8	2		T11	1
all_values[6]	auto[1]	auto[1]	auto[1]	49	1			T8	1		T9	3		T11	1
all_values[7]	auto[0]	auto[0]	auto[0]	60	1			T7	1		T8	1		T9	1
all_values[7]	auto[0]	auto[0]	auto[1]	23	1			T7	1		T9	1		T30	1
all_values[7]	auto[0]	auto[1]	auto[0]	51	1			T8	1		T11	3		T30	2
all_values[7]	auto[0]	auto[1]	auto[1]	31	1			T7	2		T8	1		T9	1
all_values[7]	auto[1]	auto[0]	auto[1]	56	1			T7	1		T9	3		T11	1
all_values[7]	auto[1]	auto[1]	auto[1]	51	1			T7	2		T8	1		T9	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal