Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	65465541	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

32879199

1

T1

62

T2

74

T3

13

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	89217541	1			T1	216		T2	111		T3	39
values[0x0]	4314115	1			T1	49		T2	5		T3	6
values[0x1]	4813084	1			T1	53		T2	5		T3	14

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	46390994	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

51953746

1

T1

147

T2

86

T3

31

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	348620	1			T6	38		T8	2		T9	2
valid_sources[0x01]	380717	1			T6	15		T32	3		T36	2
valid_sources[0x02]	374173	1			T7	2		T8	1		T9	1
valid_sources[0x03]	366983	1			T1	1		T4	1		T9	1
valid_sources[0x04]	340252	1			T9	1		T36	3		T37	1
valid_sources[0x05]	385660	1			T1	5		T2	2		T36	3
valid_sources[0x06]	398962	1			T1	7		T9	1		T36	2
valid_sources[0x07]	356029	1			T1	18		T4	1		T8	1
valid_sources[0x08]	340671	1			T9	1		T36	2		T86	1
valid_sources[0x09]	389963	1			T9	3		T36	3		T44	1
valid_sources[0x0a]	357951	1			T9	3		T33	3		T62	1
valid_sources[0x0b]	364592	1			T1	2		T4	1		T5	8
valid_sources[0x0c]	411757	1			T4	1		T7	1		T9	2
valid_sources[0x0d]	432505	1			T2	2		T9	4		T36	3
valid_sources[0x0e]	418952	1			T4	1		T36	4		T37	4
valid_sources[0x0f]	399175	1			T6	18		T9	2		T33	1
valid_sources[0x10]	388108	1			T9	1		T52	1		T37	5
valid_sources[0x11]	366308	1			T1	3		T9	2		T32	1
valid_sources[0x12]	383589	1			T1	9		T9	2		T33	1
valid_sources[0x13]	369909	1			T9	1		T36	3		T39	11
valid_sources[0x14]	356086	1			T8	2		T36	1		T37	4
valid_sources[0x15]	365786	1			T37	4		T53	1		T56	7
valid_sources[0x16]	376549	1			T1	2		T8	2		T36	2
valid_sources[0x17]	445270	1			T8	1		T9	1		T51	3
valid_sources[0x18]	366186	1			T8	1		T9	2		T36	5
valid_sources[0x19]	344221	1			T9	2		T85	2		T37	3
valid_sources[0x1a]	362953	1			T1	5		T2	1		T5	17
valid_sources[0x1b]	366418	1			T9	1		T33	1		T44	1
valid_sources[0x1c]	377381	1			T5	3		T9	3		T36	1
valid_sources[0x1d]	433758	1			T36	5		T51	1		T85	1
valid_sources[0x1e]	355056	1			T1	7		T6	36		T7	1
valid_sources[0x1f]	367203	1			T1	2		T8	1		T9	2
valid_sources[0x20]	351093	1			T2	2		T4	3		T36	2
valid_sources[0x21]	374933	1			T9	3		T36	1		T52	1
valid_sources[0x22]	387195	1			T33	2		T52	4		T37	1
valid_sources[0x23]	366647	1			T7	1		T8	1		T9	1
valid_sources[0x24]	413606	1			T9	1		T50	2		T51	4
valid_sources[0x25]	389465	1			T8	1		T9	1		T33	1
valid_sources[0x26]	359898	1			T6	14		T9	2		T51	1
valid_sources[0x27]	365322	1			T8	1		T9	3		T44	1
valid_sources[0x28]	359957	1			T8	2		T9	1		T33	1
valid_sources[0x29]	404142	1			T2	4		T8	1		T51	3
valid_sources[0x2a]	341283	1			T1	2		T9	1		T37	6
valid_sources[0x2b]	432050	1			T36	2		T40	1		T56	7
valid_sources[0x2c]	450205	1			T1	1		T4	1		T8	1
valid_sources[0x2d]	393909	1			T1	2		T8	1		T9	3
valid_sources[0x2e]	362816	1			T1	1		T8	1		T9	1
valid_sources[0x2f]	365672	1			T6	41		T8	1		T9	3
valid_sources[0x30]	394421	1			T1	5		T7	1		T9	3
valid_sources[0x31]	488984	1			T1	4		T5	36		T8	2
valid_sources[0x32]	403528	1			T2	4		T36	2		T37	2
valid_sources[0x33]	348039	1			T7	1		T9	1		T36	1
valid_sources[0x34]	353704	1			T2	1		T52	1		T85	1
valid_sources[0x35]	380566	1			T8	3		T9	2		T36	1
valid_sources[0x36]	369603	1			T1	18		T2	8		T8	2
valid_sources[0x37]	345547	1			T9	4		T36	1		T86	1
valid_sources[0x38]	401371	1			T4	4		T9	4		T51	5
valid_sources[0x39]	346994	1			T4	3		T36	4		T37	1
valid_sources[0x3a]	411554	1			T1	1		T5	14		T7	1
valid_sources[0x3b]	371203	1			T2	2		T9	1		T36	5
valid_sources[0x3c]	475397	1			T4	1		T8	1		T36	4
valid_sources[0x3d]	366345	1			T2	3		T8	1		T9	4
valid_sources[0x3e]	426052	1			T4	1		T6	20		T44	1
valid_sources[0x3f]	540615	1			T4	3		T33	1		T36	4
valid_sources[0x40]	476284	1			T9	2		T36	2		T85	1
valid_sources[0x41]	370131	1			T9	1		T36	4		T51	7
valid_sources[0x42]	354951	1			T1	1		T9	2		T50	1
valid_sources[0x43]	347161	1			T2	3		T6	68		T9	2
valid_sources[0x44]	413317	1			T5	3		T9	1		T36	1
valid_sources[0x45]	349994	1			T9	6		T37	4		T40	1
valid_sources[0x46]	358206	1			T8	1		T9	1		T52	1
valid_sources[0x47]	373494	1			T4	1		T9	1		T36	3
valid_sources[0x48]	366364	1			T8	1		T36	7		T85	1
valid_sources[0x49]	404220	1			T2	1		T37	3		T38	25
valid_sources[0x4a]	566659	1			T9	1		T36	1		T51	11
valid_sources[0x4b]	376519	1			T1	5		T8	1		T9	2
valid_sources[0x4c]	350658	1			T7	1		T9	1		T32	2
valid_sources[0x4d]	361343	1			T4	1		T8	1		T32	1
valid_sources[0x4e]	388000	1			T2	2		T5	27		T8	2
valid_sources[0x4f]	381281	1			T1	5		T4	2		T9	1
valid_sources[0x50]	378245	1			T3	12		T8	2		T9	3
valid_sources[0x51]	367644	1			T1	6		T9	1		T37	3
valid_sources[0x52]	344859	1			T1	2		T9	1		T51	2
valid_sources[0x53]	354808	1			T9	1		T36	1		T37	4
valid_sources[0x54]	348042	1			T4	1		T6	14		T9	2
valid_sources[0x55]	450199	1			T2	1		T4	2		T9	2
valid_sources[0x56]	394576	1			T8	1		T9	5		T36	3
valid_sources[0x57]	382502	1			T9	1		T86	1		T37	5
valid_sources[0x58]	364800	1			T8	2		T9	2		T36	1
valid_sources[0x59]	354383	1			T1	1		T36	2		T51	4
valid_sources[0x5a]	406819	1			T1	1		T3	18		T9	3
valid_sources[0x5b]	373175	1			T2	4		T8	1		T9	2
valid_sources[0x5c]	388895	1			T9	3		T36	5		T52	1
valid_sources[0x5d]	380428	1			T4	1		T8	1		T9	2
valid_sources[0x5e]	377619	1			T4	1		T8	1		T9	2
valid_sources[0x5f]	415919	1			T36	1		T37	1		T62	2
valid_sources[0x60]	340612	1			T4	1		T6	12		T9	2
valid_sources[0x61]	386460	1			T2	2		T9	1		T32	1
valid_sources[0x62]	357073	1			T2	1		T7	1		T8	2
valid_sources[0x63]	384603	1			T4	1		T7	1		T8	2
valid_sources[0x64]	431401	1			T8	1		T9	2		T33	1
valid_sources[0x65]	355850	1			T4	4		T9	1		T32	1
valid_sources[0x66]	364430	1			T8	1		T51	7		T52	1
valid_sources[0x67]	354663	1			T4	2		T6	20		T9	1
valid_sources[0x68]	373172	1			T2	3		T8	2		T9	3
valid_sources[0x69]	350045	1			T1	2		T9	3		T44	1
valid_sources[0x6a]	373591	1			T33	1		T36	3		T53	1
valid_sources[0x6b]	405864	1			T1	3		T8	1		T9	4
valid_sources[0x6c]	367911	1			T1	1		T2	4		T4	1
valid_sources[0x6d]	372897	1			T1	1		T2	1		T9	1
valid_sources[0x6e]	756055	1			T1	7		T2	5		T9	2
valid_sources[0x6f]	374704	1			T5	15		T9	9		T36	1
valid_sources[0x70]	374727	1			T9	4		T36	2		T37	1
valid_sources[0x71]	375615	1			T2	1		T8	2		T36	2
valid_sources[0x72]	366608	1			T1	7		T9	4		T42	23
valid_sources[0x73]	392092	1			T1	5		T7	1		T8	1
valid_sources[0x74]	341302	1			T2	1		T7	1		T8	6
valid_sources[0x75]	366269	1			T1	5		T36	3		T45	5
valid_sources[0x76]	364112	1			T2	5		T9	1		T53	1
valid_sources[0x77]	377476	1			T1	12		T9	2		T51	4
valid_sources[0x78]	380298	1			T2	3		T4	3		T8	3
valid_sources[0x79]	372309	1			T9	3		T52	1		T37	1
valid_sources[0x7a]	365054	1			T1	1		T9	3		T36	1
valid_sources[0x7b]	356897	1			T4	2		T5	10		T7	1
valid_sources[0x7c]	350376	1			T8	2		T9	1		T52	1
valid_sources[0x7d]	366947	1			T6	24		T8	1		T9	2
valid_sources[0x7e]	355602	1			T5	12		T9	1		T36	1
valid_sources[0x7f]	354169	1			T5	4		T8	1		T9	3
valid_sources[0x80]	338534	1			T5	5		T8	2		T9	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

24833492

1

T1

18

T2

66

T3

3

values[0x0]

all_enables

biggest_size

4049795

1

T1

26

T2

4

T3

4

values[0x1]

all_enables

biggest_size

3995912

1

T1

18

T2

4

T3

6