Unified Coverage Report :: Module :: uart_csr_assert_fpv

Module : uart_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_uart_csr_assert_0/uart_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.uart_csr_assert	100.00						100.00

---

Module Instance : tb.dut.uart_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : uart_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	13256262	0	0
ctrl_rd_A	2147483647	262098	0	0
intr_enable_rd_A	2147483647	233556	0	0
ovrd_rd_A	2147483647	259894	0	0
timeout_ctrl_rd_A	2147483647	259646	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	13256262	0	0
T1	5068	3	0	0
T2	1106	0	0	0
T3	1061	0	0	0
T4	1221	0	0	0
T5	4783	1	0	0
T6	7383	4	0	0
T7	1321	4	0	0
T8	2044	9	0	0
T9	3938	794	0	0
T10	1595	0	0	0
T36	0	1	0	0
T37	0	416	0	0
T45	0	23	0	0
T51	0	4	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	262098	0	0
T1	5068	126	0	0
T2	1106	0	0	0
T3	1061	48	0	0
T4	1221	10	0	0
T5	4783	285	0	0
T6	7383	0	0	0
T7	1321	0	0	0
T8	2044	15	0	0
T9	3938	0	0	0
T10	1595	0	0	0
T38	0	427	0	0
T39	0	23	0	0
T55	0	3	0	0
T56	0	174	0	0
T86	0	21	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	233556	0	0
T1	5068	183	0	0
T2	1106	0	0	0
T3	1061	9	0	0
T4	1221	94	0	0
T5	4783	200	0	0
T6	7383	0	0	0
T7	1321	0	0	0
T8	2044	34	0	0
T9	3938	0	0	0
T10	1595	0	0	0
T38	0	343	0	0
T39	0	44	0	0
T50	0	4	0	0
T63	0	12	0	0
T86	0	5	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	259894	0	0
T1	5068	60	0	0
T2	1106	0	0	0
T3	1061	8	0	0
T4	1221	2	0	0
T5	4783	35	0	0
T6	7383	0	0	0
T7	1321	0	0	0
T8	2044	29	0	0
T9	3938	0	0	0
T10	1595	0	0	0
T38	0	119	0	0
T39	0	33	0	0
T56	0	202	0	0
T70	0	19	0	0
T86	0	27	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	259646	0	0
T1	5068	52	0	0
T2	1106	0	0	0
T3	1061	20	0	0
T4	1221	6	0	0
T5	4783	53	0	0
T6	7383	0	0	0
T7	1321	0	0	0
T8	2044	27	0	0
T9	3938	0	0	0
T10	1595	0	0	0
T38	0	141	0	0
T39	0	55	0	0
T55	0	6	0	0
T56	0	245	0	0
T86	0	34	0	0