Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	72185442	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

33553911

1

T1

7

T2

14

T3

18

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	96706430	1			T1	24		T2	12		T3	20
values[0x0]	4277157	1			T1	4		T2	6		T3	6
values[0x1]	4755766	1			T1	6		T2	6		T3	14

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	51041482	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

54697871

1

T1

13

T2

15

T3

22

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	402385	1			T8	1		T34	1		T35	3
valid_sources[0x01]	406638	1			T35	4		T399	2		T41	3
valid_sources[0x02]	413104	1			T9	2		T33	4		T34	1
valid_sources[0x03]	391708	1			T1	1		T8	1		T9	1
valid_sources[0x04]	381251	1			T9	1		T56	5		T34	1
valid_sources[0x05]	385496	1			T7	1		T9	4		T33	1
valid_sources[0x06]	379703	1			T9	6		T33	1		T56	2
valid_sources[0x07]	389844	1			T7	1		T35	1		T96	1
valid_sources[0x08]	368816	1			T9	2		T33	2		T56	4
valid_sources[0x09]	383577	1			T9	3		T33	1		T35	1
valid_sources[0x0a]	404614	1			T1	1		T56	1		T34	2
valid_sources[0x0b]	378037	1			T9	2		T34	3		T35	2
valid_sources[0x0c]	518351	1			T4	1		T9	2		T33	3
valid_sources[0x0d]	384184	1			T1	2		T2	5		T9	1
valid_sources[0x0e]	507769	1			T4	1		T7	2		T34	2
valid_sources[0x0f]	435826	1			T34	1		T35	3		T76	1
valid_sources[0x10]	475117	1			T9	3		T33	6		T34	1
valid_sources[0x11]	393232	1			T34	1		T35	2		T40	1
valid_sources[0x12]	376960	1			T33	1		T57	1		T35	4
valid_sources[0x13]	414592	1			T9	1		T33	1		T56	12
valid_sources[0x14]	396876	1			T33	1		T56	2		T34	2
valid_sources[0x15]	390768	1			T9	1		T34	2		T35	3
valid_sources[0x16]	380023	1			T33	6		T56	2		T34	2
valid_sources[0x17]	463465	1			T33	2		T34	3		T35	7
valid_sources[0x18]	448935	1			T35	1		T40	2		T100	2
valid_sources[0x19]	397242	1			T9	1		T33	2		T35	3
valid_sources[0x1a]	380837	1			T8	1		T9	3		T33	2
valid_sources[0x1b]	384882	1			T9	4		T34	1		T35	5
valid_sources[0x1c]	406335	1			T10	2		T33	2		T35	1
valid_sources[0x1d]	384738	1			T2	13		T7	2		T9	4
valid_sources[0x1e]	402954	1			T9	1		T10	3		T35	2
valid_sources[0x1f]	431395	1			T1	1		T7	2		T9	4
valid_sources[0x20]	374979	1			T9	3		T33	1		T34	2
valid_sources[0x21]	1087585	1			T34	1		T97	1		T38	3
valid_sources[0x22]	400010	1			T9	3		T34	1		T35	4
valid_sources[0x23]	414316	1			T7	1		T9	1		T56	3
valid_sources[0x24]	375386	1			T9	3		T33	1		T34	3
valid_sources[0x25]	371907	1			T1	2		T4	1		T9	5
valid_sources[0x26]	373460	1			T1	1		T33	4		T35	1
valid_sources[0x27]	426151	1			T9	1		T34	1		T41	1
valid_sources[0x28]	387122	1			T10	1		T33	1		T47	1
valid_sources[0x29]	385436	1			T9	1		T34	1		T35	3
valid_sources[0x2a]	482372	1			T4	1		T9	2		T34	2
valid_sources[0x2b]	414986	1			T9	2		T33	2		T47	2
valid_sources[0x2c]	392687	1			T4	1		T9	3		T34	1
valid_sources[0x2d]	400776	1			T4	1		T33	4		T56	3
valid_sources[0x2e]	387848	1			T5	184		T9	9		T56	1
valid_sources[0x2f]	402834	1			T9	1		T56	5		T35	3
valid_sources[0x30]	514602	1			T9	1		T33	1		T34	1
valid_sources[0x31]	422104	1			T33	5		T34	1		T35	3
valid_sources[0x32]	392267	1			T9	1		T35	4		T76	1
valid_sources[0x33]	385560	1			T9	3		T33	2		T34	1
valid_sources[0x34]	382642	1			T33	1		T35	1		T40	2
valid_sources[0x35]	382173	1			T9	2		T56	1		T34	1
valid_sources[0x36]	456010	1			T1	1		T8	1		T9	1
valid_sources[0x37]	416814	1			T9	4		T33	2		T34	1
valid_sources[0x38]	394562	1			T9	2		T33	1		T34	2
valid_sources[0x39]	383662	1			T8	1		T9	2		T34	2
valid_sources[0x3a]	418297	1			T6	9		T9	2		T34	1
valid_sources[0x3b]	417025	1			T9	2		T10	1		T56	7
valid_sources[0x3c]	404869	1			T9	3		T35	1		T400	1
valid_sources[0x3d]	539706	1			T9	2		T34	1		T35	2
valid_sources[0x3e]	375222	1			T9	4		T33	4		T34	1
valid_sources[0x3f]	398549	1			T9	3		T33	1		T47	1
valid_sources[0x40]	399140	1			T9	3		T34	2		T35	4
valid_sources[0x41]	400670	1			T6	2		T7	1		T9	1
valid_sources[0x42]	418961	1			T1	1		T9	2		T10	1
valid_sources[0x43]	392482	1			T4	4		T34	1		T35	3
valid_sources[0x44]	370387	1			T9	3		T33	5		T34	2
valid_sources[0x45]	422566	1			T9	2		T34	1		T40	1
valid_sources[0x46]	390006	1			T9	3		T35	1		T41	1
valid_sources[0x47]	382314	1			T9	1		T34	1		T35	3
valid_sources[0x48]	426559	1			T9	3		T56	5		T35	5
valid_sources[0x49]	421518	1			T7	1		T9	4		T34	2
valid_sources[0x4a]	384032	1			T9	1		T34	1		T400	1
valid_sources[0x4b]	484044	1			T33	2		T34	1		T35	3
valid_sources[0x4c]	426930	1			T9	2		T57	1		T35	1
valid_sources[0x4d]	404600	1			T34	1		T35	5		T40	1
valid_sources[0x4e]	399116	1			T9	1		T56	1		T35	5
valid_sources[0x4f]	381237	1			T9	2		T33	2		T34	3
valid_sources[0x50]	384129	1			T8	1		T9	5		T56	2
valid_sources[0x51]	376073	1			T4	1		T8	1		T56	2
valid_sources[0x52]	384486	1			T7	1		T9	2		T57	2
valid_sources[0x53]	409433	1			T9	1		T33	1		T100	1
valid_sources[0x54]	402278	1			T33	3		T34	1		T35	4
valid_sources[0x55]	384350	1			T9	4		T34	3		T35	3
valid_sources[0x56]	538857	1			T1	1		T9	2		T47	1
valid_sources[0x57]	387731	1			T9	1		T33	1		T35	1
valid_sources[0x58]	380802	1			T9	1		T34	2		T35	2
valid_sources[0x59]	418165	1			T9	2		T33	3		T47	1
valid_sources[0x5a]	369219	1			T9	2		T56	6		T35	3
valid_sources[0x5b]	365006	1			T8	1		T9	1		T47	1
valid_sources[0x5c]	419082	1			T8	2		T9	2		T35	3
valid_sources[0x5d]	375139	1			T6	11		T9	1		T33	3
valid_sources[0x5e]	389571	1			T1	2		T5	5		T9	1
valid_sources[0x5f]	396940	1			T9	2		T56	1		T34	1
valid_sources[0x60]	372704	1			T9	6		T34	1		T41	2
valid_sources[0x61]	380252	1			T7	1		T9	3		T56	1
valid_sources[0x62]	384799	1			T9	2		T33	1		T34	1
valid_sources[0x63]	438879	1			T9	2		T35	1		T76	1
valid_sources[0x64]	401501	1			T6	15		T9	2		T34	1
valid_sources[0x65]	415713	1			T9	2		T35	2		T40	2
valid_sources[0x66]	388787	1			T7	1		T9	2		T33	1
valid_sources[0x67]	367230	1			T9	1		T34	2		T35	1
valid_sources[0x68]	383859	1			T33	1		T34	1		T35	2
valid_sources[0x69]	374980	1			T7	1		T9	3		T35	4
valid_sources[0x6a]	729482	1			T6	7		T9	1		T34	1
valid_sources[0x6b]	408848	1			T45	22		T56	1		T35	2
valid_sources[0x6c]	380064	1			T7	3		T9	3		T10	1
valid_sources[0x6d]	394440	1			T1	1		T4	1		T9	1
valid_sources[0x6e]	388396	1			T7	1		T9	2		T47	2
valid_sources[0x6f]	376257	1			T34	2		T35	6		T41	2
valid_sources[0x70]	370737	1			T7	1		T9	2		T34	3
valid_sources[0x71]	407675	1			T1	1		T9	1		T34	1
valid_sources[0x72]	400582	1			T9	1		T33	2		T34	1
valid_sources[0x73]	380769	1			T9	3		T56	1		T34	2
valid_sources[0x74]	382499	1			T9	2		T34	1		T35	3
valid_sources[0x75]	404031	1			T1	2		T9	2		T33	2
valid_sources[0x76]	428191	1			T9	1		T56	2		T35	3
valid_sources[0x77]	425598	1			T7	2		T9	2		T10	1
valid_sources[0x78]	570499	1			T9	2		T33	1		T34	3
valid_sources[0x79]	396784	1			T9	2		T34	2		T96	2
valid_sources[0x7a]	393238	1			T2	6		T9	2		T33	1
valid_sources[0x7b]	447456	1			T33	1		T35	2		T40	2
valid_sources[0x7c]	452682	1			T9	3		T35	6		T40	2
valid_sources[0x7d]	413767	1			T1	1		T56	6		T34	1
valid_sources[0x7e]	386680	1			T9	3		T57	1		T35	2
valid_sources[0x7f]	393914	1			T3	40		T9	1		T35	5
valid_sources[0x80]	450990	1			T9	3		T56	2		T35	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

25608913

1

T1

1

T2

8

T3

11

values[0x0]

all_enables

biggest_size

4003971

1

T1

3

T2

2

T3

3

values[0x1]

all_enables

biggest_size

3941027

1

T1

3

T2

4

T3

4