Unified Coverage Report :: Module :: uart_csr_assert_fpv

Module : uart_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_uart_csr_assert_0/uart_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.uart_csr_assert	100.00						100.00

---

Module Instance : tb.dut.uart_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : uart_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	12876287	0	0
ctrl_rd_A	2147483647	334175	0	0
intr_enable_rd_A	2147483647	291987	0	0
ovrd_rd_A	2147483647	330710	0	0
timeout_ctrl_rd_A	2147483647	332965	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	12876287	0	0
T5	2185	60	0	0
T6	1397	0	0	0
T7	1095	0	0	0
T8	971	0	0	0
T9	3044	291	0	0
T10	1049	0	0	0
T33	5840	301	0	0
T34	0	1	0	0
T35	0	1	0	0
T38	0	4	0	0
T40	0	198	0	0
T41	0	437	0	0
T45	1533	0	0	0
T46	756	0	0	0
T47	958	0	0	0
T96	0	6	0	0
T97	0	23	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	334175	0	0
T10	1049	9	0	0
T33	5840	0	0	0
T34	4981	0	0	0
T35	7206	0	0	0
T40	2756	0	0	0
T42	0	28	0	0
T45	1533	0	0	0
T46	756	0	0	0
T47	958	0	0	0
T49	0	13	0	0
T51	0	5	0	0
T56	1738	1	0	0
T57	1504	0	0	0
T77	0	22	0	0
T81	0	21	0	0
T97	0	59	0	0
T98	0	16	0	0
T99	0	30	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	291987	0	0
T3	1343	35	0	0
T4	1421	0	0	0
T5	2185	0	0	0
T6	1397	0	0	0
T7	1095	0	0	0
T8	971	5	0	0
T9	3044	0	0	0
T10	1049	37	0	0
T42	0	17	0	0
T45	1533	15	0	0
T46	756	0	0	0
T49	0	13	0	0
T56	0	2	0	0
T57	0	22	0	0
T97	0	12	0	0
T100	0	9	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	330710	0	0
T10	1049	2	0	0
T33	5840	0	0	0
T34	4981	0	0	0
T35	7206	0	0	0
T40	2756	0	0	0
T42	0	26	0	0
T45	1533	0	0	0
T46	756	0	0	0
T47	958	0	0	0
T49	0	2	0	0
T51	0	7	0	0
T56	1738	41	0	0
T57	1504	0	0	0
T77	0	9	0	0
T81	0	43	0	0
T97	0	15	0	0
T98	0	5	0	0
T99	0	49	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	332965	0	0
T10	1049	7	0	0
T33	5840	0	0	0
T34	4981	0	0	0
T35	7206	0	0	0
T40	2756	0	0	0
T42	0	23	0	0
T45	1533	0	0	0
T46	756	0	0	0
T47	958	0	0	0
T49	0	19	0	0
T56	1738	6	0	0
T57	1504	0	0	0
T74	0	45	0	0
T77	0	22	0	0
T81	0	53	0	0
T97	0	16	0	0
T98	0	14	0	0
T99	0	51	0	0