Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	65374138	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

32112123

1

T1

8

T2

17

T3

59

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	87007546	1			T1	11		T2	20		T3	55
values[0x0]	4957003	1			T1	2		T2	8		T3	16
values[0x1]	5521712	1			T1	9		T2	12		T3	23

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	46002405	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

51483856

1

T1

9

T2

18

T3

68

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	358159	1			T32	1		T34	1		T38	4
valid_sources[0x01]	387669	1			T45	1		T46	1		T32	4
valid_sources[0x02]	361364	1			T32	1		T48	1		T34	2
valid_sources[0x03]	356962	1			T32	1		T34	2		T38	3
valid_sources[0x04]	375744	1			T2	1		T5	1		T32	3
valid_sources[0x05]	352740	1			T34	1		T38	2		T81	11
valid_sources[0x06]	366910	1			T2	3		T32	1		T34	2
valid_sources[0x07]	388124	1			T46	1		T34	1		T50	1
valid_sources[0x08]	378955	1			T32	6		T34	3		T58	1
valid_sources[0x09]	466553	1			T32	1		T34	1		T38	6
valid_sources[0x0a]	362280	1			T8	16		T34	1		T38	3
valid_sources[0x0b]	367525	1			T32	1		T34	3		T50	1
valid_sources[0x0c]	394502	1			T8	9		T32	2		T34	5
valid_sources[0x0d]	361875	1			T6	2		T31	47		T32	1
valid_sources[0x0e]	428737	1			T6	2		T45	1		T32	1
valid_sources[0x0f]	336415	1			T8	27		T45	1		T32	1
valid_sources[0x10]	346926	1			T34	1		T50	1		T38	2
valid_sources[0x11]	357794	1			T5	2		T31	18		T32	2
valid_sources[0x12]	353199	1			T5	1		T6	5		T32	2
valid_sources[0x13]	364107	1			T5	5		T32	1		T34	2
valid_sources[0x14]	384745	1			T6	5		T32	1		T34	2
valid_sources[0x15]	357987	1			T45	1		T32	2		T34	1
valid_sources[0x16]	345479	1			T5	6		T32	3		T38	1
valid_sources[0x17]	367160	1			T32	3		T34	1		T50	1
valid_sources[0x18]	359836	1			T8	36		T34	2		T38	1
valid_sources[0x19]	346952	1			T32	3		T34	3		T58	1
valid_sources[0x1a]	381664	1			T32	2		T34	2		T81	4
valid_sources[0x1b]	364363	1			T32	2		T34	3		T50	1
valid_sources[0x1c]	399168	1			T32	2		T34	5		T38	3
valid_sources[0x1d]	451739	1			T31	8		T32	2		T48	1
valid_sources[0x1e]	467493	1			T32	2		T34	2		T79	2
valid_sources[0x1f]	347788	1			T5	5		T34	1		T58	3
valid_sources[0x20]	350769	1			T34	2		T81	4		T78	2
valid_sources[0x21]	360151	1			T32	2		T38	1		T81	16
valid_sources[0x22]	419174	1			T34	3		T38	3		T58	2
valid_sources[0x23]	376743	1			T32	2		T48	1		T34	3
valid_sources[0x24]	957865	1			T32	2		T34	1		T59	1
valid_sources[0x25]	392480	1			T31	9		T48	1		T34	1
valid_sources[0x26]	350983	1			T6	3		T32	4		T34	1
valid_sources[0x27]	377225	1			T45	1		T32	1		T48	1
valid_sources[0x28]	374140	1			T34	4		T81	61		T58	2
valid_sources[0x29]	395475	1			T6	10		T32	4		T34	2
valid_sources[0x2a]	368650	1			T48	1		T34	3		T50	1
valid_sources[0x2b]	350059	1			T32	1		T34	3		T38	9
valid_sources[0x2c]	356552	1			T32	6		T34	4		T38	1
valid_sources[0x2d]	364998	1			T32	2		T34	2		T397	11
valid_sources[0x2e]	365292	1			T4	40		T5	4		T32	2
valid_sources[0x2f]	371327	1			T45	1		T32	1		T34	4
valid_sources[0x30]	361620	1			T46	1		T32	2		T34	5
valid_sources[0x31]	386706	1			T45	2		T46	1		T32	2
valid_sources[0x32]	365700	1			T45	1		T32	1		T34	4
valid_sources[0x33]	364358	1			T32	1		T34	3		T50	2
valid_sources[0x34]	381458	1			T32	1		T48	1		T34	3
valid_sources[0x35]	358764	1			T32	2		T59	6		T39	1
valid_sources[0x36]	372259	1			T8	11		T32	1		T38	2
valid_sources[0x37]	375196	1			T32	3		T50	2		T58	1
valid_sources[0x38]	445427	1			T5	4		T6	5		T45	1
valid_sources[0x39]	361849	1			T32	3		T38	1		T58	1
valid_sources[0x3a]	539113	1			T2	1		T5	3		T46	2
valid_sources[0x3b]	428921	1			T46	1		T34	1		T50	1
valid_sources[0x3c]	367101	1			T32	1		T34	2		T58	2
valid_sources[0x3d]	348795	1			T6	1		T32	3		T34	1
valid_sources[0x3e]	361933	1			T46	3		T34	3		T58	5
valid_sources[0x3f]	359197	1			T32	1		T34	6		T81	68
valid_sources[0x40]	371901	1			T32	3		T34	4		T79	1
valid_sources[0x41]	370483	1			T8	10		T32	2		T34	3
valid_sources[0x42]	371555	1			T32	2		T34	1		T50	3
valid_sources[0x43]	358166	1			T32	2		T50	1		T58	3
valid_sources[0x44]	394500	1			T5	1		T32	2		T34	2
valid_sources[0x45]	367512	1			T31	17		T32	4		T34	1
valid_sources[0x46]	362045	1			T5	2		T32	2		T34	1
valid_sources[0x47]	355088	1			T9	1		T32	2		T34	3
valid_sources[0x48]	368008	1			T32	5		T34	2		T81	14
valid_sources[0x49]	353140	1			T32	1		T58	2		T59	2
valid_sources[0x4a]	367604	1			T32	1		T34	5		T38	2
valid_sources[0x4b]	342821	1			T32	1		T34	2		T39	2
valid_sources[0x4c]	373919	1			T5	1		T34	1		T38	1
valid_sources[0x4d]	356248	1			T32	2		T34	2		T50	2
valid_sources[0x4e]	354180	1			T32	1		T33	8		T34	2
valid_sources[0x4f]	368797	1			T32	7		T81	32		T78	1
valid_sources[0x50]	383496	1			T32	1		T34	2		T81	19
valid_sources[0x51]	344448	1			T5	4		T46	1		T34	2
valid_sources[0x52]	369438	1			T6	2		T32	4		T34	3
valid_sources[0x53]	363112	1			T32	3		T34	7		T38	6
valid_sources[0x54]	364414	1			T8	10		T32	1		T34	3
valid_sources[0x55]	353961	1			T32	3		T34	1		T79	1
valid_sources[0x56]	377717	1			T8	4		T32	2		T58	2
valid_sources[0x57]	374554	1			T8	6		T32	1		T34	1
valid_sources[0x58]	634342	1			T32	1		T79	1		T397	9
valid_sources[0x59]	430055	1			T32	2		T40	17		T397	11
valid_sources[0x5a]	368214	1			T32	4		T34	5		T39	2
valid_sources[0x5b]	348008	1			T31	73		T32	1		T34	3
valid_sources[0x5c]	343242	1			T32	3		T34	1		T50	2
valid_sources[0x5d]	358917	1			T5	1		T34	3		T38	6
valid_sources[0x5e]	372918	1			T8	5		T32	5		T34	3
valid_sources[0x5f]	509056	1			T32	1		T34	2		T50	1
valid_sources[0x60]	358280	1			T2	3		T32	2		T48	1
valid_sources[0x61]	359208	1			T32	1		T38	2		T79	2
valid_sources[0x62]	370599	1			T32	3		T34	3		T58	3
valid_sources[0x63]	369826	1			T5	2		T32	2		T34	2
valid_sources[0x64]	360712	1			T5	5		T32	4		T81	30
valid_sources[0x65]	363797	1			T32	1		T34	3		T38	1
valid_sources[0x66]	369428	1			T5	1		T6	1		T32	4
valid_sources[0x67]	368553	1			T32	3		T34	2		T50	1
valid_sources[0x68]	394058	1			T47	40		T32	2		T34	3
valid_sources[0x69]	360741	1			T5	6		T7	22		T34	1
valid_sources[0x6a]	368209	1			T34	3		T79	1		T40	5
valid_sources[0x6b]	410887	1			T34	1		T50	2		T58	1
valid_sources[0x6c]	349318	1			T32	2		T34	1		T50	1
valid_sources[0x6d]	350829	1			T8	3		T32	3		T34	1
valid_sources[0x6e]	363141	1			T32	1		T34	1		T38	2
valid_sources[0x6f]	389460	1			T5	1		T10	22		T34	4
valid_sources[0x70]	415202	1			T32	1		T34	1		T38	1
valid_sources[0x71]	362727	1			T32	4		T34	3		T38	6
valid_sources[0x72]	376560	1			T34	2		T50	1		T38	2
valid_sources[0x73]	353692	1			T2	12		T32	4		T50	1
valid_sources[0x74]	351442	1			T31	16		T32	1		T34	3
valid_sources[0x75]	354561	1			T32	4		T38	1		T79	1
valid_sources[0x76]	354929	1			T32	1		T34	2		T58	1
valid_sources[0x77]	439336	1			T32	3		T34	4		T58	1
valid_sources[0x78]	371707	1			T5	1		T32	3		T34	1
valid_sources[0x79]	372432	1			T32	2		T34	2		T38	1
valid_sources[0x7a]	413702	1			T2	3		T32	1		T34	4
valid_sources[0x7b]	346867	1			T8	17		T32	1		T34	5
valid_sources[0x7c]	446585	1			T46	2		T34	1		T58	1
valid_sources[0x7d]	375531	1			T5	2		T6	5		T34	3
valid_sources[0x7e]	373559	1			T32	1		T58	1		T39	1
valid_sources[0x7f]	375770	1			T32	3		T34	2		T38	1
valid_sources[0x80]	357059	1			T32	5		T34	1		T38	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

22847202

1

T1

6

T2

11

T3

25

values[0x0]

all_enables

biggest_size

4664981

1

T1

1

T2

3

T3

16

values[0x1]

all_enables

biggest_size

4599940

1

T1

1

T2

3

T3

18