Unified Coverage Report :: Module :: prim_fifo_sync_cnt

Module : prim_fifo_sync_cnt

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.uart_core.u_uart_txfifo.gen_normal_fifo.u_fifo_cnt	100.00	100.00				100.00
tb.dut.uart_core.u_uart_rxfifo.gen_normal_fifo.u_fifo_cnt	100.00	100.00				100.00

---

Module Instance : tb.dut.uart_core.u_uart_txfifo.gen_normal_fifo.u_fifo_cnt

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	84.62			100.00	100.00	u_uart_txfifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.uart_core.u_uart_rxfifo.gen_normal_fifo.u_fifo_cnt

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	84.62			100.00	100.00	u_uart_rxfifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_fifo_sync_cnt

	Line No.	Total	Covered	Percent
TOTAL		20	20	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00
CONT_ASSIGN	32	1	1	100.00
CONT_ASSIGN	33	1	1	100.00
ALWAYS	74	8	8	100.00
ALWAYS	86	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
29	1	1
30	1	1
32	1	1
33	1	1
74	1	1
75	1	1
76	1	1
77	1	1
78	1	1
79	1	1
80	1	1
81	1	1
			MISSING_ELSE
86	1	1
87	1	1
88	1	1
89	1	1
90	1	1
91	1	1
92	1	1
93	1	1
			MISSING_ELSE

---

Branch Coverage for Module : prim_fifo_sync_cnt

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
IF	74	5	5	100.00
IF	86	5	5	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	74	if ((!rst_ni))
-2-:	76	if (clr_i)
-3-:	78	if (wptr_wrap)
-4-:	80	if (incr_wptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T11,T12,T13
0	1	-	-	Covered	T11,T12,T13
0	0	1	-	Covered	T14,T17,T18
0	0	0	1	Covered	T11,T12,T13
0	0	0	0	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	86	if ((!rst_ni))
-2-:	88	if (clr_i)
-3-:	90	if (rptr_wrap)
-4-:	92	if (incr_rptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T11,T12,T13
0	1	-	-	Covered	T11,T12,T13
0	0	1	-	Covered	T14,T17,T15
0	0	0	1	Covered	T11,T12,T19
0	0	0	0	Covered	T11,T12,T13

Line Coverage for Instance : tb.dut.uart_core.u_uart_txfifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
TOTAL		20	20	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00
CONT_ASSIGN	32	1	1	100.00
CONT_ASSIGN	33	1	1	100.00
ALWAYS	74	8	8	100.00
ALWAYS	86	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
29	1	1
30	1	1
32	1	1
33	1	1
74	1	1
75	1	1
76	1	1
77	1	1
78	1	1
79	1	1
80	1	1
81	1	1
			MISSING_ELSE
86	1	1
87	1	1
88	1	1
89	1	1
90	1	1
91	1	1
92	1	1
93	1	1
			MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.uart_core.u_uart_txfifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
IF	74	5	5	100.00
IF	86	5	5	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	74	if ((!rst_ni))
-2-:	76	if (clr_i)
-3-:	78	if (wptr_wrap)
-4-:	80	if (incr_wptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T11,T12,T13
0	1	-	-	Covered	T11,T12,T13
0	0	1	-	Covered	T14,T17,T18
0	0	0	1	Covered	T11,T12,T19
0	0	0	0	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	86	if ((!rst_ni))
-2-:	88	if (clr_i)
-3-:	90	if (rptr_wrap)
-4-:	92	if (incr_rptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T11,T12,T13
0	1	-	-	Covered	T11,T12,T13
0	0	1	-	Covered	T14,T15,T16
0	0	0	1	Covered	T11,T12,T19
0	0	0	0	Covered	T11,T12,T13

Line Coverage for Instance : tb.dut.uart_core.u_uart_rxfifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
TOTAL		20	20	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00
CONT_ASSIGN	32	1	1	100.00
CONT_ASSIGN	33	1	1	100.00
ALWAYS	74	8	8	100.00
ALWAYS	86	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
29	1	1
30	1	1
32	1	1
33	1	1
74	1	1
75	1	1
76	1	1
77	1	1
78	1	1
79	1	1
80	1	1
81	1	1
			MISSING_ELSE
86	1	1
87	1	1
88	1	1
89	1	1
90	1	1
91	1	1
92	1	1
93	1	1
			MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.uart_core.u_uart_rxfifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
IF	74	5	5	100.00
IF	86	5	5	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	74	if ((!rst_ni))
-2-:	76	if (clr_i)
-3-:	78	if (wptr_wrap)
-4-:	80	if (incr_wptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T11,T12,T13
0	1	-	-	Covered	T11,T12,T13
0	0	1	-	Covered	T14,T17,T15
0	0	0	1	Covered	T11,T12,T13
0	0	0	0	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	86	if ((!rst_ni))
-2-:	88	if (clr_i)
-3-:	90	if (rptr_wrap)
-4-:	92	if (incr_rptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T11,T12,T13
0	1	-	-	Covered	T11,T12,T13
0	0	1	-	Covered	T14,T17,T15
0	0	0	1	Covered	T11,T19,T21
0	0	0	0	Covered	T11,T12,T13