Unified Coverage Report :: Module :: uart_reg_top

Module : uart_reg_top

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_uart_0.1/rtl/uart_reg_top.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.79	99.68	99.26	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_alert_test	100.00	100.00
u_chk	100.00	100.00		100.00			100.00
u_ctrl_llpbk	100.00	100.00	100.00			100.00
u_ctrl_nco	100.00	100.00	100.00			100.00
u_ctrl_nf	100.00	100.00	100.00			100.00
u_ctrl_parity_en	100.00	100.00	100.00			100.00
u_ctrl_parity_odd	100.00	100.00	100.00			100.00
u_ctrl_rx	100.00	100.00	100.00			100.00
u_ctrl_rxblvl	100.00	100.00	100.00			100.00
u_ctrl_slpbk	100.00	100.00	100.00			100.00
u_ctrl_tx	100.00	100.00	100.00			100.00
u_fifo_ctrl0_qe	100.00	100.00				100.00
u_fifo_ctrl_rxilvl	96.30	100.00	88.89			100.00
u_fifo_ctrl_rxrst	100.00	100.00	100.00			100.00
u_fifo_ctrl_txilvl	96.30	100.00	88.89			100.00
u_fifo_ctrl_txrst	100.00	100.00	100.00			100.00
u_fifo_status_rxlvl	100.00	100.00
u_fifo_status_txlvl	100.00	100.00
u_intr_enable_rx_break_err	100.00	100.00	100.00			100.00
u_intr_enable_rx_frame_err	100.00	100.00	100.00			100.00
u_intr_enable_rx_overflow	100.00	100.00	100.00			100.00
u_intr_enable_rx_parity_err	100.00	100.00	100.00			100.00
u_intr_enable_rx_timeout	100.00	100.00	100.00			100.00
u_intr_enable_rx_watermark	100.00	100.00	100.00			100.00
u_intr_enable_tx_empty	100.00	100.00	100.00			100.00
u_intr_enable_tx_watermark	100.00	100.00	100.00			100.00
u_intr_state_rx_break_err	100.00	100.00	100.00			100.00
u_intr_state_rx_frame_err	100.00	100.00	100.00			100.00
u_intr_state_rx_overflow	100.00	100.00	100.00			100.00
u_intr_state_rx_parity_err	100.00	100.00	100.00			100.00
u_intr_state_rx_timeout	100.00	100.00	100.00			100.00
u_intr_state_rx_watermark	100.00	100.00	100.00			100.00
u_intr_state_tx_empty	100.00	100.00	100.00			100.00
u_intr_state_tx_watermark	100.00	100.00	100.00			100.00
u_intr_test_rx_break_err	100.00	100.00
u_intr_test_rx_frame_err	100.00	100.00
u_intr_test_rx_overflow	100.00	100.00
u_intr_test_rx_parity_err	100.00	100.00
u_intr_test_rx_timeout	100.00	100.00
u_intr_test_rx_watermark	100.00	100.00
u_intr_test_tx_empty	100.00	100.00
u_intr_test_tx_watermark	100.00	100.00
u_ovrd_txen	100.00	100.00	100.00			100.00
u_ovrd_txval	100.00	100.00	100.00			100.00
u_prim_reg_we_check	100.00	100.00		100.00
u_rdata	100.00	100.00
u_reg_if	98.67	97.14	97.53			100.00	100.00
u_rsp_intg_gen	100.00	100.00					100.00
u_status_rxempty	100.00	100.00
u_status_rxfull	100.00	100.00
u_status_rxidle	100.00	100.00
u_status_txempty	100.00	100.00
u_status_txfull	100.00	100.00
u_status_txidle	100.00	100.00
u_timeout_ctrl_en	100.00	100.00	100.00			100.00
u_timeout_ctrl_val	100.00	100.00	100.00			100.00
u_val	100.00	100.00
u_wdata	100.00	100.00	100.00			100.00
u_wdata0_qe	100.00	100.00				100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : uart_reg_top

	Line No.	Total	Covered	Percent
TOTAL		168	168	100.00
ALWAYS	68	4	4	100.00
CONT_ASSIGN	77	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	119	1	1	100.00
CONT_ASSIGN	662	1	1	100.00
CONT_ASSIGN	677	1	1	100.00
CONT_ASSIGN	693	1	1	100.00
CONT_ASSIGN	709	1	1	100.00
CONT_ASSIGN	725	1	1	100.00
CONT_ASSIGN	741	1	1	100.00
CONT_ASSIGN	757	1	1	100.00
CONT_ASSIGN	773	1	1	100.00
CONT_ASSIGN	789	1	1	100.00
CONT_ASSIGN	795	1	1	100.00
CONT_ASSIGN	809	1	1	100.00
CONT_ASSIGN	1202	1	1	100.00
CONT_ASSIGN	1243	1	1	100.00
CONT_ASSIGN	1271	1	1	100.00
CONT_ASSIGN	1299	1	1	100.00
CONT_ASSIGN	1327	1	1	100.00
ALWAYS	1493	14	14	100.00
CONT_ASSIGN	1509	1	1	100.00
ALWAYS	1513	1	1	100.00
CONT_ASSIGN	1530	1	1	100.00
CONT_ASSIGN	1532	1	1	100.00
CONT_ASSIGN	1534	1	1	100.00
CONT_ASSIGN	1536	1	1	100.00
CONT_ASSIGN	1538	1	1	100.00
CONT_ASSIGN	1540	1	1	100.00
CONT_ASSIGN	1542	1	1	100.00
CONT_ASSIGN	1544	1	1	100.00
CONT_ASSIGN	1546	1	1	100.00
CONT_ASSIGN	1547	1	1	100.00
CONT_ASSIGN	1549	1	1	100.00
CONT_ASSIGN	1551	1	1	100.00
CONT_ASSIGN	1553	1	1	100.00
CONT_ASSIGN	1555	1	1	100.00
CONT_ASSIGN	1557	1	1	100.00
CONT_ASSIGN	1559	1	1	100.00
CONT_ASSIGN	1561	1	1	100.00
CONT_ASSIGN	1563	1	1	100.00
CONT_ASSIGN	1564	1	1	100.00
CONT_ASSIGN	1566	1	1	100.00
CONT_ASSIGN	1568	1	1	100.00
CONT_ASSIGN	1570	1	1	100.00
CONT_ASSIGN	1572	1	1	100.00
CONT_ASSIGN	1574	1	1	100.00
CONT_ASSIGN	1576	1	1	100.00
CONT_ASSIGN	1578	1	1	100.00
CONT_ASSIGN	1580	1	1	100.00
CONT_ASSIGN	1581	1	1	100.00
CONT_ASSIGN	1583	1	1	100.00
CONT_ASSIGN	1584	1	1	100.00
CONT_ASSIGN	1586	1	1	100.00
CONT_ASSIGN	1588	1	1	100.00
CONT_ASSIGN	1590	1	1	100.00
CONT_ASSIGN	1592	1	1	100.00
CONT_ASSIGN	1594	1	1	100.00
CONT_ASSIGN	1596	1	1	100.00
CONT_ASSIGN	1598	1	1	100.00
CONT_ASSIGN	1600	1	1	100.00
CONT_ASSIGN	1602	1	1	100.00
CONT_ASSIGN	1603	1	1	100.00
CONT_ASSIGN	1604	1	1	100.00
CONT_ASSIGN	1605	1	1	100.00
CONT_ASSIGN	1607	1	1	100.00
CONT_ASSIGN	1608	1	1	100.00
CONT_ASSIGN	1610	1	1	100.00
CONT_ASSIGN	1612	1	1	100.00
CONT_ASSIGN	1614	1	1	100.00
CONT_ASSIGN	1616	1	1	100.00
CONT_ASSIGN	1617	1	1	100.00
CONT_ASSIGN	1618	1	1	100.00
CONT_ASSIGN	1620	1	1	100.00
CONT_ASSIGN	1622	1	1	100.00
CONT_ASSIGN	1623	1	1	100.00
CONT_ASSIGN	1624	1	1	100.00
CONT_ASSIGN	1626	1	1	100.00
CONT_ASSIGN	1628	1	1	100.00
ALWAYS	1632	14	14	100.00
ALWAYS	1650	55	55	100.00
CONT_ASSIGN	1755	0	0
CONT_ASSIGN	1763	1	1	100.00
CONT_ASSIGN	1764	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_uart_0.1/rtl/uart_reg_top.sv' or '../src/lowrisc_ip_uart_0.1/rtl/uart_reg_top.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
68	1	1
69	1	1
70	1	1
71	1	1
			MISSING_ELSE
77	1	1
89	1	1
90	1	1
118	1	1
119	1	1
662	1	1
677	1	1
693	1	1
709	1	1
725	1	1
741	1	1
757	1	1
773	1	1
789	1	1
795	1	1
809	1	1
1202	1	1
1243	1	1
1271	1	1
1299	1	1
1327	1	1
1493	1	1
1494	1	1
1495	1	1
1496	1	1
1497	1	1
1498	1	1
1499	1	1
1500	1	1
1501	1	1
1502	1	1
1503	1	1
1504	1	1
1505	1	1
1506	1	1
1509	1	1
1513	1	1
1530	1	1
1532	1	1
1534	1	1
1536	1	1
1538	1	1
1540	1	1
1542	1	1
1544	1	1
1546	1	1
1547	1	1
1549	1	1
1551	1	1
1553	1	1
1555	1	1
1557	1	1
1559	1	1
1561	1	1
1563	1	1
1564	1	1
1566	1	1
1568	1	1
1570	1	1
1572	1	1
1574	1	1
1576	1	1
1578	1	1
1580	1	1
1581	1	1
1583	1	1
1584	1	1
1586	1	1
1588	1	1
1590	1	1
1592	1	1
1594	1	1
1596	1	1
1598	1	1
1600	1	1
1602	1	1
1603	1	1
1604	1	1
1605	1	1
1607	1	1
1608	1	1
1610	1	1
1612	1	1
1614	1	1
1616	1	1
1617	1	1
1618	1	1
1620	1	1
1622	1	1
1623	1	1
1624	1	1
1626	1	1
1628	1	1
1632	1	1
1633	1	1
1634	1	1
1635	1	1
1636	1	1
1637	1	1
1638	1	1
1639	1	1
1640	1	1
1641	1	1
1642	1	1
1643	1	1
1644	1	1
1645	1	1
1650	1	1
1651	1	1
1653	1	1
1654	1	1
1655	1	1
1656	1	1
1657	1	1
1658	1	1
1659	1	1
1660	1	1
1664	1	1
1665	1	1
1666	1	1
1667	1	1
1668	1	1
1669	1	1
1670	1	1
1671	1	1
1675	1	1
1676	1	1
1677	1	1
1678	1	1
1679	1	1
1680	1	1
1681	1	1
1682	1	1
1686	1	1
1690	1	1
1691	1	1
1692	1	1
1693	1	1
1694	1	1
1695	1	1
1696	1	1
1697	1	1
1698	1	1
1702	1	1
1703	1	1
1704	1	1
1705	1	1
1706	1	1
1707	1	1
1711	1	1
1715	1	1
1719	1	1
1720	1	1
1721	1	1
1722	1	1
1726	1	1
1727	1	1
1731	1	1
1732	1	1
1736	1	1
1740	1	1
1741	1	1
1755		unreachable
1763	1	1
1764	1	1

---

Cond Coverage for Module : uart_reg_top

	Total	Covered	Percent
Conditions	153	153	100.00
Logical	153	153	100.00
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (reg_we && ((!addrmiss)))
             ---1--    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T31,T32,T33
1	1	Covered	T1,T2,T3

 LINE       70
 EXPRESSION (intg_err || reg_we_err)
             ----1---    -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T82,T83,T84
1	0	Covered	T31,T39,T40

 LINE       77
 EXPRESSION (err_q | intg_err | reg_we_err)
             --1--   ----2---   -----3----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T82,T83,T84
0	1	0	Covered	T31,T39,T40
1	0	0	Covered	T31,T39,T40

 LINE       119
 EXPRESSION (addrmiss | wr_err | intg_err)
             ----1---   ---2--   ----3---

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T31,T39,T40
0	1	0	Covered	T32,T33,T34
1	0	0	Covered	T32,T33,T34

 LINE       1494
 EXPRESSION (reg_addr == uart_reg_pkg::UART_INTR_STATE_OFFSET)
            -------------------------1------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1495
 EXPRESSION (reg_addr == uart_reg_pkg::UART_INTR_ENABLE_OFFSET)
            -------------------------1-------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1496
 EXPRESSION (reg_addr == uart_reg_pkg::UART_INTR_TEST_OFFSET)
            ------------------------1------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1497
 EXPRESSION (reg_addr == uart_reg_pkg::UART_ALERT_TEST_OFFSET)
            -------------------------1------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1498
 EXPRESSION (reg_addr == uart_reg_pkg::UART_CTRL_OFFSET)
            ----------------------1---------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1499
 EXPRESSION (reg_addr == uart_reg_pkg::UART_STATUS_OFFSET)
            -----------------------1----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       1500
 EXPRESSION (reg_addr == uart_reg_pkg::UART_RDATA_OFFSET)
            ----------------------1----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       1501
 EXPRESSION (reg_addr == uart_reg_pkg::UART_WDATA_OFFSET)
            ----------------------1----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1502
 EXPRESSION (reg_addr == uart_reg_pkg::UART_FIFO_CTRL_OFFSET)
            ------------------------1------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1503
 EXPRESSION (reg_addr == uart_reg_pkg::UART_FIFO_STATUS_OFFSET)
            -------------------------1-------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       1504
 EXPRESSION (reg_addr == uart_reg_pkg::UART_OVRD_OFFSET)
            ----------------------1---------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1505
 EXPRESSION (reg_addr == uart_reg_pkg::UART_VAL_OFFSET)
            ---------------------1---------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T5

 LINE       1506
 EXPRESSION (reg_addr == uart_reg_pkg::UART_TIMEOUT_CTRL_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1509
 EXPRESSION ((reg_re || reg_we) ? ((~|addr_hit)) : 1'b0)
             ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1509
 SUB-EXPRESSION (reg_re || reg_we)
                 ---1--    ---2--

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       1513
 EXPRESSION 
 Number  Term
      1  reg_we & 
      2  ((addr_hit[0] & ((|(4'b1 & (~reg_be))))) | (addr_hit[1] & ((|(4'b1 & (~reg_be))))) | (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | (addr_hit[4] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[5] & ((|(4'b1 & (~reg_be))))) | (addr_hit[6] & ((|(4'b1 & (~reg_be))))) | (addr_hit[7] & ((|(4'b1 & (~reg_be))))) | (addr_hit[8] & ((|(4'b1 & (~reg_be))))) | (addr_hit[9] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[10] & ((|(4'b1 & (~reg_be))))) | (addr_hit[11] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[12] & ((|(4'b1111 & (~reg_be)))))))

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T31,T32,T33

 LINE       1513
 SUB-EXPRESSION 
 Number  Term
      1  (addr_hit[0] & ((|(4'b1 & (~reg_be))))) | 
      2  (addr_hit[1] & ((|(4'b1 & (~reg_be))))) | 
      3  (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | 
      4  (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | 
      5  (addr_hit[4] & ((|(4'b1111 & (~reg_be))))) | 
      6  (addr_hit[5] & ((|(4'b1 & (~reg_be))))) | 
      7  (addr_hit[6] & ((|(4'b1 & (~reg_be))))) | 
      8  (addr_hit[7] & ((|(4'b1 & (~reg_be))))) | 
      9  (addr_hit[8] & ((|(4'b1 & (~reg_be))))) | 
     10  (addr_hit[9] & ((|(4'b0111 & (~reg_be))))) | 
     11  (addr_hit[10] & ((|(4'b1 & (~reg_be))))) | 
     12  (addr_hit[11] & ((|(4'b0011 & (~reg_be))))) | 
     13  (addr_hit[12] & ((|(4'b1111 & (~reg_be))))))

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	Status	Tests
0	0	0	0	0	0	0	0	0	0	0	0	0	Covered	T1,T2,T3
0	0	0	0	0	0	0	0	0	0	0	0	1	Covered	T1,T2,T3
0	0	0	0	0	0	0	0	0	0	0	1	0	Covered	T2,T5,T6
0	0	0	0	0	0	0	0	0	0	1	0	0	Covered	T3,T5,T6
0	0	0	0	0	0	0	0	0	1	0	0	0	Covered	T2,T4,T5
0	0	0	0	0	0	0	0	1	0	0	0	0	Covered	T2,T4,T5
0	0	0	0	0	0	0	1	0	0	0	0	0	Covered	T3,T4,T5
0	0	0	0	0	0	1	0	0	0	0	0	0	Covered	T2,T4,T6
0	0	0	0	0	1	0	0	0	0	0	0	0	Covered	T2,T4,T5
0	0	0	0	1	0	0	0	0	0	0	0	0	Covered	T1,T2,T3
0	0	0	1	0	0	0	0	0	0	0	0	0	Covered	T1,T2,T3
0	0	1	0	0	0	0	0	0	0	0	0	0	Covered	T1,T2,T4
0	1	0	0	0	0	0	0	0	0	0	0	0	Covered	T1,T2,T3
1	0	0	0	0	0	0	0	0	0	0	0	0	Covered	T1,T2,T4

 LINE       1513
 SUB-EXPRESSION (addr_hit[0] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       1513
 SUB-EXPRESSION (addr_hit[1] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       1513
 SUB-EXPRESSION (addr_hit[2] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       1513
 SUB-EXPRESSION (addr_hit[3] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T5
1	1	Covered	T1,T2,T3

 LINE       1513
 SUB-EXPRESSION (addr_hit[4] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T5,T6
1	1	Covered	T1,T2,T3

 LINE       1513
 SUB-EXPRESSION (addr_hit[5] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T4,T5

 LINE       1513
 SUB-EXPRESSION (addr_hit[6] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T5
1	1	Covered	T2,T4,T6

 LINE       1513
 SUB-EXPRESSION (addr_hit[7] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T4,T5

 LINE       1513
 SUB-EXPRESSION (addr_hit[8] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T4,T5

 LINE       1513
 SUB-EXPRESSION (addr_hit[9] & ((|(4'b0111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T5,T6
1	1	Covered	T2,T4,T5

 LINE       1513
 SUB-EXPRESSION (addr_hit[10] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T5,T6

 LINE       1513
 SUB-EXPRESSION (addr_hit[11] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T5
1	1	Covered	T2,T5,T6

 LINE       1513
 SUB-EXPRESSION (addr_hit[12] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T5,T6
1	1	Covered	T1,T2,T3

 LINE       1530
 EXPRESSION (addr_hit[0] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T38,T41,T44
1	1	1	Covered	T1,T2,T4

 LINE       1547
 EXPRESSION (addr_hit[1] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T32,T33,T34
1	1	1	Covered	T1,T2,T3

 LINE       1564
 EXPRESSION (addr_hit[2] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T32,T34,T38
1	1	1	Covered	T1,T2,T4

 LINE       1581
 EXPRESSION (addr_hit[3] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T33,T38,T44
1	1	1	Covered	T3,T5,T8

 LINE       1584
 EXPRESSION (addr_hit[4] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T34,T38,T39
1	1	1	Covered	T3,T5,T6

 LINE       1603
 EXPRESSION (addr_hit[5] & reg_re & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T3,T4
1	1	0	Covered	T41,T43,T90
1	1	1	Covered	T3,T5,T6

 LINE       1604
 EXPRESSION (addr_hit[6] & reg_re & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T3,T4
1	1	0	Covered	T39,T40,T51
1	1	1	Covered	T11,T19,T21

 LINE       1605
 EXPRESSION (addr_hit[7] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T31,T32,T34
1	1	1	Covered	T35,T36,T37

 LINE       1608
 EXPRESSION (addr_hit[8] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T32,T33,T40
1	1	1	Covered	T3,T5,T6

 LINE       1617
 EXPRESSION (addr_hit[9] & reg_re & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T3,T4
1	1	0	Covered	T39,T41,T91
1	1	1	Covered	T3,T5,T6

 LINE       1618
 EXPRESSION (addr_hit[10] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T34,T42,T44
1	1	1	Covered	T3,T5,T6

 LINE       1623
 EXPRESSION (addr_hit[11] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T3,T5
1	1	0	Covered	T51,T92,T93
1	1	1	Covered	T3,T5,T8

 LINE       1624
 EXPRESSION (addr_hit[12] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T32,T33,T38
1	1	1	Covered	T3,T5,T6

---

Branch Coverage for Module : uart_reg_top

	Line No.	Total	Covered	Percent
Branches		19	19	100.00
TERNARY	1509	2	2	100.00
IF	68	3	3	100.00
CASE	1651	14	14	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_uart_0.1/rtl/uart_reg_top.sv' or '../src/lowrisc_ip_uart_0.1/rtl/uart_reg_top.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	1509	((reg_re || reg_we)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	68	if ((!rst_ni))
-2-:	70	if ((intg_err || reg_we_err))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T31,T39,T40
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1651	case (1'b1)

Branches:

-1-	Status	Tests
addr_hit[0]	Covered	T1,T2,T3
addr_hit[1]	Covered	T1,T2,T3
addr_hit[2]	Covered	T1,T2,T3
addr_hit[3]	Covered	T1,T2,T3
addr_hit[4]	Covered	T1,T2,T3
addr_hit[5]	Covered	T2,T3,T4
addr_hit[6]	Covered	T2,T3,T4
addr_hit[7]	Covered	T1,T2,T3
addr_hit[8]	Covered	T1,T2,T3
addr_hit[9]	Covered	T2,T3,T4
addr_hit[10]	Covered	T1,T2,T3
addr_hit[11]	Covered	T2,T3,T5
addr_hit[12]	Covered	T1,T2,T3
default	Covered	T1,T2,T3

---

Assert Coverage for Module : uart_reg_top

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
en2addrHit	2147483647	85354567	0	0
reAfterRv	2147483647	85354534	0	0
rePulse	2147483647	83990742	0	0
wePulse	2147483647	1363792	0	0

en2addrHit

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	85354567	0	0
T1	855	22	0	0
T2	1337	40	0	0
T3	2189	46	0	0
T4	1393	40	0	0
T5	1623	111	0	0
T6	1344	103	0	0
T7	1361	22	0	0
T8	1141	232	0	0
T9	817	54	0	0
T10	1317	22	0	0

reAfterRv

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	85354534	0	0
T1	855	22	0	0
T2	1337	40	0	0
T3	2189	46	0	0
T4	1393	40	0	0
T5	1623	111	0	0
T6	1344	103	0	0
T7	1361	22	0	0
T8	1141	232	0	0
T9	817	54	0	0
T10	1317	22	0	0

rePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	83990742	0	0
T1	855	11	0	0
T2	1337	20	0	0
T3	2189	36	0	0
T4	1393	20	0	0
T5	1623	101	0	0
T6	1344	59	0	0
T7	1361	11	0	0
T8	1141	127	0	0
T9	817	34	0	0
T10	1317	11	0	0

wePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1363792	0	0
T1	855	11	0	0
T2	1337	20	0	0
T3	2189	10	0	0
T4	1393	20	0	0
T5	1623	10	0	0
T6	1344	44	0	0
T7	1361	11	0	0
T8	1141	105	0	0
T9	817	20	0	0
T10	1317	11	0	0