Unified Coverage Report :: Module :: uart_csr_assert_fpv

Module : uart_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_uart_csr_assert_0/uart_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.uart_csr_assert	100.00						100.00

---

Module Instance : tb.dut.uart_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : uart_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	15204350	0	0
ctrl_rd_A	2147483647	359145	0	0
intr_enable_rd_A	2147483647	322303	0	0
ovrd_rd_A	2147483647	359918	0	0
timeout_ctrl_rd_A	2147483647	360436	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	15204350	0	0
T3	2189	4	0	0
T4	1393	0	0	0
T5	1623	0	0	0
T6	1344	0	0	0
T7	1361	0	0	0
T8	1141	0	0	0
T9	817	0	0	0
T10	1317	0	0	0
T31	4468	2	0	0
T32	0	494	0	0
T33	0	356	0	0
T34	0	576	0	0
T38	0	271	0	0
T39	0	3	0	0
T40	0	4	0	0
T41	0	3	0	0
T45	873	0	0	0
T108	0	2	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	359145	0	0
T3	2189	30	0	0
T4	1393	0	0	0
T5	1623	38	0	0
T6	1344	0	0	0
T7	1361	0	0	0
T8	1141	0	0	0
T9	817	0	0	0
T10	1317	0	0	0
T31	4468	0	0	0
T32	0	63	0	0
T36	0	3	0	0
T39	0	98	0	0
T40	0	337	0	0
T41	0	404	0	0
T42	0	9	0	0
T45	873	0	0	0
T50	0	11	0	0
T60	0	42	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	322303	0	0
T2	1337	14	0	0
T3	2189	7	0	0
T4	1393	14	0	0
T5	1623	35	0	0
T6	1344	0	0	0
T7	1361	3	0	0
T8	1141	0	0	0
T9	817	0	0	0
T10	1317	11	0	0
T31	4468	0	0	0
T32	0	37	0	0
T50	0	25	0	0
T57	0	10	0	0
T109	0	16	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	359918	0	0
T3	2189	2	0	0
T4	1393	0	0	0
T5	1623	41	0	0
T6	1344	0	0	0
T7	1361	0	0	0
T8	1141	0	0	0
T9	817	0	0	0
T10	1317	0	0	0
T31	4468	0	0	0
T32	0	71	0	0
T36	0	4	0	0
T39	0	32	0	0
T40	0	117	0	0
T41	0	112	0	0
T42	0	5	0	0
T45	873	0	0	0
T50	0	13	0	0
T60	0	5	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	360436	0	0
T3	2189	11	0	0
T4	1393	0	0	0
T5	1623	36	0	0
T6	1344	0	0	0
T7	1361	0	0	0
T8	1141	0	0	0
T9	817	0	0	0
T10	1317	0	0	0
T31	4468	0	0	0
T32	0	55	0	0
T36	0	4	0	0
T39	0	11	0	0
T40	0	110	0	0
T41	0	133	0	0
T42	0	9	0	0
T45	873	0	0	0
T50	0	26	0	0
T60	0	15	0	0