Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	66614026	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

32031493

1

T1

107

T2

235

T3

148

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	89027437	1			T1	220		T2	82		T3	87
values[0x0]	4545697	1			T1	9		T2	89		T3	62
values[0x1]	5072385	1			T1	11		T2	95		T3	53

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	46990497	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

51655022

1

T1

138

T2

247

T3

163

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	379353	1			T2	1		T8	4		T9	1
valid_sources[0x01]	367630	1			T2	1		T8	2		T36	1
valid_sources[0x02]	356462	1			T36	1		T84	6		T41	3
valid_sources[0x03]	362048	1			T1	1		T2	3		T8	7
valid_sources[0x04]	380632	1			T1	4		T2	5		T8	4
valid_sources[0x05]	341507	1			T8	2		T9	1		T36	5
valid_sources[0x06]	360076	1			T2	1		T3	9		T7	2
valid_sources[0x07]	435680	1			T1	1		T36	2		T37	5
valid_sources[0x08]	356438	1			T1	1		T8	1		T37	2
valid_sources[0x09]	355020	1			T1	2		T2	1		T3	10
valid_sources[0x0a]	356348	1			T1	1		T2	1		T8	2
valid_sources[0x0b]	357049	1			T2	1		T4	1		T8	3
valid_sources[0x0c]	352225	1			T1	1		T8	2		T36	6
valid_sources[0x0d]	417573	1			T2	1		T36	2		T81	1
valid_sources[0x0e]	366606	1			T2	1		T7	10		T8	5
valid_sources[0x0f]	360668	1			T2	1		T37	5		T84	1
valid_sources[0x10]	365110	1			T1	1		T2	1		T36	2
valid_sources[0x11]	377393	1			T1	2		T8	7		T36	5
valid_sources[0x12]	397112	1			T3	5		T4	8		T8	2
valid_sources[0x13]	380509	1			T1	2		T8	4		T36	2
valid_sources[0x14]	355796	1			T2	2		T8	3		T84	2
valid_sources[0x15]	400713	1			T1	1		T2	3		T7	2
valid_sources[0x16]	372213	1			T1	2		T2	3		T8	1
valid_sources[0x17]	367789	1			T1	2		T2	1		T84	3
valid_sources[0x18]	386255	1			T1	1		T2	1		T8	3
valid_sources[0x19]	367159	1			T1	3		T36	6		T84	7
valid_sources[0x1a]	357500	1			T2	2		T36	2		T84	7
valid_sources[0x1b]	380263	1			T1	1		T36	3		T84	3
valid_sources[0x1c]	415193	1			T1	2		T2	3		T3	3
valid_sources[0x1d]	466872	1			T1	2		T2	1		T8	3
valid_sources[0x1e]	502505	1			T1	4		T8	1		T36	4
valid_sources[0x1f]	343373	1			T1	4		T2	1		T8	2
valid_sources[0x20]	349363	1			T50	1		T36	1		T84	2
valid_sources[0x21]	458401	1			T1	3		T2	1		T3	6
valid_sources[0x22]	424540	1			T1	1		T2	1		T8	2
valid_sources[0x23]	392970	1			T1	1		T2	1		T8	1
valid_sources[0x24]	371486	1			T3	1		T8	1		T36	1
valid_sources[0x25]	384429	1			T2	1		T36	2		T84	8
valid_sources[0x26]	369752	1			T1	1		T8	5		T36	3
valid_sources[0x27]	376501	1			T1	4		T2	3		T4	1
valid_sources[0x28]	355729	1			T2	1		T3	1		T36	4
valid_sources[0x29]	360259	1			T2	3		T8	2		T9	4
valid_sources[0x2a]	375549	1			T1	5		T4	1		T8	1
valid_sources[0x2b]	591618	1			T1	1		T2	1		T3	4
valid_sources[0x2c]	375138	1			T2	2		T8	1		T36	8
valid_sources[0x2d]	357087	1			T2	1		T36	2		T37	2
valid_sources[0x2e]	377212	1			T1	1		T4	1		T8	1
valid_sources[0x2f]	364393	1			T1	1		T3	15		T8	1
valid_sources[0x30]	350495	1			T1	3		T2	1		T8	1
valid_sources[0x31]	339394	1			T2	1		T8	4		T36	3
valid_sources[0x32]	365849	1			T2	2		T3	12		T8	1
valid_sources[0x33]	374765	1			T2	1		T8	5		T36	3
valid_sources[0x34]	403067	1			T8	3		T36	3		T84	1
valid_sources[0x35]	397510	1			T1	3		T2	1		T36	1
valid_sources[0x36]	452015	1			T2	1		T8	4		T36	3
valid_sources[0x37]	391768	1			T2	1		T3	5		T4	1
valid_sources[0x38]	380306	1			T1	1		T8	1		T36	1
valid_sources[0x39]	368966	1			T1	2		T8	3		T9	3
valid_sources[0x3a]	386678	1			T1	1		T2	1		T3	5
valid_sources[0x3b]	350879	1			T1	1		T8	5		T9	1
valid_sources[0x3c]	362527	1			T8	2		T36	3		T84	11
valid_sources[0x3d]	353282	1			T2	1		T8	3		T9	3
valid_sources[0x3e]	359513	1			T8	7		T36	1		T84	4
valid_sources[0x3f]	385474	1			T2	2		T8	3		T9	5
valid_sources[0x40]	347600	1			T2	1		T8	2		T36	2
valid_sources[0x41]	483816	1			T1	3		T2	5		T3	5
valid_sources[0x42]	379497	1			T2	4		T36	1		T37	1
valid_sources[0x43]	377353	1			T2	1		T8	1		T84	5
valid_sources[0x44]	335344	1			T1	1		T7	2		T8	2
valid_sources[0x45]	362812	1			T1	1		T2	2		T8	2
valid_sources[0x46]	499474	1			T1	1		T36	1		T37	6
valid_sources[0x47]	363808	1			T1	5		T4	1		T7	7
valid_sources[0x48]	372854	1			T2	1		T5	14		T8	6
valid_sources[0x49]	383921	1			T2	2		T8	1		T36	1
valid_sources[0x4a]	429331	1			T1	1		T2	3		T8	5
valid_sources[0x4b]	370723	1			T1	2		T82	1		T84	4
valid_sources[0x4c]	354988	1			T2	1		T3	3		T36	1
valid_sources[0x4d]	375541	1			T3	1		T4	2		T8	2
valid_sources[0x4e]	410630	1			T2	1		T4	2		T8	3
valid_sources[0x4f]	367474	1			T1	2		T8	1		T36	2
valid_sources[0x50]	359279	1			T1	1		T2	1		T3	5
valid_sources[0x51]	444292	1			T1	2		T2	2		T8	5
valid_sources[0x52]	408787	1			T1	1		T36	3		T84	2
valid_sources[0x53]	359263	1			T1	3		T8	5		T9	3
valid_sources[0x54]	369155	1			T1	1		T2	2		T3	3
valid_sources[0x55]	358329	1			T8	9		T84	6		T41	1
valid_sources[0x56]	338737	1			T2	2		T8	3		T36	2
valid_sources[0x57]	348104	1			T7	3		T8	1		T36	3
valid_sources[0x58]	367073	1			T5	15		T8	4		T36	3
valid_sources[0x59]	346334	1			T6	22		T8	1		T36	1
valid_sources[0x5a]	365597	1			T1	1		T3	6		T36	1
valid_sources[0x5b]	375484	1			T2	3		T8	7		T36	6
valid_sources[0x5c]	400054	1			T2	1		T8	1		T84	6
valid_sources[0x5d]	368254	1			T2	2		T8	3		T84	1
valid_sources[0x5e]	375797	1			T1	1		T8	2		T36	4
valid_sources[0x5f]	348032	1			T1	2		T3	3		T8	4
valid_sources[0x60]	424377	1			T2	3		T8	1		T36	2
valid_sources[0x61]	407715	1			T1	1		T2	1		T8	2
valid_sources[0x62]	426890	1			T2	2		T8	2		T9	3
valid_sources[0x63]	375857	1			T1	2		T4	2		T8	5
valid_sources[0x64]	384798	1			T8	5		T36	2		T37	9
valid_sources[0x65]	376423	1			T1	1		T2	3		T3	1
valid_sources[0x66]	361767	1			T2	1		T8	1		T84	3
valid_sources[0x67]	359710	1			T2	1		T8	7		T36	1
valid_sources[0x68]	363582	1			T1	3		T2	1		T8	1
valid_sources[0x69]	375804	1			T1	1		T9	3		T36	6
valid_sources[0x6a]	361023	1			T1	1		T36	1		T84	3
valid_sources[0x6b]	397655	1			T8	3		T37	2		T84	3
valid_sources[0x6c]	381893	1			T2	1		T8	3		T36	2
valid_sources[0x6d]	917254	1			T2	1		T8	2		T9	2
valid_sources[0x6e]	359311	1			T1	2		T8	2		T36	2
valid_sources[0x6f]	448254	1			T2	1		T36	3		T37	8
valid_sources[0x70]	383159	1			T1	2		T2	2		T8	3
valid_sources[0x71]	350024	1			T1	3		T2	2		T8	3
valid_sources[0x72]	397037	1			T1	1		T2	1		T8	6
valid_sources[0x73]	347674	1			T1	2		T84	4		T41	1
valid_sources[0x74]	374965	1			T1	1		T50	1		T36	3
valid_sources[0x75]	355603	1			T1	1		T8	2		T36	2
valid_sources[0x76]	381120	1			T1	3		T2	1		T3	1
valid_sources[0x77]	342359	1			T1	1		T2	1		T8	3
valid_sources[0x78]	369606	1			T8	2		T84	1		T55	1
valid_sources[0x79]	359340	1			T1	1		T2	1		T8	5
valid_sources[0x7a]	389988	1			T1	1		T3	3		T8	2
valid_sources[0x7b]	400829	1			T8	5		T36	3		T84	3
valid_sources[0x7c]	360658	1			T1	1		T2	1		T3	9
valid_sources[0x7d]	402347	1			T1	1		T2	1		T9	1
valid_sources[0x7e]	426343	1			T1	3		T3	5		T36	3
valid_sources[0x7f]	372971	1			T2	1		T3	13		T9	1
valid_sources[0x80]	412720	1			T1	1		T8	2		T9	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

23548165

1

T1

99

T2

60

T3

43

values[0x0]

all_enables

biggest_size

4270055

1

T1

4

T2

87

T3

58

values[0x1]

all_enables

biggest_size

4213273

1

T1

4

T2

88

T3

47