Unified Coverage Report :: Module :: uart_csr_assert_fpv

Module : uart_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_uart_csr_assert_0/uart_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.uart_csr_assert	100.00						100.00

---

Module Instance : tb.dut.uart_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : uart_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	13973701	0	0
ctrl_rd_A	2147483647	256943	0	0
intr_enable_rd_A	2147483647	228722	0	0
ovrd_rd_A	2147483647	252895	0	0
timeout_ctrl_rd_A	2147483647	253052	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	13973701	0	0
T2	1439	47	0	0
T3	1900	24	0	0
T4	1223	0	0	0
T5	878	0	0	0
T6	1269	0	0	0
T7	1673	0	0	0
T8	8553	2	0	0
T9	1825	0	0	0
T10	1300	0	0	0
T36	0	654	0	0
T37	0	645	0	0
T41	0	2	0	0
T43	0	82	0	0
T49	1089	0	0	0
T83	0	54	0	0
T90	0	14	0	0
T108	0	11	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	256943	0	0
T8	8553	433	0	0
T9	1825	23	0	0
T10	1300	0	0	0
T36	4949	0	0	0
T37	10076	0	0	0
T38	0	2	0	0
T42	0	438	0	0
T44	0	25	0	0
T45	0	82	0	0
T49	1089	0	0	0
T50	1387	0	0	0
T55	0	4	0	0
T56	0	74	0	0
T73	0	16	0	0
T74	0	101	0	0
T81	1802	0	0	0
T82	1313	0	0	0
T83	1926	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	228722	0	0
T7	1673	7	0	0
T8	8553	316	0	0
T9	1825	11	0	0
T10	1300	10	0	0
T36	4949	0	0	0
T37	10076	0	0	0
T38	0	3	0	0
T42	0	371	0	0
T49	1089	0	0	0
T50	1387	0	0	0
T56	0	97	0	0
T73	0	65	0	0
T81	1802	17	0	0
T82	1313	0	0	0
T109	0	17	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	252895	0	0
T8	8553	147	0	0
T9	1825	10	0	0
T10	1300	0	0	0
T36	4949	0	0	0
T37	10076	0	0	0
T38	0	5	0	0
T42	0	102	0	0
T44	0	7	0	0
T45	0	91	0	0
T49	1089	0	0	0
T50	1387	0	0	0
T55	0	3	0	0
T56	0	54	0	0
T73	0	35	0	0
T74	0	39	0	0
T81	1802	0	0	0
T82	1313	0	0	0
T83	1926	0	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	253052	0	0
T8	8553	116	0	0
T9	1825	50	0	0
T10	1300	0	0	0
T36	4949	0	0	0
T37	10076	0	0	0
T38	0	7	0	0
T42	0	145	0	0
T44	0	10	0	0
T45	0	80	0	0
T49	1089	0	0	0
T50	1387	0	0	0
T55	0	7	0	0
T56	0	63	0	0
T73	0	41	0	0
T74	0	33	0	0
T81	1802	0	0	0
T82	1313	0	0	0
T83	1926	0	0	0