Unified Coverage Report :: Module :: uart_rx

Module : uart_rx

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_uart_0.1/rtl/uart_rx.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.uart_core.uart_rx	100.00	100.00	100.00			100.00

---

Module Instance : tb.dut.uart_core.uart_rx

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.13	100.00	99.06			98.33		uart_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : uart_rx

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	35	1	1	100.00
ALWAYS	38	11	11	100.00
ALWAYS	54	26	26	100.00
ALWAYS	93	3	3	100.00
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	102	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_uart_0.1/rtl/uart_rx.sv' or '../src/lowrisc_ip_uart_0.1/rtl/uart_rx.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
35	1	1
38	1	1
39	1	1
40	1	1
41	1	1
42	1	1
43	1	1
45	1	1
46	1	1
47	1	1
48	1	1
49	1	1
54	1	1
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
66	1	1
67	1	1
			MISSING_ELSE
70	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
77	1	1
78	1	1
81	1	1
82	1	1
84	1	1
85	1	1
86	1	1
			MISSING_ELSE
93	2	2
94	1	1
98	1	1
99	1	1
101	1	1
102	1	1

---

Cond Coverage for Module : uart_rx

	Total	Covered	Percent
Conditions	29	29	100.00
Logical	29	29	100.00
Non-Logical	0	0
Event	0	0

 LINE       70
 EXPRESSION (idle_q && ((!rx)))
             ---1--    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T12,T13
1	1	Covered	T11,T12,T13

 LINE       74
 EXPRESSION (parity_enable ? 4'd11 : 4'd10)
             ------1------

-1-	Status	Tests
0	Covered	T11,T12,T13
1	Covered	T11,T12,T13

 LINE       77
 EXPRESSION (((!idle_q)) && tick_baud_q)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T12,T13
1	1	Covered	T11,T12,T13

 LINE       78
 EXPRESSION ((bit_cnt_q == (parity_enable ? 4'd11 : 4'd10)) && rx)
             -----------------------1----------------------    -2

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T12,T13
1	1	Covered	T13,T20,T14

 LINE       78
 SUB-EXPRESSION (bit_cnt_q == (parity_enable ? 4'd11 : 4'd10))
                -----------------------1----------------------

-1-	Status	Tests
0	Covered	T11,T12,T13
1	Covered	T11,T12,T13

 LINE       86
 EXPRESSION (bit_cnt_q == 4'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T11,T12,T13
1	Covered	T11,T12,T13

 LINE       94
 EXPRESSION (tick_baud_q & (bit_cnt_q == 4'b1))
             -----1-----   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T12,T13
1	1	Covered	T11,T12,T13

 LINE       94
 SUB-EXPRESSION (bit_cnt_q == 4'b1)
                ---------1---------

-1-	Status	Tests
0	Covered	T11,T12,T13
1	Covered	T11,T12,T13

 LINE       99
 EXPRESSION (parity_enable ? sreg_q[8:1] : sreg_q[9:2])
             ------1------

-1-	Status	Tests
0	Covered	T11,T12,T13
1	Covered	T11,T12,T13

 LINE       101
 EXPRESSION (rx_valid_q & ((~sreg_q[10])))
             -----1----   -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T12,T13
1	1	Covered	T25,T29,T30

 LINE       102
 EXPRESSION (parity_enable & rx_valid_q & ((^{sreg_q[9:1], parity_odd})))
             ------1------   -----2----   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T11,T12,T13
1	0	1	Covered	T11,T12,T13
1	1	0	Covered	T11,T12,T19
1	1	1	Covered	T34,T25,T26

---

Branch Coverage for Module : uart_rx

	Line No.	Total	Covered	Percent
Branches		14	14	100.00
TERNARY	99	2	2	100.00
IF	38	2	2	100.00
IF	54	8	8	100.00
IF	93	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_uart_0.1/rtl/uart_rx.sv' or '../src/lowrisc_ip_uart_0.1/rtl/uart_rx.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	99	(parity_enable) ? 

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	38	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	54	if ((!rx_enable))
-2-:	66	if (tick_baud_x16)
-3-:	70	if ((idle_q && (!rx)))
-4-:	74	(parity_enable) ? 
-5-:	77	if (((!idle_q) && tick_baud_q))
-6-:	78	if (((bit_cnt_q == (parity_enable ? 4'd11 : 4'd10)) && rx))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
1	-	-	-	-	-	Covered	T11,T12,T13
0	1	-	-	-	-	Covered	T11,T12,T13
0	0	-	-	-	-	Covered	T11,T12,T13
0	-	1	1	-	-	Covered	T11,T12,T13
0	-	1	0	-	-	Covered	T11,T12,T13
0	-	0	-	1	1	Covered	T13,T20,T14
0	-	0	-	1	0	Covered	T11,T12,T13
0	-	0	-	0	-	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	93	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T11,T12,T13