Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	68676306	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

31079476

1

T1

112

T2

15

T3

10

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	90020267	1			T1	62		T2	47		T3	11
values[0x0]	4605405	1			T1	24		T2	11		T3	7
values[0x1]	5130110	1			T1	26		T2	9		T3	4

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	48206525	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

51549257

1

T1

112

T2

31

T3

12

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	372889	1			T5	1		T6	2		T8	2
valid_sources[0x01]	389229	1			T5	1		T6	9		T46	3
valid_sources[0x02]	470735	1			T6	10		T9	2		T46	8
valid_sources[0x03]	356863	1			T5	2		T6	2		T8	1
valid_sources[0x04]	392031	1			T5	2		T6	2		T8	1
valid_sources[0x05]	685001	1			T5	1		T6	2		T8	1
valid_sources[0x06]	414125	1			T6	3		T8	2		T46	2
valid_sources[0x07]	407322	1			T5	2		T6	3		T46	7
valid_sources[0x08]	359700	1			T5	1		T6	6		T8	2
valid_sources[0x09]	409849	1			T5	1		T6	5		T9	1
valid_sources[0x0a]	379084	1			T5	2		T6	5		T46	4
valid_sources[0x0b]	400414	1			T5	1		T6	1		T8	1
valid_sources[0x0c]	435230	1			T5	2		T6	2		T46	7
valid_sources[0x0d]	380036	1			T6	6		T8	2		T46	7
valid_sources[0x0e]	358139	1			T1	7		T5	1		T6	1
valid_sources[0x0f]	363029	1			T5	2		T6	9		T46	6
valid_sources[0x10]	373305	1			T2	2		T5	1		T6	6
valid_sources[0x11]	377651	1			T6	1		T46	9		T47	4
valid_sources[0x12]	405474	1			T2	3		T6	11		T8	1
valid_sources[0x13]	363686	1			T5	4		T6	1		T48	1
valid_sources[0x14]	351347	1			T5	1		T6	4		T9	2
valid_sources[0x15]	392581	1			T6	6		T8	1		T48	1
valid_sources[0x16]	401105	1			T6	6		T46	3		T47	4
valid_sources[0x17]	495908	1			T5	7		T6	4		T8	1
valid_sources[0x18]	370273	1			T5	2		T6	4		T8	1
valid_sources[0x19]	370150	1			T5	1		T46	3		T47	1
valid_sources[0x1a]	364700	1			T5	3		T6	7		T9	1
valid_sources[0x1b]	366615	1			T6	7		T9	1		T46	9
valid_sources[0x1c]	376290	1			T5	2		T6	4		T46	7
valid_sources[0x1d]	352847	1			T5	2		T6	6		T8	1
valid_sources[0x1e]	366945	1			T5	1		T6	1		T46	2
valid_sources[0x1f]	390461	1			T6	3		T10	2		T46	2
valid_sources[0x20]	365196	1			T5	1		T6	6		T9	1
valid_sources[0x21]	378586	1			T6	4		T46	8		T31	3
valid_sources[0x22]	591766	1			T6	7		T8	1		T46	1
valid_sources[0x23]	356048	1			T5	1		T6	3		T8	1
valid_sources[0x24]	375627	1			T5	1		T6	5		T8	1
valid_sources[0x25]	365622	1			T5	2		T6	8		T9	1
valid_sources[0x26]	391848	1			T5	1		T6	7		T8	1
valid_sources[0x27]	376748	1			T6	5		T8	1		T9	2
valid_sources[0x28]	427014	1			T5	4		T6	7		T10	3
valid_sources[0x29]	368263	1			T5	7		T6	10		T46	8
valid_sources[0x2a]	370049	1			T6	4		T8	3		T10	2
valid_sources[0x2b]	359661	1			T5	5		T6	4		T8	1
valid_sources[0x2c]	373877	1			T5	1		T6	9		T8	1
valid_sources[0x2d]	373399	1			T5	6		T6	6		T8	3
valid_sources[0x2e]	375179	1			T2	2		T5	2		T6	2
valid_sources[0x2f]	385766	1			T6	3		T8	3		T9	5
valid_sources[0x30]	385071	1			T6	6		T46	3		T73	2
valid_sources[0x31]	367064	1			T5	1		T6	3		T10	2
valid_sources[0x32]	376662	1			T6	8		T9	1		T46	10
valid_sources[0x33]	368679	1			T6	4		T46	9		T48	1
valid_sources[0x34]	348155	1			T2	3		T6	5		T8	2
valid_sources[0x35]	376986	1			T5	5		T6	7		T46	15
valid_sources[0x36]	378231	1			T6	2		T8	1		T46	5
valid_sources[0x37]	361148	1			T6	4		T9	1		T46	1
valid_sources[0x38]	386505	1			T5	4		T6	2		T31	1
valid_sources[0x39]	393864	1			T5	1		T6	2		T10	1
valid_sources[0x3a]	373921	1			T5	1		T6	7		T8	1
valid_sources[0x3b]	398490	1			T5	1		T6	3		T8	2
valid_sources[0x3c]	370679	1			T5	2		T6	2		T9	1
valid_sources[0x3d]	400633	1			T3	8		T5	4		T6	3
valid_sources[0x3e]	362958	1			T5	2		T6	6		T9	1
valid_sources[0x3f]	390796	1			T5	2		T6	6		T8	1
valid_sources[0x40]	405525	1			T6	4		T46	4		T48	1
valid_sources[0x41]	482457	1			T5	1		T6	2		T8	2
valid_sources[0x42]	390428	1			T5	3		T6	5		T8	2
valid_sources[0x43]	523216	1			T6	5		T46	12		T48	1
valid_sources[0x44]	406475	1			T5	1		T6	6		T46	5
valid_sources[0x45]	386766	1			T5	1		T6	5		T46	4
valid_sources[0x46]	361643	1			T5	1		T6	4		T10	1
valid_sources[0x47]	377873	1			T6	2		T8	1		T46	4
valid_sources[0x48]	427999	1			T5	3		T6	6		T8	1
valid_sources[0x49]	359553	1			T5	1		T6	6		T8	1
valid_sources[0x4a]	368591	1			T5	3		T6	5		T8	1
valid_sources[0x4b]	372667	1			T6	1		T8	1		T46	3
valid_sources[0x4c]	417925	1			T5	2		T6	3		T46	2
valid_sources[0x4d]	378458	1			T5	2		T6	5		T8	1
valid_sources[0x4e]	379750	1			T6	6		T10	1		T46	8
valid_sources[0x4f]	371072	1			T6	4		T46	3		T48	1
valid_sources[0x50]	400207	1			T5	2		T6	12		T9	2
valid_sources[0x51]	356065	1			T6	5		T8	1		T9	1
valid_sources[0x52]	404098	1			T5	2		T6	3		T8	1
valid_sources[0x53]	375542	1			T5	7		T6	3		T8	1
valid_sources[0x54]	355455	1			T5	3		T6	7		T9	1
valid_sources[0x55]	382524	1			T5	2		T6	2		T46	4
valid_sources[0x56]	393795	1			T5	1		T6	5		T46	3
valid_sources[0x57]	375718	1			T5	3		T6	6		T46	1
valid_sources[0x58]	355169	1			T5	1		T6	4		T46	2
valid_sources[0x59]	362638	1			T6	6		T46	18		T31	2
valid_sources[0x5a]	361210	1			T5	1		T6	4		T46	6
valid_sources[0x5b]	371440	1			T5	5		T6	3		T10	2
valid_sources[0x5c]	360166	1			T5	1		T6	3		T8	2
valid_sources[0x5d]	399754	1			T5	1		T6	6		T8	1
valid_sources[0x5e]	371485	1			T5	2		T6	5		T8	3
valid_sources[0x5f]	478961	1			T5	1		T6	6		T46	2
valid_sources[0x60]	381830	1			T1	19		T6	11		T9	1
valid_sources[0x61]	397059	1			T6	3		T8	2		T46	7
valid_sources[0x62]	373710	1			T5	1		T6	2		T8	1
valid_sources[0x63]	361929	1			T5	4		T6	5		T8	2
valid_sources[0x64]	401078	1			T5	1		T6	5		T7	15
valid_sources[0x65]	392445	1			T2	3		T5	1		T6	7
valid_sources[0x66]	633967	1			T6	5		T46	5		T48	1
valid_sources[0x67]	369778	1			T5	1		T6	2		T46	3
valid_sources[0x68]	402564	1			T6	5		T9	1		T46	1
valid_sources[0x69]	348813	1			T6	3		T8	1		T46	11
valid_sources[0x6a]	367856	1			T5	1		T6	3		T8	1
valid_sources[0x6b]	471108	1			T5	1		T6	11		T8	1
valid_sources[0x6c]	409965	1			T5	2		T6	5		T8	1
valid_sources[0x6d]	426081	1			T5	2		T6	8		T46	3
valid_sources[0x6e]	356589	1			T6	7		T8	1		T9	2
valid_sources[0x6f]	363709	1			T5	3		T6	1		T8	1
valid_sources[0x70]	386671	1			T5	6		T6	6		T8	1
valid_sources[0x71]	380764	1			T5	1		T6	9		T46	13
valid_sources[0x72]	377757	1			T5	4		T6	3		T46	10
valid_sources[0x73]	413301	1			T5	6		T6	8		T46	5
valid_sources[0x74]	358346	1			T5	2		T6	7		T46	3
valid_sources[0x75]	384894	1			T5	5		T6	4		T8	1
valid_sources[0x76]	434823	1			T5	2		T6	4		T8	1
valid_sources[0x77]	407721	1			T5	1		T6	3		T46	8
valid_sources[0x78]	399572	1			T5	3		T6	1		T10	1
valid_sources[0x79]	366069	1			T6	4		T8	1		T46	3
valid_sources[0x7a]	408541	1			T5	1		T6	7		T9	1
valid_sources[0x7b]	371684	1			T6	7		T10	1		T46	2
valid_sources[0x7c]	366239	1			T6	1		T8	1		T46	4
valid_sources[0x7d]	362473	1			T6	5		T46	1		T47	1
valid_sources[0x7e]	378283	1			T5	4		T6	3		T9	1
valid_sources[0x7f]	395095	1			T2	1		T5	2		T6	1
valid_sources[0x80]	369890	1			T5	3		T6	4		T8	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

22465930

1

T1

62

T2

6

T3

6

values[0x0]

all_enables

biggest_size

4334352

1

T1

24

T2

7

T3

3

values[0x1]

all_enables

biggest_size

4279194

1

T1

26

T2

2

T3

1