Unified Coverage Report :: Module :: uart_csr_assert_fpv

Module : uart_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_uart_csr_assert_0/uart_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.uart_csr_assert	100.00						100.00

---

Module Instance : tb.dut.uart_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : uart_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	14051665	0	0
ctrl_rd_A	2147483647	374182	0	0
intr_enable_rd_A	2147483647	332734	0	0
ovrd_rd_A	2147483647	374207	0	0
timeout_ctrl_rd_A	2147483647	373726	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	14051665	0	0
T5	4281	733	0	0
T6	8848	0	0	0
T7	1110	0	0	0
T8	7954	467	0	0
T9	1719	15	0	0
T10	1243	0	0	0
T31	0	305	0	0
T32	0	2	0	0
T36	910	0	0	0
T39	0	150	0	0
T40	0	72	0	0
T41	0	57	0	0
T46	8867	0	0	0
T47	1445	0	0	0
T48	3041	0	0	0
T106	0	33	0	0
T107	0	7	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	374182	0	0
T8	7954	11	0	0
T9	1719	47	0	0
T10	1243	0	0	0
T32	0	221	0	0
T33	1266	0	0	0
T34	0	5	0	0
T36	910	0	0	0
T46	8867	0	0	0
T47	1445	0	0	0
T48	3041	90	0	0
T49	1014	0	0	0
T50	925	2	0	0
T54	0	24	0	0
T56	0	51	0	0
T108	0	3	0	0
T109	0	54	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	332734	0	0
T3	1453	2	0	0
T4	1157	20	0	0
T5	4281	0	0	0
T6	8848	0	0	0
T7	1110	0	0	0
T8	7954	27	0	0
T9	1719	7	0	0
T10	1243	0	0	0
T32	0	235	0	0
T36	910	0	0	0
T46	8867	0	0	0
T48	0	89	0	0
T50	0	33	0	0
T51	0	20	0	0
T108	0	4	0	0
T110	0	18	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	374207	0	0
T8	7954	35	0	0
T9	1719	6	0	0
T10	1243	0	0	0
T32	0	29	0	0
T33	1266	0	0	0
T34	0	1	0	0
T36	910	0	0	0
T46	8867	0	0	0
T47	1445	0	0	0
T48	3041	73	0	0
T49	1014	0	0	0
T50	925	6	0	0
T54	0	1	0	0
T56	0	74	0	0
T108	0	5	0	0
T109	0	33	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	373726	0	0
T8	7954	20	0	0
T9	1719	10	0	0
T10	1243	0	0	0
T32	0	35	0	0
T33	1266	0	0	0
T34	0	7	0	0
T36	910	0	0	0
T46	8867	0	0	0
T47	1445	0	0	0
T48	3041	65	0	0
T49	1014	0	0	0
T50	925	9	0	0
T54	0	12	0	0
T56	0	65	0	0
T108	0	22	0	0
T109	0	60	0	0