Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	53134943	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

21972443

1

T1

168

T2

96

T3

390

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	69172211	1			T1	2444		T2	1088		T3	593
values[0x0]	2810795	1			T1	133		T2	58		T3	235
values[0x1]	3124380	1			T1	149		T2	48		T3	212

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	37303649	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

37803737

1

T1

930

T2

448

T3

503

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	257610	1			T1	23		T3	7		T7	25
valid_sources[0x01]	290491	1			T3	22		T7	16		T8	34
valid_sources[0x02]	299012	1			T1	10		T3	9		T7	8
valid_sources[0x03]	278265	1			T1	18		T3	14		T7	10
valid_sources[0x04]	265905	1			T1	5		T3	1		T7	19
valid_sources[0x05]	277992	1			T1	17		T3	5		T7	18
valid_sources[0x06]	280285	1			T1	14		T4	1		T7	21
valid_sources[0x07]	284957	1			T1	15		T3	3		T4	5
valid_sources[0x08]	425077	1			T1	3		T3	12		T4	2
valid_sources[0x09]	273561	1			T3	3		T4	1		T7	13
valid_sources[0x0a]	356894	1			T1	13		T4	1		T6	4
valid_sources[0x0b]	265257	1			T1	5		T3	3		T7	12
valid_sources[0x0c]	289272	1			T1	7		T3	10		T4	1
valid_sources[0x0d]	360232	1			T1	12		T3	18		T4	1
valid_sources[0x0e]	296443	1			T1	13		T3	4		T7	16
valid_sources[0x0f]	293525	1			T1	3		T3	11		T7	15
valid_sources[0x10]	281046	1			T1	10		T3	7		T4	5
valid_sources[0x11]	311832	1			T1	17		T3	4		T4	1
valid_sources[0x12]	259183	1			T1	23		T3	3		T4	1
valid_sources[0x13]	263808	1			T1	15		T3	3		T4	1
valid_sources[0x14]	302372	1			T1	6		T3	1		T7	20
valid_sources[0x15]	265335	1			T1	14		T3	1		T6	20
valid_sources[0x16]	277771	1			T1	14		T3	9		T7	12
valid_sources[0x17]	285370	1			T3	7		T4	1		T6	2
valid_sources[0x18]	299360	1			T1	1		T3	14		T4	3
valid_sources[0x19]	312831	1			T1	24		T4	3		T7	18
valid_sources[0x1a]	342276	1			T1	2		T3	2		T4	2
valid_sources[0x1b]	307829	1			T1	11		T4	2		T7	16
valid_sources[0x1c]	346723	1			T1	29		T3	5		T4	1
valid_sources[0x1d]	291490	1			T1	58		T3	4		T7	6
valid_sources[0x1e]	310629	1			T1	15		T3	2		T7	27
valid_sources[0x1f]	280210	1			T1	9		T3	3		T6	19
valid_sources[0x20]	289148	1			T1	15		T4	2		T7	18
valid_sources[0x21]	292042	1			T1	27		T3	13		T4	2
valid_sources[0x22]	289010	1			T1	4		T3	2		T6	37
valid_sources[0x23]	363148	1			T1	7		T3	12		T4	3
valid_sources[0x24]	315896	1			T1	13		T7	28		T8	25
valid_sources[0x25]	266421	1			T1	2		T3	7		T7	26
valid_sources[0x26]	380160	1			T1	4		T3	4		T4	3
valid_sources[0x27]	280022	1			T1	4		T4	5		T7	10
valid_sources[0x28]	256729	1			T3	1		T4	1		T7	9
valid_sources[0x29]	252627	1			T1	22		T3	3		T4	2
valid_sources[0x2a]	286334	1			T3	7		T4	2		T7	9
valid_sources[0x2b]	300388	1			T6	22		T7	23		T8	33
valid_sources[0x2c]	322250	1			T1	15		T7	11		T8	20
valid_sources[0x2d]	314024	1			T1	2		T3	11		T4	1
valid_sources[0x2e]	287301	1			T1	19		T3	2		T4	2
valid_sources[0x2f]	306441	1			T7	16		T8	27		T9	2
valid_sources[0x30]	296814	1			T1	4		T3	10		T4	2
valid_sources[0x31]	269195	1			T1	2		T3	5		T4	5
valid_sources[0x32]	270075	1			T1	14		T4	2		T7	18
valid_sources[0x33]	281009	1			T1	36		T3	4		T4	2
valid_sources[0x34]	280468	1			T1	3		T3	5		T4	1
valid_sources[0x35]	266563	1			T1	6		T7	10		T8	20
valid_sources[0x36]	312923	1			T1	20		T3	3		T7	16
valid_sources[0x37]	307364	1			T1	32		T3	12		T7	9
valid_sources[0x38]	328051	1			T3	13		T6	28		T7	24
valid_sources[0x39]	268710	1			T1	20		T3	2		T7	11
valid_sources[0x3a]	265848	1			T1	1		T2	1194		T4	2
valid_sources[0x3b]	264217	1			T1	3		T4	5		T7	16
valid_sources[0x3c]	298576	1			T1	5		T3	17		T6	30
valid_sources[0x3d]	268042	1			T1	8		T3	4		T6	23
valid_sources[0x3e]	268916	1			T1	6		T3	1		T6	3
valid_sources[0x3f]	288336	1			T1	4		T4	3		T7	20
valid_sources[0x40]	246823	1			T4	1		T6	32		T7	34
valid_sources[0x41]	281368	1			T1	6		T3	5		T4	2
valid_sources[0x42]	295668	1			T1	5		T3	2		T4	3
valid_sources[0x43]	295560	1			T3	9		T4	1		T7	9
valid_sources[0x44]	291274	1			T1	2		T3	1		T4	2
valid_sources[0x45]	270470	1			T1	14		T4	1		T7	27
valid_sources[0x46]	266346	1			T1	5		T3	11		T4	1
valid_sources[0x47]	289018	1			T1	9		T3	1		T4	3
valid_sources[0x48]	294740	1			T1	12		T4	1		T7	7
valid_sources[0x49]	294357	1			T3	2		T7	22		T8	42
valid_sources[0x4a]	366646	1			T1	7		T4	3		T6	31
valid_sources[0x4b]	271222	1			T1	10		T7	13		T8	34
valid_sources[0x4c]	264117	1			T1	21		T7	11		T8	20
valid_sources[0x4d]	270005	1			T1	5		T4	1		T7	12
valid_sources[0x4e]	286468	1			T1	18		T3	1		T4	2
valid_sources[0x4f]	266383	1			T1	2		T3	1		T4	1
valid_sources[0x50]	304047	1			T1	4		T3	6		T4	3
valid_sources[0x51]	330248	1			T1	18		T3	15		T7	14
valid_sources[0x52]	292044	1			T1	12		T3	5		T7	25
valid_sources[0x53]	287569	1			T7	12		T8	34		T9	2
valid_sources[0x54]	266122	1			T1	9		T3	6		T4	1
valid_sources[0x55]	298111	1			T1	12		T3	5		T4	1
valid_sources[0x56]	259600	1			T1	12		T3	29		T4	2
valid_sources[0x57]	279737	1			T1	24		T3	6		T7	14
valid_sources[0x58]	267867	1			T1	1		T4	2		T6	4
valid_sources[0x59]	281101	1			T1	32		T4	1		T7	23
valid_sources[0x5a]	316399	1			T3	5		T6	89		T7	26
valid_sources[0x5b]	274351	1			T1	13		T3	3		T4	1
valid_sources[0x5c]	294585	1			T1	10		T3	4		T4	4
valid_sources[0x5d]	413232	1			T1	7		T3	3		T4	1
valid_sources[0x5e]	286530	1			T1	16		T4	1		T7	14
valid_sources[0x5f]	402003	1			T1	17		T4	1		T7	17
valid_sources[0x60]	278359	1			T1	13		T3	3		T4	1
valid_sources[0x61]	268007	1			T1	6		T3	9		T4	1
valid_sources[0x62]	293579	1			T4	2		T7	29		T8	33
valid_sources[0x63]	276812	1			T1	6		T7	8		T8	32
valid_sources[0x64]	272040	1			T1	14		T4	1		T7	13
valid_sources[0x65]	282159	1			T1	4		T4	1		T6	29
valid_sources[0x66]	289030	1			T1	18		T3	5		T6	61
valid_sources[0x67]	282829	1			T1	14		T3	3		T4	3
valid_sources[0x68]	286842	1			T1	1		T3	2		T7	8
valid_sources[0x69]	320617	1			T1	13		T4	1		T7	21
valid_sources[0x6a]	287109	1			T1	6		T3	9		T4	2
valid_sources[0x6b]	269737	1			T1	35		T3	14		T6	11
valid_sources[0x6c]	289398	1			T1	24		T4	3		T6	23
valid_sources[0x6d]	410867	1			T1	12		T7	12		T8	28
valid_sources[0x6e]	264897	1			T1	12		T3	2		T4	1
valid_sources[0x6f]	300751	1			T1	14		T3	4		T7	11
valid_sources[0x70]	274088	1			T1	5		T3	5		T7	23
valid_sources[0x71]	344024	1			T1	21		T3	2		T4	1
valid_sources[0x72]	294745	1			T1	3		T3	1		T7	10
valid_sources[0x73]	276624	1			T3	11		T4	4		T7	17
valid_sources[0x74]	306744	1			T1	3		T3	2		T4	1
valid_sources[0x75]	272649	1			T1	7		T6	27		T7	22
valid_sources[0x76]	307838	1			T1	15		T3	9		T4	2
valid_sources[0x77]	268365	1			T1	2		T4	1		T7	23
valid_sources[0x78]	324860	1			T1	6		T3	8		T4	3
valid_sources[0x79]	262583	1			T1	9		T3	14		T4	1
valid_sources[0x7a]	263163	1			T1	22		T3	3		T7	13
valid_sources[0x7b]	276976	1			T1	16		T3	3		T4	4
valid_sources[0x7c]	253439	1			T1	1		T3	2		T7	11
valid_sources[0x7d]	295858	1			T1	5		T3	4		T7	15
valid_sources[0x7e]	263930	1			T1	8		T3	10		T4	1
valid_sources[0x7f]	333696	1			T4	4		T7	15		T8	34
valid_sources[0x80]	266686	1			T1	5		T3	10		T4	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

16839955

1

T1

99

T2

48

T3

247

values[0x0]

all_enables

biggest_size

2592578

1

T1

42

T2

31

T3

91

values[0x1]

all_enables

biggest_size

2539910

1

T1

27

T2

17

T3

52