Unified Coverage Report :: Module :: uart_csr_assert_fpv

Module : uart_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_uart_csr_assert_0/uart_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.uart_csr_assert	100.00						100.00

---

Module Instance : tb.dut.uart_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : uart_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	8493267	0	0
ctrl_rd_A	2147483647	130762	0	0
intr_enable_rd_A	2147483647	116271	0	0
ovrd_rd_A	2147483647	129257	0	0
timeout_ctrl_rd_A	2147483647	128934	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8493267	0	0
T13	397935	113516	0	0
T18	0	91923	0	0
T19	653425	209901	0	0
T28	0	105726	0	0
T30	251974	0	0	0
T37	0	75232	0	0
T38	0	74181	0	0
T39	0	62538	0	0
T40	0	190781	0	0
T41	0	125561	0	0
T42	0	184037	0	0
T43	276666	0	0	0
T44	206944	0	0	0
T45	833375	0	0	0
T46	103520	0	0	0
T47	970811	0	0	0
T48	175981	0	0	0
T49	181079	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	130762	0	0
T28	431160	11132	0	0
T33	2739	0	0	0
T37	313310	8455	0	0
T39	0	2595	0	0
T55	848302	0	0	0
T57	0	11228	0	0
T59	0	4007	0	0
T88	127964	0	0	0
T89	201021	0	0	0
T90	285139	0	0	0
T95	0	15669	0	0
T96	0	7112	0	0
T97	0	13982	0	0
T98	0	10809	0	0
T99	0	11233	0	0
T100	103169	0	0	0
T101	826242	0	0	0
T102	234893	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	116271	0	0
T28	431160	10393	0	0
T33	2739	0	0	0
T37	313310	7729	0	0
T39	0	2212	0	0
T55	848302	0	0	0
T57	0	10052	0	0
T59	0	3725	0	0
T88	127964	0	0	0
T89	201021	0	0	0
T90	285139	0	0	0
T95	0	13207	0	0
T96	0	6323	0	0
T97	0	12413	0	0
T100	103169	0	0	0
T101	826242	0	0	0
T102	234893	0	0	0
T103	0	27	0	0
T104	0	20	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	129257	0	0
T28	431160	11390	0	0
T33	2739	0	0	0
T37	313310	8696	0	0
T39	0	2607	0	0
T55	848302	0	0	0
T57	0	10922	0	0
T59	0	4421	0	0
T88	127964	0	0	0
T89	201021	0	0	0
T90	285139	0	0	0
T95	0	15509	0	0
T96	0	7641	0	0
T97	0	13714	0	0
T98	0	10933	0	0
T99	0	10977	0	0
T100	103169	0	0	0
T101	826242	0	0	0
T102	234893	0	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	128934	0	0
T28	431160	11801	0	0
T33	2739	0	0	0
T37	313310	8874	0	0
T39	0	2539	0	0
T55	848302	0	0	0
T57	0	11146	0	0
T59	0	4089	0	0
T88	127964	0	0	0
T89	201021	0	0	0
T90	285139	0	0	0
T95	0	15384	0	0
T96	0	7344	0	0
T97	0	14492	0	0
T98	0	10558	0	0
T99	0	10626	0	0
T100	103169	0	0	0
T101	826242	0	0	0
T102	234893	0	0	0