Unified Coverage Report :: Tests

Tests

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Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.25	99.79	98.45	100.00		99.76	100.00	97.48

Total test records in report: 1261

tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html | tests24.html | tests25.html | tests26.html

T1251	/workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.3287297764			Feb 18 12:37:29 PM PST 24	Feb 18 12:37:35 PM PST 24	167872724 ps
T1252	/workspace/coverage/cover_reg_top/40.uart_intr_test.2529486221			Feb 18 12:37:58 PM PST 24	Feb 18 12:38:06 PM PST 24	11076405 ps
T1253	/workspace/coverage/cover_reg_top/3.uart_tl_intg_err.164089630			Feb 18 12:37:34 PM PST 24	Feb 18 12:37:43 PM PST 24	48665524 ps
T1254	/workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.3717879334			Feb 18 12:37:39 PM PST 24	Feb 18 12:37:47 PM PST 24	80124902 ps
T1255	/workspace/coverage/cover_reg_top/3.uart_intr_test.1141485620			Feb 18 12:37:32 PM PST 24	Feb 18 12:37:41 PM PST 24	37733425 ps
T1256	/workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.3573884291			Feb 18 12:37:52 PM PST 24	Feb 18 12:38:01 PM PST 24	41007411 ps
T1257	/workspace/coverage/cover_reg_top/30.uart_intr_test.4171259678			Feb 18 12:37:55 PM PST 24	Feb 18 12:38:03 PM PST 24	48555393 ps
T1258	/workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.3470341646			Feb 18 12:37:50 PM PST 24	Feb 18 12:37:59 PM PST 24	105070262 ps
T1259	/workspace/coverage/cover_reg_top/2.uart_tl_errors.2346721146			Feb 18 12:37:28 PM PST 24	Feb 18 12:37:35 PM PST 24	42400800 ps
T1260	/workspace/coverage/cover_reg_top/31.uart_intr_test.20840607			Feb 18 12:37:52 PM PST 24	Feb 18 12:38:00 PM PST 24	17223275 ps
T1261	/workspace/coverage/cover_reg_top/0.uart_intr_test.2526573228			Feb 18 12:37:21 PM PST 24	Feb 18 12:37:23 PM PST 24	43032751 ps

Test location	/workspace/coverage/default/263.uart_fifo_reset.4020237102
Short name	T1
Test name
Test status
Simulation time	136716474416 ps
CPU time	29.55 seconds
Started	Feb 18 02:08:31 PM PST 24
Finished	Feb 18 02:09:03 PM PST 24
Peak memory	200084 kb
Host	smart-f4db15df-a94c-435b-8d1a-339b24299a9c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4020237102 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.uart_fifo_reset.4020237102
Directory	/workspace/263.uart_fifo_reset/latest

Test location	/workspace/coverage/default/16.uart_stress_all_with_rand_reset.1669075522
Short name	T19
Test name
Test status
Simulation time	66002546495 ps
CPU time	851.91 seconds
Started	Feb 18 02:04:33 PM PST 24
Finished	Feb 18 02:18:47 PM PST 24
Peak memory	229260 kb
Host	smart-b26019fd-9048-4ba7-8a30-6f2c82d31ee5
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669075522 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 16.uart_stress_all_with_rand_reset.1669075522
Directory	/workspace/16.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/22.uart_stress_all_with_rand_reset.1951460855
Short name	T13
Test name
Test status
Simulation time	198967560869 ps
CPU time	478.08 seconds
Started	Feb 18 02:04:46 PM PST 24
Finished	Feb 18 02:12:48 PM PST 24
Peak memory	215916 kb
Host	smart-d8800223-f1ce-43c2-99c7-446947507a3f
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951460855 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 22.uart_stress_all_with_rand_reset.1951460855
Directory	/workspace/22.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/50.uart_stress_all_with_rand_reset.807099502
Short name	T18
Test name
Test status
Simulation time	73561138851 ps
CPU time	280.71 seconds
Started	Feb 18 02:07:02 PM PST 24
Finished	Feb 18 02:11:46 PM PST 24
Peak memory	215620 kb
Host	smart-9669ec38-7c0f-4d38-a11a-313537b79528
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807099502 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 50.uart_stress_all_with_rand_reset.807099502
Directory	/workspace/50.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/44.uart_stress_all_with_rand_reset.342005
Short name	T95
Test name
Test status
Simulation time	392501069427 ps
CPU time	1197.88 seconds
Started	Feb 18 02:06:25 PM PST 24
Finished	Feb 18 02:26:26 PM PST 24
Peak memory	224704 kb
Host	smart-e1f2a7fe-c288-4626-81ec-e5e984cccad6
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342005 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_stress_all_with_rand_reset.342005
Directory	/workspace/44.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/15.uart_stress_all_with_rand_reset.457685546
Short name	T42
Test name
Test status
Simulation time	131067166701 ps
CPU time	1188.94 seconds
Started	Feb 18 02:04:18 PM PST 24
Finished	Feb 18 02:24:10 PM PST 24
Peak memory	212500 kb
Host	smart-127313f5-eafa-4cad-b454-bee9c17fb1df
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457685546 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 15.uart_stress_all_with_rand_reset.457685546
Directory	/workspace/15.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/44.uart_stress_all.1776100838
Short name	T29
Test name
Test status
Simulation time	331131511258 ps
CPU time	575.97 seconds
Started	Feb 18 02:06:26 PM PST 24
Finished	Feb 18 02:16:05 PM PST 24
Peak memory	199976 kb
Host	smart-3365c17e-dbf5-41dd-b02a-f7502c089618
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776100838 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_stress_all.1776100838
Directory	/workspace/44.uart_stress_all/latest

Test location	/workspace/coverage/default/24.uart_long_xfer_wo_dly.990437801
Short name	T11
Test name
Test status
Simulation time	131630478965 ps
CPU time	715.1 seconds
Started	Feb 18 02:04:53 PM PST 24
Finished	Feb 18 02:16:55 PM PST 24
Peak memory	200012 kb
Host	smart-118bf179-b7be-4dc4-a353-545433548d38
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=990437801 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_long_xfer_wo_dly.990437801
Directory	/workspace/24.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/32.uart_rx_parity_err.612938391
Short name	T52
Test name
Test status
Simulation time	376401499170 ps
CPU time	78.33 seconds
Started	Feb 18 02:05:26 PM PST 24
Finished	Feb 18 02:06:51 PM PST 24
Peak memory	200024 kb
Host	smart-83596153-0bce-4b56-90ee-2976618a1253
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=612938391 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_parity_err.612938391
Directory	/workspace/32.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/1.uart_sec_cm.3210096605
Short name	T33
Test name
Test status
Simulation time	144279429 ps
CPU time	0.76 seconds
Started	Feb 18 02:03:41 PM PST 24
Finished	Feb 18 02:03:55 PM PST 24
Peak memory	217196 kb
Host	smart-5c43c8b4-1696-4db0-b3af-993363f4e89a
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210096605 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_sec_cm.3210096605
Directory	/workspace/1.uart_sec_cm/latest

Test location	/workspace/coverage/default/47.uart_long_xfer_wo_dly.765819221
Short name	T410
Test name
Test status
Simulation time	95106744210 ps
CPU time	243.52 seconds
Started	Feb 18 02:06:42 PM PST 24
Finished	Feb 18 02:10:48 PM PST 24
Peak memory	200048 kb
Host	smart-9272b464-f3f2-4b15-9dbc-c4b61c864345
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=765819221 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_long_xfer_wo_dly.765819221
Directory	/workspace/47.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/205.uart_fifo_reset.2814396136
Short name	T14
Test name
Test status
Simulation time	101578941682 ps
CPU time	91.15 seconds
Started	Feb 18 02:08:04 PM PST 24
Finished	Feb 18 02:09:36 PM PST 24
Peak memory	199692 kb
Host	smart-985010d9-52ed-4d2d-bc07-4cc1a5cca866
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2814396136 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.uart_fifo_reset.2814396136
Directory	/workspace/205.uart_fifo_reset/latest

Test location	/workspace/coverage/default/2.uart_stress_all.325089880
Short name	T145
Test name
Test status
Simulation time	185624765580 ps
CPU time	99.17 seconds
Started	Feb 18 02:03:39 PM PST 24
Finished	Feb 18 02:05:31 PM PST 24
Peak memory	208736 kb
Host	smart-ff33f69f-51fb-4e5d-8d37-6016460bf284
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325089880 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_stress_all.325089880
Directory	/workspace/2.uart_stress_all/latest

Test location	/workspace/coverage/default/16.uart_stress_all.3772345587
Short name	T282
Test name
Test status
Simulation time	147442915246 ps
CPU time	848.51 seconds
Started	Feb 18 02:04:26 PM PST 24
Finished	Feb 18 02:18:38 PM PST 24
Peak memory	208516 kb
Host	smart-8f22dd35-a890-46c4-8afa-7d05016343fb
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772345587 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_stress_all.3772345587
Directory	/workspace/16.uart_stress_all/latest

Test location	/workspace/coverage/default/229.uart_fifo_reset.136885900
Short name	T36
Test name
Test status
Simulation time	106629090051 ps
CPU time	41.68 seconds
Started	Feb 18 02:08:19 PM PST 24
Finished	Feb 18 02:09:05 PM PST 24
Peak memory	200112 kb
Host	smart-f82e8c21-22f3-4cb5-91ab-9a5341314256
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=136885900 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.uart_fifo_reset.136885900
Directory	/workspace/229.uart_fifo_reset/latest

Test location	/workspace/coverage/default/1.uart_fifo_full.2351428451
Short name	T320
Test name
Test status
Simulation time	118181152585 ps
CPU time	41.64 seconds
Started	Feb 18 02:03:25 PM PST 24
Finished	Feb 18 02:04:10 PM PST 24
Peak memory	200000 kb
Host	smart-9ecd4ecc-9156-489e-8398-bd5dc54f5a5a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2351428451 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_full.2351428451
Directory	/workspace/1.uart_fifo_full/latest

Test location	/workspace/coverage/default/65.uart_stress_all_with_rand_reset.3085425715
Short name	T259
Test name
Test status
Simulation time	375469786396 ps
CPU time	1070.73 seconds
Started	Feb 18 02:07:13 PM PST 24
Finished	Feb 18 02:25:06 PM PST 24
Peak memory	226704 kb
Host	smart-12e27d32-699d-479c-ae2b-6122db71c613
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085425715 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 65.uart_stress_all_with_rand_reset.3085425715
Directory	/workspace/65.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/43.uart_stress_all.3581049542
Short name	T325
Test name
Test status
Simulation time	148502757012 ps
CPU time	371.98 seconds
Started	Feb 18 02:06:24 PM PST 24
Finished	Feb 18 02:12:40 PM PST 24
Peak memory	208484 kb
Host	smart-7c1c3f0d-8f5c-443f-a0a3-337fa3af0296
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581049542 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_stress_all.3581049542
Directory	/workspace/43.uart_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/11.uart_tl_intg_err.1331641764
Short name	T84
Test name
Test status
Simulation time	346616151 ps
CPU time	1.35 seconds
Started	Feb 18 12:37:41 PM PST 24
Finished	Feb 18 12:37:48 PM PST 24
Peak memory	199280 kb
Host	smart-161f1b43-fbec-4d5f-afcb-a5091ad73e31
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331641764 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_intg_err.1331641764
Directory	/workspace/11.uart_tl_intg_err/latest

Test location	/workspace/coverage/default/1.uart_alert_test.1589298314
Short name	T448
Test name
Test status
Simulation time	84299663 ps
CPU time	0.55 seconds
Started	Feb 18 02:03:26 PM PST 24
Finished	Feb 18 02:03:29 PM PST 24
Peak memory	195508 kb
Host	smart-cc7593c3-3761-4857-8d1b-36ff75bccb46
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589298314 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_alert_test.1589298314
Directory	/workspace/1.uart_alert_test/latest

Test location	/workspace/coverage/cover_reg_top/3.uart_csr_rw.3192410635
Short name	T66
Test name
Test status
Simulation time	20569282 ps
CPU time	0.6 seconds
Started	Feb 18 12:37:47 PM PST 24
Finished	Feb 18 12:37:53 PM PST 24
Peak memory	195340 kb
Host	smart-cbcff784-4851-4595-9ed7-d1351bc0c4f1
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192410635 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_rw.3192410635
Directory	/workspace/3.uart_csr_rw/latest

Test location	/workspace/coverage/default/38.uart_stress_all.2038843356
Short name	T120
Test name
Test status
Simulation time	229737078867 ps
CPU time	1108.21 seconds
Started	Feb 18 02:05:59 PM PST 24
Finished	Feb 18 02:24:32 PM PST 24
Peak memory	199996 kb
Host	smart-e84fd189-a938-4215-bbcc-3775d35be168
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038843356 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_stress_all.2038843356
Directory	/workspace/38.uart_stress_all/latest

Test location	/workspace/coverage/default/3.uart_rx_parity_err.2803570275
Short name	T365
Test name
Test status
Simulation time	302765860284 ps
CPU time	110.17 seconds
Started	Feb 18 02:03:42 PM PST 24
Finished	Feb 18 02:05:47 PM PST 24
Peak memory	200020 kb
Host	smart-4d5f0a15-6315-4e59-9c3b-e014240e2fc6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2803570275 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_parity_err.2803570275
Directory	/workspace/3.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/29.uart_fifo_reset.572443246
Short name	T226
Test name
Test status
Simulation time	206988394316 ps
CPU time	279.88 seconds
Started	Feb 18 02:05:17 PM PST 24
Finished	Feb 18 02:09:58 PM PST 24
Peak memory	199996 kb
Host	smart-a2a2c24f-766e-4968-a065-2bf67e926c92
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=572443246 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_reset.572443246
Directory	/workspace/29.uart_fifo_reset/latest

Test location	/workspace/coverage/default/63.uart_stress_all_with_rand_reset.1509577012
Short name	T230
Test name
Test status
Simulation time	402661552178 ps
CPU time	881.72 seconds
Started	Feb 18 02:07:01 PM PST 24
Finished	Feb 18 02:21:46 PM PST 24
Peak memory	224952 kb
Host	smart-773f67b7-11ba-4ed5-9483-03477d2af143
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509577012 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 63.uart_stress_all_with_rand_reset.1509577012
Directory	/workspace/63.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/3.uart_fifo_overflow.3066870528
Short name	T9
Test name
Test status
Simulation time	250044521262 ps
CPU time	40.52 seconds
Started	Feb 18 02:03:38 PM PST 24
Finished	Feb 18 02:04:32 PM PST 24
Peak memory	200080 kb
Host	smart-70d7b78f-dba4-4e4b-83a9-8f4f3c8677eb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3066870528 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_overflow.3066870528
Directory	/workspace/3.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/31.uart_stress_all_with_rand_reset.2344705550
Short name	T28
Test name
Test status
Simulation time	87991185467 ps
CPU time	374.47 seconds
Started	Feb 18 02:05:19 PM PST 24
Finished	Feb 18 02:11:36 PM PST 24
Peak memory	215636 kb
Host	smart-df52d57e-9d92-450d-98ce-0664a1afddae
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344705550 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 31.uart_stress_all_with_rand_reset.2344705550
Directory	/workspace/31.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/19.uart_fifo_full.42084078
Short name	T309
Test name
Test status
Simulation time	70451838978 ps
CPU time	27.02 seconds
Started	Feb 18 02:04:24 PM PST 24
Finished	Feb 18 02:04:53 PM PST 24
Peak memory	200008 kb
Host	smart-923e7c6c-be39-41b9-a285-53aba68a557d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=42084078 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_full.42084078
Directory	/workspace/19.uart_fifo_full/latest

Test location	/workspace/coverage/default/37.uart_fifo_full.2267471696
Short name	T314
Test name
Test status
Simulation time	158342022226 ps
CPU time	68.05 seconds
Started	Feb 18 02:05:50 PM PST 24
Finished	Feb 18 02:07:06 PM PST 24
Peak memory	199920 kb
Host	smart-14a1a748-cb97-4d3e-89f9-08b67c356b8a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2267471696 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_full.2267471696
Directory	/workspace/37.uart_fifo_full/latest

Test location	/workspace/coverage/default/42.uart_stress_all_with_rand_reset.3132460231
Short name	T96
Test name
Test status
Simulation time	318902387908 ps
CPU time	335.58 seconds
Started	Feb 18 02:06:21 PM PST 24
Finished	Feb 18 02:12:01 PM PST 24
Peak memory	216732 kb
Host	smart-9b71b01b-d238-4fc6-9579-019765b20a02
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132460231 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 42.uart_stress_all_with_rand_reset.3132460231
Directory	/workspace/42.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/153.uart_fifo_reset.985324869
Short name	T165
Test name
Test status
Simulation time	75854864087 ps
CPU time	19.92 seconds
Started	Feb 18 02:07:36 PM PST 24
Finished	Feb 18 02:07:58 PM PST 24
Peak memory	200072 kb
Host	smart-d5cfb43a-bd68-4208-ae35-13a9eb09c031
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=985324869 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.uart_fifo_reset.985324869
Directory	/workspace/153.uart_fifo_reset/latest

Test location	/workspace/coverage/default/142.uart_fifo_reset.1257282826
Short name	T140
Test name
Test status
Simulation time	115479073371 ps
CPU time	50.84 seconds
Started	Feb 18 02:07:32 PM PST 24
Finished	Feb 18 02:08:26 PM PST 24
Peak memory	200004 kb
Host	smart-25e2bb40-251b-4827-9ebe-16f37a20a80b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1257282826 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.uart_fifo_reset.1257282826
Directory	/workspace/142.uart_fifo_reset/latest

Test location	/workspace/coverage/default/251.uart_fifo_reset.3745861068
Short name	T126
Test name
Test status
Simulation time	24676709403 ps
CPU time	25.94 seconds
Started	Feb 18 02:08:33 PM PST 24
Finished	Feb 18 02:09:06 PM PST 24
Peak memory	200048 kb
Host	smart-93c3fee4-3779-4a44-8012-5ac1dbea16c3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3745861068 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.uart_fifo_reset.3745861068
Directory	/workspace/251.uart_fifo_reset/latest

Test location	/workspace/coverage/default/80.uart_fifo_reset.1238390125
Short name	T129
Test name
Test status
Simulation time	19868585564 ps
CPU time	30.92 seconds
Started	Feb 18 02:07:10 PM PST 24
Finished	Feb 18 02:07:42 PM PST 24
Peak memory	200076 kb
Host	smart-4529bd81-e118-4bb8-a8ba-a35e183648da
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1238390125 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.uart_fifo_reset.1238390125
Directory	/workspace/80.uart_fifo_reset/latest

Test location	/workspace/coverage/default/151.uart_fifo_reset.439063943
Short name	T219
Test name
Test status
Simulation time	58993917341 ps
CPU time	14.47 seconds
Started	Feb 18 02:07:31 PM PST 24
Finished	Feb 18 02:07:48 PM PST 24
Peak memory	199920 kb
Host	smart-2bdd266c-703b-47e0-b8d1-5a0b51773cbb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=439063943 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.uart_fifo_reset.439063943
Directory	/workspace/151.uart_fifo_reset/latest

Test location	/workspace/coverage/default/2.uart_fifo_reset.1349267640
Short name	T119
Test name
Test status
Simulation time	35168934141 ps
CPU time	84.25 seconds
Started	Feb 18 02:03:32 PM PST 24
Finished	Feb 18 02:05:04 PM PST 24
Peak memory	200032 kb
Host	smart-ddb452ac-ff87-423c-be60-c25215f9bb79
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1349267640 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_reset.1349267640
Directory	/workspace/2.uart_fifo_reset/latest

Test location	/workspace/coverage/cover_reg_top/5.uart_tl_intg_err.2983567843
Short name	T384
Test name
Test status
Simulation time	95948058 ps
CPU time	1.34 seconds
Started	Feb 18 12:37:35 PM PST 24
Finished	Feb 18 12:37:44 PM PST 24
Peak memory	199248 kb
Host	smart-56d61789-9a84-4585-8756-a05fb3425eca
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983567843 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_intg_err.2983567843
Directory	/workspace/5.uart_tl_intg_err/latest

Test location	/workspace/coverage/default/250.uart_fifo_reset.2304512084
Short name	T187
Test name
Test status
Simulation time	82182940253 ps
CPU time	116.57 seconds
Started	Feb 18 02:08:34 PM PST 24
Finished	Feb 18 02:10:38 PM PST 24
Peak memory	200040 kb
Host	smart-a18e758b-30a3-4a59-acd3-6a1f09efde1d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2304512084 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.uart_fifo_reset.2304512084
Directory	/workspace/250.uart_fifo_reset/latest

Test location	/workspace/coverage/default/9.uart_rx_parity_err.2825607170
Short name	T92
Test name
Test status
Simulation time	9561850865 ps
CPU time	16.62 seconds
Started	Feb 18 02:03:57 PM PST 24
Finished	Feb 18 02:04:20 PM PST 24
Peak memory	200004 kb
Host	smart-48c24991-4b59-4821-a634-d113db6736e2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2825607170 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_parity_err.2825607170
Directory	/workspace/9.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/116.uart_fifo_reset.1116594455
Short name	T205
Test name
Test status
Simulation time	133022634566 ps
CPU time	57.74 seconds
Started	Feb 18 02:07:24 PM PST 24
Finished	Feb 18 02:08:24 PM PST 24
Peak memory	200100 kb
Host	smart-825c6117-832e-4db5-b49d-f4d2728b9c7b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1116594455 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.uart_fifo_reset.1116594455
Directory	/workspace/116.uart_fifo_reset/latest

Test location	/workspace/coverage/default/123.uart_fifo_reset.3396068063
Short name	T329
Test name
Test status
Simulation time	59095158076 ps
CPU time	14.67 seconds
Started	Feb 18 02:07:31 PM PST 24
Finished	Feb 18 02:07:47 PM PST 24
Peak memory	200024 kb
Host	smart-daa617a1-4d81-4173-83a7-1fc27812a816
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3396068063 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.uart_fifo_reset.3396068063
Directory	/workspace/123.uart_fifo_reset/latest

Test location	/workspace/coverage/default/269.uart_fifo_reset.763124560
Short name	T315
Test name
Test status
Simulation time	21512945117 ps
CPU time	13.85 seconds
Started	Feb 18 02:08:32 PM PST 24
Finished	Feb 18 02:08:52 PM PST 24
Peak memory	199832 kb
Host	smart-47a2206d-4fb9-4458-a452-5a4437c9c57f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=763124560 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.uart_fifo_reset.763124560
Directory	/workspace/269.uart_fifo_reset/latest

Test location	/workspace/coverage/default/36.uart_fifo_reset.3922542308
Short name	T143
Test name
Test status
Simulation time	24586844431 ps
CPU time	57.42 seconds
Started	Feb 18 02:05:47 PM PST 24
Finished	Feb 18 02:06:53 PM PST 24
Peak memory	200044 kb
Host	smart-ed536174-954f-44b7-99d3-2238bd732cbb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3922542308 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_reset.3922542308
Directory	/workspace/36.uart_fifo_reset/latest

Test location	/workspace/coverage/default/103.uart_fifo_reset.2501256842
Short name	T246
Test name
Test status
Simulation time	41138228798 ps
CPU time	72.08 seconds
Started	Feb 18 02:07:22 PM PST 24
Finished	Feb 18 02:08:37 PM PST 24
Peak memory	200048 kb
Host	smart-bb91cdc1-8bb2-478b-8fde-e175d2fc265a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2501256842 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.uart_fifo_reset.2501256842
Directory	/workspace/103.uart_fifo_reset/latest

Test location	/workspace/coverage/default/19.uart_noise_filter.820434843
Short name	T128
Test name
Test status
Simulation time	42066358240 ps
CPU time	77.95 seconds
Started	Feb 18 02:04:35 PM PST 24
Finished	Feb 18 02:05:57 PM PST 24
Peak memory	208324 kb
Host	smart-9a45a226-d058-478f-89cf-2b03e74ed672
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=820434843 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_noise_filter.820434843
Directory	/workspace/19.uart_noise_filter/latest

Test location	/workspace/coverage/default/197.uart_fifo_reset.2066943698
Short name	T193
Test name
Test status
Simulation time	109326628586 ps
CPU time	174.46 seconds
Started	Feb 18 02:07:58 PM PST 24
Finished	Feb 18 02:10:54 PM PST 24
Peak memory	200056 kb
Host	smart-178bbad9-914f-4f1a-882e-946002ab819e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2066943698 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.uart_fifo_reset.2066943698
Directory	/workspace/197.uart_fifo_reset/latest

Test location	/workspace/coverage/default/256.uart_fifo_reset.1615055091
Short name	T118
Test name
Test status
Simulation time	57372618868 ps
CPU time	43.93 seconds
Started	Feb 18 02:08:31 PM PST 24
Finished	Feb 18 02:09:18 PM PST 24
Peak memory	200052 kb
Host	smart-d4fafe29-32a5-4ef4-8870-bdbee859ae9e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1615055091 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.uart_fifo_reset.1615055091
Directory	/workspace/256.uart_fifo_reset/latest

Test location	/workspace/coverage/default/4.uart_rx_parity_err.2092091761
Short name	T409
Test name
Test status
Simulation time	78560176341 ps
CPU time	124.45 seconds
Started	Feb 18 02:03:33 PM PST 24
Finished	Feb 18 02:05:47 PM PST 24
Peak memory	200004 kb
Host	smart-a12b14c8-f747-4c8c-95fa-d12f63b8aa4b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2092091761 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_parity_err.2092091761
Directory	/workspace/4.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/42.uart_stress_all.1188563846
Short name	T91
Test name
Test status
Simulation time	144801890702 ps
CPU time	714.77 seconds
Started	Feb 18 02:06:24 PM PST 24
Finished	Feb 18 02:18:22 PM PST 24
Peak memory	200104 kb
Host	smart-7e099c68-d202-4cb1-9ec5-fa40db7ea382
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188563846 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_stress_all.1188563846
Directory	/workspace/42.uart_stress_all/latest

Test location	/workspace/coverage/default/48.uart_stress_all.3170488833
Short name	T319
Test name
Test status
Simulation time	309266836037 ps
CPU time	116.11 seconds
Started	Feb 18 02:06:58 PM PST 24
Finished	Feb 18 02:08:59 PM PST 24
Peak memory	200068 kb
Host	smart-9859b159-c3eb-4503-8fb9-096529ee2fa3
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170488833 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_stress_all.3170488833
Directory	/workspace/48.uart_stress_all/latest

Test location	/workspace/coverage/default/90.uart_stress_all_with_rand_reset.4069780718
Short name	T168
Test name
Test status
Simulation time	221499558153 ps
CPU time	1249.86 seconds
Started	Feb 18 02:07:21 PM PST 24
Finished	Feb 18 02:28:14 PM PST 24
Peak memory	233172 kb
Host	smart-889d0cb3-c3b6-4df2-8816-651a3284251f
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069780718 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 90.uart_stress_all_with_rand_reset.4069780718
Directory	/workspace/90.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/11.uart_fifo_full.3537117593
Short name	T364
Test name
Test status
Simulation time	92850840441 ps
CPU time	10.88 seconds
Started	Feb 18 02:04:04 PM PST 24
Finished	Feb 18 02:04:20 PM PST 24
Peak memory	199912 kb
Host	smart-2b6201a7-3ee4-4098-a75b-9e4796389d24
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3537117593 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_full.3537117593
Directory	/workspace/11.uart_fifo_full/latest

Test location	/workspace/coverage/default/117.uart_fifo_reset.376163800
Short name	T374
Test name
Test status
Simulation time	13024721728 ps
CPU time	23.57 seconds
Started	Feb 18 02:07:27 PM PST 24
Finished	Feb 18 02:07:52 PM PST 24
Peak memory	199884 kb
Host	smart-6c1f9870-7c25-45cc-8e41-4a25616de236
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=376163800 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.uart_fifo_reset.376163800
Directory	/workspace/117.uart_fifo_reset/latest

Test location	/workspace/coverage/default/119.uart_fifo_reset.3250305759
Short name	T152
Test name
Test status
Simulation time	32947162029 ps
CPU time	31.8 seconds
Started	Feb 18 02:07:29 PM PST 24
Finished	Feb 18 02:08:03 PM PST 24
Peak memory	199784 kb
Host	smart-ac7bce25-aa10-4450-a565-55afa38e4c02
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3250305759 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.uart_fifo_reset.3250305759
Directory	/workspace/119.uart_fifo_reset/latest

Test location	/workspace/coverage/default/125.uart_fifo_reset.2587476053
Short name	T223
Test name
Test status
Simulation time	32740645666 ps
CPU time	25.21 seconds
Started	Feb 18 02:07:29 PM PST 24
Finished	Feb 18 02:07:56 PM PST 24
Peak memory	200020 kb
Host	smart-5a504d29-44a9-46a2-a665-963aa2b329af
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2587476053 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.uart_fifo_reset.2587476053
Directory	/workspace/125.uart_fifo_reset/latest

Test location	/workspace/coverage/default/143.uart_fifo_reset.4111325345
Short name	T257
Test name
Test status
Simulation time	107002604984 ps
CPU time	12.48 seconds
Started	Feb 18 02:07:34 PM PST 24
Finished	Feb 18 02:07:49 PM PST 24
Peak memory	199444 kb
Host	smart-66e823c4-dfcf-4dc9-9351-851880f78473
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4111325345 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.uart_fifo_reset.4111325345
Directory	/workspace/143.uart_fifo_reset/latest

Test location	/workspace/coverage/default/202.uart_fifo_reset.3051709679
Short name	T250
Test name
Test status
Simulation time	161577918101 ps
CPU time	35.69 seconds
Started	Feb 18 02:08:02 PM PST 24
Finished	Feb 18 02:08:39 PM PST 24
Peak memory	200036 kb
Host	smart-8f1da6c1-4674-4e54-bc00-8c5a4ea3f28d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3051709679 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.uart_fifo_reset.3051709679
Directory	/workspace/202.uart_fifo_reset/latest

Test location	/workspace/coverage/default/286.uart_fifo_reset.720772329
Short name	T324
Test name
Test status
Simulation time	191517109869 ps
CPU time	220.93 seconds
Started	Feb 18 02:08:45 PM PST 24
Finished	Feb 18 02:12:33 PM PST 24
Peak memory	200012 kb
Host	smart-e7bd8f5b-4a89-42c8-b948-83057229b2e4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=720772329 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.uart_fifo_reset.720772329
Directory	/workspace/286.uart_fifo_reset/latest

Test location	/workspace/coverage/default/54.uart_fifo_reset.1648915654
Short name	T330
Test name
Test status
Simulation time	68990720216 ps
CPU time	54.57 seconds
Started	Feb 18 02:07:11 PM PST 24
Finished	Feb 18 02:08:07 PM PST 24
Peak memory	200044 kb
Host	smart-9e916ac1-f04c-4e8d-9941-5a00479e24bf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1648915654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.uart_fifo_reset.1648915654
Directory	/workspace/54.uart_fifo_reset/latest

Test location	/workspace/coverage/default/104.uart_fifo_reset.1675745917
Short name	T170
Test name
Test status
Simulation time	108190620585 ps
CPU time	50.48 seconds
Started	Feb 18 02:07:23 PM PST 24
Finished	Feb 18 02:08:16 PM PST 24
Peak memory	199704 kb
Host	smart-735f1522-a5b5-4a1d-98e2-80704b6a01bd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1675745917 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.uart_fifo_reset.1675745917
Directory	/workspace/104.uart_fifo_reset/latest

Test location	/workspace/coverage/default/122.uart_fifo_reset.1450010776
Short name	T269
Test name
Test status
Simulation time	104166867285 ps
CPU time	70.8 seconds
Started	Feb 18 02:07:37 PM PST 24
Finished	Feb 18 02:08:49 PM PST 24
Peak memory	199784 kb
Host	smart-3a5cc117-b760-4dfe-a337-2783390a2eaf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1450010776 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.uart_fifo_reset.1450010776
Directory	/workspace/122.uart_fifo_reset/latest

Test location	/workspace/coverage/default/13.uart_rx_parity_err.1386975796
Short name	T47
Test name
Test status
Simulation time	38832487880 ps
CPU time	20.97 seconds
Started	Feb 18 02:04:08 PM PST 24
Finished	Feb 18 02:04:34 PM PST 24
Peak memory	200020 kb
Host	smart-036b3868-9ec0-4f92-964e-cb668f1e97e8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1386975796 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_parity_err.1386975796
Directory	/workspace/13.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/15.uart_stress_all.1308131884
Short name	T368
Test name
Test status
Simulation time	550743016724 ps
CPU time	1703.32 seconds
Started	Feb 18 02:04:17 PM PST 24
Finished	Feb 18 02:32:44 PM PST 24
Peak memory	200048 kb
Host	smart-6063e060-5c74-4b6b-8384-1ac8e27b8eac
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308131884 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_stress_all.1308131884
Directory	/workspace/15.uart_stress_all/latest

Test location	/workspace/coverage/default/170.uart_fifo_reset.3618228028
Short name	T195
Test name
Test status
Simulation time	43341008904 ps
CPU time	18.68 seconds
Started	Feb 18 02:07:50 PM PST 24
Finished	Feb 18 02:08:09 PM PST 24
Peak memory	200028 kb
Host	smart-a25b4853-f03a-47d9-95c4-74616478a795
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3618228028 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.uart_fifo_reset.3618228028
Directory	/workspace/170.uart_fifo_reset/latest

Test location	/workspace/coverage/default/203.uart_fifo_reset.611668380
Short name	T236
Test name
Test status
Simulation time	73763213539 ps
CPU time	32.41 seconds
Started	Feb 18 02:08:04 PM PST 24
Finished	Feb 18 02:08:38 PM PST 24
Peak memory	200056 kb
Host	smart-3ab80617-aded-473b-bb30-3e8d8b01701b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=611668380 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.uart_fifo_reset.611668380
Directory	/workspace/203.uart_fifo_reset/latest

Test location	/workspace/coverage/default/235.uart_fifo_reset.3124581544
Short name	T158
Test name
Test status
Simulation time	68929858874 ps
CPU time	12.99 seconds
Started	Feb 18 02:08:19 PM PST 24
Finished	Feb 18 02:08:37 PM PST 24
Peak memory	200024 kb
Host	smart-63272d89-9e86-4ee6-ba50-822383e25919
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3124581544 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.uart_fifo_reset.3124581544
Directory	/workspace/235.uart_fifo_reset/latest

Test location	/workspace/coverage/default/239.uart_fifo_reset.1953285819
Short name	T141
Test name
Test status
Simulation time	99586973251 ps
CPU time	47.4 seconds
Started	Feb 18 02:08:29 PM PST 24
Finished	Feb 18 02:09:19 PM PST 24
Peak memory	199828 kb
Host	smart-07c452de-d612-4f20-abe9-89e5f979652f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1953285819 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.uart_fifo_reset.1953285819
Directory	/workspace/239.uart_fifo_reset/latest

Test location	/workspace/coverage/default/26.uart_stress_all.3397602397
Short name	T370
Test name
Test status
Simulation time	204669117161 ps
CPU time	363.82 seconds
Started	Feb 18 02:05:03 PM PST 24
Finished	Feb 18 02:11:10 PM PST 24
Peak memory	200040 kb
Host	smart-9216cd11-b8d6-403f-80e5-5d7b292a3384
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397602397 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_stress_all.3397602397
Directory	/workspace/26.uart_stress_all/latest

Test location	/workspace/coverage/default/43.uart_stress_all_with_rand_reset.1572371787
Short name	T307
Test name
Test status
Simulation time	129688691405 ps
CPU time	360.56 seconds
Started	Feb 18 02:06:19 PM PST 24
Finished	Feb 18 02:12:24 PM PST 24
Peak memory	211036 kb
Host	smart-760b8409-e7ec-438e-b1fd-b985c635baf0
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572371787 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 43.uart_stress_all_with_rand_reset.1572371787
Directory	/workspace/43.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.uart_tl_intg_err.2895885537
Short name	T79
Test name
Test status
Simulation time	337136471 ps
CPU time	1.3 seconds
Started	Feb 18 12:37:29 PM PST 24
Finished	Feb 18 12:37:37 PM PST 24
Peak memory	199240 kb
Host	smart-07956fd9-1451-48d2-9af1-f157a025b265
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895885537 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_intg_err.2895885537
Directory	/workspace/1.uart_tl_intg_err/latest

Test location	/workspace/coverage/default/0.uart_stress_all.3516325355
Short name	T215
Test name
Test status
Simulation time	359253968809 ps
CPU time	635.89 seconds
Started	Feb 18 02:03:26 PM PST 24
Finished	Feb 18 02:14:05 PM PST 24
Peak memory	200032 kb
Host	smart-088310d3-4171-4a80-8be0-d4fab1397e0b
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516325355 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_stress_all.3516325355
Directory	/workspace/0.uart_stress_all/latest

Test location	/workspace/coverage/default/100.uart_fifo_reset.2311663699
Short name	T786
Test name
Test status
Simulation time	49391410242 ps
CPU time	21.84 seconds
Started	Feb 18 02:07:20 PM PST 24
Finished	Feb 18 02:07:45 PM PST 24
Peak memory	200004 kb
Host	smart-c65278e5-6cc9-495a-8580-8afe03ab4c84
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2311663699 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.uart_fifo_reset.2311663699
Directory	/workspace/100.uart_fifo_reset/latest

Test location	/workspace/coverage/default/11.uart_fifo_overflow.888025027
Short name	T288
Test name
Test status
Simulation time	45590970799 ps
CPU time	13.96 seconds
Started	Feb 18 02:04:10 PM PST 24
Finished	Feb 18 02:04:28 PM PST 24
Peak memory	197908 kb
Host	smart-1a7fc546-52a0-495c-99c7-71cb7d65df45
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=888025027 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_overflow.888025027
Directory	/workspace/11.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/11.uart_fifo_reset.2323881595
Short name	T244
Test name
Test status
Simulation time	178965267111 ps
CPU time	52.91 seconds
Started	Feb 18 02:04:07 PM PST 24
Finished	Feb 18 02:05:04 PM PST 24
Peak memory	200056 kb
Host	smart-bce0bca1-a285-4969-9041-dc5be1c4e1dc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2323881595 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_reset.2323881595
Directory	/workspace/11.uart_fifo_reset/latest

Test location	/workspace/coverage/default/115.uart_fifo_reset.3537056359
Short name	T1053
Test name
Test status
Simulation time	14479947256 ps
CPU time	23.45 seconds
Started	Feb 18 02:07:27 PM PST 24
Finished	Feb 18 02:07:51 PM PST 24
Peak memory	199752 kb
Host	smart-bcd5cf37-7b2d-4c8c-a220-3a8f827320d0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3537056359 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.uart_fifo_reset.3537056359
Directory	/workspace/115.uart_fifo_reset/latest

Test location	/workspace/coverage/default/128.uart_fifo_reset.3529606471
Short name	T150
Test name
Test status
Simulation time	76361175475 ps
CPU time	12.94 seconds
Started	Feb 18 02:07:28 PM PST 24
Finished	Feb 18 02:07:42 PM PST 24
Peak memory	200092 kb
Host	smart-c61f0740-1cbb-4444-9b6f-0d244f6fd55e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3529606471 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.uart_fifo_reset.3529606471
Directory	/workspace/128.uart_fifo_reset/latest

Test location	/workspace/coverage/default/132.uart_fifo_reset.3132129831
Short name	T346
Test name
Test status
Simulation time	42347418388 ps
CPU time	16.21 seconds
Started	Feb 18 02:07:38 PM PST 24
Finished	Feb 18 02:07:55 PM PST 24
Peak memory	200044 kb
Host	smart-fa54b510-104c-4375-9755-25a488fb597d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3132129831 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.uart_fifo_reset.3132129831
Directory	/workspace/132.uart_fifo_reset/latest

Test location	/workspace/coverage/default/135.uart_fifo_reset.3142188724
Short name	T208
Test name
Test status
Simulation time	173757609138 ps
CPU time	54.73 seconds
Started	Feb 18 02:07:36 PM PST 24
Finished	Feb 18 02:08:32 PM PST 24
Peak memory	200124 kb
Host	smart-ee4ef7c0-497f-48ff-9a0a-bf20b0aef13b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3142188724 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.uart_fifo_reset.3142188724
Directory	/workspace/135.uart_fifo_reset/latest

Test location	/workspace/coverage/default/14.uart_fifo_overflow.3550889697
Short name	T240
Test name
Test status
Simulation time	32108692340 ps
CPU time	32.22 seconds
Started	Feb 18 02:04:10 PM PST 24
Finished	Feb 18 02:04:46 PM PST 24
Peak memory	200020 kb
Host	smart-1cac5824-49a1-4332-a7b7-aed8d2a85ad5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3550889697 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_overflow.3550889697
Directory	/workspace/14.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/14.uart_stress_all.1868859431
Short name	T220
Test name
Test status
Simulation time	177110828035 ps
CPU time	81.09 seconds
Started	Feb 18 02:04:06 PM PST 24
Finished	Feb 18 02:05:32 PM PST 24
Peak memory	200080 kb
Host	smart-2ffef86c-5b26-41f2-a343-65e942365e80
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868859431 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_stress_all.1868859431
Directory	/workspace/14.uart_stress_all/latest

Test location	/workspace/coverage/default/148.uart_fifo_reset.1822602496
Short name	T213
Test name
Test status
Simulation time	158145719911 ps
CPU time	24.5 seconds
Started	Feb 18 02:07:32 PM PST 24
Finished	Feb 18 02:07:59 PM PST 24
Peak memory	199992 kb
Host	smart-c21d9f65-2059-49c5-8ec5-0ba062c710ea
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1822602496 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.uart_fifo_reset.1822602496
Directory	/workspace/148.uart_fifo_reset/latest

Test location	/workspace/coverage/default/166.uart_fifo_reset.3675273733
Short name	T957
Test name
Test status
Simulation time	45831570861 ps
CPU time	71.97 seconds
Started	Feb 18 02:07:46 PM PST 24
Finished	Feb 18 02:09:00 PM PST 24
Peak memory	200096 kb
Host	smart-bb38797d-12d4-4693-9cae-e5855015c5e9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3675273733 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.uart_fifo_reset.3675273733
Directory	/workspace/166.uart_fifo_reset/latest

Test location	/workspace/coverage/default/167.uart_fifo_reset.233315162
Short name	T326
Test name
Test status
Simulation time	59833130763 ps
CPU time	20.9 seconds
Started	Feb 18 02:07:45 PM PST 24
Finished	Feb 18 02:08:08 PM PST 24
Peak memory	200048 kb
Host	smart-28f8882a-e9a8-43ed-90a2-2ac5a3e05a5e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=233315162 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.uart_fifo_reset.233315162
Directory	/workspace/167.uart_fifo_reset/latest

Test location	/workspace/coverage/default/169.uart_fifo_reset.1386522203
Short name	T335
Test name
Test status
Simulation time	12589491721 ps
CPU time	9.68 seconds
Started	Feb 18 02:07:44 PM PST 24
Finished	Feb 18 02:07:55 PM PST 24
Peak memory	200104 kb
Host	smart-e64fe73f-0b1b-45e6-afd0-5438d7d92ce9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1386522203 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.uart_fifo_reset.1386522203
Directory	/workspace/169.uart_fifo_reset/latest

Test location	/workspace/coverage/default/17.uart_stress_all.1304708802
Short name	T772
Test name
Test status
Simulation time	473445306476 ps
CPU time	235.99 seconds
Started	Feb 18 02:04:25 PM PST 24
Finished	Feb 18 02:08:22 PM PST 24
Peak memory	208496 kb
Host	smart-dc0de855-c22f-4a93-9eaa-0a36c682106f
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304708802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_stress_all.1304708802
Directory	/workspace/17.uart_stress_all/latest

Test location	/workspace/coverage/default/17.uart_stress_all_with_rand_reset.4253465650
Short name	T361
Test name
Test status
Simulation time	104803275027 ps
CPU time	637.11 seconds
Started	Feb 18 02:04:24 PM PST 24
Finished	Feb 18 02:15:03 PM PST 24
Peak memory	216616 kb
Host	smart-8c90d17f-6bcb-44c5-b723-68ce69ea2450
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253465650 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 17.uart_stress_all_with_rand_reset.4253465650
Directory	/workspace/17.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/176.uart_fifo_reset.834515250
Short name	T298
Test name
Test status
Simulation time	224721500310 ps
CPU time	370.97 seconds
Started	Feb 18 02:07:53 PM PST 24
Finished	Feb 18 02:14:09 PM PST 24
Peak memory	200124 kb
Host	smart-d623fca0-c285-46a3-b4a0-a004273e2554
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=834515250 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.uart_fifo_reset.834515250
Directory	/workspace/176.uart_fifo_reset/latest

Test location	/workspace/coverage/default/195.uart_fifo_reset.3212384922
Short name	T271
Test name
Test status
Simulation time	83493740515 ps
CPU time	54.85 seconds
Started	Feb 18 02:08:03 PM PST 24
Finished	Feb 18 02:08:59 PM PST 24
Peak memory	200088 kb
Host	smart-19ce65e7-476c-4739-9bdc-cfef4c279774
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3212384922 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.uart_fifo_reset.3212384922
Directory	/workspace/195.uart_fifo_reset/latest

Test location	/workspace/coverage/default/198.uart_fifo_reset.1849671308
Short name	T277
Test name
Test status
Simulation time	34710528912 ps
CPU time	29.56 seconds
Started	Feb 18 02:08:07 PM PST 24
Finished	Feb 18 02:08:39 PM PST 24
Peak memory	199792 kb
Host	smart-09626860-cb79-4e2e-a040-34d36270b7c6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1849671308 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.uart_fifo_reset.1849671308
Directory	/workspace/198.uart_fifo_reset/latest

Test location	/workspace/coverage/default/20.uart_fifo_reset.1906623878
Short name	T233
Test name
Test status
Simulation time	121952905142 ps
CPU time	107.61 seconds
Started	Feb 18 02:04:40 PM PST 24
Finished	Feb 18 02:06:32 PM PST 24
Peak memory	200040 kb
Host	smart-a7abb757-b9e7-4938-b783-93354fe0f829
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1906623878 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_reset.1906623878
Directory	/workspace/20.uart_fifo_reset/latest

Test location	/workspace/coverage/default/208.uart_fifo_reset.1755130739
Short name	T340
Test name
Test status
Simulation time	116040395974 ps
CPU time	61.59 seconds
Started	Feb 18 02:08:13 PM PST 24
Finished	Feb 18 02:09:18 PM PST 24
Peak memory	200040 kb
Host	smart-6cc21608-f6fc-44e3-9a64-dd55cdef4916
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1755130739 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.uart_fifo_reset.1755130739
Directory	/workspace/208.uart_fifo_reset/latest

Test location	/workspace/coverage/default/21.uart_fifo_reset.2954448215
Short name	T135
Test name
Test status
Simulation time	59144030283 ps
CPU time	10.94 seconds
Started	Feb 18 02:04:47 PM PST 24
Finished	Feb 18 02:05:01 PM PST 24
Peak memory	199532 kb
Host	smart-61e8bff3-4737-4e42-9438-ea96fadf473b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2954448215 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_reset.2954448215
Directory	/workspace/21.uart_fifo_reset/latest

Test location	/workspace/coverage/default/216.uart_fifo_reset.2716660189
Short name	T255
Test name
Test status
Simulation time	64033283429 ps
CPU time	45.89 seconds
Started	Feb 18 02:08:15 PM PST 24
Finished	Feb 18 02:09:04 PM PST 24
Peak memory	200028 kb
Host	smart-b3db16a6-5c41-421d-87f6-229c44f812c2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2716660189 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.uart_fifo_reset.2716660189
Directory	/workspace/216.uart_fifo_reset/latest

Test location	/workspace/coverage/default/218.uart_fifo_reset.425120559
Short name	T334
Test name
Test status
Simulation time	152077447365 ps
CPU time	61.03 seconds
Started	Feb 18 02:08:14 PM PST 24
Finished	Feb 18 02:09:18 PM PST 24
Peak memory	200024 kb
Host	smart-3dade662-03e4-4b1a-8f95-60370051a0de
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=425120559 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.uart_fifo_reset.425120559
Directory	/workspace/218.uart_fifo_reset/latest

Test location	/workspace/coverage/default/22.uart_fifo_overflow.3400728502
Short name	T131
Test name
Test status
Simulation time	117933713239 ps
CPU time	171.82 seconds
Started	Feb 18 02:04:46 PM PST 24
Finished	Feb 18 02:07:41 PM PST 24
Peak memory	200000 kb
Host	smart-4a966f15-189b-451b-81a1-04d995004eab
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3400728502 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_overflow.3400728502
Directory	/workspace/22.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/24.uart_fifo_reset.2135967738
Short name	T253
Test name
Test status
Simulation time	27453620257 ps
CPU time	9.3 seconds
Started	Feb 18 02:04:54 PM PST 24
Finished	Feb 18 02:05:09 PM PST 24
Peak memory	199988 kb
Host	smart-bfa47b7d-7714-431a-88b0-ae43ba3da3d9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2135967738 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_reset.2135967738
Directory	/workspace/24.uart_fifo_reset/latest

Test location	/workspace/coverage/default/24.uart_stress_all.2172671781
Short name	T363
Test name
Test status
Simulation time	68979043841 ps
CPU time	111.97 seconds
Started	Feb 18 02:04:52 PM PST 24
Finished	Feb 18 02:06:51 PM PST 24
Peak memory	200120 kb
Host	smart-aff81be0-a72a-494e-88c6-70e4e13bd14a
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172671781 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_stress_all.2172671781
Directory	/workspace/24.uart_stress_all/latest

Test location	/workspace/coverage/default/245.uart_fifo_reset.4216542357
Short name	T130
Test name
Test status
Simulation time	116342549148 ps
CPU time	24.42 seconds
Started	Feb 18 02:08:18 PM PST 24
Finished	Feb 18 02:08:46 PM PST 24
Peak memory	200000 kb
Host	smart-2f173a59-8883-4b93-b065-5a920c01292e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4216542357 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.uart_fifo_reset.4216542357
Directory	/workspace/245.uart_fifo_reset/latest

Test location	/workspace/coverage/default/26.uart_perf.2216436105
Short name	T283
Test name
Test status
Simulation time	13968112613 ps
CPU time	157.3 seconds
Started	Feb 18 02:04:59 PM PST 24
Finished	Feb 18 02:07:40 PM PST 24
Peak memory	200068 kb
Host	smart-ba718da0-0c87-49c7-963d-c2919fd4f322
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2216436105 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_perf.2216436105
Directory	/workspace/26.uart_perf/latest

Test location	/workspace/coverage/default/264.uart_fifo_reset.604587758
Short name	T289
Test name
Test status
Simulation time	222452299122 ps
CPU time	479.29 seconds
Started	Feb 18 02:08:34 PM PST 24
Finished	Feb 18 02:16:42 PM PST 24
Peak memory	200164 kb
Host	smart-f29978ea-a1df-45b4-b3aa-1031caa24370
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=604587758 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.uart_fifo_reset.604587758
Directory	/workspace/264.uart_fifo_reset/latest

Test location	/workspace/coverage/default/265.uart_fifo_reset.1217264840
Short name	T77
Test name
Test status
Simulation time	69277017235 ps
CPU time	58.2 seconds
Started	Feb 18 02:08:29 PM PST 24
Finished	Feb 18 02:09:30 PM PST 24
Peak memory	200052 kb
Host	smart-323d0a28-6de6-471c-a6aa-1a7e701e136a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1217264840 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.uart_fifo_reset.1217264840
Directory	/workspace/265.uart_fifo_reset/latest

Test location	/workspace/coverage/default/268.uart_fifo_reset.1658619275
Short name	T379
Test name
Test status
Simulation time	20047363777 ps
CPU time	37.41 seconds
Started	Feb 18 02:08:33 PM PST 24
Finished	Feb 18 02:09:19 PM PST 24
Peak memory	200088 kb
Host	smart-2ed891f8-dc26-46dd-ad54-766acc145a00
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1658619275 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.uart_fifo_reset.1658619275
Directory	/workspace/268.uart_fifo_reset/latest

Test location	/workspace/coverage/default/276.uart_fifo_reset.3720383685
Short name	T197
Test name
Test status
Simulation time	41086938956 ps
CPU time	37.47 seconds
Started	Feb 18 02:08:31 PM PST 24
Finished	Feb 18 02:09:10 PM PST 24
Peak memory	200032 kb
Host	smart-7fc835e2-cc34-4c8f-98c7-c3f9e3e77591
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3720383685 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.uart_fifo_reset.3720383685
Directory	/workspace/276.uart_fifo_reset/latest

Test location	/workspace/coverage/default/280.uart_fifo_reset.1584886662
Short name	T275
Test name
Test status
Simulation time	146972727174 ps
CPU time	62.79 seconds
Started	Feb 18 02:08:38 PM PST 24
Finished	Feb 18 02:09:48 PM PST 24
Peak memory	199932 kb
Host	smart-255e2c6d-6c89-4f7f-81b7-98308dfdcfac
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1584886662 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.uart_fifo_reset.1584886662
Directory	/workspace/280.uart_fifo_reset/latest

Test location	/workspace/coverage/default/31.uart_fifo_overflow.3549319874
Short name	T286
Test name
Test status
Simulation time	45156126619 ps
CPU time	19.59 seconds
Started	Feb 18 02:05:22 PM PST 24
Finished	Feb 18 02:05:45 PM PST 24
Peak memory	199108 kb
Host	smart-a3d7ab5b-02c4-41c7-a4cb-2d1682b58ab7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3549319874 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_overflow.3549319874
Directory	/workspace/31.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/37.uart_fifo_reset.1191028205
Short name	T281
Test name
Test status
Simulation time	38301492827 ps
CPU time	15.19 seconds
Started	Feb 18 02:05:55 PM PST 24
Finished	Feb 18 02:06:16 PM PST 24
Peak memory	199880 kb
Host	smart-a2fbbb20-667f-4f6e-939c-45d46b9e3664
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1191028205 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_reset.1191028205
Directory	/workspace/37.uart_fifo_reset/latest

Test location	/workspace/coverage/default/38.uart_fifo_reset.2309301243
Short name	T200
Test name
Test status
Simulation time	45907696900 ps
CPU time	23.6 seconds
Started	Feb 18 02:05:57 PM PST 24
Finished	Feb 18 02:06:26 PM PST 24
Peak memory	200060 kb
Host	smart-a2ce8d0f-74e4-4b8a-842e-8643c8e7f5d2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2309301243 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_reset.2309301243
Directory	/workspace/38.uart_fifo_reset/latest

Test location	/workspace/coverage/default/39.uart_long_xfer_wo_dly.2439918714
Short name	T285
Test name
Test status
Simulation time	142325903848 ps
CPU time	516.87 seconds
Started	Feb 18 02:06:05 PM PST 24
Finished	Feb 18 02:14:44 PM PST 24
Peak memory	200032 kb
Host	smart-dc949921-9d84-4c3b-927e-3066818c7a52
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2439918714 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_long_xfer_wo_dly.2439918714
Directory	/workspace/39.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/47.uart_fifo_reset.4292826202
Short name	T359
Test name
Test status
Simulation time	59508739967 ps
CPU time	32.87 seconds
Started	Feb 18 02:06:46 PM PST 24
Finished	Feb 18 02:07:20 PM PST 24
Peak memory	200108 kb
Host	smart-5d9bce88-6095-4398-90d2-38021fd1dc81
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4292826202 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_reset.4292826202
Directory	/workspace/47.uart_fifo_reset/latest

Test location	/workspace/coverage/default/49.uart_fifo_overflow.4263528119
Short name	T284
Test name
Test status
Simulation time	23873761867 ps
CPU time	47.31 seconds
Started	Feb 18 02:07:00 PM PST 24
Finished	Feb 18 02:07:51 PM PST 24
Peak memory	199944 kb
Host	smart-f5d21673-b722-40b1-901b-015db137edf6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4263528119 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_overflow.4263528119
Directory	/workspace/49.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/51.uart_fifo_reset.3435897420
Short name	T248
Test name
Test status
Simulation time	14694431532 ps
CPU time	11.57 seconds
Started	Feb 18 02:06:46 PM PST 24
Finished	Feb 18 02:06:59 PM PST 24
Peak memory	199908 kb
Host	smart-35bd710d-97a8-4ec1-a6fc-c08ef7279b7b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3435897420 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.uart_fifo_reset.3435897420
Directory	/workspace/51.uart_fifo_reset/latest

Test location	/workspace/coverage/default/67.uart_fifo_reset.3720761634
Short name	T322
Test name
Test status
Simulation time	95995974055 ps
CPU time	143.01 seconds
Started	Feb 18 02:07:10 PM PST 24
Finished	Feb 18 02:09:34 PM PST 24
Peak memory	199960 kb
Host	smart-26f5d1d3-32af-4fba-b51f-9c2fc2e84609
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3720761634 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.uart_fifo_reset.3720761634
Directory	/workspace/67.uart_fifo_reset/latest

Test location	/workspace/coverage/default/79.uart_fifo_reset.2584034370
Short name	T337
Test name
Test status
Simulation time	48836019662 ps
CPU time	88.07 seconds
Started	Feb 18 02:07:13 PM PST 24
Finished	Feb 18 02:08:42 PM PST 24
Peak memory	200048 kb
Host	smart-32ac6789-9471-4769-a6ba-ed202ec3e2e9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2584034370 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.uart_fifo_reset.2584034370
Directory	/workspace/79.uart_fifo_reset/latest

Test location	/workspace/coverage/default/91.uart_fifo_reset.2213062937
Short name	T206
Test name
Test status
Simulation time	100247762109 ps
CPU time	49.65 seconds
Started	Feb 18 02:07:14 PM PST 24
Finished	Feb 18 02:08:05 PM PST 24
Peak memory	200124 kb
Host	smart-c45062e1-116a-4f7d-8be8-53f9c094037c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2213062937 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.uart_fifo_reset.2213062937
Directory	/workspace/91.uart_fifo_reset/latest

Test location	/workspace/coverage/default/98.uart_stress_all_with_rand_reset.271873070
Short name	T381
Test name
Test status
Simulation time	416459332553 ps
CPU time	441.67 seconds
Started	Feb 18 02:07:21 PM PST 24
Finished	Feb 18 02:14:46 PM PST 24
Peak memory	224916 kb
Host	smart-ea32ebdf-c951-45a7-873a-65dee7cd9540
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271873070 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 98.uart_stress_all_with_rand_reset.271873070
Directory	/workspace/98.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.uart_csr_aliasing.3969249849
Short name	T1224
Test name
Test status
Simulation time	43522160 ps
CPU time	0.66 seconds
Started	Feb 18 12:37:20 PM PST 24
Finished	Feb 18 12:37:22 PM PST 24
Peak memory	195416 kb
Host	smart-32215dea-6436-4eeb-82e5-11ec3b5ea019
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969249849 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_aliasing.3969249849
Directory	/workspace/0.uart_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.2751342998
Short name	T1247
Test name
Test status
Simulation time	1038360640 ps
CPU time	2.51 seconds
Started	Feb 18 12:37:22 PM PST 24
Finished	Feb 18 12:37:26 PM PST 24
Peak memory	197716 kb
Host	smart-dda6f33d-dda2-46d5-a3d0-834db13b0829
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751342998 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_bit_bash.2751342998
Directory	/workspace/0.uart_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.1883095691
Short name	T1236
Test name
Test status
Simulation time	55828660 ps
CPU time	0.63 seconds
Started	Feb 18 12:37:23 PM PST 24
Finished	Feb 18 12:37:25 PM PST 24
Peak memory	195416 kb
Host	smart-0c690c89-0dcf-4bbf-96fa-59af7f6c966f
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883095691 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_hw_reset.1883095691
Directory	/workspace/0.uart_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.1082305083
Short name	T1124
Test name
Test status
Simulation time	86406308 ps
CPU time	1.36 seconds
Started	Feb 18 12:37:31 PM PST 24
Finished	Feb 18 12:37:41 PM PST 24
Peak memory	200228 kb
Host	smart-b54bfd10-df93-4ac6-8558-e780d547576e
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082305083 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_mem_rw_with_rand_reset.1082305083
Directory	/workspace/0.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.uart_csr_rw.488611758
Short name	T1147
Test name
Test status
Simulation time	38652306 ps
CPU time	0.57 seconds
Started	Feb 18 12:37:21 PM PST 24
Finished	Feb 18 12:37:24 PM PST 24
Peak memory	195416 kb
Host	smart-9245ae10-c0aa-4087-9063-ed45a71a3568
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488611758 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_rw.488611758
Directory	/workspace/0.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/0.uart_intr_test.2526573228
Short name	T1261
Test name
Test status
Simulation time	43032751 ps
CPU time	0.58 seconds
Started	Feb 18 12:37:21 PM PST 24
Finished	Feb 18 12:37:23 PM PST 24
Peak memory	185224 kb
Host	smart-7dd17c46-5097-45b1-8bb3-c0da5257d48c
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526573228 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_intr_test.2526573228
Directory	/workspace/0.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.3492664371
Short name	T1159
Test name
Test status
Simulation time	37168845 ps
CPU time	0.66 seconds
Started	Feb 18 12:37:27 PM PST 24
Finished	Feb 18 12:37:33 PM PST 24
Peak memory	195712 kb
Host	smart-81ec61e8-3fc3-41f6-a684-a86e24743b38
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492664371 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_same_csr _outstanding.3492664371
Directory	/workspace/0.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/0.uart_tl_errors.4203840014
Short name	T1245
Test name
Test status
Simulation time	77717568 ps
CPU time	1.63 seconds
Started	Feb 18 12:37:21 PM PST 24
Finished	Feb 18 12:37:24 PM PST 24
Peak memory	200100 kb
Host	smart-cc0d0dcd-c778-42aa-a83c-ab379a94a624
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203840014 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_errors.4203840014
Directory	/workspace/0.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/0.uart_tl_intg_err.3197418949
Short name	T1187
Test name
Test status
Simulation time	40654475 ps
CPU time	0.93 seconds
Started	Feb 18 12:37:24 PM PST 24
Finished	Feb 18 12:37:26 PM PST 24
Peak memory	198892 kb
Host	smart-24f8dcc1-ad2b-463d-b193-c09c05635888
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197418949 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_intg_err.3197418949
Directory	/workspace/0.uart_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/1.uart_csr_aliasing.1613382161
Short name	T1208
Test name
Test status
Simulation time	20999858 ps
CPU time	0.69 seconds
Started	Feb 18 12:37:30 PM PST 24
Finished	Feb 18 12:37:39 PM PST 24
Peak memory	195436 kb
Host	smart-82d5c63e-f00d-4fcf-9755-696776a43a02
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613382161 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_aliasing.1613382161
Directory	/workspace/1.uart_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.511349338
Short name	T1128
Test name
Test status
Simulation time	2715586833 ps
CPU time	2.62 seconds
Started	Feb 18 12:37:27 PM PST 24
Finished	Feb 18 12:37:34 PM PST 24
Peak memory	197856 kb
Host	smart-8b642723-090b-4985-ad54-fc8000c08da6
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511349338 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_bit_bash.511349338
Directory	/workspace/1.uart_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.2940643661
Short name	T1151
Test name
Test status
Simulation time	16490938 ps
CPU time	0.61 seconds
Started	Feb 18 12:37:32 PM PST 24
Finished	Feb 18 12:37:41 PM PST 24
Peak memory	195392 kb
Host	smart-70656c4c-e547-4d4d-96de-ecdeafdf0724
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940643661 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_hw_reset.2940643661
Directory	/workspace/1.uart_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.865846001
Short name	T1231
Test name
Test status
Simulation time	204821535 ps
CPU time	2.64 seconds
Started	Feb 18 12:37:27 PM PST 24
Finished	Feb 18 12:37:35 PM PST 24
Peak memory	200156 kb
Host	smart-31025351-6717-4d63-90f4-4b33a98087f6
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865846001 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_mem_rw_with_rand_reset.865846001
Directory	/workspace/1.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.uart_csr_rw.1182577890
Short name	T1152
Test name
Test status
Simulation time	58471574 ps
CPU time	0.63 seconds
Started	Feb 18 12:37:31 PM PST 24
Finished	Feb 18 12:37:40 PM PST 24
Peak memory	195440 kb
Host	smart-bfec9370-1c35-4399-a199-a07d6455942d
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182577890 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_rw.1182577890
Directory	/workspace/1.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/1.uart_intr_test.3286786897
Short name	T1175
Test name
Test status
Simulation time	24684959 ps
CPU time	0.63 seconds
Started	Feb 18 12:37:32 PM PST 24
Finished	Feb 18 12:37:41 PM PST 24
Peak memory	185148 kb
Host	smart-74133289-ed19-4406-8e88-35c0e90ac7a2
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286786897 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_intr_test.3286786897
Directory	/workspace/1.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.3287297764
Short name	T1251
Test name
Test status
Simulation time	167872724 ps
CPU time	0.76 seconds
Started	Feb 18 12:37:29 PM PST 24
Finished	Feb 18 12:37:35 PM PST 24
Peak memory	196784 kb
Host	smart-5e2a28a2-ed49-4521-b9a0-d33525b2effd
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287297764 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_same_csr _outstanding.3287297764
Directory	/workspace/1.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/1.uart_tl_errors.1439611860
Short name	T1180
Test name
Test status
Simulation time	164514763 ps
CPU time	1.82 seconds
Started	Feb 18 12:37:31 PM PST 24
Finished	Feb 18 12:37:42 PM PST 24
Peak memory	200140 kb
Host	smart-611b374b-dc40-4d2f-88ca-a395ba20558e
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439611860 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_errors.1439611860
Directory	/workspace/1.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.211659988
Short name	T1141
Test name
Test status
Simulation time	42074735 ps
CPU time	1.13 seconds
Started	Feb 18 12:37:40 PM PST 24
Finished	Feb 18 12:37:47 PM PST 24
Peak memory	200048 kb
Host	smart-d4299007-b9ae-4fe6-9fcd-203f38f787cc
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211659988 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_csr_mem_rw_with_rand_reset.211659988
Directory	/workspace/10.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/10.uart_csr_rw.1554005132
Short name	T1183
Test name
Test status
Simulation time	13068443 ps
CPU time	0.6 seconds
Started	Feb 18 12:37:42 PM PST 24
Finished	Feb 18 12:37:49 PM PST 24
Peak memory	195356 kb
Host	smart-6c0b219d-1fc5-43b3-8a11-1ff006381355
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554005132 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_csr_rw.1554005132
Directory	/workspace/10.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/10.uart_intr_test.268182951
Short name	T1211
Test name
Test status
Simulation time	23716963 ps
CPU time	0.54 seconds
Started	Feb 18 12:37:43 PM PST 24
Finished	Feb 18 12:37:49 PM PST 24
Peak memory	185196 kb
Host	smart-c5516bb4-bc78-4c3a-b535-1ddf0d521b61
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268182951 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_intr_test.268182951
Directory	/workspace/10.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.3717879334
Short name	T1254
Test name
Test status
Simulation time	80124902 ps
CPU time	0.73 seconds
Started	Feb 18 12:37:39 PM PST 24
Finished	Feb 18 12:37:47 PM PST 24
Peak memory	196144 kb
Host	smart-eac54287-5b04-42f1-8112-fd0ce88fa150
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717879334 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_same_cs r_outstanding.3717879334
Directory	/workspace/10.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/10.uart_tl_errors.111179813
Short name	T1136
Test name
Test status
Simulation time	296039190 ps
CPU time	1.9 seconds
Started	Feb 18 12:37:41 PM PST 24
Finished	Feb 18 12:37:49 PM PST 24
Peak memory	200204 kb
Host	smart-1d21a55d-8db5-4790-816f-c28a20a7e5c1
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111179813 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_errors.111179813
Directory	/workspace/10.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/10.uart_tl_intg_err.3581575853
Short name	T383
Test name
Test status
Simulation time	1591018937 ps
CPU time	1.34 seconds
Started	Feb 18 12:37:40 PM PST 24
Finished	Feb 18 12:37:48 PM PST 24
Peak memory	199272 kb
Host	smart-e7ff3b21-3349-45ea-9a48-697d9cb7aca1
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581575853 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_intg_err.3581575853
Directory	/workspace/10.uart_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.3843457931
Short name	T1150
Test name
Test status
Simulation time	250017387 ps
CPU time	1.73 seconds
Started	Feb 18 12:37:47 PM PST 24
Finished	Feb 18 12:37:54 PM PST 24
Peak memory	200212 kb
Host	smart-7a3d51b6-1a54-4e36-9fb4-89a74b440ccd
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843457931 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_csr_mem_rw_with_rand_reset.3843457931
Directory	/workspace/11.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/11.uart_csr_rw.1617876150
Short name	T1196
Test name
Test status
Simulation time	15154483 ps
CPU time	0.58 seconds
Started	Feb 18 12:37:42 PM PST 24
Finished	Feb 18 12:37:49 PM PST 24
Peak memory	195236 kb
Host	smart-82014410-b0ca-4fec-ac47-c9a0d79850fd
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617876150 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_csr_rw.1617876150
Directory	/workspace/11.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/11.uart_intr_test.2476701603
Short name	T1214
Test name
Test status
Simulation time	99651761 ps
CPU time	0.54 seconds
Started	Feb 18 12:37:43 PM PST 24
Finished	Feb 18 12:37:49 PM PST 24
Peak memory	185196 kb
Host	smart-0de5ab7c-695c-42fd-83e1-1c0e58fa651e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476701603 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_intr_test.2476701603
Directory	/workspace/11.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.3935403170
Short name	T1232
Test name
Test status
Simulation time	22182749 ps
CPU time	0.65 seconds
Started	Feb 18 12:37:39 PM PST 24
Finished	Feb 18 12:37:46 PM PST 24
Peak memory	195564 kb
Host	smart-c93d99f2-b247-4aa2-bcf6-fd48b2346121
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935403170 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_same_cs r_outstanding.3935403170
Directory	/workspace/11.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/11.uart_tl_errors.631519841
Short name	T1122
Test name
Test status
Simulation time	57778866 ps
CPU time	1.03 seconds
Started	Feb 18 12:37:39 PM PST 24
Finished	Feb 18 12:37:47 PM PST 24
Peak memory	199288 kb
Host	smart-5cd75210-2d46-44cc-81ac-a21cfc6cdfe2
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631519841 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_errors.631519841
Directory	/workspace/11.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.3558283514
Short name	T1174
Test name
Test status
Simulation time	56788523 ps
CPU time	1.41 seconds
Started	Feb 18 12:37:43 PM PST 24
Finished	Feb 18 12:37:51 PM PST 24
Peak memory	200180 kb
Host	smart-1acbce9a-3625-4c65-9b5e-8301a8f7710a
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558283514 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_csr_mem_rw_with_rand_reset.3558283514
Directory	/workspace/12.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/12.uart_csr_rw.1548889969
Short name	T67
Test name
Test status
Simulation time	27672446 ps
CPU time	0.69 seconds
Started	Feb 18 12:37:43 PM PST 24
Finished	Feb 18 12:37:50 PM PST 24
Peak memory	195316 kb
Host	smart-ede0b591-7e75-4451-b5dc-4f6bc9cb7fdf
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548889969 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_csr_rw.1548889969
Directory	/workspace/12.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/12.uart_intr_test.3794663838
Short name	T1189
Test name
Test status
Simulation time	54156671 ps
CPU time	0.61 seconds
Started	Feb 18 12:37:43 PM PST 24
Finished	Feb 18 12:37:50 PM PST 24
Peak memory	185156 kb
Host	smart-d12ab905-3e6a-4295-acf2-a41d5ff4645c
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794663838 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_intr_test.3794663838
Directory	/workspace/12.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.3990993455
Short name	T1142
Test name
Test status
Simulation time	33736978 ps
CPU time	0.76 seconds
Started	Feb 18 12:37:43 PM PST 24
Finished	Feb 18 12:37:50 PM PST 24
Peak memory	196920 kb
Host	smart-1b4c035c-4a6d-483f-a64f-91195eeb71df
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990993455 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_same_cs r_outstanding.3990993455
Directory	/workspace/12.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/12.uart_tl_errors.176205800
Short name	T1219
Test name
Test status
Simulation time	40238875 ps
CPU time	1.96 seconds
Started	Feb 18 12:37:42 PM PST 24
Finished	Feb 18 12:37:50 PM PST 24
Peak memory	199988 kb
Host	smart-0e358c23-3fb6-4ef3-8be9-50d365e79bc9
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176205800 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_errors.176205800
Directory	/workspace/12.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/12.uart_tl_intg_err.2254410771
Short name	T1250
Test name
Test status
Simulation time	71378426 ps
CPU time	1 seconds
Started	Feb 18 12:37:41 PM PST 24
Finished	Feb 18 12:37:48 PM PST 24
Peak memory	199080 kb
Host	smart-60bf7057-21db-4e43-bf90-e284f7b60bdc
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254410771 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_intg_err.2254410771
Directory	/workspace/12.uart_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.1864203994
Short name	T1144
Test name
Test status
Simulation time	528142843 ps
CPU time	2.23 seconds
Started	Feb 18 12:37:48 PM PST 24
Finished	Feb 18 12:37:56 PM PST 24
Peak memory	199988 kb
Host	smart-da722720-459e-4e84-96d2-58316993a7f7
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864203994 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_csr_mem_rw_with_rand_reset.1864203994
Directory	/workspace/13.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/13.uart_csr_rw.2458843445
Short name	T75
Test name
Test status
Simulation time	11301228 ps
CPU time	0.59 seconds
Started	Feb 18 12:37:49 PM PST 24
Finished	Feb 18 12:37:55 PM PST 24
Peak memory	195424 kb
Host	smart-444ca6a2-9799-4a75-b69a-044e1278020d
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458843445 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_csr_rw.2458843445
Directory	/workspace/13.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/13.uart_intr_test.4218973400
Short name	T1135
Test name
Test status
Simulation time	97159928 ps
CPU time	0.58 seconds
Started	Feb 18 12:37:50 PM PST 24
Finished	Feb 18 12:37:58 PM PST 24
Peak memory	185228 kb
Host	smart-56b4bf96-c0e2-42bb-881c-1bd90f4e6b55
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218973400 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_intr_test.4218973400
Directory	/workspace/13.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.4219168619
Short name	T1149
Test name
Test status
Simulation time	15550336 ps
CPU time	0.6 seconds
Started	Feb 18 12:37:58 PM PST 24
Finished	Feb 18 12:38:06 PM PST 24
Peak memory	195492 kb
Host	smart-1736eb1f-0b91-496e-bc5d-bdc21cfce141
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219168619 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_same_cs r_outstanding.4219168619
Directory	/workspace/13.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/13.uart_tl_errors.49010237
Short name	T1143
Test name
Test status
Simulation time	645233577 ps
CPU time	1.26 seconds
Started	Feb 18 12:37:44 PM PST 24
Finished	Feb 18 12:37:50 PM PST 24
Peak memory	200136 kb
Host	smart-06ecaa8b-6e1f-4dc5-89bd-01f5d422776a
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49010237 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_errors.49010237
Directory	/workspace/13.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/13.uart_tl_intg_err.2028231821
Short name	T385
Test name
Test status
Simulation time	53741096 ps
CPU time	1.03 seconds
Started	Feb 18 12:37:40 PM PST 24
Finished	Feb 18 12:37:47 PM PST 24
Peak memory	198824 kb
Host	smart-b41bcfca-3c82-4616-b7e4-8541087f460d
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028231821 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_intg_err.2028231821
Directory	/workspace/13.uart_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.69677874
Short name	T1179
Test name
Test status
Simulation time	37583346 ps
CPU time	0.98 seconds
Started	Feb 18 12:37:50 PM PST 24
Finished	Feb 18 12:37:59 PM PST 24
Peak memory	199964 kb
Host	smart-6f579c52-0b01-46b3-b983-415513f9a5b4
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69677874 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 14.uart_csr_mem_rw_with_rand_reset.69677874
Directory	/workspace/14.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/14.uart_csr_rw.1390139043
Short name	T73
Test name
Test status
Simulation time	27506717 ps
CPU time	0.58 seconds
Started	Feb 18 12:37:49 PM PST 24
Finished	Feb 18 12:37:56 PM PST 24
Peak memory	195432 kb
Host	smart-6ac4b090-c214-4bfa-9b66-2fa7656b7ade
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390139043 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_csr_rw.1390139043
Directory	/workspace/14.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/14.uart_intr_test.2353848045
Short name	T1176
Test name
Test status
Simulation time	13172615 ps
CPU time	0.58 seconds
Started	Feb 18 12:37:58 PM PST 24
Finished	Feb 18 12:38:06 PM PST 24
Peak memory	185028 kb
Host	smart-dda92be4-11f3-415c-8e60-3abdac32cb30
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353848045 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_intr_test.2353848045
Directory	/workspace/14.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.3573884291
Short name	T1256
Test name
Test status
Simulation time	41007411 ps
CPU time	0.65 seconds
Started	Feb 18 12:37:52 PM PST 24
Finished	Feb 18 12:38:01 PM PST 24
Peak memory	195764 kb
Host	smart-09349267-e8e4-43d7-a71b-477097dae6c6
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573884291 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_same_cs r_outstanding.3573884291
Directory	/workspace/14.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/14.uart_tl_errors.3877708885
Short name	T1157
Test name
Test status
Simulation time	26029500 ps
CPU time	1.48 seconds
Started	Feb 18 12:37:48 PM PST 24
Finished	Feb 18 12:37:55 PM PST 24
Peak memory	200188 kb
Host	smart-565f6ac4-aed8-4018-8801-94249deb66c3
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877708885 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_errors.3877708885
Directory	/workspace/14.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/14.uart_tl_intg_err.599316843
Short name	T83
Test name
Test status
Simulation time	340814916 ps
CPU time	1.03 seconds
Started	Feb 18 12:37:48 PM PST 24
Finished	Feb 18 12:37:54 PM PST 24
Peak memory	198996 kb
Host	smart-e1632747-b0b3-4f09-b150-8115d5d8fe7b
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599316843 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_intg_err.599316843
Directory	/workspace/14.uart_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.4219247486
Short name	T1181
Test name
Test status
Simulation time	18800813 ps
CPU time	0.96 seconds
Started	Feb 18 12:37:48 PM PST 24
Finished	Feb 18 12:37:55 PM PST 24
Peak memory	200000 kb
Host	smart-f0cbf7c5-6c90-48ba-83a7-3d4f045cf14a
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219247486 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_csr_mem_rw_with_rand_reset.4219247486
Directory	/workspace/15.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/15.uart_csr_rw.2876980110
Short name	T1184
Test name
Test status
Simulation time	45365223 ps
CPU time	0.62 seconds
Started	Feb 18 12:37:49 PM PST 24
Finished	Feb 18 12:37:55 PM PST 24
Peak memory	195344 kb
Host	smart-8e164961-cee5-43d3-9d72-6e776a81f2b3
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876980110 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_csr_rw.2876980110
Directory	/workspace/15.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/15.uart_intr_test.633330451
Short name	T1239
Test name
Test status
Simulation time	17743419 ps
CPU time	0.59 seconds
Started	Feb 18 12:37:47 PM PST 24
Finished	Feb 18 12:37:53 PM PST 24
Peak memory	194420 kb
Host	smart-fa9aee55-9c1d-4df8-87d9-62a8dd703cec
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633330451 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_intr_test.633330451
Directory	/workspace/15.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.4248223165
Short name	T1222
Test name
Test status
Simulation time	18361190 ps
CPU time	0.8 seconds
Started	Feb 18 12:37:53 PM PST 24
Finished	Feb 18 12:38:02 PM PST 24
Peak memory	197140 kb
Host	smart-32ef43e8-f863-48b6-91ce-fb8bdeb25a6d
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248223165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_same_cs r_outstanding.4248223165
Directory	/workspace/15.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/15.uart_tl_errors.265451392
Short name	T1171
Test name
Test status
Simulation time	213599510 ps
CPU time	1.36 seconds
Started	Feb 18 12:37:55 PM PST 24
Finished	Feb 18 12:38:04 PM PST 24
Peak memory	200224 kb
Host	smart-b7f1a868-18c2-468f-9c67-f16b04a69d39
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265451392 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_errors.265451392
Directory	/workspace/15.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/15.uart_tl_intg_err.2259682060
Short name	T81
Test name
Test status
Simulation time	134446143 ps
CPU time	1.22 seconds
Started	Feb 18 12:37:55 PM PST 24
Finished	Feb 18 12:38:04 PM PST 24
Peak memory	199328 kb
Host	smart-219c0ee7-9e5b-435a-9697-79ae2b4324c1
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259682060 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_intg_err.2259682060
Directory	/workspace/15.uart_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.3001305590
Short name	T1191
Test name
Test status
Simulation time	212397652 ps
CPU time	1.48 seconds
Started	Feb 18 12:37:52 PM PST 24
Finished	Feb 18 12:38:02 PM PST 24
Peak memory	200160 kb
Host	smart-ed0a45e4-6a71-4741-b121-70420f99808e
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001305590 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_csr_mem_rw_with_rand_reset.3001305590
Directory	/workspace/16.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/16.uart_csr_rw.3961145576
Short name	T1139
Test name
Test status
Simulation time	46121135 ps
CPU time	0.6 seconds
Started	Feb 18 12:37:52 PM PST 24
Finished	Feb 18 12:38:00 PM PST 24
Peak memory	195436 kb
Host	smart-6b75265c-748c-480f-9fef-2a41b7d3497a
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961145576 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_csr_rw.3961145576
Directory	/workspace/16.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/16.uart_intr_test.2377055168
Short name	T1241
Test name
Test status
Simulation time	13658450 ps
CPU time	0.6 seconds
Started	Feb 18 12:37:48 PM PST 24
Finished	Feb 18 12:37:54 PM PST 24
Peak memory	194344 kb
Host	smart-b56cd2f4-c53e-40f6-aa80-0b90dee39cd9
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377055168 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_intr_test.2377055168
Directory	/workspace/16.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.3470341646
Short name	T1258
Test name
Test status
Simulation time	105070262 ps
CPU time	0.74 seconds
Started	Feb 18 12:37:50 PM PST 24
Finished	Feb 18 12:37:59 PM PST 24
Peak memory	196864 kb
Host	smart-db6bba2d-45ab-4da2-9be7-1aeaab327d8a
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470341646 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_same_cs r_outstanding.3470341646
Directory	/workspace/16.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/16.uart_tl_errors.2315496406
Short name	T1188
Test name
Test status
Simulation time	73544175 ps
CPU time	1.1 seconds
Started	Feb 18 12:37:48 PM PST 24
Finished	Feb 18 12:37:54 PM PST 24
Peak memory	200052 kb
Host	smart-cf3f2a00-3582-4609-8bab-5ec4c1d018e0
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315496406 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_errors.2315496406
Directory	/workspace/16.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/16.uart_tl_intg_err.3652722689
Short name	T78
Test name
Test status
Simulation time	98187772 ps
CPU time	1.33 seconds
Started	Feb 18 12:37:50 PM PST 24
Finished	Feb 18 12:37:59 PM PST 24
Peak memory	199156 kb
Host	smart-6b7aab80-fb84-41ae-b288-986a1bff3f95
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652722689 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_intg_err.3652722689
Directory	/workspace/16.uart_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.2878952209
Short name	T1133
Test name
Test status
Simulation time	36689895 ps
CPU time	1.08 seconds
Started	Feb 18 12:37:45 PM PST 24
Finished	Feb 18 12:37:52 PM PST 24
Peak memory	199896 kb
Host	smart-5ff5c311-0808-4fa6-9b3a-133a24220645
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878952209 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_csr_mem_rw_with_rand_reset.2878952209
Directory	/workspace/17.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/17.uart_csr_rw.549604646
Short name	T1162
Test name
Test status
Simulation time	10921519 ps
CPU time	0.59 seconds
Started	Feb 18 12:37:49 PM PST 24
Finished	Feb 18 12:37:55 PM PST 24
Peak memory	195412 kb
Host	smart-b16ddfa9-9739-48ec-9708-54016ff1e882
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549604646 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_csr_rw.549604646
Directory	/workspace/17.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/17.uart_intr_test.456544401
Short name	T1123
Test name
Test status
Simulation time	20306540 ps
CPU time	0.56 seconds
Started	Feb 18 12:37:58 PM PST 24
Finished	Feb 18 12:38:06 PM PST 24
Peak memory	185056 kb
Host	smart-6cb56f86-2e7d-4349-ad14-39c79c0b38ab
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456544401 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_intr_test.456544401
Directory	/workspace/17.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.1909867007
Short name	T1158
Test name
Test status
Simulation time	23678761 ps
CPU time	0.71 seconds
Started	Feb 18 12:37:48 PM PST 24
Finished	Feb 18 12:37:54 PM PST 24
Peak memory	196016 kb
Host	smart-95aa10e1-c3c1-44f8-86ed-3e0a56d0a3dd
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909867007 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_same_cs r_outstanding.1909867007
Directory	/workspace/17.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/17.uart_tl_errors.240840688
Short name	T1146
Test name
Test status
Simulation time	339925952 ps
CPU time	1.82 seconds
Started	Feb 18 12:37:48 PM PST 24
Finished	Feb 18 12:37:56 PM PST 24
Peak memory	200060 kb
Host	smart-8991a22b-d197-4f8e-931f-33e34a49c07d
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240840688 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_errors.240840688
Directory	/workspace/17.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/17.uart_tl_intg_err.1676218589
Short name	T82
Test name
Test status
Simulation time	736939049 ps
CPU time	0.98 seconds
Started	Feb 18 12:37:47 PM PST 24
Finished	Feb 18 12:37:53 PM PST 24
Peak memory	199004 kb
Host	smart-7abeae4b-89ec-46a2-9994-11508c740476
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676218589 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_intg_err.1676218589
Directory	/workspace/17.uart_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.800645662
Short name	T1170
Test name
Test status
Simulation time	125437285 ps
CPU time	2.07 seconds
Started	Feb 18 12:37:58 PM PST 24
Finished	Feb 18 12:38:08 PM PST 24
Peak memory	200188 kb
Host	smart-9fdda91a-0bc3-4c75-8083-247f0b4625bc
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800645662 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_csr_mem_rw_with_rand_reset.800645662
Directory	/workspace/18.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/18.uart_csr_rw.4257637455
Short name	T71
Test name
Test status
Simulation time	21009853 ps
CPU time	0.65 seconds
Started	Feb 18 12:37:50 PM PST 24
Finished	Feb 18 12:37:58 PM PST 24
Peak memory	195424 kb
Host	smart-6d4d224f-64a8-4401-9e69-04c83fdf6eb3
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257637455 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_csr_rw.4257637455
Directory	/workspace/18.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/18.uart_intr_test.3001943822
Short name	T1199
Test name
Test status
Simulation time	21803349 ps
CPU time	0.6 seconds
Started	Feb 18 12:37:46 PM PST 24
Finished	Feb 18 12:37:52 PM PST 24
Peak memory	185164 kb
Host	smart-7208e7c8-34e2-42e4-91e2-93c5515da3b1
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001943822 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_intr_test.3001943822
Directory	/workspace/18.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.2434401182
Short name	T1200
Test name
Test status
Simulation time	69518601 ps
CPU time	0.78 seconds
Started	Feb 18 12:37:50 PM PST 24
Finished	Feb 18 12:37:58 PM PST 24
Peak memory	196988 kb
Host	smart-dd3ddca0-2864-4013-bdfd-ffdc76da299d
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434401182 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_same_cs r_outstanding.2434401182
Directory	/workspace/18.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/18.uart_tl_errors.2147729832
Short name	T1193
Test name
Test status
Simulation time	314059574 ps
CPU time	1.92 seconds
Started	Feb 18 12:37:49 PM PST 24
Finished	Feb 18 12:37:58 PM PST 24
Peak memory	200176 kb
Host	smart-4fe97d7f-b57d-4123-a414-06bcfa98a32f
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147729832 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_errors.2147729832
Directory	/workspace/18.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/18.uart_tl_intg_err.2561870685
Short name	T1220
Test name
Test status
Simulation time	51891046 ps
CPU time	0.99 seconds
Started	Feb 18 12:37:58 PM PST 24
Finished	Feb 18 12:38:07 PM PST 24
Peak memory	198936 kb
Host	smart-dfb9acbb-9565-42a1-9f17-4c0ded927a77
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561870685 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_intg_err.2561870685
Directory	/workspace/18.uart_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.1558623089
Short name	T1246
Test name
Test status
Simulation time	446417677 ps
CPU time	2.33 seconds
Started	Feb 18 12:37:50 PM PST 24
Finished	Feb 18 12:37:59 PM PST 24
Peak memory	200184 kb
Host	smart-915bbd6d-b971-45bd-b610-bb0d24d8b35f
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558623089 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_csr_mem_rw_with_rand_reset.1558623089
Directory	/workspace/19.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/19.uart_csr_rw.2374090655
Short name	T63
Test name
Test status
Simulation time	130483183 ps
CPU time	0.6 seconds
Started	Feb 18 12:37:50 PM PST 24
Finished	Feb 18 12:37:58 PM PST 24
Peak memory	195412 kb
Host	smart-817679b2-365c-4f44-81c0-bf1882fb0709
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374090655 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_csr_rw.2374090655
Directory	/workspace/19.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/19.uart_intr_test.1513797432
Short name	T1132
Test name
Test status
Simulation time	13739504 ps
CPU time	0.59 seconds
Started	Feb 18 12:37:50 PM PST 24
Finished	Feb 18 12:37:57 PM PST 24
Peak memory	185176 kb
Host	smart-069bbe5b-a3bf-4520-8ce8-20cdf904c759
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513797432 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_intr_test.1513797432
Directory	/workspace/19.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.3048464658
Short name	T76
Test name
Test status
Simulation time	33469788 ps
CPU time	0.75 seconds
Started	Feb 18 12:37:48 PM PST 24
Finished	Feb 18 12:37:54 PM PST 24
Peak memory	196036 kb
Host	smart-9ce7eabc-63b7-44e1-b4e8-8114b6dbb623
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048464658 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_same_cs r_outstanding.3048464658
Directory	/workspace/19.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/19.uart_tl_errors.2268027480
Short name	T1163
Test name
Test status
Simulation time	285278745 ps
CPU time	1.74 seconds
Started	Feb 18 12:37:48 PM PST 24
Finished	Feb 18 12:37:55 PM PST 24
Peak memory	200184 kb
Host	smart-263107a0-c980-43ea-a2fb-fee6db3882e7
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268027480 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_errors.2268027480
Directory	/workspace/19.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/19.uart_tl_intg_err.507353054
Short name	T1210
Test name
Test status
Simulation time	53427280 ps
CPU time	0.97 seconds
Started	Feb 18 12:37:50 PM PST 24
Finished	Feb 18 12:37:59 PM PST 24
Peak memory	198912 kb
Host	smart-c38ba3d5-3985-4a14-86f1-14c9c422855d
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507353054 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_intg_err.507353054
Directory	/workspace/19.uart_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/2.uart_csr_aliasing.3927972905
Short name	T1213
Test name
Test status
Simulation time	60843558 ps
CPU time	0.67 seconds
Started	Feb 18 12:37:30 PM PST 24
Finished	Feb 18 12:37:39 PM PST 24
Peak memory	194740 kb
Host	smart-5b360f87-9b18-45b6-835e-76bd49dbb7fe
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927972905 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_aliasing.3927972905
Directory	/workspace/2.uart_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.4038015212
Short name	T1225
Test name
Test status
Simulation time	347339259 ps
CPU time	1.5 seconds
Started	Feb 18 12:37:32 PM PST 24
Finished	Feb 18 12:37:42 PM PST 24
Peak memory	197788 kb
Host	smart-c06c3562-cbda-45cd-b6ce-0e15347a051c
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038015212 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_bit_bash.4038015212
Directory	/workspace/2.uart_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.3245882136
Short name	T1177
Test name
Test status
Simulation time	21755633 ps
CPU time	0.62 seconds
Started	Feb 18 12:37:27 PM PST 24
Finished	Feb 18 12:37:33 PM PST 24
Peak memory	195392 kb
Host	smart-ad5c50d4-b422-404e-a050-efe63be0d593
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245882136 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_hw_reset.3245882136
Directory	/workspace/2.uart_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.3238482356
Short name	T1248
Test name
Test status
Simulation time	65572645 ps
CPU time	1.43 seconds
Started	Feb 18 12:37:30 PM PST 24
Finished	Feb 18 12:37:40 PM PST 24
Peak memory	200196 kb
Host	smart-9329c0b1-98d0-4868-ad95-2af1dec80d08
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238482356 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_mem_rw_with_rand_reset.3238482356
Directory	/workspace/2.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.uart_csr_rw.892634298
Short name	T65
Test name
Test status
Simulation time	54014605 ps
CPU time	0.64 seconds
Started	Feb 18 12:37:29 PM PST 24
Finished	Feb 18 12:37:37 PM PST 24
Peak memory	195416 kb
Host	smart-ef65e1de-84e9-428c-bca4-30d003213049
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892634298 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_rw.892634298
Directory	/workspace/2.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/2.uart_intr_test.1503514549
Short name	T1125
Test name
Test status
Simulation time	30321670 ps
CPU time	0.57 seconds
Started	Feb 18 12:37:30 PM PST 24
Finished	Feb 18 12:37:39 PM PST 24
Peak memory	185216 kb
Host	smart-2764be22-36d9-4d8f-9152-cb36456fa43f
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503514549 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_intr_test.1503514549
Directory	/workspace/2.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.1461220050
Short name	T1216
Test name
Test status
Simulation time	62137536 ps
CPU time	0.69 seconds
Started	Feb 18 12:37:32 PM PST 24
Finished	Feb 18 12:37:41 PM PST 24
Peak memory	196692 kb
Host	smart-7cacc74b-b996-4c97-a3f0-e2c77058a347
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461220050 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_same_csr _outstanding.1461220050
Directory	/workspace/2.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/2.uart_tl_errors.2346721146
Short name	T1259
Test name
Test status
Simulation time	42400800 ps
CPU time	1.19 seconds
Started	Feb 18 12:37:28 PM PST 24
Finished	Feb 18 12:37:35 PM PST 24
Peak memory	200188 kb
Host	smart-31ed7e17-745b-4dff-9959-38ec368fccc7
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346721146 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_errors.2346721146
Directory	/workspace/2.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/2.uart_tl_intg_err.634063473
Short name	T80
Test name
Test status
Simulation time	74595130 ps
CPU time	0.92 seconds
Started	Feb 18 12:37:31 PM PST 24
Finished	Feb 18 12:37:41 PM PST 24
Peak memory	198852 kb
Host	smart-7f4f60dd-d2d6-47d9-924c-36a4ffa27e45
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634063473 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_intg_err.634063473
Directory	/workspace/2.uart_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/20.uart_intr_test.493050547
Short name	T1228
Test name
Test status
Simulation time	48167030 ps
CPU time	0.57 seconds
Started	Feb 18 12:37:51 PM PST 24
Finished	Feb 18 12:38:00 PM PST 24
Peak memory	185180 kb
Host	smart-71250da0-5b87-4a0d-8e20-8312e9d0776f
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493050547 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.uart_intr_test.493050547
Directory	/workspace/20.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/21.uart_intr_test.2702471965
Short name	T1205
Test name
Test status
Simulation time	37535606 ps
CPU time	0.58 seconds
Started	Feb 18 12:37:48 PM PST 24
Finished	Feb 18 12:37:55 PM PST 24
Peak memory	194412 kb
Host	smart-d3cf866f-1c1c-4fbe-bea4-ca30df7dbbd6
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702471965 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.uart_intr_test.2702471965
Directory	/workspace/21.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/22.uart_intr_test.3611347426
Short name	T1134
Test name
Test status
Simulation time	36698595 ps
CPU time	0.56 seconds
Started	Feb 18 12:37:52 PM PST 24
Finished	Feb 18 12:38:01 PM PST 24
Peak memory	194400 kb
Host	smart-642245b7-2037-46e0-b086-82fe7db166fd
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611347426 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.uart_intr_test.3611347426
Directory	/workspace/22.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/23.uart_intr_test.2586557348
Short name	T1182
Test name
Test status
Simulation time	92755087 ps
CPU time	0.53 seconds
Started	Feb 18 12:37:46 PM PST 24
Finished	Feb 18 12:37:52 PM PST 24
Peak memory	185156 kb
Host	smart-00ab2ae3-1a0c-45b6-8684-44c8221a1796
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586557348 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.uart_intr_test.2586557348
Directory	/workspace/23.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/24.uart_intr_test.2408607509
Short name	T1217
Test name
Test status
Simulation time	14900294 ps
CPU time	0.61 seconds
Started	Feb 18 12:37:53 PM PST 24
Finished	Feb 18 12:38:02 PM PST 24
Peak memory	194244 kb
Host	smart-026cb332-fa24-44a8-a887-ee0640bd463a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408607509 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.uart_intr_test.2408607509
Directory	/workspace/24.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/25.uart_intr_test.1558043278
Short name	T1195
Test name
Test status
Simulation time	23722936 ps
CPU time	0.57 seconds
Started	Feb 18 12:37:51 PM PST 24
Finished	Feb 18 12:38:00 PM PST 24
Peak memory	185156 kb
Host	smart-ee2c6c82-1ddf-4ba6-aae7-3682113d4031
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558043278 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.uart_intr_test.1558043278
Directory	/workspace/25.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/26.uart_intr_test.1830685867
Short name	T1155
Test name
Test status
Simulation time	60265431 ps
CPU time	0.58 seconds
Started	Feb 18 12:37:53 PM PST 24
Finished	Feb 18 12:38:02 PM PST 24
Peak memory	185052 kb
Host	smart-c0e48248-5961-4c90-af9c-17995a9171fb
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830685867 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.uart_intr_test.1830685867
Directory	/workspace/26.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/27.uart_intr_test.3680088886
Short name	T1197
Test name
Test status
Simulation time	167119981 ps
CPU time	0.58 seconds
Started	Feb 18 12:37:54 PM PST 24
Finished	Feb 18 12:38:02 PM PST 24
Peak memory	185172 kb
Host	smart-4ec2e7bd-9e85-4ebc-83ec-69e9d62fadfd
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680088886 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.uart_intr_test.3680088886
Directory	/workspace/27.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/28.uart_intr_test.1137239303
Short name	T1192
Test name
Test status
Simulation time	13150439 ps
CPU time	0.57 seconds
Started	Feb 18 12:37:54 PM PST 24
Finished	Feb 18 12:38:02 PM PST 24
Peak memory	194292 kb
Host	smart-894ef15c-8073-4565-a938-ee7648c49885
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137239303 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.uart_intr_test.1137239303
Directory	/workspace/28.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/29.uart_intr_test.3782428967
Short name	T1249
Test name
Test status
Simulation time	40841639 ps
CPU time	0.56 seconds
Started	Feb 18 12:37:50 PM PST 24
Finished	Feb 18 12:37:57 PM PST 24
Peak memory	194420 kb
Host	smart-2d1b516a-bba9-484b-9a15-63cfc03ceb89
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782428967 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.uart_intr_test.3782428967
Directory	/workspace/29.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/3.uart_csr_aliasing.3264593470
Short name	T69
Test name
Test status
Simulation time	186557087 ps
CPU time	0.67 seconds
Started	Feb 18 12:37:47 PM PST 24
Finished	Feb 18 12:37:53 PM PST 24
Peak memory	195416 kb
Host	smart-3bc5d6c6-a5c8-4906-b75b-8f975d51e332
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264593470 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_aliasing.3264593470
Directory	/workspace/3.uart_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.4235192047
Short name	T1240
Test name
Test status
Simulation time	57366206 ps
CPU time	2.24 seconds
Started	Feb 18 12:37:42 PM PST 24
Finished	Feb 18 12:37:50 PM PST 24
Peak memory	197512 kb
Host	smart-a43e6d00-0b96-4f7f-8325-a2007654cd95
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235192047 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_bit_bash.4235192047
Directory	/workspace/3.uart_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.2608233699
Short name	T68
Test name
Test status
Simulation time	63072467 ps
CPU time	0.62 seconds
Started	Feb 18 12:37:39 PM PST 24
Finished	Feb 18 12:37:46 PM PST 24
Peak memory	195476 kb
Host	smart-cad8ae51-60d5-4399-8121-a43b047eef2c
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608233699 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_hw_reset.2608233699
Directory	/workspace/3.uart_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.270314141
Short name	T1137
Test name
Test status
Simulation time	180248585 ps
CPU time	1.93 seconds
Started	Feb 18 12:37:33 PM PST 24
Finished	Feb 18 12:37:44 PM PST 24
Peak memory	200216 kb
Host	smart-34bddbe6-e3aa-4782-866f-265e367c169a
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270314141 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_mem_rw_with_rand_reset.270314141
Directory	/workspace/3.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.uart_intr_test.1141485620
Short name	T1255
Test name
Test status
Simulation time	37733425 ps
CPU time	0.59 seconds
Started	Feb 18 12:37:32 PM PST 24
Finished	Feb 18 12:37:41 PM PST 24
Peak memory	185156 kb
Host	smart-78e166eb-ddee-480c-861f-79969f2ce576
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141485620 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_intr_test.1141485620
Directory	/workspace/3.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.2840971883
Short name	T1198
Test name
Test status
Simulation time	19253940 ps
CPU time	0.65 seconds
Started	Feb 18 12:37:33 PM PST 24
Finished	Feb 18 12:37:43 PM PST 24
Peak memory	195552 kb
Host	smart-628a093c-fcae-4d2f-bc5f-644bdd899221
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840971883 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_same_csr _outstanding.2840971883
Directory	/workspace/3.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/3.uart_tl_errors.1310427852
Short name	T1160
Test name
Test status
Simulation time	155722887 ps
CPU time	2 seconds
Started	Feb 18 12:37:32 PM PST 24
Finished	Feb 18 12:37:42 PM PST 24
Peak memory	200192 kb
Host	smart-add415a1-2574-4eb8-9bfd-dc5ba5bab0b0
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310427852 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_errors.1310427852
Directory	/workspace/3.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/3.uart_tl_intg_err.164089630
Short name	T1253
Test name
Test status
Simulation time	48665524 ps
CPU time	0.94 seconds
Started	Feb 18 12:37:34 PM PST 24
Finished	Feb 18 12:37:43 PM PST 24
Peak memory	198572 kb
Host	smart-b5f5c203-2fb9-4147-a7ff-7b754061d5f9
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164089630 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_intg_err.164089630
Directory	/workspace/3.uart_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/30.uart_intr_test.4171259678
Short name	T1257
Test name
Test status
Simulation time	48555393 ps
CPU time	0.58 seconds
Started	Feb 18 12:37:55 PM PST 24
Finished	Feb 18 12:38:03 PM PST 24
Peak memory	194376 kb
Host	smart-715ed5d9-15fc-4a0f-bcd8-001bcd53f2ce
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171259678 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.uart_intr_test.4171259678
Directory	/workspace/30.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/31.uart_intr_test.20840607
Short name	T1260
Test name
Test status
Simulation time	17223275 ps
CPU time	0.58 seconds
Started	Feb 18 12:37:52 PM PST 24
Finished	Feb 18 12:38:00 PM PST 24
Peak memory	185152 kb
Host	smart-876d78ab-1c5c-4f40-a966-aefc4ada9296
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20840607 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.uart_intr_test.20840607
Directory	/workspace/31.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/32.uart_intr_test.4247500191
Short name	T1227
Test name
Test status
Simulation time	17727884 ps
CPU time	0.6 seconds
Started	Feb 18 12:37:52 PM PST 24
Finished	Feb 18 12:38:01 PM PST 24
Peak memory	185156 kb
Host	smart-8bd8bd06-c2c6-4317-ac13-d7f357cea669
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247500191 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.uart_intr_test.4247500191
Directory	/workspace/32.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/33.uart_intr_test.2240514996
Short name	T1237
Test name
Test status
Simulation time	15700908 ps
CPU time	0.57 seconds
Started	Feb 18 12:37:52 PM PST 24
Finished	Feb 18 12:38:01 PM PST 24
Peak memory	185140 kb
Host	smart-99a0dd09-4df6-4cc3-aff0-e787152b11e4
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240514996 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.uart_intr_test.2240514996
Directory	/workspace/33.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/34.uart_intr_test.1094548143
Short name	T1233
Test name
Test status
Simulation time	46829118 ps
CPU time	0.59 seconds
Started	Feb 18 12:37:55 PM PST 24
Finished	Feb 18 12:38:04 PM PST 24
Peak memory	185092 kb
Host	smart-6696f9c7-0988-42e6-bdf7-90a67f9e9066
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094548143 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.uart_intr_test.1094548143
Directory	/workspace/34.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/35.uart_intr_test.4103924056
Short name	T1185
Test name
Test status
Simulation time	14147568 ps
CPU time	0.57 seconds
Started	Feb 18 12:37:54 PM PST 24
Finished	Feb 18 12:38:03 PM PST 24
Peak memory	185156 kb
Host	smart-2f69592d-6005-43b3-90ba-0b55ad0b0756
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103924056 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.uart_intr_test.4103924056
Directory	/workspace/35.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/36.uart_intr_test.3836854815
Short name	T1165
Test name
Test status
Simulation time	17028770 ps
CPU time	0.59 seconds
Started	Feb 18 12:37:54 PM PST 24
Finished	Feb 18 12:38:03 PM PST 24
Peak memory	185176 kb
Host	smart-88bbb141-a24f-4311-ab80-d8793523a3e0
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836854815 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.uart_intr_test.3836854815
Directory	/workspace/36.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/37.uart_intr_test.4082444254
Short name	T1153
Test name
Test status
Simulation time	45656214 ps
CPU time	0.54 seconds
Started	Feb 18 12:37:54 PM PST 24
Finished	Feb 18 12:38:02 PM PST 24
Peak memory	185168 kb
Host	smart-2c7cb137-0523-4018-b49e-603e3d5c3505
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082444254 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.uart_intr_test.4082444254
Directory	/workspace/37.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/38.uart_intr_test.3832265096
Short name	T1140
Test name
Test status
Simulation time	11137337 ps
CPU time	0.56 seconds
Started	Feb 18 12:37:53 PM PST 24
Finished	Feb 18 12:38:02 PM PST 24
Peak memory	194404 kb
Host	smart-4a84f263-afd6-41dc-9888-c10b28b52e7b
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832265096 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.uart_intr_test.3832265096
Directory	/workspace/38.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/39.uart_intr_test.1284218625
Short name	T1168
Test name
Test status
Simulation time	43643793 ps
CPU time	0.57 seconds
Started	Feb 18 12:37:56 PM PST 24
Finished	Feb 18 12:38:05 PM PST 24
Peak memory	185176 kb
Host	smart-fc6d581f-b953-46f9-b260-4def08481161
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284218625 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.uart_intr_test.1284218625
Directory	/workspace/39.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/4.uart_csr_aliasing.58871324
Short name	T1131
Test name
Test status
Simulation time	43840843 ps
CPU time	0.65 seconds
Started	Feb 18 12:37:35 PM PST 24
Finished	Feb 18 12:37:44 PM PST 24
Peak memory	194624 kb
Host	smart-aa364fa8-814d-40b5-8c41-961ede71fa6c
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58871324 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_aliasing.58871324
Directory	/workspace/4.uart_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.719279280
Short name	T1166
Test name
Test status
Simulation time	344158201 ps
CPU time	2.46 seconds
Started	Feb 18 12:37:39 PM PST 24
Finished	Feb 18 12:37:48 PM PST 24
Peak memory	197700 kb
Host	smart-903ec817-7f73-47ae-a172-a7d5c85e6100
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719279280 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_bit_bash.719279280
Directory	/workspace/4.uart_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.471978338
Short name	T1229
Test name
Test status
Simulation time	1051070510 ps
CPU time	1.31 seconds
Started	Feb 18 12:37:37 PM PST 24
Finished	Feb 18 12:37:45 PM PST 24
Peak memory	195432 kb
Host	smart-eff4b01b-8265-40da-ac87-069514cee2a8
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471978338 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_hw_reset.471978338
Directory	/workspace/4.uart_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.2460003445
Short name	T1234
Test name
Test status
Simulation time	43275176 ps
CPU time	2.04 seconds
Started	Feb 18 12:37:35 PM PST 24
Finished	Feb 18 12:37:45 PM PST 24
Peak memory	200180 kb
Host	smart-73bb666b-5df7-4df8-ad39-96e6c8dc2df4
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460003445 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_mem_rw_with_rand_reset.2460003445
Directory	/workspace/4.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.uart_csr_rw.1939439294
Short name	T1209
Test name
Test status
Simulation time	111570866 ps
CPU time	0.58 seconds
Started	Feb 18 12:37:34 PM PST 24
Finished	Feb 18 12:37:43 PM PST 24
Peak memory	195416 kb
Host	smart-1a9a87e2-f11b-4781-93c4-9406c3469b6a
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939439294 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_rw.1939439294
Directory	/workspace/4.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/4.uart_intr_test.3312199244
Short name	T1173
Test name
Test status
Simulation time	16840410 ps
CPU time	0.56 seconds
Started	Feb 18 12:37:32 PM PST 24
Finished	Feb 18 12:37:41 PM PST 24
Peak memory	184980 kb
Host	smart-72c775a9-050b-4ba6-a593-985c6ebcc658
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312199244 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_intr_test.3312199244
Directory	/workspace/4.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.95241097
Short name	T1204
Test name
Test status
Simulation time	34393477 ps
CPU time	0.76 seconds
Started	Feb 18 12:37:42 PM PST 24
Finished	Feb 18 12:37:48 PM PST 24
Peak memory	196992 kb
Host	smart-d750ea88-f487-44e1-9f0d-e8668a885c2a
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95241097 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_same_csr_o utstanding.95241097
Directory	/workspace/4.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/4.uart_tl_errors.1903782326
Short name	T1145
Test name
Test status
Simulation time	194050745 ps
CPU time	1.37 seconds
Started	Feb 18 12:37:34 PM PST 24
Finished	Feb 18 12:37:44 PM PST 24
Peak memory	200120 kb
Host	smart-bd7eb664-de1c-4229-adc1-63493035b416
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903782326 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_errors.1903782326
Directory	/workspace/4.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/4.uart_tl_intg_err.1961384961
Short name	T1154
Test name
Test status
Simulation time	57252988 ps
CPU time	0.97 seconds
Started	Feb 18 12:37:39 PM PST 24
Finished	Feb 18 12:37:46 PM PST 24
Peak memory	199080 kb
Host	smart-032170d7-cd18-45d1-99e6-d79edf1de7a3
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961384961 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_intg_err.1961384961
Directory	/workspace/4.uart_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/40.uart_intr_test.2529486221
Short name	T1252
Test name
Test status
Simulation time	11076405 ps
CPU time	0.6 seconds
Started	Feb 18 12:37:58 PM PST 24
Finished	Feb 18 12:38:06 PM PST 24
Peak memory	185196 kb
Host	smart-bec32ddb-016a-4413-97a7-470ce87e3b63
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529486221 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.uart_intr_test.2529486221
Directory	/workspace/40.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/41.uart_intr_test.1090672082
Short name	T1202
Test name
Test status
Simulation time	17124707 ps
CPU time	0.58 seconds
Started	Feb 18 12:37:55 PM PST 24
Finished	Feb 18 12:38:04 PM PST 24
Peak memory	194416 kb
Host	smart-fb2a4850-3d4f-4181-8da1-c15030cae1fe
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090672082 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.uart_intr_test.1090672082
Directory	/workspace/41.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/42.uart_intr_test.3082030167
Short name	T1226
Test name
Test status
Simulation time	16322147 ps
CPU time	0.65 seconds
Started	Feb 18 12:37:57 PM PST 24
Finished	Feb 18 12:38:05 PM PST 24
Peak memory	185220 kb
Host	smart-c795e153-f88c-49f4-b414-bc9f0ea975f4
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082030167 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.uart_intr_test.3082030167
Directory	/workspace/42.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/43.uart_intr_test.2899751626
Short name	T1148
Test name
Test status
Simulation time	13392859 ps
CPU time	0.58 seconds
Started	Feb 18 12:37:56 PM PST 24
Finished	Feb 18 12:38:04 PM PST 24
Peak memory	185176 kb
Host	smart-fb0545cd-2de1-4edf-bf2b-2836805fc946
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899751626 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.uart_intr_test.2899751626
Directory	/workspace/43.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/44.uart_intr_test.298477687
Short name	T1138
Test name
Test status
Simulation time	13696110 ps
CPU time	0.59 seconds
Started	Feb 18 12:37:56 PM PST 24
Finished	Feb 18 12:38:04 PM PST 24
Peak memory	194452 kb
Host	smart-b07c5d7e-e6c5-4efc-b234-3443297a3937
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298477687 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.uart_intr_test.298477687
Directory	/workspace/44.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/45.uart_intr_test.4193771187
Short name	T1186
Test name
Test status
Simulation time	15574647 ps
CPU time	0.55 seconds
Started	Feb 18 12:37:55 PM PST 24
Finished	Feb 18 12:38:03 PM PST 24
Peak memory	185252 kb
Host	smart-7e21d6fc-8d23-4381-aac4-f367b6b8f77a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193771187 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.uart_intr_test.4193771187
Directory	/workspace/45.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/46.uart_intr_test.1225369390
Short name	T1178
Test name
Test status
Simulation time	12046598 ps
CPU time	0.57 seconds
Started	Feb 18 12:37:55 PM PST 24
Finished	Feb 18 12:38:04 PM PST 24
Peak memory	194416 kb
Host	smart-5b3625e6-4127-40e0-9681-a782ab40b6ff
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225369390 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.uart_intr_test.1225369390
Directory	/workspace/46.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/47.uart_intr_test.4168771091
Short name	T1126
Test name
Test status
Simulation time	21331159 ps
CPU time	0.57 seconds
Started	Feb 18 12:37:57 PM PST 24
Finished	Feb 18 12:38:05 PM PST 24
Peak memory	185176 kb
Host	smart-015d57fa-edf3-4068-aaf9-6eebf605bb66
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168771091 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.uart_intr_test.4168771091
Directory	/workspace/47.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/48.uart_intr_test.3752496524
Short name	T1203
Test name
Test status
Simulation time	35278324 ps
CPU time	0.62 seconds
Started	Feb 18 12:37:59 PM PST 24
Finished	Feb 18 12:38:07 PM PST 24
Peak memory	194420 kb
Host	smart-de6e1fcb-86d8-4225-a7c4-663b82548b81
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752496524 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.uart_intr_test.3752496524
Directory	/workspace/48.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/49.uart_intr_test.1310679929
Short name	T1156
Test name
Test status
Simulation time	14574053 ps
CPU time	0.59 seconds
Started	Feb 18 12:37:56 PM PST 24
Finished	Feb 18 12:38:04 PM PST 24
Peak memory	185156 kb
Host	smart-bd403abf-caa6-4d64-8896-d8630ad0d5ff
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310679929 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.uart_intr_test.1310679929
Directory	/workspace/49.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.1165796738
Short name	T1221
Test name
Test status
Simulation time	177274358 ps
CPU time	1.73 seconds
Started	Feb 18 12:37:47 PM PST 24
Finished	Feb 18 12:37:54 PM PST 24
Peak memory	200192 kb
Host	smart-6594c56e-1237-4a4a-9e9d-ada8252be360
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165796738 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_csr_mem_rw_with_rand_reset.1165796738
Directory	/workspace/5.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/5.uart_csr_rw.3778977671
Short name	T1164
Test name
Test status
Simulation time	17679269 ps
CPU time	0.61 seconds
Started	Feb 18 12:37:32 PM PST 24
Finished	Feb 18 12:37:41 PM PST 24
Peak memory	195444 kb
Host	smart-c66265f1-bea7-4bec-8a81-f4162741ff23
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778977671 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_csr_rw.3778977671
Directory	/workspace/5.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/5.uart_intr_test.2976017092
Short name	T1238
Test name
Test status
Simulation time	14096049 ps
CPU time	0.62 seconds
Started	Feb 18 12:37:34 PM PST 24
Finished	Feb 18 12:37:43 PM PST 24
Peak memory	194372 kb
Host	smart-105a0ab5-fb9c-414f-9acc-bb1475857a6c
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976017092 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_intr_test.2976017092
Directory	/workspace/5.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.764858702
Short name	T1167
Test name
Test status
Simulation time	121933740 ps
CPU time	0.73 seconds
Started	Feb 18 12:37:47 PM PST 24
Finished	Feb 18 12:37:53 PM PST 24
Peak memory	196900 kb
Host	smart-fdb6c16a-5896-4038-9ca4-e0b081a6645e
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764858702 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_same_csr_ outstanding.764858702
Directory	/workspace/5.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/5.uart_tl_errors.1784004939
Short name	T1242
Test name
Test status
Simulation time	305572591 ps
CPU time	1.8 seconds
Started	Feb 18 12:37:35 PM PST 24
Finished	Feb 18 12:37:45 PM PST 24
Peak memory	200152 kb
Host	smart-ecbfd63f-e7cd-4e8a-823e-40b2ce749329
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784004939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_errors.1784004939
Directory	/workspace/5.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.4250306447
Short name	T1244
Test name
Test status
Simulation time	128265373 ps
CPU time	1.84 seconds
Started	Feb 18 12:37:47 PM PST 24
Finished	Feb 18 12:37:54 PM PST 24
Peak memory	200212 kb
Host	smart-0d8bed98-0e8a-495e-a25d-47e8c1129a37
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250306447 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_csr_mem_rw_with_rand_reset.4250306447
Directory	/workspace/6.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/6.uart_csr_rw.1960937134
Short name	T64
Test name
Test status
Simulation time	65885590 ps
CPU time	0.59 seconds
Started	Feb 18 12:37:35 PM PST 24
Finished	Feb 18 12:37:44 PM PST 24
Peak memory	195392 kb
Host	smart-75a27377-053b-490d-aa19-4a1b9bcb7722
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960937134 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_csr_rw.1960937134
Directory	/workspace/6.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/6.uart_intr_test.1472875324
Short name	T1169
Test name
Test status
Simulation time	13863606 ps
CPU time	0.59 seconds
Started	Feb 18 12:37:39 PM PST 24
Finished	Feb 18 12:37:46 PM PST 24
Peak memory	185172 kb
Host	smart-868462a1-288d-47a3-92f4-86a5bd964eeb
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472875324 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_intr_test.1472875324
Directory	/workspace/6.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.3631366751
Short name	T1243
Test name
Test status
Simulation time	14227467 ps
CPU time	0.69 seconds
Started	Feb 18 12:37:32 PM PST 24
Finished	Feb 18 12:37:41 PM PST 24
Peak memory	196940 kb
Host	smart-9b90c950-35d8-45f2-bf91-c3d0047fef4e
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631366751 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_same_csr _outstanding.3631366751
Directory	/workspace/6.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/6.uart_tl_errors.738589167
Short name	T1207
Test name
Test status
Simulation time	92161075 ps
CPU time	1.91 seconds
Started	Feb 18 12:37:33 PM PST 24
Finished	Feb 18 12:37:43 PM PST 24
Peak memory	200216 kb
Host	smart-1d30757a-33f8-4663-8938-906ce76d9f5d
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738589167 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_errors.738589167
Directory	/workspace/6.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/6.uart_tl_intg_err.3229603149
Short name	T85
Test name
Test status
Simulation time	54127895 ps
CPU time	0.95 seconds
Started	Feb 18 12:37:42 PM PST 24
Finished	Feb 18 12:37:49 PM PST 24
Peak memory	198872 kb
Host	smart-91866b3a-5846-4750-ab58-ea90ad03b623
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229603149 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_intg_err.3229603149
Directory	/workspace/6.uart_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.3532160064
Short name	T1130
Test name
Test status
Simulation time	124286026 ps
CPU time	1.43 seconds
Started	Feb 18 12:37:39 PM PST 24
Finished	Feb 18 12:37:47 PM PST 24
Peak memory	200228 kb
Host	smart-aeec53b9-fab9-4586-9b6b-ef9b45c5bff0
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532160064 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_csr_mem_rw_with_rand_reset.3532160064
Directory	/workspace/7.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/7.uart_csr_rw.4267985516
Short name	T74
Test name
Test status
Simulation time	46663632 ps
CPU time	0.64 seconds
Started	Feb 18 12:37:34 PM PST 24
Finished	Feb 18 12:37:43 PM PST 24
Peak memory	195420 kb
Host	smart-8c1d7e22-0efb-49d1-b979-e6c28008343d
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267985516 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_csr_rw.4267985516
Directory	/workspace/7.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/7.uart_intr_test.1930717707
Short name	T1215
Test name
Test status
Simulation time	15440204 ps
CPU time	0.58 seconds
Started	Feb 18 12:37:37 PM PST 24
Finished	Feb 18 12:37:45 PM PST 24
Peak memory	185164 kb
Host	smart-a7fa09ee-3d87-4825-973f-533ed25cc26e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930717707 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_intr_test.1930717707
Directory	/workspace/7.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.1729193283
Short name	T1194
Test name
Test status
Simulation time	290466757 ps
CPU time	0.78 seconds
Started	Feb 18 12:37:35 PM PST 24
Finished	Feb 18 12:37:44 PM PST 24
Peak memory	196996 kb
Host	smart-140a7231-a52e-404b-ab83-2b522663fc7b
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729193283 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_same_csr _outstanding.1729193283
Directory	/workspace/7.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/7.uart_tl_errors.363538266
Short name	T1161
Test name
Test status
Simulation time	1437762168 ps
CPU time	2.47 seconds
Started	Feb 18 12:37:47 PM PST 24
Finished	Feb 18 12:37:55 PM PST 24
Peak memory	200192 kb
Host	smart-be028132-8651-40f3-ad97-419726b1e0be
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363538266 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_errors.363538266
Directory	/workspace/7.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/7.uart_tl_intg_err.3524158310
Short name	T1190
Test name
Test status
Simulation time	83558019 ps
CPU time	1.32 seconds
Started	Feb 18 12:37:34 PM PST 24
Finished	Feb 18 12:37:44 PM PST 24
Peak memory	199232 kb
Host	smart-2e36c2a4-76aa-41fa-b385-4cc0f0cef1b8
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524158310 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_intg_err.3524158310
Directory	/workspace/7.uart_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.2333899563
Short name	T1201
Test name
Test status
Simulation time	433879840 ps
CPU time	2.12 seconds
Started	Feb 18 12:37:42 PM PST 24
Finished	Feb 18 12:37:50 PM PST 24
Peak memory	200168 kb
Host	smart-c4f51ec1-87c9-4600-aaca-6e3d78d6a942
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333899563 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_csr_mem_rw_with_rand_reset.2333899563
Directory	/workspace/8.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/8.uart_csr_rw.3876976095
Short name	T70
Test name
Test status
Simulation time	66790007 ps
CPU time	0.63 seconds
Started	Feb 18 12:37:41 PM PST 24
Finished	Feb 18 12:37:47 PM PST 24
Peak memory	195416 kb
Host	smart-baf2d65b-51bb-456d-83a2-10a7862d7320
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876976095 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_csr_rw.3876976095
Directory	/workspace/8.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/8.uart_intr_test.1038867464
Short name	T1230
Test name
Test status
Simulation time	13593529 ps
CPU time	0.56 seconds
Started	Feb 18 12:37:42 PM PST 24
Finished	Feb 18 12:37:49 PM PST 24
Peak memory	185148 kb
Host	smart-54ca8201-a7d2-43c5-a7f8-73f2163c04d3
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038867464 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_intr_test.1038867464
Directory	/workspace/8.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.1389466959
Short name	T1172
Test name
Test status
Simulation time	20819938 ps
CPU time	0.64 seconds
Started	Feb 18 12:37:41 PM PST 24
Finished	Feb 18 12:37:47 PM PST 24
Peak memory	194480 kb
Host	smart-554ac472-1bd4-4c37-9c2f-96a7a930df58
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389466959 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_same_csr _outstanding.1389466959
Directory	/workspace/8.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/8.uart_tl_errors.4036474271
Short name	T1129
Test name
Test status
Simulation time	28145346 ps
CPU time	1.39 seconds
Started	Feb 18 12:37:39 PM PST 24
Finished	Feb 18 12:37:47 PM PST 24
Peak memory	200228 kb
Host	smart-0e9c5e84-4fe0-4605-8c3b-11ff374dab8f
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036474271 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_errors.4036474271
Directory	/workspace/8.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/8.uart_tl_intg_err.3289001871
Short name	T1235
Test name
Test status
Simulation time	251129839 ps
CPU time	1.36 seconds
Started	Feb 18 12:37:38 PM PST 24
Finished	Feb 18 12:37:46 PM PST 24
Peak memory	199384 kb
Host	smart-585c22cb-062d-4e78-8193-d14074becbfe
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289001871 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_intg_err.3289001871
Directory	/workspace/8.uart_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.293810665
Short name	T1127
Test name
Test status
Simulation time	50051652 ps
CPU time	1.39 seconds
Started	Feb 18 12:37:43 PM PST 24
Finished	Feb 18 12:37:50 PM PST 24
Peak memory	200028 kb
Host	smart-e60f62b1-dd80-46e1-ae09-f2c3fe6c1abb
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293810665 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_csr_mem_rw_with_rand_reset.293810665
Directory	/workspace/9.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/9.uart_csr_rw.2975758735
Short name	T72
Test name
Test status
Simulation time	13859931 ps
CPU time	0.64 seconds
Started	Feb 18 12:37:38 PM PST 24
Finished	Feb 18 12:37:45 PM PST 24
Peak memory	195408 kb
Host	smart-37199823-f386-42e2-a304-9fcf5a965dcb
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975758735 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_csr_rw.2975758735
Directory	/workspace/9.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/9.uart_intr_test.2733592302
Short name	T1206
Test name
Test status
Simulation time	15888597 ps
CPU time	0.57 seconds
Started	Feb 18 12:37:38 PM PST 24
Finished	Feb 18 12:37:45 PM PST 24
Peak memory	185160 kb
Host	smart-aab94a90-6b9a-44ce-9db0-d6c4609b8b8e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733592302 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_intr_test.2733592302
Directory	/workspace/9.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.2689365248
Short name	T1218
Test name
Test status
Simulation time	208385668 ps
CPU time	0.69 seconds
Started	Feb 18 12:37:39 PM PST 24
Finished	Feb 18 12:37:46 PM PST 24
Peak memory	195852 kb
Host	smart-edc64ef9-0284-444c-8c23-9ef375a24113
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689365248 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_same_csr _outstanding.2689365248
Directory	/workspace/9.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/9.uart_tl_errors.1495776218
Short name	T1223
Test name
Test status
Simulation time	85684391 ps
CPU time	1.62 seconds
Started	Feb 18 12:37:39 PM PST 24
Finished	Feb 18 12:37:47 PM PST 24
Peak memory	200124 kb
Host	smart-6aabd6b8-aa13-425d-ba3d-0a444c71ce3e
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495776218 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_errors.1495776218
Directory	/workspace/9.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/9.uart_tl_intg_err.2928472871
Short name	T1212
Test name
Test status
Simulation time	90945109 ps
CPU time	1.35 seconds
Started	Feb 18 12:37:40 PM PST 24
Finished	Feb 18 12:37:47 PM PST 24
Peak memory	199236 kb
Host	smart-061f6dd4-3f65-4767-9e26-c1bfb15b39c1
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928472871 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_intg_err.2928472871
Directory	/workspace/9.uart_tl_intg_err/latest

Test location	/workspace/coverage/default/0.uart_alert_test.944581566
Short name	T886
Test name
Test status
Simulation time	53592647 ps
CPU time	0.59 seconds
Started	Feb 18 02:03:32 PM PST 24
Finished	Feb 18 02:03:35 PM PST 24
Peak memory	195536 kb
Host	smart-d1010d2c-abdf-429b-acc8-81cee027746c
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944581566 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_alert_test.944581566
Directory	/workspace/0.uart_alert_test/latest

Test location	/workspace/coverage/default/0.uart_fifo_full.1157644196
Short name	T372
Test name
Test status
Simulation time	169657684957 ps
CPU time	47.97 seconds
Started	Feb 18 02:03:26 PM PST 24
Finished	Feb 18 02:04:17 PM PST 24
Peak memory	200076 kb
Host	smart-1aac53bc-5e05-4696-8235-d206903dc254
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1157644196 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_full.1157644196
Directory	/workspace/0.uart_fifo_full/latest

Test location	/workspace/coverage/default/0.uart_fifo_overflow.1190434864
Short name	T45
Test name
Test status
Simulation time	83337548696 ps
CPU time	126.25 seconds
Started	Feb 18 02:03:27 PM PST 24
Finished	Feb 18 02:05:35 PM PST 24
Peak memory	200080 kb
Host	smart-2e18734e-f0ab-4a23-aa48-f22c1c4ab694
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1190434864 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_overflow.1190434864
Directory	/workspace/0.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/0.uart_fifo_reset.1557769832
Short name	T1088
Test name
Test status
Simulation time	43674319572 ps
CPU time	60.71 seconds
Started	Feb 18 02:03:24 PM PST 24
Finished	Feb 18 02:04:28 PM PST 24
Peak memory	200128 kb
Host	smart-263a725e-6f15-41b6-b5db-6868a40323e5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1557769832 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_reset.1557769832
Directory	/workspace/0.uart_fifo_reset/latest

Test location	/workspace/coverage/default/0.uart_intr.658690163
Short name	T1024
Test name
Test status
Simulation time	589897386850 ps
CPU time	824.76 seconds
Started	Feb 18 02:03:27 PM PST 24
Finished	Feb 18 02:17:14 PM PST 24
Peak memory	199800 kb
Host	smart-6620db76-6206-43bb-8e81-97a9ec9e023c
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658690163 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_intr.658690163
Directory	/workspace/0.uart_intr/latest

Test location	/workspace/coverage/default/0.uart_long_xfer_wo_dly.3232126474
Short name	T462
Test name
Test status
Simulation time	152256003356 ps
CPU time	848.99 seconds
Started	Feb 18 02:03:29 PM PST 24
Finished	Feb 18 02:17:39 PM PST 24
Peak memory	200104 kb
Host	smart-ac7af169-db2e-4d03-8405-6422b1654026
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3232126474 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_long_xfer_wo_dly.3232126474
Directory	/workspace/0.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/0.uart_loopback.459474368
Short name	T1081
Test name
Test status
Simulation time	6573382267 ps
CPU time	4.95 seconds
Started	Feb 18 02:03:25 PM PST 24
Finished	Feb 18 02:03:33 PM PST 24
Peak memory	198272 kb
Host	smart-870438f9-3d86-4a99-af83-8aecf15e8602
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=459474368 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_loopback.459474368
Directory	/workspace/0.uart_loopback/latest

Test location	/workspace/coverage/default/0.uart_noise_filter.2976298934
Short name	T780
Test name
Test status
Simulation time	54560824447 ps
CPU time	6.56 seconds
Started	Feb 18 02:03:23 PM PST 24
Finished	Feb 18 02:03:31 PM PST 24
Peak memory	193636 kb
Host	smart-b8bf6153-4f80-4d79-b82c-3c50ee35ae2c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2976298934 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_noise_filter.2976298934
Directory	/workspace/0.uart_noise_filter/latest

Test location	/workspace/coverage/default/0.uart_perf.1223577437
Short name	T999
Test name
Test status
Simulation time	19481393474 ps
CPU time	956.68 seconds
Started	Feb 18 02:03:26 PM PST 24
Finished	Feb 18 02:19:26 PM PST 24
Peak memory	200012 kb
Host	smart-008ae83d-029e-4318-b18d-4a90937cb1a2
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1223577437 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_perf.1223577437
Directory	/workspace/0.uart_perf/latest

Test location	/workspace/coverage/default/0.uart_rx_oversample.703400098
Short name	T596
Test name
Test status
Simulation time	889406927 ps
CPU time	3.77 seconds
Started	Feb 18 02:03:27 PM PST 24
Finished	Feb 18 02:03:33 PM PST 24
Peak memory	197676 kb
Host	smart-57a35008-4970-45cd-9b38-e2ae86fda136
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=703400098 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_oversample.703400098
Directory	/workspace/0.uart_rx_oversample/latest

Test location	/workspace/coverage/default/0.uart_rx_parity_err.2263136119
Short name	T686
Test name
Test status
Simulation time	72215484350 ps
CPU time	64.21 seconds
Started	Feb 18 02:03:25 PM PST 24
Finished	Feb 18 02:04:33 PM PST 24
Peak memory	200040 kb
Host	smart-a7b6c5d2-8f44-48ab-b74a-e8ec54280491
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2263136119 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_parity_err.2263136119
Directory	/workspace/0.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/0.uart_rx_start_bit_filter.2748850082
Short name	T1075
Test name
Test status
Simulation time	1507579723 ps
CPU time	3.22 seconds
Started	Feb 18 02:03:26 PM PST 24
Finished	Feb 18 02:03:32 PM PST 24
Peak memory	195324 kb
Host	smart-6915a9ab-a1db-474a-ac47-5d7c563672b9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2748850082 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_start_bit_filter.2748850082
Directory	/workspace/0.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/0.uart_sec_cm.3319829986
Short name	T34
Test name
Test status
Simulation time	39773646 ps
CPU time	0.77 seconds
Started	Feb 18 02:03:34 PM PST 24
Finished	Feb 18 02:03:43 PM PST 24
Peak memory	217068 kb
Host	smart-b91a4c67-2c87-4f0d-a158-440ec8bb428a
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319829986 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_sec_cm.3319829986
Directory	/workspace/0.uart_sec_cm/latest

Test location	/workspace/coverage/default/0.uart_smoke.1124010073
Short name	T881
Test name
Test status
Simulation time	952267214 ps
CPU time	2.86 seconds
Started	Feb 18 02:03:22 PM PST 24
Finished	Feb 18 02:03:27 PM PST 24
Peak memory	197832 kb
Host	smart-d24dff36-5fc4-48dc-a88f-6661391e12e6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1124010073 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_smoke.1124010073
Directory	/workspace/0.uart_smoke/latest

Test location	/workspace/coverage/default/0.uart_tx_ovrd.2733798523
Short name	T422
Test name
Test status
Simulation time	6417074195 ps
CPU time	11.99 seconds
Started	Feb 18 02:03:25 PM PST 24
Finished	Feb 18 02:03:40 PM PST 24
Peak memory	200004 kb
Host	smart-1ab26f5f-a365-43a4-ae1b-bcabc034f397
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2733798523 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_ovrd.2733798523
Directory	/workspace/0.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/0.uart_tx_rx.3035702431
Short name	T136
Test name
Test status
Simulation time	77856076638 ps
CPU time	36.55 seconds
Started	Feb 18 02:03:31 PM PST 24
Finished	Feb 18 02:04:09 PM PST 24
Peak memory	200052 kb
Host	smart-93f3618e-37c2-4b74-8ebe-04e788fe8233
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3035702431 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_rx.3035702431
Directory	/workspace/0.uart_tx_rx/latest

Test location	/workspace/coverage/default/1.uart_fifo_overflow.1714485243
Short name	T936
Test name
Test status
Simulation time	53819073729 ps
CPU time	39.87 seconds
Started	Feb 18 02:03:31 PM PST 24
Finished	Feb 18 02:04:12 PM PST 24
Peak memory	200052 kb
Host	smart-8bbbca57-aa28-4485-b4b2-6881b7d294b3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1714485243 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_overflow.1714485243
Directory	/workspace/1.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/1.uart_fifo_reset.2354846602
Short name	T949
Test name
Test status
Simulation time	22859656218 ps
CPU time	17.82 seconds
Started	Feb 18 02:03:32 PM PST 24
Finished	Feb 18 02:03:52 PM PST 24
Peak memory	200104 kb
Host	smart-ca4b8e8f-6be5-4a89-a46f-66a6baaca7df
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2354846602 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_reset.2354846602
Directory	/workspace/1.uart_fifo_reset/latest

Test location	/workspace/coverage/default/1.uart_intr.3830089828
Short name	T679
Test name
Test status
Simulation time	276683978946 ps
CPU time	467.78 seconds
Started	Feb 18 02:03:39 PM PST 24
Finished	Feb 18 02:11:39 PM PST 24
Peak memory	199964 kb
Host	smart-df1bed6c-221c-4332-a5fb-f4f620436e03
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830089828 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_intr.3830089828
Directory	/workspace/1.uart_intr/latest

Test location	/workspace/coverage/default/1.uart_long_xfer_wo_dly.2717215068
Short name	T1019
Test name
Test status
Simulation time	67715220475 ps
CPU time	263.12 seconds
Started	Feb 18 02:03:39 PM PST 24
Finished	Feb 18 02:08:15 PM PST 24
Peak memory	199916 kb
Host	smart-7b07c786-f1f7-475f-a6fc-fe82bda4130d
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2717215068 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_long_xfer_wo_dly.2717215068
Directory	/workspace/1.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/1.uart_loopback.300364676
Short name	T955
Test name
Test status
Simulation time	619424162 ps
CPU time	1.06 seconds
Started	Feb 18 02:03:32 PM PST 24
Finished	Feb 18 02:03:37 PM PST 24
Peak memory	195476 kb
Host	smart-c8af01d2-301f-417f-998e-d48ea8c12292
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=300364676 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_loopback.300364676
Directory	/workspace/1.uart_loopback/latest

Test location	/workspace/coverage/default/1.uart_noise_filter.1120372282
Short name	T788
Test name
Test status
Simulation time	209345757994 ps
CPU time	49.72 seconds
Started	Feb 18 02:03:32 PM PST 24
Finished	Feb 18 02:04:26 PM PST 24
Peak memory	199892 kb
Host	smart-e73b537f-e7aa-44f3-b32f-607de23e06e8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1120372282 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_noise_filter.1120372282
Directory	/workspace/1.uart_noise_filter/latest

Test location	/workspace/coverage/default/1.uart_perf.1028947981
Short name	T741
Test name
Test status
Simulation time	14690807522 ps
CPU time	178.84 seconds
Started	Feb 18 02:03:35 PM PST 24
Finished	Feb 18 02:06:43 PM PST 24
Peak memory	200012 kb
Host	smart-a7140fd4-5880-4356-9c93-254f43ccbd6d
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1028947981 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_perf.1028947981
Directory	/workspace/1.uart_perf/latest

Test location	/workspace/coverage/default/1.uart_rx_oversample.1615351590
Short name	T436
Test name
Test status
Simulation time	451640102 ps
CPU time	1.63 seconds
Started	Feb 18 02:03:25 PM PST 24
Finished	Feb 18 02:03:30 PM PST 24
Peak memory	197760 kb
Host	smart-61986bff-9186-4bac-9829-a9e7cebf106f
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1615351590 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_oversample.1615351590
Directory	/workspace/1.uart_rx_oversample/latest

Test location	/workspace/coverage/default/1.uart_rx_parity_err.2743116512
Short name	T817
Test name
Test status
Simulation time	51393662823 ps
CPU time	86.91 seconds
Started	Feb 18 02:03:41 PM PST 24
Finished	Feb 18 02:05:22 PM PST 24
Peak memory	200028 kb
Host	smart-e427ec74-7dca-4454-96c3-d3f2066ed138
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2743116512 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_parity_err.2743116512
Directory	/workspace/1.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/1.uart_rx_start_bit_filter.4019557089
Short name	T1094
Test name
Test status
Simulation time	40243842816 ps
CPU time	60.82 seconds
Started	Feb 18 02:03:31 PM PST 24
Finished	Feb 18 02:04:33 PM PST 24
Peak memory	195492 kb
Host	smart-4698f6f9-1e0c-45f2-9e11-eb38cbc5c355
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4019557089 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_start_bit_filter.4019557089
Directory	/workspace/1.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/1.uart_smoke.1955131508
Short name	T473
Test name
Test status
Simulation time	621010355 ps
CPU time	3.63 seconds
Started	Feb 18 02:03:28 PM PST 24
Finished	Feb 18 02:03:33 PM PST 24
Peak memory	198916 kb
Host	smart-857d84fe-eb61-4d3f-be9e-06f517cd0af9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1955131508 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_smoke.1955131508
Directory	/workspace/1.uart_smoke/latest

Test location	/workspace/coverage/default/1.uart_stress_all.381153928
Short name	T942
Test name
Test status
Simulation time	282125280355 ps
CPU time	831.26 seconds
Started	Feb 18 02:03:33 PM PST 24
Finished	Feb 18 02:17:32 PM PST 24
Peak memory	200056 kb
Host	smart-3d798543-f313-4c01-8e1c-fda696906262
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381153928 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_stress_all.381153928
Directory	/workspace/1.uart_stress_all/latest

Test location	/workspace/coverage/default/1.uart_stress_all_with_rand_reset.2309189870
Short name	T599
Test name
Test status
Simulation time	27889403994 ps
CPU time	211.97 seconds
Started	Feb 18 02:03:31 PM PST 24
Finished	Feb 18 02:07:04 PM PST 24
Peak memory	216108 kb
Host	smart-875c7d39-617f-4735-a7b5-4d5f89b9744f
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309189870 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 1.uart_stress_all_with_rand_reset.2309189870
Directory	/workspace/1.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/1.uart_tx_ovrd.2191010120
Short name	T1044
Test name
Test status
Simulation time	703116618 ps
CPU time	3.03 seconds
Started	Feb 18 02:03:33 PM PST 24
Finished	Feb 18 02:03:44 PM PST 24
Peak memory	199380 kb
Host	smart-a3e4195c-ff6a-4088-a45d-37134b0d2e7c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2191010120 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_ovrd.2191010120
Directory	/workspace/1.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/1.uart_tx_rx.2816928512
Short name	T618
Test name
Test status
Simulation time	73354837575 ps
CPU time	87.6 seconds
Started	Feb 18 02:03:34 PM PST 24
Finished	Feb 18 02:05:10 PM PST 24
Peak memory	200028 kb
Host	smart-333a5fdf-ee2a-4de5-95fb-13f7feb47d45
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2816928512 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_rx.2816928512
Directory	/workspace/1.uart_tx_rx/latest

Test location	/workspace/coverage/default/10.uart_alert_test.1031291839
Short name	T727
Test name
Test status
Simulation time	45812363 ps
CPU time	0.57 seconds
Started	Feb 18 02:04:04 PM PST 24
Finished	Feb 18 02:04:09 PM PST 24
Peak memory	195392 kb
Host	smart-3872a78f-b7e3-43c4-95ba-72b5e069f92e
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031291839 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_alert_test.1031291839
Directory	/workspace/10.uart_alert_test/latest

Test location	/workspace/coverage/default/10.uart_fifo_full.1213460622
Short name	T355
Test name
Test status
Simulation time	201208619896 ps
CPU time	192.13 seconds
Started	Feb 18 02:03:58 PM PST 24
Finished	Feb 18 02:07:17 PM PST 24
Peak memory	200040 kb
Host	smart-1ed11fe5-b9e3-46dc-b99c-85626d72f0e3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1213460622 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_full.1213460622
Directory	/workspace/10.uart_fifo_full/latest

Test location	/workspace/coverage/default/10.uart_fifo_overflow.632754844
Short name	T366
Test name
Test status
Simulation time	40330307092 ps
CPU time	67.28 seconds
Started	Feb 18 02:03:56 PM PST 24
Finished	Feb 18 02:05:09 PM PST 24
Peak memory	199688 kb
Host	smart-1396a39d-ec33-4711-969f-d48fe52d1ead
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=632754844 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_overflow.632754844
Directory	/workspace/10.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/10.uart_fifo_reset.2538292821
Short name	T110
Test name
Test status
Simulation time	126487253229 ps
CPU time	228.86 seconds
Started	Feb 18 02:03:56 PM PST 24
Finished	Feb 18 02:07:51 PM PST 24
Peak memory	200120 kb
Host	smart-d191da22-590d-4262-940c-3502cfa625d1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2538292821 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_reset.2538292821
Directory	/workspace/10.uart_fifo_reset/latest

Test location	/workspace/coverage/default/10.uart_intr.2675879277
Short name	T822
Test name
Test status
Simulation time	249106416033 ps
CPU time	91.88 seconds
Started	Feb 18 02:03:56 PM PST 24
Finished	Feb 18 02:05:34 PM PST 24
Peak memory	196696 kb
Host	smart-2209ea47-9a4c-4562-a350-08535935844d
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675879277 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_intr.2675879277
Directory	/workspace/10.uart_intr/latest

Test location	/workspace/coverage/default/10.uart_long_xfer_wo_dly.3392748156
Short name	T557
Test name
Test status
Simulation time	51404420518 ps
CPU time	248.22 seconds
Started	Feb 18 02:03:56 PM PST 24
Finished	Feb 18 02:08:11 PM PST 24
Peak memory	200032 kb
Host	smart-5f765b4a-d0f2-41ea-955f-eabac7f92f53
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3392748156 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_long_xfer_wo_dly.3392748156
Directory	/workspace/10.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/10.uart_loopback.1427378041
Short name	T517
Test name
Test status
Simulation time	8571221806 ps
CPU time	18.33 seconds
Started	Feb 18 02:04:01 PM PST 24
Finished	Feb 18 02:04:25 PM PST 24
Peak memory	198628 kb
Host	smart-7debd022-c215-4699-9b66-ed454d08129c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1427378041 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_loopback.1427378041
Directory	/workspace/10.uart_loopback/latest

Test location	/workspace/coverage/default/10.uart_noise_filter.689334544
Short name	T726
Test name
Test status
Simulation time	184612163502 ps
CPU time	72.47 seconds
Started	Feb 18 02:03:55 PM PST 24
Finished	Feb 18 02:05:14 PM PST 24
Peak memory	200228 kb
Host	smart-36024ced-7fc6-46a6-89c7-02f91f67cda8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=689334544 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_noise_filter.689334544
Directory	/workspace/10.uart_noise_filter/latest

Test location	/workspace/coverage/default/10.uart_perf.1773698623
Short name	T573
Test name
Test status
Simulation time	6723652870 ps
CPU time	298.06 seconds
Started	Feb 18 02:03:58 PM PST 24
Finished	Feb 18 02:09:02 PM PST 24
Peak memory	200092 kb
Host	smart-1b03cec3-2381-4b72-a721-fcad91d86858
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1773698623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_perf.1773698623
Directory	/workspace/10.uart_perf/latest

Test location	/workspace/coverage/default/10.uart_rx_oversample.4253332862
Short name	T683
Test name
Test status
Simulation time	2178991185 ps
CPU time	22.72 seconds
Started	Feb 18 02:03:57 PM PST 24
Finished	Feb 18 02:04:26 PM PST 24
Peak memory	197796 kb
Host	smart-26ec83d8-ec03-47ce-8e6f-059774124632
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4253332862 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_oversample.4253332862
Directory	/workspace/10.uart_rx_oversample/latest

Test location	/workspace/coverage/default/10.uart_rx_parity_err.4104659105
Short name	T605
Test name
Test status
Simulation time	100112199347 ps
CPU time	134.63 seconds
Started	Feb 18 02:03:59 PM PST 24
Finished	Feb 18 02:06:20 PM PST 24
Peak memory	199948 kb
Host	smart-7cdf69ef-b287-4c02-8600-658e4bcaf8f8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4104659105 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_parity_err.4104659105
Directory	/workspace/10.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/10.uart_rx_start_bit_filter.387415721
Short name	T681
Test name
Test status
Simulation time	2832275489 ps
CPU time	4.96 seconds
Started	Feb 18 02:03:58 PM PST 24
Finished	Feb 18 02:04:09 PM PST 24
Peak memory	195516 kb
Host	smart-2372bad9-1f9c-4ded-bb55-e64658deea3c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=387415721 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_start_bit_filter.387415721
Directory	/workspace/10.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/10.uart_smoke.1064580098
Short name	T471
Test name
Test status
Simulation time	544477218 ps
CPU time	2.47 seconds
Started	Feb 18 02:04:01 PM PST 24
Finished	Feb 18 02:04:09 PM PST 24
Peak memory	197868 kb
Host	smart-7428877f-574e-4cf5-8a8a-213a106cf097
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1064580098 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_smoke.1064580098
Directory	/workspace/10.uart_smoke/latest

Test location	/workspace/coverage/default/10.uart_stress_all.3633338919
Short name	T373
Test name
Test status
Simulation time	646804495152 ps
CPU time	842.84 seconds
Started	Feb 18 02:03:56 PM PST 24
Finished	Feb 18 02:18:05 PM PST 24
Peak memory	200032 kb
Host	smart-05b61106-7fc7-407f-8b1c-695c24c3d1b0
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633338919 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_stress_all.3633338919
Directory	/workspace/10.uart_stress_all/latest

Test location	/workspace/coverage/default/10.uart_tx_ovrd.1700254176
Short name	T558
Test name
Test status
Simulation time	6125649245 ps
CPU time	12.54 seconds
Started	Feb 18 02:03:59 PM PST 24
Finished	Feb 18 02:04:17 PM PST 24
Peak memory	199596 kb
Host	smart-2b3d6a93-16b1-419d-9be8-f3a406c7c96c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1700254176 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_ovrd.1700254176
Directory	/workspace/10.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/10.uart_tx_rx.2137263052
Short name	T164
Test name
Test status
Simulation time	15727420799 ps
CPU time	8.57 seconds
Started	Feb 18 02:03:58 PM PST 24
Finished	Feb 18 02:04:13 PM PST 24
Peak memory	200000 kb
Host	smart-56da3086-0510-4af9-a5eb-d506713abea8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2137263052 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_rx.2137263052
Directory	/workspace/10.uart_tx_rx/latest

Test location	/workspace/coverage/default/101.uart_fifo_reset.4139666923
Short name	T810
Test name
Test status
Simulation time	162066281588 ps
CPU time	232.05 seconds
Started	Feb 18 02:07:21 PM PST 24
Finished	Feb 18 02:11:16 PM PST 24
Peak memory	200060 kb
Host	smart-421aafbb-66df-46ad-8bbc-73b1257a8a49
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4139666923 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.uart_fifo_reset.4139666923
Directory	/workspace/101.uart_fifo_reset/latest

Test location	/workspace/coverage/default/102.uart_fifo_reset.1921891349
Short name	T637
Test name
Test status
Simulation time	71566501678 ps
CPU time	106.11 seconds
Started	Feb 18 02:07:20 PM PST 24
Finished	Feb 18 02:09:09 PM PST 24
Peak memory	199956 kb
Host	smart-205f4568-f755-4c48-a510-9eb4d08d4fd8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1921891349 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.uart_fifo_reset.1921891349
Directory	/workspace/102.uart_fifo_reset/latest

Test location	/workspace/coverage/default/105.uart_fifo_reset.3122957400
Short name	T176
Test name
Test status
Simulation time	46919804987 ps
CPU time	17.81 seconds
Started	Feb 18 02:07:22 PM PST 24
Finished	Feb 18 02:07:44 PM PST 24
Peak memory	199640 kb
Host	smart-814b784f-313b-4c3d-81a3-638011ccbef8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3122957400 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.uart_fifo_reset.3122957400
Directory	/workspace/105.uart_fifo_reset/latest

Test location	/workspace/coverage/default/106.uart_fifo_reset.3475545624
Short name	T175
Test name
Test status
Simulation time	8522939853 ps
CPU time	16.4 seconds
Started	Feb 18 02:07:21 PM PST 24
Finished	Feb 18 02:07:42 PM PST 24
Peak memory	199896 kb
Host	smart-a6d6f554-9c57-422d-bb21-ae5c24fcd719
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3475545624 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.uart_fifo_reset.3475545624
Directory	/workspace/106.uart_fifo_reset/latest

Test location	/workspace/coverage/default/107.uart_fifo_reset.1882030201
Short name	T1016
Test name
Test status
Simulation time	13787653335 ps
CPU time	25.12 seconds
Started	Feb 18 02:07:24 PM PST 24
Finished	Feb 18 02:07:51 PM PST 24
Peak memory	199788 kb
Host	smart-92ea21e2-7a7c-49e0-82b0-7c93ea5b0541
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1882030201 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.uart_fifo_reset.1882030201
Directory	/workspace/107.uart_fifo_reset/latest

Test location	/workspace/coverage/default/108.uart_fifo_reset.1915591293
Short name	T292
Test name
Test status
Simulation time	115113610948 ps
CPU time	44.42 seconds
Started	Feb 18 02:07:31 PM PST 24
Finished	Feb 18 02:08:17 PM PST 24
Peak memory	199932 kb
Host	smart-13a19682-a486-4b9d-b209-ac54955dd832
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1915591293 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.uart_fifo_reset.1915591293
Directory	/workspace/108.uart_fifo_reset/latest

Test location	/workspace/coverage/default/109.uart_fifo_reset.3890726946
Short name	T317
Test name
Test status
Simulation time	62483279005 ps
CPU time	71.78 seconds
Started	Feb 18 02:07:32 PM PST 24
Finished	Feb 18 02:08:47 PM PST 24
Peak memory	200008 kb
Host	smart-c6b53d7c-c9c6-4ebe-a4b6-30ae21ea9000
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3890726946 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.uart_fifo_reset.3890726946
Directory	/workspace/109.uart_fifo_reset/latest

Test location	/workspace/coverage/default/11.uart_alert_test.312819508
Short name	T840
Test name
Test status
Simulation time	14506653 ps
CPU time	0.58 seconds
Started	Feb 18 02:04:11 PM PST 24
Finished	Feb 18 02:04:16 PM PST 24
Peak memory	195500 kb
Host	smart-dff24726-a277-42cc-9d9c-dc693e2dbb02
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312819508 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_alert_test.312819508
Directory	/workspace/11.uart_alert_test/latest

Test location	/workspace/coverage/default/11.uart_intr.2234447121
Short name	T938
Test name
Test status
Simulation time	668358130119 ps
CPU time	208.39 seconds
Started	Feb 18 02:04:01 PM PST 24
Finished	Feb 18 02:07:35 PM PST 24
Peak memory	198248 kb
Host	smart-7caec772-9642-4042-b585-d43283a049ed
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234447121 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_intr.2234447121
Directory	/workspace/11.uart_intr/latest

Test location	/workspace/coverage/default/11.uart_long_xfer_wo_dly.3627007501
Short name	T554
Test name
Test status
Simulation time	156884911435 ps
CPU time	284.72 seconds
Started	Feb 18 02:04:03 PM PST 24
Finished	Feb 18 02:08:53 PM PST 24
Peak memory	200020 kb
Host	smart-bf17d598-5afd-4814-8608-ebac377a1a07
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3627007501 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_long_xfer_wo_dly.3627007501
Directory	/workspace/11.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/11.uart_loopback.4156424689
Short name	T481
Test name
Test status
Simulation time	2839044246 ps
CPU time	4.66 seconds
Started	Feb 18 02:04:08 PM PST 24
Finished	Feb 18 02:04:17 PM PST 24
Peak memory	195488 kb
Host	smart-36c39658-275e-44d5-942f-99a2f03a99db
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4156424689 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_loopback.4156424689
Directory	/workspace/11.uart_loopback/latest

Test location	/workspace/coverage/default/11.uart_noise_filter.1884468144
Short name	T848
Test name
Test status
Simulation time	6195829606 ps
CPU time	11.19 seconds
Started	Feb 18 02:04:11 PM PST 24
Finished	Feb 18 02:04:27 PM PST 24
Peak memory	193712 kb
Host	smart-121fdff4-7592-4ca2-a0c3-ba238cf7939b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1884468144 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_noise_filter.1884468144
Directory	/workspace/11.uart_noise_filter/latest

Test location	/workspace/coverage/default/11.uart_perf.1931714876
Short name	T739
Test name
Test status
Simulation time	10131794763 ps
CPU time	307.95 seconds
Started	Feb 18 02:04:17 PM PST 24
Finished	Feb 18 02:09:28 PM PST 24
Peak memory	199928 kb
Host	smart-d9c9884c-3d3b-494f-89d6-971ac2057f2e
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1931714876 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_perf.1931714876
Directory	/workspace/11.uart_perf/latest

Test location	/workspace/coverage/default/11.uart_rx_oversample.2785407488
Short name	T583
Test name
Test status
Simulation time	3679074918 ps
CPU time	7.86 seconds
Started	Feb 18 02:04:17 PM PST 24
Finished	Feb 18 02:04:28 PM PST 24
Peak memory	197776 kb
Host	smart-0d4dd780-90e9-48b9-8c3f-7e2571356200
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2785407488 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_oversample.2785407488
Directory	/workspace/11.uart_rx_oversample/latest

Test location	/workspace/coverage/default/11.uart_rx_parity_err.3607791313
Short name	T1059
Test name
Test status
Simulation time	55624282843 ps
CPU time	43.25 seconds
Started	Feb 18 02:04:10 PM PST 24
Finished	Feb 18 02:04:57 PM PST 24
Peak memory	200052 kb
Host	smart-5906223e-21a4-43c2-a4b8-af48a175ec3f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3607791313 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_parity_err.3607791313
Directory	/workspace/11.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/11.uart_rx_start_bit_filter.37850437
Short name	T415
Test name
Test status
Simulation time	4079454323 ps
CPU time	2.22 seconds
Started	Feb 18 02:04:02 PM PST 24
Finished	Feb 18 02:04:10 PM PST 24
Peak memory	195820 kb
Host	smart-f7eecd22-4a05-41ed-be87-f75352a0361e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=37850437 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_start_bit_filter.37850437
Directory	/workspace/11.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/11.uart_smoke.3792820870
Short name	T829
Test name
Test status
Simulation time	487140634 ps
CPU time	1.24 seconds
Started	Feb 18 02:04:04 PM PST 24
Finished	Feb 18 02:04:10 PM PST 24
Peak memory	198236 kb
Host	smart-235280e2-eaa8-4543-a7d9-19b40d864118
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3792820870 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_smoke.3792820870
Directory	/workspace/11.uart_smoke/latest

Test location	/workspace/coverage/default/11.uart_stress_all.3653749385
Short name	T416
Test name
Test status
Simulation time	233646068255 ps
CPU time	227.85 seconds
Started	Feb 18 02:04:05 PM PST 24
Finished	Feb 18 02:07:57 PM PST 24
Peak memory	216532 kb
Host	smart-b8ef3cf9-7971-4f35-9568-281cbeee5506
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653749385 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_stress_all.3653749385
Directory	/workspace/11.uart_stress_all/latest

Test location	/workspace/coverage/default/11.uart_stress_all_with_rand_reset.2474490549
Short name	T41
Test name
Test status
Simulation time	31382240711 ps
CPU time	365.25 seconds
Started	Feb 18 02:04:02 PM PST 24
Finished	Feb 18 02:10:12 PM PST 24
Peak memory	208364 kb
Host	smart-9e19f9b3-af4e-4fc3-a1b8-ad889b1ed06d
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474490549 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 11.uart_stress_all_with_rand_reset.2474490549
Directory	/workspace/11.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/11.uart_tx_ovrd.3032642042
Short name	T743
Test name
Test status
Simulation time	405422828 ps
CPU time	1.12 seconds
Started	Feb 18 02:03:59 PM PST 24
Finished	Feb 18 02:04:06 PM PST 24
Peak memory	198812 kb
Host	smart-6c299ed3-fc5e-42eb-9f76-8305e6472693
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3032642042 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_ovrd.3032642042
Directory	/workspace/11.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/11.uart_tx_rx.3356705712
Short name	T992
Test name
Test status
Simulation time	45879890516 ps
CPU time	83.99 seconds
Started	Feb 18 02:04:03 PM PST 24
Finished	Feb 18 02:05:32 PM PST 24
Peak memory	200060 kb
Host	smart-3b15107e-cfb1-4b9c-9029-07c8fc01300c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3356705712 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_rx.3356705712
Directory	/workspace/11.uart_tx_rx/latest

Test location	/workspace/coverage/default/110.uart_fifo_reset.4277261787
Short name	T747
Test name
Test status
Simulation time	15716622578 ps
CPU time	24.06 seconds
Started	Feb 18 02:07:34 PM PST 24
Finished	Feb 18 02:08:01 PM PST 24
Peak memory	200036 kb
Host	smart-c7b36bdd-267f-4eaa-8fca-d47b4fc855b7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4277261787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.uart_fifo_reset.4277261787
Directory	/workspace/110.uart_fifo_reset/latest

Test location	/workspace/coverage/default/111.uart_fifo_reset.2072580258
Short name	T153
Test name
Test status
Simulation time	95330924705 ps
CPU time	40.94 seconds
Started	Feb 18 02:07:31 PM PST 24
Finished	Feb 18 02:08:14 PM PST 24
Peak memory	199340 kb
Host	smart-96472127-ebf7-4580-b49a-148cdf0659d4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2072580258 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.uart_fifo_reset.2072580258
Directory	/workspace/111.uart_fifo_reset/latest

Test location	/workspace/coverage/default/112.uart_fifo_reset.825209350
Short name	T699
Test name
Test status
Simulation time	41410839267 ps
CPU time	34.91 seconds
Started	Feb 18 02:07:28 PM PST 24
Finished	Feb 18 02:08:04 PM PST 24
Peak memory	199452 kb
Host	smart-0fefaa02-d90f-4d39-ae9d-15b9e2e62890
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=825209350 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.uart_fifo_reset.825209350
Directory	/workspace/112.uart_fifo_reset/latest

Test location	/workspace/coverage/default/113.uart_fifo_reset.1244716580
Short name	T742
Test name
Test status
Simulation time	143636716571 ps
CPU time	56.77 seconds
Started	Feb 18 02:07:28 PM PST 24
Finished	Feb 18 02:08:26 PM PST 24
Peak memory	199424 kb
Host	smart-1f36d343-5a26-4a19-ac0f-49ef854d9bd1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1244716580 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.uart_fifo_reset.1244716580
Directory	/workspace/113.uart_fifo_reset/latest

Test location	/workspace/coverage/default/114.uart_fifo_reset.3099692278
Short name	T749
Test name
Test status
Simulation time	214763096044 ps
CPU time	73.76 seconds
Started	Feb 18 02:07:28 PM PST 24
Finished	Feb 18 02:08:43 PM PST 24
Peak memory	199964 kb
Host	smart-100ac73f-1ff2-4247-8d30-c53b75047d86
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3099692278 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.uart_fifo_reset.3099692278
Directory	/workspace/114.uart_fifo_reset/latest

Test location	/workspace/coverage/default/118.uart_fifo_reset.158554260
Short name	T708
Test name
Test status
Simulation time	18095138708 ps
CPU time	26.89 seconds
Started	Feb 18 02:07:28 PM PST 24
Finished	Feb 18 02:07:56 PM PST 24
Peak memory	199964 kb
Host	smart-749b216a-3e18-417e-ba18-e7011cb6507e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=158554260 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.uart_fifo_reset.158554260
Directory	/workspace/118.uart_fifo_reset/latest

Test location	/workspace/coverage/default/12.uart_alert_test.2002127778
Short name	T969
Test name
Test status
Simulation time	12719277 ps
CPU time	0.59 seconds
Started	Feb 18 02:04:11 PM PST 24
Finished	Feb 18 02:04:16 PM PST 24
Peak memory	195504 kb
Host	smart-38335932-9849-48db-bfc4-889017732397
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002127778 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_alert_test.2002127778
Directory	/workspace/12.uart_alert_test/latest

Test location	/workspace/coverage/default/12.uart_fifo_full.973193788
Short name	T941
Test name
Test status
Simulation time	54976811990 ps
CPU time	30.63 seconds
Started	Feb 18 02:04:04 PM PST 24
Finished	Feb 18 02:04:39 PM PST 24
Peak memory	200028 kb
Host	smart-70a3bfdb-3fe3-4345-b25e-6cdf71f5eefd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=973193788 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_full.973193788
Directory	/workspace/12.uart_fifo_full/latest

Test location	/workspace/coverage/default/12.uart_fifo_overflow.2692067320
Short name	T689
Test name
Test status
Simulation time	299492875246 ps
CPU time	456.02 seconds
Started	Feb 18 02:04:09 PM PST 24
Finished	Feb 18 02:11:50 PM PST 24
Peak memory	200072 kb
Host	smart-cf9cc298-4bec-4df5-bf4a-d5f8a25b45d9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2692067320 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_overflow.2692067320
Directory	/workspace/12.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/12.uart_fifo_reset.1899878613
Short name	T138
Test name
Test status
Simulation time	30540986880 ps
CPU time	45.44 seconds
Started	Feb 18 02:04:06 PM PST 24
Finished	Feb 18 02:04:55 PM PST 24
Peak memory	199056 kb
Host	smart-cc1ba92c-2028-440a-9a62-49d08484aac2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1899878613 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_reset.1899878613
Directory	/workspace/12.uart_fifo_reset/latest

Test location	/workspace/coverage/default/12.uart_long_xfer_wo_dly.1604369899
Short name	T620
Test name
Test status
Simulation time	89903690985 ps
CPU time	166.45 seconds
Started	Feb 18 02:04:07 PM PST 24
Finished	Feb 18 02:06:57 PM PST 24
Peak memory	200048 kb
Host	smart-463b4bf9-7a13-499a-9ade-40d1b0e499bd
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1604369899 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_long_xfer_wo_dly.1604369899
Directory	/workspace/12.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/12.uart_noise_filter.1825508668
Short name	T996
Test name
Test status
Simulation time	28560052827 ps
CPU time	23.52 seconds
Started	Feb 18 02:04:06 PM PST 24
Finished	Feb 18 02:04:34 PM PST 24
Peak memory	195696 kb
Host	smart-4826cd2d-1c8d-4508-b812-5b40dbc7933c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1825508668 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_noise_filter.1825508668
Directory	/workspace/12.uart_noise_filter/latest

Test location	/workspace/coverage/default/12.uart_perf.724135241
Short name	T876
Test name
Test status
Simulation time	9561902037 ps
CPU time	117.93 seconds
Started	Feb 18 02:04:10 PM PST 24
Finished	Feb 18 02:06:12 PM PST 24
Peak memory	200020 kb
Host	smart-f32f79b8-6833-4f5e-b462-cb4d3b963846
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=724135241 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_perf.724135241
Directory	/workspace/12.uart_perf/latest

Test location	/workspace/coverage/default/12.uart_rx_oversample.3617475077
Short name	T671
Test name
Test status
Simulation time	951936109 ps
CPU time	8.51 seconds
Started	Feb 18 02:04:05 PM PST 24
Finished	Feb 18 02:04:18 PM PST 24
Peak memory	197676 kb
Host	smart-b57167d5-cd5f-4ea3-9cd8-911b1c57c2f0
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3617475077 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_oversample.3617475077
Directory	/workspace/12.uart_rx_oversample/latest

Test location	/workspace/coverage/default/12.uart_rx_parity_err.335450355
Short name	T390
Test name
Test status
Simulation time	158240451251 ps
CPU time	246.29 seconds
Started	Feb 18 02:04:17 PM PST 24
Finished	Feb 18 02:08:27 PM PST 24
Peak memory	200016 kb
Host	smart-720f4175-6886-4792-b00b-6e2a0b1bc8ac
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=335450355 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_parity_err.335450355
Directory	/workspace/12.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/12.uart_rx_start_bit_filter.2590978940
Short name	T576
Test name
Test status
Simulation time	2063402773 ps
CPU time	3.95 seconds
Started	Feb 18 02:04:11 PM PST 24
Finished	Feb 18 02:04:20 PM PST 24
Peak memory	195512 kb
Host	smart-b30fa142-d4d9-49a4-8d82-2f48ca869bad
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2590978940 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_start_bit_filter.2590978940
Directory	/workspace/12.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/12.uart_smoke.26777496
Short name	T628
Test name
Test status
Simulation time	5996466313 ps
CPU time	45.61 seconds
Started	Feb 18 02:04:01 PM PST 24
Finished	Feb 18 02:04:53 PM PST 24
Peak memory	199616 kb
Host	smart-f5c0b682-e0d5-49bf-a239-e0d10889c671
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=26777496 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_smoke.26777496
Directory	/workspace/12.uart_smoke/latest

Test location	/workspace/coverage/default/12.uart_stress_all.2652328329
Short name	T1031
Test name
Test status
Simulation time	233195112390 ps
CPU time	63.02 seconds
Started	Feb 18 02:04:11 PM PST 24
Finished	Feb 18 02:05:18 PM PST 24
Peak memory	200076 kb
Host	smart-47994922-7f0a-4150-8b3e-51e3f761415e
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652328329 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_stress_all.2652328329
Directory	/workspace/12.uart_stress_all/latest

Test location	/workspace/coverage/default/12.uart_stress_all_with_rand_reset.813473867
Short name	T434
Test name
Test status
Simulation time	42107342626 ps
CPU time	506.91 seconds
Started	Feb 18 02:04:10 PM PST 24
Finished	Feb 18 02:12:41 PM PST 24
Peak memory	212000 kb
Host	smart-d62a5365-aa00-4246-8f07-7e773cd52721
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813473867 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 12.uart_stress_all_with_rand_reset.813473867
Directory	/workspace/12.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/12.uart_tx_ovrd.4139098798
Short name	T703
Test name
Test status
Simulation time	7147972051 ps
CPU time	21.21 seconds
Started	Feb 18 02:04:04 PM PST 24
Finished	Feb 18 02:04:30 PM PST 24
Peak memory	199804 kb
Host	smart-0a6ad5b9-6960-4a2e-9ce8-1a8d6c102bac
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4139098798 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_ovrd.4139098798
Directory	/workspace/12.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/12.uart_tx_rx.265581760
Short name	T797
Test name
Test status
Simulation time	25658354797 ps
CPU time	45.09 seconds
Started	Feb 18 02:04:01 PM PST 24
Finished	Feb 18 02:04:52 PM PST 24
Peak memory	199876 kb
Host	smart-fd7820d3-2ed5-4346-b47a-9161514acf66
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=265581760 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_rx.265581760
Directory	/workspace/12.uart_tx_rx/latest

Test location	/workspace/coverage/default/120.uart_fifo_reset.1489425498
Short name	T235
Test name
Test status
Simulation time	147119426387 ps
CPU time	72.42 seconds
Started	Feb 18 02:07:28 PM PST 24
Finished	Feb 18 02:08:42 PM PST 24
Peak memory	199428 kb
Host	smart-bfba97fc-9652-4c20-ab07-20d2331d1568
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1489425498 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.uart_fifo_reset.1489425498
Directory	/workspace/120.uart_fifo_reset/latest

Test location	/workspace/coverage/default/121.uart_fifo_reset.2893164860
Short name	T582
Test name
Test status
Simulation time	166006113369 ps
CPU time	15.75 seconds
Started	Feb 18 02:07:24 PM PST 24
Finished	Feb 18 02:07:42 PM PST 24
Peak memory	200012 kb
Host	smart-0246d9d5-3dfc-45be-98e8-53831db60bcc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2893164860 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.uart_fifo_reset.2893164860
Directory	/workspace/121.uart_fifo_reset/latest

Test location	/workspace/coverage/default/124.uart_fifo_reset.327449156
Short name	T1026
Test name
Test status
Simulation time	33897948098 ps
CPU time	9.85 seconds
Started	Feb 18 02:07:27 PM PST 24
Finished	Feb 18 02:07:38 PM PST 24
Peak memory	198676 kb
Host	smart-65a3b464-da15-48c0-8f8f-293d7e77aa31
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=327449156 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.uart_fifo_reset.327449156
Directory	/workspace/124.uart_fifo_reset/latest

Test location	/workspace/coverage/default/126.uart_fifo_reset.3369911249
Short name	T757
Test name
Test status
Simulation time	118391133706 ps
CPU time	177.2 seconds
Started	Feb 18 02:07:26 PM PST 24
Finished	Feb 18 02:10:25 PM PST 24
Peak memory	200112 kb
Host	smart-07a6a4c2-9b42-44ea-bb9c-967691693699
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3369911249 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.uart_fifo_reset.3369911249
Directory	/workspace/126.uart_fifo_reset/latest

Test location	/workspace/coverage/default/127.uart_fifo_reset.141125384
Short name	T231
Test name
Test status
Simulation time	3141894058 ps
CPU time	5.87 seconds
Started	Feb 18 02:07:26 PM PST 24
Finished	Feb 18 02:07:33 PM PST 24
Peak memory	200048 kb
Host	smart-8378d2e9-f123-4db2-b0a6-38ced43920c5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=141125384 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.uart_fifo_reset.141125384
Directory	/workspace/127.uart_fifo_reset/latest

Test location	/workspace/coverage/default/129.uart_fifo_reset.3308184582
Short name	T174
Test name
Test status
Simulation time	22483718867 ps
CPU time	38.39 seconds
Started	Feb 18 02:07:25 PM PST 24
Finished	Feb 18 02:08:05 PM PST 24
Peak memory	200036 kb
Host	smart-92549cb7-5157-4f64-a9df-5a9b0f3d7aa1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3308184582 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.uart_fifo_reset.3308184582
Directory	/workspace/129.uart_fifo_reset/latest

Test location	/workspace/coverage/default/13.uart_alert_test.4259093241
Short name	T464
Test name
Test status
Simulation time	36187923 ps
CPU time	0.57 seconds
Started	Feb 18 02:04:21 PM PST 24
Finished	Feb 18 02:04:25 PM PST 24
Peak memory	194048 kb
Host	smart-2b39af64-cc36-4204-998e-154c14796b4c
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259093241 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_alert_test.4259093241
Directory	/workspace/13.uart_alert_test/latest

Test location	/workspace/coverage/default/13.uart_fifo_full.277705719
Short name	T586
Test name
Test status
Simulation time	181209895083 ps
CPU time	72.24 seconds
Started	Feb 18 02:04:10 PM PST 24
Finished	Feb 18 02:05:26 PM PST 24
Peak memory	199996 kb
Host	smart-0eba07e6-52ad-4ec4-9db4-34e6800fb77f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=277705719 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_full.277705719
Directory	/workspace/13.uart_fifo_full/latest

Test location	/workspace/coverage/default/13.uart_fifo_overflow.592671983
Short name	T785
Test name
Test status
Simulation time	115193448885 ps
CPU time	46.11 seconds
Started	Feb 18 02:04:05 PM PST 24
Finished	Feb 18 02:04:56 PM PST 24
Peak memory	198912 kb
Host	smart-cd59dd78-930f-4e5e-97ca-eb794b2f3827
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=592671983 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_overflow.592671983
Directory	/workspace/13.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/13.uart_fifo_reset.738176100
Short name	T1036
Test name
Test status
Simulation time	111664763635 ps
CPU time	42.23 seconds
Started	Feb 18 02:04:05 PM PST 24
Finished	Feb 18 02:04:52 PM PST 24
Peak memory	200124 kb
Host	smart-e0572bd9-4372-4409-8e6f-f5675299db60
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=738176100 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_reset.738176100
Directory	/workspace/13.uart_fifo_reset/latest

Test location	/workspace/coverage/default/13.uart_intr.3988491652
Short name	T1083
Test name
Test status
Simulation time	2302702181869 ps
CPU time	917.26 seconds
Started	Feb 18 02:04:11 PM PST 24
Finished	Feb 18 02:19:33 PM PST 24
Peak memory	199972 kb
Host	smart-b9001388-1628-412c-87bf-ec79b6a8d9e2
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988491652 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_intr.3988491652
Directory	/workspace/13.uart_intr/latest

Test location	/workspace/coverage/default/13.uart_long_xfer_wo_dly.2933078873
Short name	T834
Test name
Test status
Simulation time	47773484048 ps
CPU time	336.04 seconds
Started	Feb 18 02:04:04 PM PST 24
Finished	Feb 18 02:09:45 PM PST 24
Peak memory	200020 kb
Host	smart-ad654a4e-f828-46c1-bd76-1a159e210a21
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2933078873 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_long_xfer_wo_dly.2933078873
Directory	/workspace/13.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/13.uart_loopback.344840996
Short name	T1074
Test name
Test status
Simulation time	3800944446 ps
CPU time	3.62 seconds
Started	Feb 18 02:04:07 PM PST 24
Finished	Feb 18 02:04:15 PM PST 24
Peak memory	198996 kb
Host	smart-eaeb0602-5cb5-4094-8788-86874467ab6c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=344840996 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_loopback.344840996
Directory	/workspace/13.uart_loopback/latest

Test location	/workspace/coverage/default/13.uart_noise_filter.3720266539
Short name	T974
Test name
Test status
Simulation time	213511571668 ps
CPU time	25.54 seconds
Started	Feb 18 02:04:10 PM PST 24
Finished	Feb 18 02:04:39 PM PST 24
Peak memory	199032 kb
Host	smart-62ec28b6-2897-4d5f-a710-812ed1bc243a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3720266539 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_noise_filter.3720266539
Directory	/workspace/13.uart_noise_filter/latest

Test location	/workspace/coverage/default/13.uart_perf.2467798361
Short name	T609
Test name
Test status
Simulation time	14945659957 ps
CPU time	418.56 seconds
Started	Feb 18 02:04:14 PM PST 24
Finished	Feb 18 02:11:18 PM PST 24
Peak memory	200036 kb
Host	smart-5ddb36ef-2620-47f5-8af2-e5dfd85b51ec
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2467798361 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_perf.2467798361
Directory	/workspace/13.uart_perf/latest

Test location	/workspace/coverage/default/13.uart_rx_oversample.996320472
Short name	T733
Test name
Test status
Simulation time	2895416105 ps
CPU time	4.46 seconds
Started	Feb 18 02:04:01 PM PST 24
Finished	Feb 18 02:04:11 PM PST 24
Peak memory	197892 kb
Host	smart-e1b1d06f-e789-4182-9cc5-c471d17966df
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=996320472 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_oversample.996320472
Directory	/workspace/13.uart_rx_oversample/latest

Test location	/workspace/coverage/default/13.uart_rx_start_bit_filter.2517661994
Short name	T523
Test name
Test status
Simulation time	4355065421 ps
CPU time	1.47 seconds
Started	Feb 18 02:04:01 PM PST 24
Finished	Feb 18 02:04:09 PM PST 24
Peak memory	195800 kb
Host	smart-11eec23d-5540-4f5c-bb2b-d462ff52bbbe
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2517661994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_start_bit_filter.2517661994
Directory	/workspace/13.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/13.uart_smoke.1455670496
Short name	T487
Test name
Test status
Simulation time	6066254354 ps
CPU time	10.77 seconds
Started	Feb 18 02:04:03 PM PST 24
Finished	Feb 18 02:04:19 PM PST 24
Peak memory	198872 kb
Host	smart-52b97b1a-6783-4ba4-8e36-55f542a83e5f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1455670496 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_smoke.1455670496
Directory	/workspace/13.uart_smoke/latest

Test location	/workspace/coverage/default/13.uart_tx_ovrd.762972687
Short name	T799
Test name
Test status
Simulation time	1078230119 ps
CPU time	4 seconds
Started	Feb 18 02:04:06 PM PST 24
Finished	Feb 18 02:04:15 PM PST 24
Peak memory	198360 kb
Host	smart-a0839086-ea90-4cf4-a024-d7da13d4ec7e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=762972687 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_ovrd.762972687
Directory	/workspace/13.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/13.uart_tx_rx.2283090175
Short name	T531
Test name
Test status
Simulation time	113753472566 ps
CPU time	160.06 seconds
Started	Feb 18 02:04:08 PM PST 24
Finished	Feb 18 02:06:53 PM PST 24
Peak memory	200020 kb
Host	smart-50f1cb6d-3cd5-4cd8-b042-5de95caf093d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2283090175 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_rx.2283090175
Directory	/workspace/13.uart_tx_rx/latest

Test location	/workspace/coverage/default/130.uart_fifo_reset.1475103904
Short name	T603
Test name
Test status
Simulation time	72817375814 ps
CPU time	30.2 seconds
Started	Feb 18 02:07:38 PM PST 24
Finished	Feb 18 02:08:09 PM PST 24
Peak memory	200048 kb
Host	smart-20fce7f3-d7d8-486e-b5b5-ae687edff4a3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1475103904 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.uart_fifo_reset.1475103904
Directory	/workspace/130.uart_fifo_reset/latest

Test location	/workspace/coverage/default/131.uart_fifo_reset.3754861951
Short name	T306
Test name
Test status
Simulation time	68486513748 ps
CPU time	38.35 seconds
Started	Feb 18 02:07:31 PM PST 24
Finished	Feb 18 02:08:11 PM PST 24
Peak memory	199904 kb
Host	smart-8fec46d4-a688-4905-8848-fb6fd23b2c01
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3754861951 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.uart_fifo_reset.3754861951
Directory	/workspace/131.uart_fifo_reset/latest

Test location	/workspace/coverage/default/133.uart_fifo_reset.2143256170
Short name	T1095
Test name
Test status
Simulation time	89574568626 ps
CPU time	19.04 seconds
Started	Feb 18 02:07:33 PM PST 24
Finished	Feb 18 02:07:54 PM PST 24
Peak memory	200048 kb
Host	smart-e2c4193e-1720-44d4-9f8e-1c83ed85212b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2143256170 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.uart_fifo_reset.2143256170
Directory	/workspace/133.uart_fifo_reset/latest

Test location	/workspace/coverage/default/134.uart_fifo_reset.3839449946
Short name	T1067
Test name
Test status
Simulation time	27395484588 ps
CPU time	48.12 seconds
Started	Feb 18 02:07:38 PM PST 24
Finished	Feb 18 02:08:27 PM PST 24
Peak memory	200132 kb
Host	smart-8f3e2884-af6a-4cc9-b77e-3b22f610a449
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3839449946 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.uart_fifo_reset.3839449946
Directory	/workspace/134.uart_fifo_reset/latest

Test location	/workspace/coverage/default/136.uart_fifo_reset.2863739833
Short name	T845
Test name
Test status
Simulation time	32265519157 ps
CPU time	55.78 seconds
Started	Feb 18 02:07:33 PM PST 24
Finished	Feb 18 02:08:31 PM PST 24
Peak memory	200008 kb
Host	smart-416b48d8-c882-4be6-aece-4b80434f52c9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2863739833 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.uart_fifo_reset.2863739833
Directory	/workspace/136.uart_fifo_reset/latest

Test location	/workspace/coverage/default/137.uart_fifo_reset.4275425793
Short name	T308
Test name
Test status
Simulation time	11127780811 ps
CPU time	13.83 seconds
Started	Feb 18 02:07:38 PM PST 24
Finished	Feb 18 02:07:52 PM PST 24
Peak memory	200024 kb
Host	smart-56951b32-f4dc-491f-9ffa-3402fad2f6f3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4275425793 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.uart_fifo_reset.4275425793
Directory	/workspace/137.uart_fifo_reset/latest

Test location	/workspace/coverage/default/138.uart_fifo_reset.3371685835
Short name	T247
Test name
Test status
Simulation time	23429180596 ps
CPU time	11.08 seconds
Started	Feb 18 02:07:39 PM PST 24
Finished	Feb 18 02:07:51 PM PST 24
Peak memory	199976 kb
Host	smart-cf452d33-f6e4-4679-a9f6-37fb103942bb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3371685835 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.uart_fifo_reset.3371685835
Directory	/workspace/138.uart_fifo_reset/latest

Test location	/workspace/coverage/default/139.uart_fifo_reset.3584983338
Short name	T53
Test name
Test status
Simulation time	91570572052 ps
CPU time	29.67 seconds
Started	Feb 18 02:07:31 PM PST 24
Finished	Feb 18 02:08:03 PM PST 24
Peak memory	199824 kb
Host	smart-07036bfc-4487-4024-83fb-9a462a19f4bf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3584983338 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.uart_fifo_reset.3584983338
Directory	/workspace/139.uart_fifo_reset/latest

Test location	/workspace/coverage/default/14.uart_alert_test.3611802211
Short name	T439
Test name
Test status
Simulation time	43042558 ps
CPU time	0.62 seconds
Started	Feb 18 02:04:10 PM PST 24
Finished	Feb 18 02:04:15 PM PST 24
Peak memory	195504 kb
Host	smart-c99428f1-e38d-4111-8707-dc0c1c23f70b
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611802211 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_alert_test.3611802211
Directory	/workspace/14.uart_alert_test/latest

Test location	/workspace/coverage/default/14.uart_fifo_full.3393672027
Short name	T258
Test name
Test status
Simulation time	77107522209 ps
CPU time	63.55 seconds
Started	Feb 18 02:04:21 PM PST 24
Finished	Feb 18 02:05:28 PM PST 24
Peak memory	199640 kb
Host	smart-a584a333-406e-4271-9a1b-7311c6a1a4ef
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3393672027 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_full.3393672027
Directory	/workspace/14.uart_fifo_full/latest

Test location	/workspace/coverage/default/14.uart_fifo_reset.3578625859
Short name	T301
Test name
Test status
Simulation time	29984235784 ps
CPU time	52.85 seconds
Started	Feb 18 02:04:21 PM PST 24
Finished	Feb 18 02:05:17 PM PST 24
Peak memory	199064 kb
Host	smart-c83208c6-0f7a-496f-98b0-c0d3173feed1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3578625859 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_reset.3578625859
Directory	/workspace/14.uart_fifo_reset/latest

Test location	/workspace/coverage/default/14.uart_intr.494564403
Short name	T16
Test name
Test status
Simulation time	220225633470 ps
CPU time	364.35 seconds
Started	Feb 18 02:04:07 PM PST 24
Finished	Feb 18 02:10:16 PM PST 24
Peak memory	200032 kb
Host	smart-24868260-0056-4a4e-82a9-4dd5955a1534
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494564403 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_intr.494564403
Directory	/workspace/14.uart_intr/latest

Test location	/workspace/coverage/default/14.uart_long_xfer_wo_dly.4203315664
Short name	T539
Test name
Test status
Simulation time	176893802817 ps
CPU time	949.43 seconds
Started	Feb 18 02:04:09 PM PST 24
Finished	Feb 18 02:20:03 PM PST 24
Peak memory	200020 kb
Host	smart-e985cf56-4f4d-489f-8f33-715a4e30a288
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4203315664 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_long_xfer_wo_dly.4203315664
Directory	/workspace/14.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/14.uart_loopback.1115789939
Short name	T26
Test name
Test status
Simulation time	6868295645 ps
CPU time	4.82 seconds
Started	Feb 18 02:04:21 PM PST 24
Finished	Feb 18 02:04:29 PM PST 24
Peak memory	199232 kb
Host	smart-652cc6f4-04e0-44a3-a561-139bb6fc0579
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1115789939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_loopback.1115789939
Directory	/workspace/14.uart_loopback/latest

Test location	/workspace/coverage/default/14.uart_noise_filter.3145334372
Short name	T577
Test name
Test status
Simulation time	121518037845 ps
CPU time	17.87 seconds
Started	Feb 18 02:04:07 PM PST 24
Finished	Feb 18 02:04:29 PM PST 24
Peak memory	196520 kb
Host	smart-002b5e82-2652-47f3-802a-5aede4921275
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3145334372 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_noise_filter.3145334372
Directory	/workspace/14.uart_noise_filter/latest

Test location	/workspace/coverage/default/14.uart_perf.2623757227
Short name	T1098
Test name
Test status
Simulation time	19690451172 ps
CPU time	476 seconds
Started	Feb 18 02:04:07 PM PST 24
Finished	Feb 18 02:12:08 PM PST 24
Peak memory	200052 kb
Host	smart-c631d743-ddb6-44e9-9abd-813b90a8d2f7
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2623757227 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_perf.2623757227
Directory	/workspace/14.uart_perf/latest

Test location	/workspace/coverage/default/14.uart_rx_oversample.4202821104
Short name	T885
Test name
Test status
Simulation time	4450233100 ps
CPU time	34.4 seconds
Started	Feb 18 02:04:21 PM PST 24
Finished	Feb 18 02:04:58 PM PST 24
Peak memory	198180 kb
Host	smart-32685f80-5591-410f-85af-9ff3f3e501a6
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4202821104 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_oversample.4202821104
Directory	/workspace/14.uart_rx_oversample/latest

Test location	/workspace/coverage/default/14.uart_rx_parity_err.3823899914
Short name	T961
Test name
Test status
Simulation time	31059873035 ps
CPU time	47.18 seconds
Started	Feb 18 02:04:07 PM PST 24
Finished	Feb 18 02:04:59 PM PST 24
Peak memory	200008 kb
Host	smart-4376e871-0f72-4ed2-b05c-f06dff4b73ff
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3823899914 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_parity_err.3823899914
Directory	/workspace/14.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/14.uart_rx_start_bit_filter.3803900400
Short name	T491
Test name
Test status
Simulation time	63664051073 ps
CPU time	96.41 seconds
Started	Feb 18 02:04:08 PM PST 24
Finished	Feb 18 02:05:49 PM PST 24
Peak memory	195868 kb
Host	smart-f16a89fa-be1a-4654-a6fa-8d3be15bcb77
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3803900400 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_start_bit_filter.3803900400
Directory	/workspace/14.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/14.uart_smoke.1691708866
Short name	T893
Test name
Test status
Simulation time	534298353 ps
CPU time	1.6 seconds
Started	Feb 18 02:04:11 PM PST 24
Finished	Feb 18 02:04:16 PM PST 24
Peak memory	198884 kb
Host	smart-fb86b411-5072-48c4-b375-eebeb85c9ef1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1691708866 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_smoke.1691708866
Directory	/workspace/14.uart_smoke/latest

Test location	/workspace/coverage/default/14.uart_stress_all_with_rand_reset.4064991860
Short name	T386
Test name
Test status
Simulation time	66512592269 ps
CPU time	347.25 seconds
Started	Feb 18 02:04:11 PM PST 24
Finished	Feb 18 02:10:02 PM PST 24
Peak memory	216736 kb
Host	smart-673d09af-d38d-4ecc-ba92-b1a0a6e246f4
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064991860 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 14.uart_stress_all_with_rand_reset.4064991860
Directory	/workspace/14.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/14.uart_tx_ovrd.501030640
Short name	T1054
Test name
Test status
Simulation time	7512856161 ps
CPU time	6.91 seconds
Started	Feb 18 02:04:10 PM PST 24
Finished	Feb 18 02:04:21 PM PST 24
Peak memory	199576 kb
Host	smart-51455a3f-820b-4ddd-bffc-5c681f04ef82
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=501030640 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_ovrd.501030640
Directory	/workspace/14.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/14.uart_tx_rx.3514542704
Short name	T622
Test name
Test status
Simulation time	32563881651 ps
CPU time	48.44 seconds
Started	Feb 18 02:04:08 PM PST 24
Finished	Feb 18 02:05:01 PM PST 24
Peak memory	199960 kb
Host	smart-2c95dc8b-b1d6-4ff8-98df-8b32e628ecbe
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3514542704 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_rx.3514542704
Directory	/workspace/14.uart_tx_rx/latest

Test location	/workspace/coverage/default/140.uart_fifo_reset.2761364575
Short name	T937
Test name
Test status
Simulation time	20336154375 ps
CPU time	29.97 seconds
Started	Feb 18 02:07:35 PM PST 24
Finished	Feb 18 02:08:07 PM PST 24
Peak memory	199984 kb
Host	smart-12953dad-b95e-4701-8a7e-e8bef53bd9f5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2761364575 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.uart_fifo_reset.2761364575
Directory	/workspace/140.uart_fifo_reset/latest

Test location	/workspace/coverage/default/141.uart_fifo_reset.1626289430
Short name	T270
Test name
Test status
Simulation time	16910731771 ps
CPU time	18.1 seconds
Started	Feb 18 02:07:35 PM PST 24
Finished	Feb 18 02:07:55 PM PST 24
Peak memory	199904 kb
Host	smart-5306715f-5ee6-4b0b-ab3f-14c60d8e9534
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1626289430 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.uart_fifo_reset.1626289430
Directory	/workspace/141.uart_fifo_reset/latest

Test location	/workspace/coverage/default/144.uart_fifo_reset.1448953428
Short name	T166
Test name
Test status
Simulation time	21779926925 ps
CPU time	9.31 seconds
Started	Feb 18 02:07:36 PM PST 24
Finished	Feb 18 02:07:47 PM PST 24
Peak memory	199648 kb
Host	smart-e7702e58-7b29-44eb-8da3-74ee4cb52791
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1448953428 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.uart_fifo_reset.1448953428
Directory	/workspace/144.uart_fifo_reset/latest

Test location	/workspace/coverage/default/145.uart_fifo_reset.1425826936
Short name	T568
Test name
Test status
Simulation time	141209261097 ps
CPU time	55.06 seconds
Started	Feb 18 02:07:38 PM PST 24
Finished	Feb 18 02:08:34 PM PST 24
Peak memory	199936 kb
Host	smart-ef6e866b-a1f8-4c12-9aea-42c425f5dae1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1425826936 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.uart_fifo_reset.1425826936
Directory	/workspace/145.uart_fifo_reset/latest

Test location	/workspace/coverage/default/146.uart_fifo_reset.2196144575
Short name	T221
Test name
Test status
Simulation time	102267572194 ps
CPU time	167.62 seconds
Started	Feb 18 02:07:32 PM PST 24
Finished	Feb 18 02:10:23 PM PST 24
Peak memory	200116 kb
Host	smart-6d515fdc-05ba-45bd-9b17-408f191bec26
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2196144575 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.uart_fifo_reset.2196144575
Directory	/workspace/146.uart_fifo_reset/latest

Test location	/workspace/coverage/default/147.uart_fifo_reset.318370271
Short name	T1108
Test name
Test status
Simulation time	197617073349 ps
CPU time	30.41 seconds
Started	Feb 18 02:07:33 PM PST 24
Finished	Feb 18 02:08:06 PM PST 24
Peak memory	199612 kb
Host	smart-5518a22b-e406-4f0b-9723-86f380e73d1c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=318370271 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.uart_fifo_reset.318370271
Directory	/workspace/147.uart_fifo_reset/latest

Test location	/workspace/coverage/default/149.uart_fifo_reset.1951095133
Short name	T196
Test name
Test status
Simulation time	50463836406 ps
CPU time	43.38 seconds
Started	Feb 18 02:07:33 PM PST 24
Finished	Feb 18 02:08:19 PM PST 24
Peak memory	199236 kb
Host	smart-831b682b-7877-480f-8ea2-4d3f517adc80
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1951095133 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.uart_fifo_reset.1951095133
Directory	/workspace/149.uart_fifo_reset/latest

Test location	/workspace/coverage/default/15.uart_alert_test.364876426
Short name	T980
Test name
Test status
Simulation time	13438945 ps
CPU time	0.56 seconds
Started	Feb 18 02:04:18 PM PST 24
Finished	Feb 18 02:04:22 PM PST 24
Peak memory	194552 kb
Host	smart-e3635f47-5e87-4950-ac6a-22a1acd56391
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364876426 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_alert_test.364876426
Directory	/workspace/15.uart_alert_test/latest

Test location	/workspace/coverage/default/15.uart_fifo_full.948068048
Short name	T299
Test name
Test status
Simulation time	64981058649 ps
CPU time	104.69 seconds
Started	Feb 18 02:04:06 PM PST 24
Finished	Feb 18 02:05:55 PM PST 24
Peak memory	200092 kb
Host	smart-8d22c234-2091-4df9-ad50-82814eb6c804
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=948068048 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_full.948068048
Directory	/workspace/15.uart_fifo_full/latest

Test location	/workspace/coverage/default/15.uart_fifo_overflow.3953329602
Short name	T198
Test name
Test status
Simulation time	40927910709 ps
CPU time	16.87 seconds
Started	Feb 18 02:04:07 PM PST 24
Finished	Feb 18 02:04:28 PM PST 24
Peak memory	199364 kb
Host	smart-a4dfa40a-c207-4bdc-9c01-d11fdec3d671
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3953329602 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_overflow.3953329602
Directory	/workspace/15.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/15.uart_fifo_reset.1395585889
Short name	T1037
Test name
Test status
Simulation time	141110313902 ps
CPU time	221.12 seconds
Started	Feb 18 02:04:09 PM PST 24
Finished	Feb 18 02:07:55 PM PST 24
Peak memory	199908 kb
Host	smart-c5bb176b-4450-46b2-9745-642a99bff52e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1395585889 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_reset.1395585889
Directory	/workspace/15.uart_fifo_reset/latest

Test location	/workspace/coverage/default/15.uart_intr.1274287091
Short name	T619
Test name
Test status
Simulation time	2536650445884 ps
CPU time	3550.16 seconds
Started	Feb 18 02:04:13 PM PST 24
Finished	Feb 18 03:03:29 PM PST 24
Peak memory	198656 kb
Host	smart-daf20391-c256-4786-955d-9b9fd7b7df65
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274287091 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_intr.1274287091
Directory	/workspace/15.uart_intr/latest

Test location	/workspace/coverage/default/15.uart_long_xfer_wo_dly.3800438933
Short name	T745
Test name
Test status
Simulation time	95173991225 ps
CPU time	600.49 seconds
Started	Feb 18 02:04:15 PM PST 24
Finished	Feb 18 02:14:20 PM PST 24
Peak memory	200088 kb
Host	smart-0db2dcda-4504-4f83-82c0-9650f0ba1ce3
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3800438933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_long_xfer_wo_dly.3800438933
Directory	/workspace/15.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/15.uart_loopback.1654505581
Short name	T543
Test name
Test status
Simulation time	8676622024 ps
CPU time	17.17 seconds
Started	Feb 18 02:04:14 PM PST 24
Finished	Feb 18 02:04:36 PM PST 24
Peak memory	197964 kb
Host	smart-3e5895fc-5f20-42e3-8481-6bd7b4c9dbaf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1654505581 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_loopback.1654505581
Directory	/workspace/15.uart_loopback/latest

Test location	/workspace/coverage/default/15.uart_noise_filter.147617160
Short name	T1029
Test name
Test status
Simulation time	15063851079 ps
CPU time	24.28 seconds
Started	Feb 18 02:04:13 PM PST 24
Finished	Feb 18 02:04:41 PM PST 24
Peak memory	195544 kb
Host	smart-4be09e25-9e45-4e7c-ba14-6b52cda43fbc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=147617160 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_noise_filter.147617160
Directory	/workspace/15.uart_noise_filter/latest

Test location	/workspace/coverage/default/15.uart_perf.3600112288
Short name	T564
Test name
Test status
Simulation time	8522656089 ps
CPU time	131.55 seconds
Started	Feb 18 02:04:14 PM PST 24
Finished	Feb 18 02:06:30 PM PST 24
Peak memory	200092 kb
Host	smart-4ce5e202-cc39-4757-9c5a-e989dc2cfefb
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3600112288 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_perf.3600112288
Directory	/workspace/15.uart_perf/latest

Test location	/workspace/coverage/default/15.uart_rx_oversample.3733153382
Short name	T860
Test name
Test status
Simulation time	1283464406 ps
CPU time	7.79 seconds
Started	Feb 18 02:04:10 PM PST 24
Finished	Feb 18 02:04:22 PM PST 24
Peak memory	198060 kb
Host	smart-125d61b4-cdb2-4b85-9735-27724c70f170
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3733153382 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_oversample.3733153382
Directory	/workspace/15.uart_rx_oversample/latest

Test location	/workspace/coverage/default/15.uart_rx_parity_err.1820342869
Short name	T412
Test name
Test status
Simulation time	220383882557 ps
CPU time	420.02 seconds
Started	Feb 18 02:04:12 PM PST 24
Finished	Feb 18 02:11:17 PM PST 24
Peak memory	200076 kb
Host	smart-3409308f-0d96-455f-8f91-307253b0be31
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1820342869 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_parity_err.1820342869
Directory	/workspace/15.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/15.uart_rx_start_bit_filter.1153031370
Short name	T585
Test name
Test status
Simulation time	3917204671 ps
CPU time	7.17 seconds
Started	Feb 18 02:04:19 PM PST 24
Finished	Feb 18 02:04:29 PM PST 24
Peak memory	195868 kb
Host	smart-a14251a4-8a54-4a2a-8e7e-9bccc8423236
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1153031370 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_start_bit_filter.1153031370
Directory	/workspace/15.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/15.uart_smoke.2444746005
Short name	T710
Test name
Test status
Simulation time	690483317 ps
CPU time	3.16 seconds
Started	Feb 18 02:04:10 PM PST 24
Finished	Feb 18 02:04:17 PM PST 24
Peak memory	199144 kb
Host	smart-d6226b16-c08f-4b8c-81d4-309ba2deb294
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2444746005 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_smoke.2444746005
Directory	/workspace/15.uart_smoke/latest

Test location	/workspace/coverage/default/15.uart_tx_ovrd.1180694175
Short name	T835
Test name
Test status
Simulation time	1634593634 ps
CPU time	1.72 seconds
Started	Feb 18 02:04:20 PM PST 24
Finished	Feb 18 02:04:24 PM PST 24
Peak memory	198264 kb
Host	smart-5e0129af-58a8-4340-bfb0-9aeb6923a7c0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1180694175 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_ovrd.1180694175
Directory	/workspace/15.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/15.uart_tx_rx.1169946221
Short name	T591
Test name
Test status
Simulation time	60933551200 ps
CPU time	24.71 seconds
Started	Feb 18 02:04:17 PM PST 24
Finished	Feb 18 02:04:45 PM PST 24
Peak memory	199964 kb
Host	smart-995baa7a-c890-45f2-b4d5-c97e592108d7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1169946221 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_rx.1169946221
Directory	/workspace/15.uart_tx_rx/latest

Test location	/workspace/coverage/default/150.uart_fifo_reset.343681060
Short name	T1087
Test name
Test status
Simulation time	165789860829 ps
CPU time	28.67 seconds
Started	Feb 18 02:07:31 PM PST 24
Finished	Feb 18 02:08:01 PM PST 24
Peak memory	200056 kb
Host	smart-57059ada-af9c-488c-8b00-f367d80728e5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=343681060 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.uart_fifo_reset.343681060
Directory	/workspace/150.uart_fifo_reset/latest

Test location	/workspace/coverage/default/152.uart_fifo_reset.2469259327
Short name	T617
Test name
Test status
Simulation time	89691464778 ps
CPU time	73.53 seconds
Started	Feb 18 02:07:35 PM PST 24
Finished	Feb 18 02:08:50 PM PST 24
Peak memory	200016 kb
Host	smart-7a935acf-86f2-44fa-a7c9-3bbe2b43f7dc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2469259327 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.uart_fifo_reset.2469259327
Directory	/workspace/152.uart_fifo_reset/latest

Test location	/workspace/coverage/default/154.uart_fifo_reset.3792380975
Short name	T654
Test name
Test status
Simulation time	8148997029 ps
CPU time	12.74 seconds
Started	Feb 18 02:07:47 PM PST 24
Finished	Feb 18 02:08:01 PM PST 24
Peak memory	199588 kb
Host	smart-77dff7f0-ab26-4f08-9415-f4e94a824a9d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3792380975 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.uart_fifo_reset.3792380975
Directory	/workspace/154.uart_fifo_reset/latest

Test location	/workspace/coverage/default/155.uart_fifo_reset.1484563290
Short name	T105
Test name
Test status
Simulation time	30101507662 ps
CPU time	29.58 seconds
Started	Feb 18 02:07:49 PM PST 24
Finished	Feb 18 02:08:19 PM PST 24
Peak memory	200068 kb
Host	smart-5fcaf9da-df42-41f7-89b2-0d8d7d6f4f77
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1484563290 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.uart_fifo_reset.1484563290
Directory	/workspace/155.uart_fifo_reset/latest

Test location	/workspace/coverage/default/156.uart_fifo_reset.3811803628
Short name	T185
Test name
Test status
Simulation time	111931593173 ps
CPU time	34.64 seconds
Started	Feb 18 02:07:48 PM PST 24
Finished	Feb 18 02:08:24 PM PST 24
Peak memory	200052 kb
Host	smart-e78c9ae9-9fce-4a4a-80e3-44d42703da8b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3811803628 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.uart_fifo_reset.3811803628
Directory	/workspace/156.uart_fifo_reset/latest

Test location	/workspace/coverage/default/157.uart_fifo_reset.2560698923
Short name	T624
Test name
Test status
Simulation time	108836714443 ps
CPU time	47.04 seconds
Started	Feb 18 02:07:49 PM PST 24
Finished	Feb 18 02:08:36 PM PST 24
Peak memory	200100 kb
Host	smart-9488d8a7-3a45-4b6c-93fa-0bf159932a34
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2560698923 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.uart_fifo_reset.2560698923
Directory	/workspace/157.uart_fifo_reset/latest

Test location	/workspace/coverage/default/158.uart_fifo_reset.2698865091
Short name	T910
Test name
Test status
Simulation time	18554914265 ps
CPU time	32.35 seconds
Started	Feb 18 02:07:46 PM PST 24
Finished	Feb 18 02:08:20 PM PST 24
Peak memory	200064 kb
Host	smart-ccfe3eea-e7fb-4e3e-a246-b1812fb269a3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2698865091 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.uart_fifo_reset.2698865091
Directory	/workspace/158.uart_fifo_reset/latest

Test location	/workspace/coverage/default/159.uart_fifo_reset.3714223299
Short name	T222
Test name
Test status
Simulation time	154922957641 ps
CPU time	54.69 seconds
Started	Feb 18 02:07:45 PM PST 24
Finished	Feb 18 02:08:42 PM PST 24
Peak memory	200028 kb
Host	smart-16cd41ce-9996-4ee4-8b4f-4e2d315d285d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3714223299 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.uart_fifo_reset.3714223299
Directory	/workspace/159.uart_fifo_reset/latest

Test location	/workspace/coverage/default/16.uart_alert_test.3971747844
Short name	T542
Test name
Test status
Simulation time	10422542 ps
CPU time	0.58 seconds
Started	Feb 18 02:04:28 PM PST 24
Finished	Feb 18 02:04:32 PM PST 24
Peak memory	194480 kb
Host	smart-3e117a4a-c799-4a18-99f0-f63bab115019
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971747844 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_alert_test.3971747844
Directory	/workspace/16.uart_alert_test/latest

Test location	/workspace/coverage/default/16.uart_fifo_full.2312988448
Short name	T148
Test name
Test status
Simulation time	136663543921 ps
CPU time	47.27 seconds
Started	Feb 18 02:04:18 PM PST 24
Finished	Feb 18 02:05:08 PM PST 24
Peak memory	200056 kb
Host	smart-7894d17c-229b-41c4-b79c-a3006018a5ea
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2312988448 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_full.2312988448
Directory	/workspace/16.uart_fifo_full/latest

Test location	/workspace/coverage/default/16.uart_fifo_overflow.2995528546
Short name	T351
Test name
Test status
Simulation time	9638023690 ps
CPU time	17.34 seconds
Started	Feb 18 02:04:20 PM PST 24
Finished	Feb 18 02:04:40 PM PST 24
Peak memory	199032 kb
Host	smart-1165ed63-d353-4345-85b1-222d83c91515
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2995528546 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_overflow.2995528546
Directory	/workspace/16.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/16.uart_fifo_reset.1128711816
Short name	T293
Test name
Test status
Simulation time	91076126922 ps
CPU time	155.19 seconds
Started	Feb 18 02:04:20 PM PST 24
Finished	Feb 18 02:06:59 PM PST 24
Peak memory	199768 kb
Host	smart-5a479e43-e887-4fa4-a875-a88af6b653ff
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1128711816 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_reset.1128711816
Directory	/workspace/16.uart_fifo_reset/latest

Test location	/workspace/coverage/default/16.uart_intr.3643053660
Short name	T922
Test name
Test status
Simulation time	110986454028 ps
CPU time	217.49 seconds
Started	Feb 18 02:04:26 PM PST 24
Finished	Feb 18 02:08:08 PM PST 24
Peak memory	199812 kb
Host	smart-b631c1cb-ee19-487a-a55d-6d859c2f30ff
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643053660 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_intr.3643053660
Directory	/workspace/16.uart_intr/latest

Test location	/workspace/coverage/default/16.uart_long_xfer_wo_dly.1618676309
Short name	T397
Test name
Test status
Simulation time	106952141061 ps
CPU time	233.8 seconds
Started	Feb 18 02:04:35 PM PST 24
Finished	Feb 18 02:08:32 PM PST 24
Peak memory	199944 kb
Host	smart-291903f5-7bf8-48c9-975e-527061993ad2
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1618676309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_long_xfer_wo_dly.1618676309
Directory	/workspace/16.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/16.uart_loopback.2954781852
Short name	T587
Test name
Test status
Simulation time	3616000220 ps
CPU time	7 seconds
Started	Feb 18 02:04:30 PM PST 24
Finished	Feb 18 02:04:40 PM PST 24
Peak memory	197328 kb
Host	smart-fc08699e-61bd-424d-8514-6ffa0f7419fb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2954781852 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_loopback.2954781852
Directory	/workspace/16.uart_loopback/latest

Test location	/workspace/coverage/default/16.uart_noise_filter.1787419136
Short name	T847
Test name
Test status
Simulation time	66904702521 ps
CPU time	62.79 seconds
Started	Feb 18 02:04:27 PM PST 24
Finished	Feb 18 02:05:34 PM PST 24
Peak memory	198824 kb
Host	smart-725bac47-6489-4299-b7c2-498898244325
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1787419136 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_noise_filter.1787419136
Directory	/workspace/16.uart_noise_filter/latest

Test location	/workspace/coverage/default/16.uart_perf.2701182265
Short name	T783
Test name
Test status
Simulation time	12763975689 ps
CPU time	721.12 seconds
Started	Feb 18 02:04:24 PM PST 24
Finished	Feb 18 02:16:27 PM PST 24
Peak memory	200084 kb
Host	smart-042a2230-d488-4abb-ad5c-2b8fda791a46
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2701182265 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_perf.2701182265
Directory	/workspace/16.uart_perf/latest

Test location	/workspace/coverage/default/16.uart_rx_oversample.3476165890
Short name	T516
Test name
Test status
Simulation time	680027391 ps
CPU time	5.16 seconds
Started	Feb 18 02:04:13 PM PST 24
Finished	Feb 18 02:04:23 PM PST 24
Peak memory	197676 kb
Host	smart-3f496eca-a585-4d9e-8acb-39b07b700585
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3476165890 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_oversample.3476165890
Directory	/workspace/16.uart_rx_oversample/latest

Test location	/workspace/coverage/default/16.uart_rx_parity_err.2578728743
Short name	T242
Test name
Test status
Simulation time	146590310626 ps
CPU time	36.16 seconds
Started	Feb 18 02:04:26 PM PST 24
Finished	Feb 18 02:05:05 PM PST 24
Peak memory	199984 kb
Host	smart-af0782e3-6e69-4f61-944d-f37547468bb5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2578728743 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_parity_err.2578728743
Directory	/workspace/16.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/16.uart_rx_start_bit_filter.1971466390
Short name	T423
Test name
Test status
Simulation time	4253015957 ps
CPU time	6.61 seconds
Started	Feb 18 02:04:18 PM PST 24
Finished	Feb 18 02:04:28 PM PST 24
Peak memory	195864 kb
Host	smart-691ee8c8-c53b-4c26-a87e-da0bf5a090d4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1971466390 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_start_bit_filter.1971466390
Directory	/workspace/16.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/16.uart_smoke.463617394
Short name	T824
Test name
Test status
Simulation time	265540775 ps
CPU time	2.48 seconds
Started	Feb 18 02:04:14 PM PST 24
Finished	Feb 18 02:04:21 PM PST 24
Peak memory	198524 kb
Host	smart-69b39213-a599-497b-ae12-eba98aaa67c5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=463617394 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_smoke.463617394
Directory	/workspace/16.uart_smoke/latest

Test location	/workspace/coverage/default/16.uart_tx_ovrd.373071974
Short name	T1000
Test name
Test status
Simulation time	6395650239 ps
CPU time	17.66 seconds
Started	Feb 18 02:04:20 PM PST 24
Finished	Feb 18 02:04:41 PM PST 24
Peak memory	198996 kb
Host	smart-0150c6de-d667-40ef-afde-80dbba286a19
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=373071974 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_ovrd.373071974
Directory	/workspace/16.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/16.uart_tx_rx.1556289378
Short name	T7
Test name
Test status
Simulation time	21880897946 ps
CPU time	22.37 seconds
Started	Feb 18 02:04:14 PM PST 24
Finished	Feb 18 02:04:41 PM PST 24
Peak memory	200044 kb
Host	smart-45e2db64-5fe8-4f29-8bc4-415012efb5af
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1556289378 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_rx.1556289378
Directory	/workspace/16.uart_tx_rx/latest

Test location	/workspace/coverage/default/160.uart_fifo_reset.3753923182
Short name	T898
Test name
Test status
Simulation time	74335749582 ps
CPU time	24.4 seconds
Started	Feb 18 02:07:45 PM PST 24
Finished	Feb 18 02:08:11 PM PST 24
Peak memory	199928 kb
Host	smart-8d4821cf-7a45-4f4b-b5c8-1686df3ded4d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3753923182 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.uart_fifo_reset.3753923182
Directory	/workspace/160.uart_fifo_reset/latest

Test location	/workspace/coverage/default/161.uart_fifo_reset.3993865885
Short name	T668
Test name
Test status
Simulation time	24019861666 ps
CPU time	38.29 seconds
Started	Feb 18 02:07:49 PM PST 24
Finished	Feb 18 02:08:28 PM PST 24
Peak memory	200092 kb
Host	smart-c89245ce-0fab-4ca3-90a2-5859c9f8c071
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3993865885 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.uart_fifo_reset.3993865885
Directory	/workspace/161.uart_fifo_reset/latest

Test location	/workspace/coverage/default/162.uart_fifo_reset.3113242748
Short name	T970
Test name
Test status
Simulation time	97242347173 ps
CPU time	74.37 seconds
Started	Feb 18 02:07:44 PM PST 24
Finished	Feb 18 02:08:59 PM PST 24
Peak memory	199944 kb
Host	smart-9d1ba1b5-e565-442c-b18f-590a7a21b8f6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3113242748 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.uart_fifo_reset.3113242748
Directory	/workspace/162.uart_fifo_reset/latest

Test location	/workspace/coverage/default/163.uart_fifo_reset.4139071221
Short name	T203
Test name
Test status
Simulation time	145503932767 ps
CPU time	51.32 seconds
Started	Feb 18 02:07:45 PM PST 24
Finished	Feb 18 02:08:38 PM PST 24
Peak memory	199484 kb
Host	smart-7dfc0c47-e02a-41b8-87c2-e55db1a3ee15
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4139071221 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.uart_fifo_reset.4139071221
Directory	/workspace/163.uart_fifo_reset/latest

Test location	/workspace/coverage/default/164.uart_fifo_reset.4070181895
Short name	T958
Test name
Test status
Simulation time	57568841527 ps
CPU time	96.84 seconds
Started	Feb 18 02:07:44 PM PST 24
Finished	Feb 18 02:09:23 PM PST 24
Peak memory	199916 kb
Host	smart-b897f93b-e399-4bdf-8059-9196be7a9601
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4070181895 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.uart_fifo_reset.4070181895
Directory	/workspace/164.uart_fifo_reset/latest

Test location	/workspace/coverage/default/165.uart_fifo_reset.880819619
Short name	T262
Test name
Test status
Simulation time	200207305644 ps
CPU time	29.93 seconds
Started	Feb 18 02:07:43 PM PST 24
Finished	Feb 18 02:08:15 PM PST 24
Peak memory	200004 kb
Host	smart-07b95d5c-d9c4-4b0b-8233-cecb9e37cbe3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=880819619 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.uart_fifo_reset.880819619
Directory	/workspace/165.uart_fifo_reset/latest

Test location	/workspace/coverage/default/168.uart_fifo_reset.3970625276
Short name	T163
Test name
Test status
Simulation time	71391329107 ps
CPU time	30.47 seconds
Started	Feb 18 02:07:45 PM PST 24
Finished	Feb 18 02:08:18 PM PST 24
Peak memory	200008 kb
Host	smart-ec69962f-cea3-49d2-b982-080689aaa637
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3970625276 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.uart_fifo_reset.3970625276
Directory	/workspace/168.uart_fifo_reset/latest

Test location	/workspace/coverage/default/17.uart_alert_test.3035003365
Short name	T890
Test name
Test status
Simulation time	12771770 ps
CPU time	0.56 seconds
Started	Feb 18 02:04:33 PM PST 24
Finished	Feb 18 02:04:36 PM PST 24
Peak memory	194372 kb
Host	smart-3c7dba2d-ac12-4626-a3b4-03e1b78088db
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035003365 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_alert_test.3035003365
Directory	/workspace/17.uart_alert_test/latest

Test location	/workspace/coverage/default/17.uart_fifo_full.2447306521
Short name	T680
Test name
Test status
Simulation time	156706011973 ps
CPU time	61.95 seconds
Started	Feb 18 02:04:30 PM PST 24
Finished	Feb 18 02:05:35 PM PST 24
Peak memory	200024 kb
Host	smart-9283dad9-886e-479a-92fd-4c91a76b0f8a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2447306521 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_full.2447306521
Directory	/workspace/17.uart_fifo_full/latest

Test location	/workspace/coverage/default/17.uart_fifo_overflow.3601788137
Short name	T354
Test name
Test status
Simulation time	192619887053 ps
CPU time	269.72 seconds
Started	Feb 18 02:04:18 PM PST 24
Finished	Feb 18 02:08:51 PM PST 24
Peak memory	200100 kb
Host	smart-8306aede-2e78-46c8-a62a-69920279719e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3601788137 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_overflow.3601788137
Directory	/workspace/17.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/17.uart_fifo_reset.856195614
Short name	T101
Test name
Test status
Simulation time	17213122566 ps
CPU time	14.59 seconds
Started	Feb 18 02:04:16 PM PST 24
Finished	Feb 18 02:04:35 PM PST 24
Peak memory	199248 kb
Host	smart-81e331e7-df1c-4f04-b76a-1ae53f2eae61
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=856195614 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_reset.856195614
Directory	/workspace/17.uart_fifo_reset/latest

Test location	/workspace/coverage/default/17.uart_intr.429844202
Short name	T874
Test name
Test status
Simulation time	592643440751 ps
CPU time	1027.33 seconds
Started	Feb 18 02:04:17 PM PST 24
Finished	Feb 18 02:21:28 PM PST 24
Peak memory	199240 kb
Host	smart-b92aae28-e40e-4833-8782-8862a13efe5b
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429844202 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_intr.429844202
Directory	/workspace/17.uart_intr/latest

Test location	/workspace/coverage/default/17.uart_long_xfer_wo_dly.1163257568
Short name	T631
Test name
Test status
Simulation time	285407611409 ps
CPU time	225.07 seconds
Started	Feb 18 02:04:36 PM PST 24
Finished	Feb 18 02:08:25 PM PST 24
Peak memory	200008 kb
Host	smart-2ed4b7b2-f0c4-4f68-87b6-eecd04f08819
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1163257568 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_long_xfer_wo_dly.1163257568
Directory	/workspace/17.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/17.uart_loopback.3379781690
Short name	T695
Test name
Test status
Simulation time	2795469664 ps
CPU time	6.67 seconds
Started	Feb 18 02:04:24 PM PST 24
Finished	Feb 18 02:04:32 PM PST 24
Peak memory	198180 kb
Host	smart-aefa5924-35f0-4f48-b695-2b8de45e04b9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3379781690 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_loopback.3379781690
Directory	/workspace/17.uart_loopback/latest

Test location	/workspace/coverage/default/17.uart_noise_filter.834357465
Short name	T600
Test name
Test status
Simulation time	7086252508 ps
CPU time	13.23 seconds
Started	Feb 18 02:04:33 PM PST 24
Finished	Feb 18 02:04:49 PM PST 24
Peak memory	197480 kb
Host	smart-b2f584ed-a8a1-44d1-a7b3-1880a03ad45b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=834357465 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_noise_filter.834357465
Directory	/workspace/17.uart_noise_filter/latest

Test location	/workspace/coverage/default/17.uart_perf.2030932227
Short name	T426
Test name
Test status
Simulation time	14990280115 ps
CPU time	186.19 seconds
Started	Feb 18 02:04:21 PM PST 24
Finished	Feb 18 02:07:30 PM PST 24
Peak memory	200016 kb
Host	smart-61a43a6e-fdf6-46a4-84f1-cd50bdf647bc
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2030932227 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_perf.2030932227
Directory	/workspace/17.uart_perf/latest

Test location	/workspace/coverage/default/17.uart_rx_oversample.2780894198
Short name	T1014
Test name
Test status
Simulation time	2354030453 ps
CPU time	6.72 seconds
Started	Feb 18 02:04:26 PM PST 24
Finished	Feb 18 02:04:36 PM PST 24
Peak memory	198612 kb
Host	smart-fb42eabc-9217-488a-9cfa-496591b6646d
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2780894198 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_oversample.2780894198
Directory	/workspace/17.uart_rx_oversample/latest

Test location	/workspace/coverage/default/17.uart_rx_parity_err.1843551773
Short name	T701
Test name
Test status
Simulation time	20481747421 ps
CPU time	30.25 seconds
Started	Feb 18 02:04:19 PM PST 24
Finished	Feb 18 02:04:52 PM PST 24
Peak memory	198596 kb
Host	smart-a8b4397f-ee52-478c-a301-e682490193a3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1843551773 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_parity_err.1843551773
Directory	/workspace/17.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/17.uart_rx_start_bit_filter.67670547
Short name	T964
Test name
Test status
Simulation time	4834251465 ps
CPU time	2.47 seconds
Started	Feb 18 02:04:23 PM PST 24
Finished	Feb 18 02:04:28 PM PST 24
Peak memory	195872 kb
Host	smart-ddc9ebb7-c094-4cf6-8291-1a2abc508c1b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=67670547 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_start_bit_filter.67670547
Directory	/workspace/17.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/17.uart_smoke.3681697905
Short name	T490
Test name
Test status
Simulation time	487512542 ps
CPU time	1.45 seconds
Started	Feb 18 02:04:35 PM PST 24
Finished	Feb 18 02:04:40 PM PST 24
Peak memory	197876 kb
Host	smart-89697b5b-d254-4b34-bb8e-0cd545e3b117
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3681697905 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_smoke.3681697905
Directory	/workspace/17.uart_smoke/latest

Test location	/workspace/coverage/default/17.uart_tx_ovrd.645892388
Short name	T920
Test name
Test status
Simulation time	7342626403 ps
CPU time	12.25 seconds
Started	Feb 18 02:04:20 PM PST 24
Finished	Feb 18 02:04:36 PM PST 24
Peak memory	199292 kb
Host	smart-9e345548-0d1b-492e-83b2-f89842370c3d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=645892388 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_ovrd.645892388
Directory	/workspace/17.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/17.uart_tx_rx.2245080459
Short name	T633
Test name
Test status
Simulation time	55845835336 ps
CPU time	27.96 seconds
Started	Feb 18 02:04:23 PM PST 24
Finished	Feb 18 02:04:53 PM PST 24
Peak memory	200012 kb
Host	smart-c51a9eff-5fc7-464d-b545-09a752941623
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2245080459 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_rx.2245080459
Directory	/workspace/17.uart_tx_rx/latest

Test location	/workspace/coverage/default/171.uart_fifo_reset.78789562
Short name	T602
Test name
Test status
Simulation time	10635211749 ps
CPU time	13.84 seconds
Started	Feb 18 02:07:45 PM PST 24
Finished	Feb 18 02:08:02 PM PST 24
Peak memory	200064 kb
Host	smart-4bf66f98-5e19-4237-94fb-cad766fe2d95
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=78789562 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.uart_fifo_reset.78789562
Directory	/workspace/171.uart_fifo_reset/latest

Test location	/workspace/coverage/default/172.uart_fifo_reset.2033585006
Short name	T295
Test name
Test status
Simulation time	103801258895 ps
CPU time	161.41 seconds
Started	Feb 18 02:07:51 PM PST 24
Finished	Feb 18 02:10:37 PM PST 24
Peak memory	199612 kb
Host	smart-a6d1b8c8-c451-4c82-b9b7-af7102306f89
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2033585006 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.uart_fifo_reset.2033585006
Directory	/workspace/172.uart_fifo_reset/latest

Test location	/workspace/coverage/default/173.uart_fifo_reset.1320134787
Short name	T1111
Test name
Test status
Simulation time	91882383200 ps
CPU time	75.66 seconds
Started	Feb 18 02:07:45 PM PST 24
Finished	Feb 18 02:09:03 PM PST 24
Peak memory	200036 kb
Host	smart-076dbded-be2b-40a1-a636-3967a3d4bbc7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1320134787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.uart_fifo_reset.1320134787
Directory	/workspace/173.uart_fifo_reset/latest

Test location	/workspace/coverage/default/174.uart_fifo_reset.1938353626
Short name	T1115
Test name
Test status
Simulation time	25923637430 ps
CPU time	6.6 seconds
Started	Feb 18 02:07:47 PM PST 24
Finished	Feb 18 02:07:55 PM PST 24
Peak memory	199784 kb
Host	smart-2e547d9f-8c5a-4eaa-a5cd-fc6db55b751d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1938353626 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.uart_fifo_reset.1938353626
Directory	/workspace/174.uart_fifo_reset/latest

Test location	/workspace/coverage/default/175.uart_fifo_reset.2482899554
Short name	T1041
Test name
Test status
Simulation time	83469992527 ps
CPU time	36.43 seconds
Started	Feb 18 02:07:52 PM PST 24
Finished	Feb 18 02:08:34 PM PST 24
Peak memory	199376 kb
Host	smart-3bda35f9-e57f-4119-a898-8822f1a97625
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2482899554 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.uart_fifo_reset.2482899554
Directory	/workspace/175.uart_fifo_reset/latest

Test location	/workspace/coverage/default/177.uart_fifo_reset.1160823935
Short name	T975
Test name
Test status
Simulation time	188322085928 ps
CPU time	18.53 seconds
Started	Feb 18 02:07:54 PM PST 24
Finished	Feb 18 02:08:17 PM PST 24
Peak memory	200056 kb
Host	smart-f9e6fc50-36b5-4683-afab-e2e861a8ddea
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1160823935 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.uart_fifo_reset.1160823935
Directory	/workspace/177.uart_fifo_reset/latest

Test location	/workspace/coverage/default/178.uart_fifo_reset.987886875
Short name	T305
Test name
Test status
Simulation time	20915619378 ps
CPU time	18.61 seconds
Started	Feb 18 02:07:56 PM PST 24
Finished	Feb 18 02:08:18 PM PST 24
Peak memory	199636 kb
Host	smart-51234568-c0b5-4508-92a9-6d457a4e07e1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=987886875 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.uart_fifo_reset.987886875
Directory	/workspace/178.uart_fifo_reset/latest

Test location	/workspace/coverage/default/179.uart_fifo_reset.2913392326
Short name	T884
Test name
Test status
Simulation time	167339254476 ps
CPU time	63.73 seconds
Started	Feb 18 02:07:53 PM PST 24
Finished	Feb 18 02:09:02 PM PST 24
Peak memory	200120 kb
Host	smart-371b6982-3678-40ce-81f8-d696f03fbacf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2913392326 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.uart_fifo_reset.2913392326
Directory	/workspace/179.uart_fifo_reset/latest

Test location	/workspace/coverage/default/18.uart_alert_test.1488975864
Short name	T611
Test name
Test status
Simulation time	13440180 ps
CPU time	0.56 seconds
Started	Feb 18 02:04:31 PM PST 24
Finished	Feb 18 02:04:34 PM PST 24
Peak memory	195524 kb
Host	smart-98a8c408-330c-4230-ab75-f4d2dd7e1ce0
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488975864 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_alert_test.1488975864
Directory	/workspace/18.uart_alert_test/latest

Test location	/workspace/coverage/default/18.uart_fifo_full.3431482994
Short name	T899
Test name
Test status
Simulation time	32338442709 ps
CPU time	52.88 seconds
Started	Feb 18 02:04:34 PM PST 24
Finished	Feb 18 02:05:31 PM PST 24
Peak memory	200056 kb
Host	smart-5098519f-268b-4a1d-9da5-2da2a1d495df
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3431482994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_full.3431482994
Directory	/workspace/18.uart_fifo_full/latest

Test location	/workspace/coverage/default/18.uart_fifo_overflow.3661484954
Short name	T896
Test name
Test status
Simulation time	40863893531 ps
CPU time	18.29 seconds
Started	Feb 18 02:04:34 PM PST 24
Finished	Feb 18 02:04:55 PM PST 24
Peak memory	200056 kb
Host	smart-de7610d0-f5eb-4749-a379-846b26634348
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3661484954 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_overflow.3661484954
Directory	/workspace/18.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/18.uart_fifo_reset.1630459007
Short name	T227
Test name
Test status
Simulation time	296039658665 ps
CPU time	325.51 seconds
Started	Feb 18 02:04:24 PM PST 24
Finished	Feb 18 02:09:51 PM PST 24
Peak memory	200080 kb
Host	smart-c1c9c7a1-3655-4256-bdf3-6e2c6c811aec
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1630459007 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_reset.1630459007
Directory	/workspace/18.uart_fifo_reset/latest

Test location	/workspace/coverage/default/18.uart_intr.192742312
Short name	T1076
Test name
Test status
Simulation time	247301007055 ps
CPU time	44.54 seconds
Started	Feb 18 02:04:24 PM PST 24
Finished	Feb 18 02:05:10 PM PST 24
Peak memory	200004 kb
Host	smart-de492bb5-4ee9-438d-a419-a3ede6a5f8bc
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192742312 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_intr.192742312
Directory	/workspace/18.uart_intr/latest

Test location	/workspace/coverage/default/18.uart_long_xfer_wo_dly.1349542492
Short name	T55
Test name
Test status
Simulation time	121185976387 ps
CPU time	69.96 seconds
Started	Feb 18 02:04:24 PM PST 24
Finished	Feb 18 02:05:36 PM PST 24
Peak memory	200068 kb
Host	smart-968be38b-ef3a-43c0-af89-3d35b25a7458
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1349542492 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_long_xfer_wo_dly.1349542492
Directory	/workspace/18.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/18.uart_loopback.2856728816
Short name	T809
Test name
Test status
Simulation time	7029977965 ps
CPU time	12.68 seconds
Started	Feb 18 02:04:25 PM PST 24
Finished	Feb 18 02:04:39 PM PST 24
Peak memory	199948 kb
Host	smart-3d53eda7-7b58-4319-81c8-b4cb8a329491
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2856728816 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_loopback.2856728816
Directory	/workspace/18.uart_loopback/latest

Test location	/workspace/coverage/default/18.uart_noise_filter.3107822361
Short name	T776
Test name
Test status
Simulation time	38678549656 ps
CPU time	91.74 seconds
Started	Feb 18 02:04:32 PM PST 24
Finished	Feb 18 02:06:07 PM PST 24
Peak memory	200284 kb
Host	smart-3ad81823-cb81-4878-b9b4-6aefe60133da
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3107822361 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_noise_filter.3107822361
Directory	/workspace/18.uart_noise_filter/latest

Test location	/workspace/coverage/default/18.uart_perf.1210460631
Short name	T468
Test name
Test status
Simulation time	11253416876 ps
CPU time	539.41 seconds
Started	Feb 18 02:04:37 PM PST 24
Finished	Feb 18 02:13:40 PM PST 24
Peak memory	200096 kb
Host	smart-abb5d60c-65a3-42ba-852a-12c57cbe2332
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1210460631 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_perf.1210460631
Directory	/workspace/18.uart_perf/latest

Test location	/workspace/coverage/default/18.uart_rx_oversample.3195864111
Short name	T806
Test name
Test status
Simulation time	2354185476 ps
CPU time	14.18 seconds
Started	Feb 18 02:04:34 PM PST 24
Finished	Feb 18 02:04:51 PM PST 24
Peak memory	198360 kb
Host	smart-e83bd4c1-4625-44d5-a610-4aa0afbba1f1
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3195864111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_oversample.3195864111
Directory	/workspace/18.uart_rx_oversample/latest

Test location	/workspace/coverage/default/18.uart_rx_parity_err.393900215
Short name	T406
Test name
Test status
Simulation time	440482099980 ps
CPU time	57.61 seconds
Started	Feb 18 02:04:39 PM PST 24
Finished	Feb 18 02:05:40 PM PST 24
Peak memory	199940 kb
Host	smart-153315d3-ac23-4382-ad4c-fdb52fcc5f0c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=393900215 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_parity_err.393900215
Directory	/workspace/18.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/18.uart_rx_start_bit_filter.3413510844
Short name	T1077
Test name
Test status
Simulation time	4994249992 ps
CPU time	7.23 seconds
Started	Feb 18 02:04:37 PM PST 24
Finished	Feb 18 02:04:48 PM PST 24
Peak memory	195800 kb
Host	smart-b95b76e3-7dfb-4851-bde6-5992536f8272
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3413510844 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_start_bit_filter.3413510844
Directory	/workspace/18.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/18.uart_smoke.90079589
Short name	T1045
Test name
Test status
Simulation time	692410812 ps
CPU time	2.43 seconds
Started	Feb 18 02:04:32 PM PST 24
Finished	Feb 18 02:04:37 PM PST 24
Peak memory	198492 kb
Host	smart-ee6f52d7-10b6-4db2-983b-7c84cae19987
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=90079589 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_smoke.90079589
Directory	/workspace/18.uart_smoke/latest

Test location	/workspace/coverage/default/18.uart_stress_all.3755726768
Short name	T820
Test name
Test status
Simulation time	300509064818 ps
CPU time	1322.02 seconds
Started	Feb 18 02:04:34 PM PST 24
Finished	Feb 18 02:26:39 PM PST 24
Peak memory	208316 kb
Host	smart-3b72216a-44b9-478e-afea-045f554767fb
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755726768 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_stress_all.3755726768
Directory	/workspace/18.uart_stress_all/latest

Test location	/workspace/coverage/default/18.uart_stress_all_with_rand_reset.2468592149
Short name	T38
Test name
Test status
Simulation time	70122789988 ps
CPU time	215.21 seconds
Started	Feb 18 02:04:34 PM PST 24
Finished	Feb 18 02:08:12 PM PST 24
Peak memory	216760 kb
Host	smart-c23a9b27-d0c0-43f3-ba3f-4ca0e4eaff35
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468592149 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 18.uart_stress_all_with_rand_reset.2468592149
Directory	/workspace/18.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/18.uart_tx_ovrd.3249139637
Short name	T990
Test name
Test status
Simulation time	329628393 ps
CPU time	2.29 seconds
Started	Feb 18 02:04:33 PM PST 24
Finished	Feb 18 02:04:38 PM PST 24
Peak memory	198076 kb
Host	smart-24838e8a-9119-4288-875f-e0a9d646817f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3249139637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_ovrd.3249139637
Directory	/workspace/18.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/18.uart_tx_rx.1043149378
Short name	T396
Test name
Test status
Simulation time	55858198462 ps
CPU time	31.57 seconds
Started	Feb 18 02:04:33 PM PST 24
Finished	Feb 18 02:05:07 PM PST 24
Peak memory	200124 kb
Host	smart-e3059bd9-a0b3-4795-bf8a-741f40b12caa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1043149378 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_rx.1043149378
Directory	/workspace/18.uart_tx_rx/latest

Test location	/workspace/coverage/default/180.uart_fifo_reset.431467715
Short name	T1007
Test name
Test status
Simulation time	81871057992 ps
CPU time	35.5 seconds
Started	Feb 18 02:07:53 PM PST 24
Finished	Feb 18 02:08:33 PM PST 24
Peak memory	200012 kb
Host	smart-1c92fca7-6fc0-426d-93f3-6dc0b98b0e7c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=431467715 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.uart_fifo_reset.431467715
Directory	/workspace/180.uart_fifo_reset/latest

Test location	/workspace/coverage/default/181.uart_fifo_reset.3236913641
Short name	T875
Test name
Test status
Simulation time	128527318708 ps
CPU time	87.18 seconds
Started	Feb 18 02:07:50 PM PST 24
Finished	Feb 18 02:09:18 PM PST 24
Peak memory	199996 kb
Host	smart-5010049f-fe12-40fd-b4f7-de08c5163e92
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3236913641 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.uart_fifo_reset.3236913641
Directory	/workspace/181.uart_fifo_reset/latest

Test location	/workspace/coverage/default/182.uart_fifo_reset.1882387028
Short name	T316
Test name
Test status
Simulation time	157879137476 ps
CPU time	86.57 seconds
Started	Feb 18 02:07:55 PM PST 24
Finished	Feb 18 02:09:25 PM PST 24
Peak memory	200108 kb
Host	smart-b271fea7-d738-4e5a-b03e-936a849857dd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1882387028 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.uart_fifo_reset.1882387028
Directory	/workspace/182.uart_fifo_reset/latest

Test location	/workspace/coverage/default/183.uart_fifo_reset.2031266258
Short name	T1091
Test name
Test status
Simulation time	4615107498 ps
CPU time	7.52 seconds
Started	Feb 18 02:07:56 PM PST 24
Finished	Feb 18 02:08:07 PM PST 24
Peak memory	198260 kb
Host	smart-8f4ef581-c649-400f-9e84-351767f4928b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2031266258 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.uart_fifo_reset.2031266258
Directory	/workspace/183.uart_fifo_reset/latest

Test location	/workspace/coverage/default/184.uart_fifo_reset.3486694520
Short name	T114
Test name
Test status
Simulation time	26321705868 ps
CPU time	37.11 seconds
Started	Feb 18 02:07:54 PM PST 24
Finished	Feb 18 02:08:35 PM PST 24
Peak memory	200028 kb
Host	smart-c3ddd96f-34a4-4380-8356-f517d1f8e599
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3486694520 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.uart_fifo_reset.3486694520
Directory	/workspace/184.uart_fifo_reset/latest

Test location	/workspace/coverage/default/185.uart_fifo_reset.2802061110
Short name	T1012
Test name
Test status
Simulation time	64976666311 ps
CPU time	65.45 seconds
Started	Feb 18 02:07:54 PM PST 24
Finished	Feb 18 02:09:04 PM PST 24
Peak memory	200028 kb
Host	smart-1877ac3d-afad-49c1-9957-7035621677a4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2802061110 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.uart_fifo_reset.2802061110
Directory	/workspace/185.uart_fifo_reset/latest

Test location	/workspace/coverage/default/186.uart_fifo_reset.1858939076
Short name	T300
Test name
Test status
Simulation time	67327658262 ps
CPU time	108.43 seconds
Started	Feb 18 02:07:55 PM PST 24
Finished	Feb 18 02:09:47 PM PST 24
Peak memory	200120 kb
Host	smart-840c069c-b835-48cd-9cf2-1c3016cfdbcb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1858939076 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.uart_fifo_reset.1858939076
Directory	/workspace/186.uart_fifo_reset/latest

Test location	/workspace/coverage/default/187.uart_fifo_reset.1514102445
Short name	T1089
Test name
Test status
Simulation time	92831060962 ps
CPU time	154.18 seconds
Started	Feb 18 02:07:47 PM PST 24
Finished	Feb 18 02:10:23 PM PST 24
Peak memory	199832 kb
Host	smart-a4bf30c1-babe-4b0d-a533-ecf9fb909d4b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1514102445 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.uart_fifo_reset.1514102445
Directory	/workspace/187.uart_fifo_reset/latest

Test location	/workspace/coverage/default/188.uart_fifo_reset.2756498808
Short name	T778
Test name
Test status
Simulation time	22283968231 ps
CPU time	21.07 seconds
Started	Feb 18 02:07:55 PM PST 24
Finished	Feb 18 02:08:20 PM PST 24
Peak memory	199500 kb
Host	smart-a6d3fa59-a8b7-4100-8460-d998a6ee1649
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2756498808 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.uart_fifo_reset.2756498808
Directory	/workspace/188.uart_fifo_reset/latest

Test location	/workspace/coverage/default/189.uart_fifo_reset.1446914046
Short name	T159
Test name
Test status
Simulation time	100480332285 ps
CPU time	147.95 seconds
Started	Feb 18 02:07:51 PM PST 24
Finished	Feb 18 02:10:24 PM PST 24
Peak memory	200088 kb
Host	smart-5cec88d9-3c1b-4eac-a6f0-80000531a92f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1446914046 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.uart_fifo_reset.1446914046
Directory	/workspace/189.uart_fifo_reset/latest

Test location	/workspace/coverage/default/19.uart_alert_test.2563838660
Short name	T930
Test name
Test status
Simulation time	51195808 ps
CPU time	0.56 seconds
Started	Feb 18 02:04:35 PM PST 24
Finished	Feb 18 02:04:40 PM PST 24
Peak memory	195444 kb
Host	smart-d7bc8a46-c6dc-4781-8fa9-acb83bd0f6ef
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563838660 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_alert_test.2563838660
Directory	/workspace/19.uart_alert_test/latest

Test location	/workspace/coverage/default/19.uart_fifo_overflow.998150518
Short name	T341
Test name
Test status
Simulation time	44569720405 ps
CPU time	56.28 seconds
Started	Feb 18 02:04:23 PM PST 24
Finished	Feb 18 02:05:22 PM PST 24
Peak memory	200084 kb
Host	smart-117687e3-8815-4b53-8963-de2c336a057c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=998150518 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_overflow.998150518
Directory	/workspace/19.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/19.uart_fifo_reset.1233850824
Short name	T303
Test name
Test status
Simulation time	34034271345 ps
CPU time	30.76 seconds
Started	Feb 18 02:04:25 PM PST 24
Finished	Feb 18 02:04:59 PM PST 24
Peak memory	200120 kb
Host	smart-62efda3f-c318-4997-8f05-5c1f0abdf565
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1233850824 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_reset.1233850824
Directory	/workspace/19.uart_fifo_reset/latest

Test location	/workspace/coverage/default/19.uart_intr.3956923190
Short name	T978
Test name
Test status
Simulation time	467837161211 ps
CPU time	293.47 seconds
Started	Feb 18 02:04:40 PM PST 24
Finished	Feb 18 02:09:37 PM PST 24
Peak memory	200040 kb
Host	smart-20168855-a901-4b3f-aba7-c1e322ef3d4f
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956923190 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_intr.3956923190
Directory	/workspace/19.uart_intr/latest

Test location	/workspace/coverage/default/19.uart_long_xfer_wo_dly.2939204822
Short name	T291
Test name
Test status
Simulation time	77302129545 ps
CPU time	267.99 seconds
Started	Feb 18 02:04:35 PM PST 24
Finished	Feb 18 02:09:06 PM PST 24
Peak memory	200136 kb
Host	smart-c665de16-55a1-4263-a660-85ae2ad0036f
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2939204822 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_long_xfer_wo_dly.2939204822
Directory	/workspace/19.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/19.uart_loopback.4245212132
Short name	T444
Test name
Test status
Simulation time	3998049789 ps
CPU time	7.29 seconds
Started	Feb 18 02:04:36 PM PST 24
Finished	Feb 18 02:04:47 PM PST 24
Peak memory	197400 kb
Host	smart-a5892d84-9893-4069-85bc-0d5a5a6d2bac
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4245212132 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_loopback.4245212132
Directory	/workspace/19.uart_loopback/latest

Test location	/workspace/coverage/default/19.uart_perf.2378503365
Short name	T962
Test name
Test status
Simulation time	25714665003 ps
CPU time	1279 seconds
Started	Feb 18 02:04:35 PM PST 24
Finished	Feb 18 02:25:58 PM PST 24
Peak memory	200092 kb
Host	smart-18b7cc16-693a-40d2-b43a-7dfee19e2f9d
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2378503365 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_perf.2378503365
Directory	/workspace/19.uart_perf/latest

Test location	/workspace/coverage/default/19.uart_rx_oversample.2685304110
Short name	T963
Test name
Test status
Simulation time	3750728219 ps
CPU time	14.74 seconds
Started	Feb 18 02:04:33 PM PST 24
Finished	Feb 18 02:04:51 PM PST 24
Peak memory	198468 kb
Host	smart-78633d94-6ff2-4268-9fd3-cdc756e490bd
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2685304110 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_oversample.2685304110
Directory	/workspace/19.uart_rx_oversample/latest

Test location	/workspace/coverage/default/19.uart_rx_parity_err.3492689613
Short name	T859
Test name
Test status
Simulation time	49823839710 ps
CPU time	33.68 seconds
Started	Feb 18 02:04:37 PM PST 24
Finished	Feb 18 02:05:14 PM PST 24
Peak memory	199400 kb
Host	smart-75ba0410-b607-47af-89c3-e55dc7ef2e40
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3492689613 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_parity_err.3492689613
Directory	/workspace/19.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/19.uart_rx_start_bit_filter.172907187
Short name	T463
Test name
Test status
Simulation time	2196929980 ps
CPU time	3.6 seconds
Started	Feb 18 02:04:35 PM PST 24
Finished	Feb 18 02:04:42 PM PST 24
Peak memory	195408 kb
Host	smart-fd24f054-a803-4f62-bd9b-11d774b609d1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=172907187 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_start_bit_filter.172907187
Directory	/workspace/19.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/19.uart_smoke.1784421483
Short name	T932
Test name
Test status
Simulation time	6197000299 ps
CPU time	12.83 seconds
Started	Feb 18 02:04:37 PM PST 24
Finished	Feb 18 02:04:54 PM PST 24
Peak memory	199444 kb
Host	smart-31b920b0-d5ff-46ec-9e23-b0ec211effba
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1784421483 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_smoke.1784421483
Directory	/workspace/19.uart_smoke/latest

Test location	/workspace/coverage/default/19.uart_stress_all.2662153924
Short name	T492
Test name
Test status
Simulation time	56822226579 ps
CPU time	43.65 seconds
Started	Feb 18 02:04:35 PM PST 24
Finished	Feb 18 02:05:22 PM PST 24
Peak memory	199936 kb
Host	smart-864850d4-e061-462a-9ebc-fbcfd106c641
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662153924 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_stress_all.2662153924
Directory	/workspace/19.uart_stress_all/latest

Test location	/workspace/coverage/default/19.uart_stress_all_with_rand_reset.3695551245
Short name	T395
Test name
Test status
Simulation time	115152157201 ps
CPU time	736.37 seconds
Started	Feb 18 02:04:37 PM PST 24
Finished	Feb 18 02:16:57 PM PST 24
Peak memory	216560 kb
Host	smart-ee2392fb-0843-48da-90ad-524025c6c60d
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695551245 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 19.uart_stress_all_with_rand_reset.3695551245
Directory	/workspace/19.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/19.uart_tx_ovrd.362863502
Short name	T730
Test name
Test status
Simulation time	978769278 ps
CPU time	2.94 seconds
Started	Feb 18 02:04:36 PM PST 24
Finished	Feb 18 02:04:42 PM PST 24
Peak memory	198016 kb
Host	smart-ae999911-9b80-49fa-b5b1-ac236866595c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=362863502 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_ovrd.362863502
Directory	/workspace/19.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/19.uart_tx_rx.1913784425
Short name	T427
Test name
Test status
Simulation time	107186516992 ps
CPU time	233.05 seconds
Started	Feb 18 02:04:24 PM PST 24
Finished	Feb 18 02:08:19 PM PST 24
Peak memory	200108 kb
Host	smart-d852eb2b-0f3c-4eeb-aa9b-1d463d07be5d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1913784425 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_rx.1913784425
Directory	/workspace/19.uart_tx_rx/latest

Test location	/workspace/coverage/default/190.uart_fifo_reset.423410222
Short name	T134
Test name
Test status
Simulation time	111791811858 ps
CPU time	95.37 seconds
Started	Feb 18 02:07:52 PM PST 24
Finished	Feb 18 02:09:32 PM PST 24
Peak memory	200116 kb
Host	smart-6aa2e5b7-61f4-4966-8f71-9f52855b76cc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=423410222 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.uart_fifo_reset.423410222
Directory	/workspace/190.uart_fifo_reset/latest

Test location	/workspace/coverage/default/191.uart_fifo_reset.4155128623
Short name	T267
Test name
Test status
Simulation time	23800970509 ps
CPU time	12.95 seconds
Started	Feb 18 02:08:02 PM PST 24
Finished	Feb 18 02:08:17 PM PST 24
Peak memory	200032 kb
Host	smart-97912528-328e-48eb-8d48-9d85ab1b5c31
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4155128623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.uart_fifo_reset.4155128623
Directory	/workspace/191.uart_fifo_reset/latest

Test location	/workspace/coverage/default/192.uart_fifo_reset.1735356347
Short name	T789
Test name
Test status
Simulation time	110161772546 ps
CPU time	21.88 seconds
Started	Feb 18 02:08:03 PM PST 24
Finished	Feb 18 02:08:26 PM PST 24
Peak memory	200036 kb
Host	smart-4197a923-350f-4cd7-9947-629291d769a6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1735356347 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.uart_fifo_reset.1735356347
Directory	/workspace/192.uart_fifo_reset/latest

Test location	/workspace/coverage/default/193.uart_fifo_reset.2630050673
Short name	T782
Test name
Test status
Simulation time	21425861137 ps
CPU time	8.82 seconds
Started	Feb 18 02:08:03 PM PST 24
Finished	Feb 18 02:08:13 PM PST 24
Peak memory	199844 kb
Host	smart-4a7766bb-b671-4cc3-9e53-c8d40810ac90
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2630050673 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.uart_fifo_reset.2630050673
Directory	/workspace/193.uart_fifo_reset/latest

Test location	/workspace/coverage/default/194.uart_fifo_reset.2332572550
Short name	T976
Test name
Test status
Simulation time	18360020344 ps
CPU time	43.12 seconds
Started	Feb 18 02:08:03 PM PST 24
Finished	Feb 18 02:08:48 PM PST 24
Peak memory	200112 kb
Host	smart-15dbf7e3-2e2d-4f9d-83ae-1b925cac982a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2332572550 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.uart_fifo_reset.2332572550
Directory	/workspace/194.uart_fifo_reset/latest

Test location	/workspace/coverage/default/196.uart_fifo_reset.1811843350
Short name	T825
Test name
Test status
Simulation time	28645505027 ps
CPU time	46.03 seconds
Started	Feb 18 02:08:05 PM PST 24
Finished	Feb 18 02:08:52 PM PST 24
Peak memory	200028 kb
Host	smart-c51de0eb-fd29-425b-92e1-ba01d15be181
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1811843350 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.uart_fifo_reset.1811843350
Directory	/workspace/196.uart_fifo_reset/latest

Test location	/workspace/coverage/default/199.uart_fifo_reset.4018472471
Short name	T132
Test name
Test status
Simulation time	186198278369 ps
CPU time	108.13 seconds
Started	Feb 18 02:08:05 PM PST 24
Finished	Feb 18 02:09:56 PM PST 24
Peak memory	200124 kb
Host	smart-9bc79225-dab8-4026-b623-edc9ef6b3a01
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4018472471 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.uart_fifo_reset.4018472471
Directory	/workspace/199.uart_fifo_reset/latest

Test location	/workspace/coverage/default/2.uart_alert_test.624109900
Short name	T567
Test name
Test status
Simulation time	11299501 ps
CPU time	0.61 seconds
Started	Feb 18 02:03:32 PM PST 24
Finished	Feb 18 02:03:42 PM PST 24
Peak memory	195524 kb
Host	smart-ccd841bf-3d13-45e0-b31e-a3bfdc0a62c8
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624109900 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_alert_test.624109900
Directory	/workspace/2.uart_alert_test/latest

Test location	/workspace/coverage/default/2.uart_fifo_full.3866174504
Short name	T1056
Test name
Test status
Simulation time	120475953643 ps
CPU time	45.02 seconds
Started	Feb 18 02:03:27 PM PST 24
Finished	Feb 18 02:04:14 PM PST 24
Peak memory	200060 kb
Host	smart-b5cf6c3e-286a-48a9-be69-10595bcf5c1a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3866174504 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_full.3866174504
Directory	/workspace/2.uart_fifo_full/latest

Test location	/workspace/coverage/default/2.uart_fifo_overflow.2530084124
Short name	T667
Test name
Test status
Simulation time	26723517863 ps
CPU time	19.95 seconds
Started	Feb 18 02:03:33 PM PST 24
Finished	Feb 18 02:04:02 PM PST 24
Peak memory	198948 kb
Host	smart-ff26cb79-ac8c-497a-ba78-a2c15d1ddeed
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2530084124 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_overflow.2530084124
Directory	/workspace/2.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/2.uart_intr.1563752390
Short name	T715
Test name
Test status
Simulation time	824713117813 ps
CPU time	714.1 seconds
Started	Feb 18 02:03:32 PM PST 24
Finished	Feb 18 02:15:30 PM PST 24
Peak memory	199244 kb
Host	smart-8880111b-c66f-4ad8-b44e-f5f62d78e7ea
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563752390 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_intr.1563752390
Directory	/workspace/2.uart_intr/latest

Test location	/workspace/coverage/default/2.uart_long_xfer_wo_dly.2024417833
Short name	T51
Test name
Test status
Simulation time	150352026994 ps
CPU time	660.61 seconds
Started	Feb 18 02:03:32 PM PST 24
Finished	Feb 18 02:14:35 PM PST 24
Peak memory	200052 kb
Host	smart-05747f88-ceca-4099-b05a-ad2b0ff9d3f8
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2024417833 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_long_xfer_wo_dly.2024417833
Directory	/workspace/2.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/2.uart_loopback.4079539537
Short name	T466
Test name
Test status
Simulation time	538830796 ps
CPU time	1.93 seconds
Started	Feb 18 02:03:28 PM PST 24
Finished	Feb 18 02:03:31 PM PST 24
Peak memory	197440 kb
Host	smart-144008eb-b307-4cef-84de-6db0d6474fcd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4079539537 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_loopback.4079539537
Directory	/workspace/2.uart_loopback/latest

Test location	/workspace/coverage/default/2.uart_noise_filter.3796243944
Short name	T106
Test name
Test status
Simulation time	50130578273 ps
CPU time	74.04 seconds
Started	Feb 18 02:03:33 PM PST 24
Finished	Feb 18 02:04:56 PM PST 24
Peak memory	197096 kb
Host	smart-6cb0f88c-8b27-40c2-82af-481dd345cb99
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3796243944 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_noise_filter.3796243944
Directory	/workspace/2.uart_noise_filter/latest

Test location	/workspace/coverage/default/2.uart_perf.1982015980
Short name	T488
Test name
Test status
Simulation time	14183888922 ps
CPU time	661.77 seconds
Started	Feb 18 02:03:32 PM PST 24
Finished	Feb 18 02:14:37 PM PST 24
Peak memory	200080 kb
Host	smart-8148c90d-f5e0-4c66-af9d-5add4670ad87
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1982015980 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_perf.1982015980
Directory	/workspace/2.uart_perf/latest

Test location	/workspace/coverage/default/2.uart_rx_oversample.681608241
Short name	T644
Test name
Test status
Simulation time	1643105921 ps
CPU time	2.63 seconds
Started	Feb 18 02:03:26 PM PST 24
Finished	Feb 18 02:03:31 PM PST 24
Peak memory	198192 kb
Host	smart-54a23f9c-3c12-42eb-a9f7-5038fe097534
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=681608241 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_oversample.681608241
Directory	/workspace/2.uart_rx_oversample/latest

Test location	/workspace/coverage/default/2.uart_rx_parity_err.3219777154
Short name	T280
Test name
Test status
Simulation time	52917337108 ps
CPU time	66.64 seconds
Started	Feb 18 02:03:32 PM PST 24
Finished	Feb 18 02:04:43 PM PST 24
Peak memory	200052 kb
Host	smart-4441372e-f3dc-475e-85c3-ee4c63ad14da
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3219777154 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_parity_err.3219777154
Directory	/workspace/2.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/2.uart_rx_start_bit_filter.1114303334
Short name	T532
Test name
Test status
Simulation time	4713715429 ps
CPU time	2.77 seconds
Started	Feb 18 02:03:32 PM PST 24
Finished	Feb 18 02:03:43 PM PST 24
Peak memory	195796 kb
Host	smart-a2bb273c-c6a3-4702-9d6c-5cbd0ee1f3b2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1114303334 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_start_bit_filter.1114303334
Directory	/workspace/2.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/2.uart_sec_cm.575389000
Short name	T86
Test name
Test status
Simulation time	234772782 ps
CPU time	0.87 seconds
Started	Feb 18 02:03:36 PM PST 24
Finished	Feb 18 02:03:50 PM PST 24
Peak memory	217248 kb
Host	smart-7822d201-7ee4-409b-a63a-5b7cec79d874
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575389000 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_sec_cm.575389000
Directory	/workspace/2.uart_sec_cm/latest

Test location	/workspace/coverage/default/2.uart_smoke.1628138472
Short name	T960
Test name
Test status
Simulation time	5469215147 ps
CPU time	20.99 seconds
Started	Feb 18 02:03:33 PM PST 24
Finished	Feb 18 02:04:03 PM PST 24
Peak memory	199632 kb
Host	smart-310e62e6-7d3e-4f8c-91a2-3d3f6a8eec92
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1628138472 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_smoke.1628138472
Directory	/workspace/2.uart_smoke/latest

Test location	/workspace/coverage/default/2.uart_tx_ovrd.3565324781
Short name	T529
Test name
Test status
Simulation time	553161905 ps
CPU time	2.04 seconds
Started	Feb 18 02:03:32 PM PST 24
Finished	Feb 18 02:03:38 PM PST 24
Peak memory	198020 kb
Host	smart-817d49bd-70ea-4e63-9a1f-ba7554e6e1c0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3565324781 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_ovrd.3565324781
Directory	/workspace/2.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/2.uart_tx_rx.3274831875
Short name	T563
Test name
Test status
Simulation time	9322726611 ps
CPU time	15.42 seconds
Started	Feb 18 02:03:31 PM PST 24
Finished	Feb 18 02:03:47 PM PST 24
Peak memory	199708 kb
Host	smart-d686cb39-cc31-4859-ab7e-5fc2b52f1824
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3274831875 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_rx.3274831875
Directory	/workspace/2.uart_tx_rx/latest

Test location	/workspace/coverage/default/20.uart_alert_test.1377401888
Short name	T1006
Test name
Test status
Simulation time	31723120 ps
CPU time	0.53 seconds
Started	Feb 18 02:04:41 PM PST 24
Finished	Feb 18 02:04:46 PM PST 24
Peak memory	194480 kb
Host	smart-0007f46c-f6b4-4eac-84a4-9e67aee38d0c
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377401888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_alert_test.1377401888
Directory	/workspace/20.uart_alert_test/latest

Test location	/workspace/coverage/default/20.uart_fifo_full.3855736931
Short name	T868
Test name
Test status
Simulation time	106358544266 ps
CPU time	154.5 seconds
Started	Feb 18 02:04:35 PM PST 24
Finished	Feb 18 02:07:14 PM PST 24
Peak memory	200000 kb
Host	smart-7861f9a8-2b23-4668-a261-201184bc0850
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3855736931 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_full.3855736931
Directory	/workspace/20.uart_fifo_full/latest

Test location	/workspace/coverage/default/20.uart_fifo_overflow.1846797837
Short name	T911
Test name
Test status
Simulation time	88996320341 ps
CPU time	74.12 seconds
Started	Feb 18 02:04:34 PM PST 24
Finished	Feb 18 02:05:51 PM PST 24
Peak memory	200040 kb
Host	smart-0481c481-b992-4c01-8323-4fc837313390
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1846797837 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_overflow.1846797837
Directory	/workspace/20.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/20.uart_intr.3853574862
Short name	T581
Test name
Test status
Simulation time	140559997554 ps
CPU time	224.74 seconds
Started	Feb 18 02:04:42 PM PST 24
Finished	Feb 18 02:08:30 PM PST 24
Peak memory	198232 kb
Host	smart-8d0e9d48-06c4-4daa-abfb-6d33be866c19
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853574862 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_intr.3853574862
Directory	/workspace/20.uart_intr/latest

Test location	/workspace/coverage/default/20.uart_long_xfer_wo_dly.3580684813
Short name	T552
Test name
Test status
Simulation time	33615745644 ps
CPU time	190.48 seconds
Started	Feb 18 02:04:44 PM PST 24
Finished	Feb 18 02:07:58 PM PST 24
Peak memory	200004 kb
Host	smart-ddaeb898-5412-4520-83d7-c019d2651cbd
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3580684813 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_long_xfer_wo_dly.3580684813
Directory	/workspace/20.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/20.uart_loopback.524805020
Short name	T457
Test name
Test status
Simulation time	5028463753 ps
CPU time	5.58 seconds
Started	Feb 18 02:04:39 PM PST 24
Finished	Feb 18 02:04:49 PM PST 24
Peak memory	198408 kb
Host	smart-c7fa9694-95ab-4f0c-bc58-c45262688b2d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=524805020 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_loopback.524805020
Directory	/workspace/20.uart_loopback/latest

Test location	/workspace/coverage/default/20.uart_noise_filter.303108836
Short name	T511
Test name
Test status
Simulation time	18093225083 ps
CPU time	7.34 seconds
Started	Feb 18 02:04:41 PM PST 24
Finished	Feb 18 02:04:52 PM PST 24
Peak memory	194676 kb
Host	smart-590d8b2b-190c-480d-a94f-5a079e5a68f9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=303108836 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_noise_filter.303108836
Directory	/workspace/20.uart_noise_filter/latest

Test location	/workspace/coverage/default/20.uart_perf.2979944192
Short name	T392
Test name
Test status
Simulation time	28953075171 ps
CPU time	334.72 seconds
Started	Feb 18 02:04:44 PM PST 24
Finished	Feb 18 02:10:22 PM PST 24
Peak memory	200068 kb
Host	smart-9293db98-f4ee-47ee-ac42-dabb65270e06
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2979944192 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_perf.2979944192
Directory	/workspace/20.uart_perf/latest

Test location	/workspace/coverage/default/20.uart_rx_oversample.125869485
Short name	T735
Test name
Test status
Simulation time	2929226474 ps
CPU time	12.07 seconds
Started	Feb 18 02:04:51 PM PST 24
Finished	Feb 18 02:05:10 PM PST 24
Peak memory	198036 kb
Host	smart-8da0ec5d-6787-4200-a615-a2100cbe7ae9
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=125869485 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_oversample.125869485
Directory	/workspace/20.uart_rx_oversample/latest

Test location	/workspace/coverage/default/20.uart_rx_parity_err.3810957313
Short name	T380
Test name
Test status
Simulation time	93459809801 ps
CPU time	37.34 seconds
Started	Feb 18 02:04:38 PM PST 24
Finished	Feb 18 02:05:19 PM PST 24
Peak memory	200088 kb
Host	smart-35f30c7e-3ca8-4916-a198-f520421d8305
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3810957313 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_parity_err.3810957313
Directory	/workspace/20.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/20.uart_rx_start_bit_filter.892518322
Short name	T1090
Test name
Test status
Simulation time	1423418470 ps
CPU time	3.07 seconds
Started	Feb 18 02:04:38 PM PST 24
Finished	Feb 18 02:04:45 PM PST 24
Peak memory	195456 kb
Host	smart-6304cebe-b9ad-4c11-a7c9-4d2ced6b9a77
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=892518322 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_start_bit_filter.892518322
Directory	/workspace/20.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/20.uart_smoke.2771264344
Short name	T1046
Test name
Test status
Simulation time	699927242 ps
CPU time	1.31 seconds
Started	Feb 18 02:04:39 PM PST 24
Finished	Feb 18 02:04:44 PM PST 24
Peak memory	198152 kb
Host	smart-482f6e29-f3d4-4f04-a3f8-2e3f61860de0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2771264344 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_smoke.2771264344
Directory	/workspace/20.uart_smoke/latest

Test location	/workspace/coverage/default/20.uart_stress_all.3603431237
Short name	T761
Test name
Test status
Simulation time	107542961730 ps
CPU time	46.52 seconds
Started	Feb 18 02:04:47 PM PST 24
Finished	Feb 18 02:05:37 PM PST 24
Peak memory	200220 kb
Host	smart-0bca62dd-2587-40ae-98c8-8fd42817466b
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603431237 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_stress_all.3603431237
Directory	/workspace/20.uart_stress_all/latest

Test location	/workspace/coverage/default/20.uart_stress_all_with_rand_reset.4223849949
Short name	T266
Test name
Test status
Simulation time	143571903558 ps
CPU time	383.72 seconds
Started	Feb 18 02:04:42 PM PST 24
Finished	Feb 18 02:11:09 PM PST 24
Peak memory	211872 kb
Host	smart-32321213-6a8d-49d6-a21e-bd5ba0f109d8
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223849949 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 20.uart_stress_all_with_rand_reset.4223849949
Directory	/workspace/20.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/20.uart_tx_ovrd.2415123049
Short name	T452
Test name
Test status
Simulation time	943975570 ps
CPU time	1.48 seconds
Started	Feb 18 02:04:42 PM PST 24
Finished	Feb 18 02:04:47 PM PST 24
Peak memory	196660 kb
Host	smart-0ac99ae5-b91b-4e7e-bad8-307d197fa6d2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2415123049 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_ovrd.2415123049
Directory	/workspace/20.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/20.uart_tx_rx.3739893882
Short name	T394
Test name
Test status
Simulation time	29548012945 ps
CPU time	52.3 seconds
Started	Feb 18 02:04:32 PM PST 24
Finished	Feb 18 02:05:27 PM PST 24
Peak memory	200016 kb
Host	smart-1be34003-e926-4742-b48b-92b9606adb66
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3739893882 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_rx.3739893882
Directory	/workspace/20.uart_tx_rx/latest

Test location	/workspace/coverage/default/200.uart_fifo_reset.2511838365
Short name	T336
Test name
Test status
Simulation time	6548624237 ps
CPU time	11.69 seconds
Started	Feb 18 02:08:04 PM PST 24
Finished	Feb 18 02:08:17 PM PST 24
Peak memory	199352 kb
Host	smart-b670c688-d50b-4de0-9d51-b0f37f13dab5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2511838365 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.uart_fifo_reset.2511838365
Directory	/workspace/200.uart_fifo_reset/latest

Test location	/workspace/coverage/default/201.uart_fifo_reset.2970314228
Short name	T869
Test name
Test status
Simulation time	186432873491 ps
CPU time	68.01 seconds
Started	Feb 18 02:08:03 PM PST 24
Finished	Feb 18 02:09:12 PM PST 24
Peak memory	199876 kb
Host	smart-ffa87222-83f7-4e0c-8078-66db15b0fc2f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2970314228 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.uart_fifo_reset.2970314228
Directory	/workspace/201.uart_fifo_reset/latest

Test location	/workspace/coverage/default/204.uart_fifo_reset.4285534860
Short name	T486
Test name
Test status
Simulation time	12886198764 ps
CPU time	7.08 seconds
Started	Feb 18 02:08:03 PM PST 24
Finished	Feb 18 02:08:11 PM PST 24
Peak memory	200068 kb
Host	smart-a771ccd5-2b42-4d41-a3c5-11123c8c0a88
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4285534860 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.uart_fifo_reset.4285534860
Directory	/workspace/204.uart_fifo_reset/latest

Test location	/workspace/coverage/default/206.uart_fifo_reset.480295538
Short name	T225
Test name
Test status
Simulation time	89117609818 ps
CPU time	39.25 seconds
Started	Feb 18 02:08:07 PM PST 24
Finished	Feb 18 02:08:49 PM PST 24
Peak memory	200032 kb
Host	smart-e412e077-7530-498d-b99b-0f37e449d59b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=480295538 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.uart_fifo_reset.480295538
Directory	/workspace/206.uart_fifo_reset/latest

Test location	/workspace/coverage/default/207.uart_fifo_reset.464821536
Short name	T983
Test name
Test status
Simulation time	286395142267 ps
CPU time	51 seconds
Started	Feb 18 02:08:11 PM PST 24
Finished	Feb 18 02:09:04 PM PST 24
Peak memory	200108 kb
Host	smart-71b6683e-2b93-4b98-a927-83a08ba0a858
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=464821536 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.uart_fifo_reset.464821536
Directory	/workspace/207.uart_fifo_reset/latest

Test location	/workspace/coverage/default/209.uart_fifo_reset.70872427
Short name	T651
Test name
Test status
Simulation time	13238408633 ps
CPU time	19.23 seconds
Started	Feb 18 02:08:12 PM PST 24
Finished	Feb 18 02:08:34 PM PST 24
Peak memory	199652 kb
Host	smart-03ddd7d4-145e-4884-a403-cdbf7392dd5e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=70872427 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.uart_fifo_reset.70872427
Directory	/workspace/209.uart_fifo_reset/latest

Test location	/workspace/coverage/default/21.uart_alert_test.2865355114
Short name	T765
Test name
Test status
Simulation time	25711545 ps
CPU time	0.58 seconds
Started	Feb 18 02:04:40 PM PST 24
Finished	Feb 18 02:04:45 PM PST 24
Peak memory	194560 kb
Host	smart-1be98cb2-1ea0-46df-b5a2-96a25a819cc1
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865355114 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_alert_test.2865355114
Directory	/workspace/21.uart_alert_test/latest

Test location	/workspace/coverage/default/21.uart_fifo_full.3908007548
Short name	T664
Test name
Test status
Simulation time	91464102327 ps
CPU time	142.08 seconds
Started	Feb 18 02:04:41 PM PST 24
Finished	Feb 18 02:07:07 PM PST 24
Peak memory	200036 kb
Host	smart-98d4056a-650f-4bc7-a3b3-23c198e7f1cc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3908007548 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_full.3908007548
Directory	/workspace/21.uart_fifo_full/latest

Test location	/workspace/coverage/default/21.uart_fifo_overflow.4128953044
Short name	T260
Test name
Test status
Simulation time	95612084051 ps
CPU time	35.57 seconds
Started	Feb 18 02:04:38 PM PST 24
Finished	Feb 18 02:05:17 PM PST 24
Peak memory	200036 kb
Host	smart-5dcf839c-cdc7-4f35-b81d-b5dfdf50db4c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4128953044 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_overflow.4128953044
Directory	/workspace/21.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/21.uart_intr.2857462170
Short name	T503
Test name
Test status
Simulation time	674904733165 ps
CPU time	166.7 seconds
Started	Feb 18 02:04:40 PM PST 24
Finished	Feb 18 02:07:30 PM PST 24
Peak memory	199300 kb
Host	smart-7a1e129c-a942-4d09-bb01-0e928af2455f
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857462170 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_intr.2857462170
Directory	/workspace/21.uart_intr/latest

Test location	/workspace/coverage/default/21.uart_long_xfer_wo_dly.399355799
Short name	T565
Test name
Test status
Simulation time	103006929201 ps
CPU time	83.95 seconds
Started	Feb 18 02:04:40 PM PST 24
Finished	Feb 18 02:06:08 PM PST 24
Peak memory	200044 kb
Host	smart-6ee50c51-b978-48e3-a74e-91028de273f4
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=399355799 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_long_xfer_wo_dly.399355799
Directory	/workspace/21.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/21.uart_loopback.633922017
Short name	T657
Test name
Test status
Simulation time	9106135472 ps
CPU time	7.1 seconds
Started	Feb 18 02:04:42 PM PST 24
Finished	Feb 18 02:04:53 PM PST 24
Peak memory	198984 kb
Host	smart-18024071-51de-4d69-983b-d50b8d5669eb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=633922017 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_loopback.633922017
Directory	/workspace/21.uart_loopback/latest

Test location	/workspace/coverage/default/21.uart_noise_filter.1670588036
Short name	T521
Test name
Test status
Simulation time	75738885426 ps
CPU time	51.14 seconds
Started	Feb 18 02:04:40 PM PST 24
Finished	Feb 18 02:05:35 PM PST 24
Peak memory	199656 kb
Host	smart-9ec1d736-747b-49af-9989-1c9d33868ff5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1670588036 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_noise_filter.1670588036
Directory	/workspace/21.uart_noise_filter/latest

Test location	/workspace/coverage/default/21.uart_perf.2081108796
Short name	T758
Test name
Test status
Simulation time	13502769245 ps
CPU time	160.83 seconds
Started	Feb 18 02:04:41 PM PST 24
Finished	Feb 18 02:07:25 PM PST 24
Peak memory	200072 kb
Host	smart-82cae0f9-cb34-43a2-8760-27d539f96842
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2081108796 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_perf.2081108796
Directory	/workspace/21.uart_perf/latest

Test location	/workspace/coverage/default/21.uart_rx_oversample.2249048147
Short name	T23
Test name
Test status
Simulation time	2247291458 ps
CPU time	3.4 seconds
Started	Feb 18 02:04:39 PM PST 24
Finished	Feb 18 02:04:46 PM PST 24
Peak memory	198340 kb
Host	smart-4b01f169-c5b4-40cd-b0a2-a5df07e93fe5
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2249048147 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_oversample.2249048147
Directory	/workspace/21.uart_rx_oversample/latest

Test location	/workspace/coverage/default/21.uart_rx_parity_err.1837253609
Short name	T272
Test name
Test status
Simulation time	205979133915 ps
CPU time	92.43 seconds
Started	Feb 18 02:04:47 PM PST 24
Finished	Feb 18 02:06:23 PM PST 24
Peak memory	199228 kb
Host	smart-ca585ad1-cc4e-4712-ae00-a7e255a5b9cf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1837253609 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_parity_err.1837253609
Directory	/workspace/21.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/21.uart_rx_start_bit_filter.874799123
Short name	T1023
Test name
Test status
Simulation time	4028879900 ps
CPU time	3.84 seconds
Started	Feb 18 02:04:44 PM PST 24
Finished	Feb 18 02:04:51 PM PST 24
Peak memory	195852 kb
Host	smart-fd8ffbcf-7997-4ab6-9886-b115b5d35795
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=874799123 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_start_bit_filter.874799123
Directory	/workspace/21.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/21.uart_smoke.438540539
Short name	T693
Test name
Test status
Simulation time	5987868981 ps
CPU time	7.45 seconds
Started	Feb 18 02:04:39 PM PST 24
Finished	Feb 18 02:04:50 PM PST 24
Peak memory	200096 kb
Host	smart-8d00fcd0-ba9d-4e72-bb57-220a92177f8a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=438540539 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_smoke.438540539
Directory	/workspace/21.uart_smoke/latest

Test location	/workspace/coverage/default/21.uart_stress_all.483226096
Short name	T156
Test name
Test status
Simulation time	233619479632 ps
CPU time	298.82 seconds
Started	Feb 18 02:04:46 PM PST 24
Finished	Feb 18 02:09:48 PM PST 24
Peak memory	200048 kb
Host	smart-b78d57a0-9e61-480b-8782-5166f45b3e00
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483226096 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_stress_all.483226096
Directory	/workspace/21.uart_stress_all/latest

Test location	/workspace/coverage/default/21.uart_tx_ovrd.757352911
Short name	T447
Test name
Test status
Simulation time	696594906 ps
CPU time	1.55 seconds
Started	Feb 18 02:04:39 PM PST 24
Finished	Feb 18 02:04:44 PM PST 24
Peak memory	198840 kb
Host	smart-426ee07e-d882-4f22-a52f-e0572d313d52
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=757352911 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_ovrd.757352911
Directory	/workspace/21.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/21.uart_tx_rx.1204254579
Short name	T839
Test name
Test status
Simulation time	79490522169 ps
CPU time	35.95 seconds
Started	Feb 18 02:04:40 PM PST 24
Finished	Feb 18 02:05:20 PM PST 24
Peak memory	199684 kb
Host	smart-7b80eb29-df89-4cae-a071-b80744d1508f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1204254579 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_rx.1204254579
Directory	/workspace/21.uart_tx_rx/latest

Test location	/workspace/coverage/default/210.uart_fifo_reset.2988214064
Short name	T321
Test name
Test status
Simulation time	45034098747 ps
CPU time	15.85 seconds
Started	Feb 18 02:08:14 PM PST 24
Finished	Feb 18 02:08:32 PM PST 24
Peak memory	199176 kb
Host	smart-c463dd14-bf17-4b55-812d-762a5cdde8a6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2988214064 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.uart_fifo_reset.2988214064
Directory	/workspace/210.uart_fifo_reset/latest

Test location	/workspace/coverage/default/211.uart_fifo_reset.2354165272
Short name	T111
Test name
Test status
Simulation time	26508381701 ps
CPU time	50.54 seconds
Started	Feb 18 02:08:12 PM PST 24
Finished	Feb 18 02:09:05 PM PST 24
Peak memory	200112 kb
Host	smart-cdd3559c-a872-4c86-a9b2-93365888b39f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2354165272 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.uart_fifo_reset.2354165272
Directory	/workspace/211.uart_fifo_reset/latest

Test location	/workspace/coverage/default/212.uart_fifo_reset.1916969235
Short name	T3
Test name
Test status
Simulation time	108239361030 ps
CPU time	157.76 seconds
Started	Feb 18 02:08:11 PM PST 24
Finished	Feb 18 02:10:51 PM PST 24
Peak memory	199976 kb
Host	smart-50972070-c9e5-4ad3-b47e-76a030c72611
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1916969235 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.uart_fifo_reset.1916969235
Directory	/workspace/212.uart_fifo_reset/latest

Test location	/workspace/coverage/default/213.uart_fifo_reset.3819717604
Short name	T1078
Test name
Test status
Simulation time	98397632380 ps
CPU time	137.79 seconds
Started	Feb 18 02:08:11 PM PST 24
Finished	Feb 18 02:10:30 PM PST 24
Peak memory	200036 kb
Host	smart-28991056-de57-4db6-9fd8-beb57a1cc80d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3819717604 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.uart_fifo_reset.3819717604
Directory	/workspace/213.uart_fifo_reset/latest

Test location	/workspace/coverage/default/214.uart_fifo_reset.3767072781
Short name	T704
Test name
Test status
Simulation time	146779542279 ps
CPU time	67.7 seconds
Started	Feb 18 02:08:15 PM PST 24
Finished	Feb 18 02:09:25 PM PST 24
Peak memory	200024 kb
Host	smart-487b9f1a-f1fd-472e-8a32-d4633aeeaa15
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3767072781 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.uart_fifo_reset.3767072781
Directory	/workspace/214.uart_fifo_reset/latest

Test location	/workspace/coverage/default/215.uart_fifo_reset.148751467
Short name	T2
Test name
Test status
Simulation time	13649949948 ps
CPU time	23.86 seconds
Started	Feb 18 02:08:12 PM PST 24
Finished	Feb 18 02:08:38 PM PST 24
Peak memory	199640 kb
Host	smart-a9b5e1fc-7302-4616-a194-dca1b1cdf5e4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=148751467 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.uart_fifo_reset.148751467
Directory	/workspace/215.uart_fifo_reset/latest

Test location	/workspace/coverage/default/217.uart_fifo_reset.2056909411
Short name	T172
Test name
Test status
Simulation time	66504707613 ps
CPU time	53.23 seconds
Started	Feb 18 02:08:19 PM PST 24
Finished	Feb 18 02:09:17 PM PST 24
Peak memory	200124 kb
Host	smart-b10b2b9d-410a-4d11-b549-a4732e4c86b1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2056909411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.uart_fifo_reset.2056909411
Directory	/workspace/217.uart_fifo_reset/latest

Test location	/workspace/coverage/default/219.uart_fifo_reset.2616244371
Short name	T239
Test name
Test status
Simulation time	7499143470 ps
CPU time	8.36 seconds
Started	Feb 18 02:08:11 PM PST 24
Finished	Feb 18 02:08:21 PM PST 24
Peak memory	200112 kb
Host	smart-47b5efca-8bce-47a6-879c-f44d6a1815f5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2616244371 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.uart_fifo_reset.2616244371
Directory	/workspace/219.uart_fifo_reset/latest

Test location	/workspace/coverage/default/22.uart_alert_test.4171034645
Short name	T32
Test name
Test status
Simulation time	13409253 ps
CPU time	0.59 seconds
Started	Feb 18 02:04:48 PM PST 24
Finished	Feb 18 02:04:52 PM PST 24
Peak memory	195524 kb
Host	smart-92b603a5-167f-4402-9e83-7dab1b320f87
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171034645 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_alert_test.4171034645
Directory	/workspace/22.uart_alert_test/latest

Test location	/workspace/coverage/default/22.uart_fifo_full.1260669124
Short name	T387
Test name
Test status
Simulation time	112849897560 ps
CPU time	34.84 seconds
Started	Feb 18 02:04:54 PM PST 24
Finished	Feb 18 02:05:35 PM PST 24
Peak memory	199976 kb
Host	smart-b385783f-af8d-426a-bd38-d4a8086938b6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1260669124 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_full.1260669124
Directory	/workspace/22.uart_fifo_full/latest

Test location	/workspace/coverage/default/22.uart_fifo_reset.3629425516
Short name	T674
Test name
Test status
Simulation time	9210842412 ps
CPU time	8.45 seconds
Started	Feb 18 02:04:47 PM PST 24
Finished	Feb 18 02:04:59 PM PST 24
Peak memory	200100 kb
Host	smart-c4a6695c-b983-47c0-b6c0-09860e2fadec
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3629425516 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_reset.3629425516
Directory	/workspace/22.uart_fifo_reset/latest

Test location	/workspace/coverage/default/22.uart_intr.1515156675
Short name	T813
Test name
Test status
Simulation time	798062074058 ps
CPU time	447.95 seconds
Started	Feb 18 02:04:46 PM PST 24
Finished	Feb 18 02:12:17 PM PST 24
Peak memory	198416 kb
Host	smart-6d752480-eac9-49cc-856b-86e043684fee
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515156675 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_intr.1515156675
Directory	/workspace/22.uart_intr/latest

Test location	/workspace/coverage/default/22.uart_long_xfer_wo_dly.2481817640
Short name	T428
Test name
Test status
Simulation time	67672571581 ps
CPU time	409.99 seconds
Started	Feb 18 02:04:50 PM PST 24
Finished	Feb 18 02:11:46 PM PST 24
Peak memory	199944 kb
Host	smart-927d34ad-8f58-4469-92a3-ecf422813832
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2481817640 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_long_xfer_wo_dly.2481817640
Directory	/workspace/22.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/22.uart_loopback.3269576702
Short name	T1004
Test name
Test status
Simulation time	1445905165 ps
CPU time	1.19 seconds
Started	Feb 18 02:04:48 PM PST 24
Finished	Feb 18 02:04:53 PM PST 24
Peak memory	195412 kb
Host	smart-d1ca7ec7-9bea-4564-a7af-d9f700ee03c9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3269576702 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_loopback.3269576702
Directory	/workspace/22.uart_loopback/latest

Test location	/workspace/coverage/default/22.uart_noise_filter.989435842
Short name	T666
Test name
Test status
Simulation time	101576927414 ps
CPU time	253.45 seconds
Started	Feb 18 02:04:50 PM PST 24
Finished	Feb 18 02:09:09 PM PST 24
Peak memory	200148 kb
Host	smart-3603cc9c-12ac-4aca-9921-fed52169eef2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=989435842 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_noise_filter.989435842
Directory	/workspace/22.uart_noise_filter/latest

Test location	/workspace/coverage/default/22.uart_perf.2645717800
Short name	T498
Test name
Test status
Simulation time	13832730787 ps
CPU time	195.49 seconds
Started	Feb 18 02:04:50 PM PST 24
Finished	Feb 18 02:08:12 PM PST 24
Peak memory	199928 kb
Host	smart-f9579bb2-b900-4e25-b64c-d5e3a39728ec
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2645717800 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_perf.2645717800
Directory	/workspace/22.uart_perf/latest

Test location	/workspace/coverage/default/22.uart_rx_oversample.2873573206
Short name	T575
Test name
Test status
Simulation time	909870047 ps
CPU time	2.16 seconds
Started	Feb 18 02:04:50 PM PST 24
Finished	Feb 18 02:04:58 PM PST 24
Peak memory	198028 kb
Host	smart-92449e9c-3a26-4ac2-b4d9-e0fb7e62e60b
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2873573206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_oversample.2873573206
Directory	/workspace/22.uart_rx_oversample/latest

Test location	/workspace/coverage/default/22.uart_rx_parity_err.2012099580
Short name	T687
Test name
Test status
Simulation time	31635725528 ps
CPU time	13.48 seconds
Started	Feb 18 02:04:45 PM PST 24
Finished	Feb 18 02:05:02 PM PST 24
Peak memory	200092 kb
Host	smart-0c600b4b-a98c-4e78-adca-5a82191c8207
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2012099580 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_parity_err.2012099580
Directory	/workspace/22.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/22.uart_rx_start_bit_filter.1731927555
Short name	T984
Test name
Test status
Simulation time	83882835133 ps
CPU time	19.05 seconds
Started	Feb 18 02:04:51 PM PST 24
Finished	Feb 18 02:05:16 PM PST 24
Peak memory	195840 kb
Host	smart-3a772d93-f1f3-4743-a58b-b44466936e2f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1731927555 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_start_bit_filter.1731927555
Directory	/workspace/22.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/22.uart_smoke.3370600367
Short name	T1061
Test name
Test status
Simulation time	473295812 ps
CPU time	2.24 seconds
Started	Feb 18 02:04:41 PM PST 24
Finished	Feb 18 02:04:47 PM PST 24
Peak memory	197860 kb
Host	smart-b1738f19-2f70-480c-8ccb-ced33e285401
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3370600367 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_smoke.3370600367
Directory	/workspace/22.uart_smoke/latest

Test location	/workspace/coverage/default/22.uart_stress_all.1050812060
Short name	T107
Test name
Test status
Simulation time	133001308413 ps
CPU time	196.68 seconds
Started	Feb 18 02:04:46 PM PST 24
Finished	Feb 18 02:08:06 PM PST 24
Peak memory	200072 kb
Host	smart-5e3807ff-cc75-4a4f-80c8-b1047c5dfff5
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050812060 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_stress_all.1050812060
Directory	/workspace/22.uart_stress_all/latest

Test location	/workspace/coverage/default/22.uart_tx_ovrd.2768946076
Short name	T459
Test name
Test status
Simulation time	847559570 ps
CPU time	2.7 seconds
Started	Feb 18 02:04:48 PM PST 24
Finished	Feb 18 02:04:55 PM PST 24
Peak memory	198448 kb
Host	smart-fe4df97f-aeb6-4a08-9561-730c872caeb9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2768946076 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_ovrd.2768946076
Directory	/workspace/22.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/22.uart_tx_rx.4040718615
Short name	T766
Test name
Test status
Simulation time	42395562837 ps
CPU time	22.37 seconds
Started	Feb 18 02:04:38 PM PST 24
Finished	Feb 18 02:05:04 PM PST 24
Peak memory	200052 kb
Host	smart-05e0f0f2-7708-4138-8cfe-1c5811d3e864
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4040718615 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_rx.4040718615
Directory	/workspace/22.uart_tx_rx/latest

Test location	/workspace/coverage/default/220.uart_fifo_reset.2838091738
Short name	T891
Test name
Test status
Simulation time	81283836632 ps
CPU time	141.2 seconds
Started	Feb 18 02:08:11 PM PST 24
Finished	Feb 18 02:10:33 PM PST 24
Peak memory	200112 kb
Host	smart-43492c64-446b-4fcc-8a87-b9d5d9241586
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2838091738 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.uart_fifo_reset.2838091738
Directory	/workspace/220.uart_fifo_reset/latest

Test location	/workspace/coverage/default/221.uart_fifo_reset.3967143710
Short name	T723
Test name
Test status
Simulation time	31059793651 ps
CPU time	12.51 seconds
Started	Feb 18 02:08:13 PM PST 24
Finished	Feb 18 02:08:28 PM PST 24
Peak memory	200024 kb
Host	smart-afc6aa2c-6c07-45a5-84c6-3237952c378a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3967143710 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.uart_fifo_reset.3967143710
Directory	/workspace/221.uart_fifo_reset/latest

Test location	/workspace/coverage/default/222.uart_fifo_reset.2121228936
Short name	T1038
Test name
Test status
Simulation time	28320615796 ps
CPU time	24.99 seconds
Started	Feb 18 02:08:17 PM PST 24
Finished	Feb 18 02:08:46 PM PST 24
Peak memory	200012 kb
Host	smart-854710ec-da87-4cc5-b6ad-a4beb3781b36
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2121228936 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.uart_fifo_reset.2121228936
Directory	/workspace/222.uart_fifo_reset/latest

Test location	/workspace/coverage/default/223.uart_fifo_reset.2303691426
Short name	T562
Test name
Test status
Simulation time	39224518456 ps
CPU time	14.75 seconds
Started	Feb 18 02:08:17 PM PST 24
Finished	Feb 18 02:08:36 PM PST 24
Peak memory	199748 kb
Host	smart-13a0c875-7e88-4375-aae9-84ba743aef13
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2303691426 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.uart_fifo_reset.2303691426
Directory	/workspace/223.uart_fifo_reset/latest

Test location	/workspace/coverage/default/224.uart_fifo_reset.36283062
Short name	T713
Test name
Test status
Simulation time	108781088709 ps
CPU time	19.83 seconds
Started	Feb 18 02:08:17 PM PST 24
Finished	Feb 18 02:08:40 PM PST 24
Peak memory	200040 kb
Host	smart-7a62da5e-e64f-41ad-b1d1-d52e8cf1be17
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=36283062 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.uart_fifo_reset.36283062
Directory	/workspace/224.uart_fifo_reset/latest

Test location	/workspace/coverage/default/225.uart_fifo_reset.1818535422
Short name	T243
Test name
Test status
Simulation time	38843352172 ps
CPU time	29.54 seconds
Started	Feb 18 02:08:17 PM PST 24
Finished	Feb 18 02:08:49 PM PST 24
Peak memory	200044 kb
Host	smart-75a95bbd-2371-4cbe-af16-e869e3e92627
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1818535422 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.uart_fifo_reset.1818535422
Directory	/workspace/225.uart_fifo_reset/latest

Test location	/workspace/coverage/default/226.uart_fifo_reset.1512797503
Short name	T382
Test name
Test status
Simulation time	105770503391 ps
CPU time	12.73 seconds
Started	Feb 18 02:08:21 PM PST 24
Finished	Feb 18 02:08:38 PM PST 24
Peak memory	199776 kb
Host	smart-24ad2a3a-b086-4d5b-950c-1bd6896b7095
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1512797503 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.uart_fifo_reset.1512797503
Directory	/workspace/226.uart_fifo_reset/latest

Test location	/workspace/coverage/default/227.uart_fifo_reset.4151415515
Short name	T88
Test name
Test status
Simulation time	129256750117 ps
CPU time	185.26 seconds
Started	Feb 18 02:08:23 PM PST 24
Finished	Feb 18 02:11:31 PM PST 24
Peak memory	200024 kb
Host	smart-707915c9-4296-4ec3-aa70-b6c7106381e4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4151415515 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.uart_fifo_reset.4151415515
Directory	/workspace/227.uart_fifo_reset/latest

Test location	/workspace/coverage/default/228.uart_fifo_reset.2285780700
Short name	T125
Test name
Test status
Simulation time	124897998597 ps
CPU time	38.23 seconds
Started	Feb 18 02:08:29 PM PST 24
Finished	Feb 18 02:09:10 PM PST 24
Peak memory	199896 kb
Host	smart-7a499abd-a5d6-4b19-a6de-655807557dd4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2285780700 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.uart_fifo_reset.2285780700
Directory	/workspace/228.uart_fifo_reset/latest

Test location	/workspace/coverage/default/23.uart_alert_test.701877005
Short name	T592
Test name
Test status
Simulation time	41485806 ps
CPU time	0.56 seconds
Started	Feb 18 02:04:52 PM PST 24
Finished	Feb 18 02:05:00 PM PST 24
Peak memory	194420 kb
Host	smart-fbb48f55-81c0-40f1-b461-a03e1152e277
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701877005 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_alert_test.701877005
Directory	/workspace/23.uart_alert_test/latest

Test location	/workspace/coverage/default/23.uart_fifo_full.2386145080
Short name	T921
Test name
Test status
Simulation time	216146078666 ps
CPU time	348.18 seconds
Started	Feb 18 02:04:48 PM PST 24
Finished	Feb 18 02:10:41 PM PST 24
Peak memory	200124 kb
Host	smart-1c786755-d172-4d57-a246-2f630c13d0f3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2386145080 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_full.2386145080
Directory	/workspace/23.uart_fifo_full/latest

Test location	/workspace/coverage/default/23.uart_fifo_overflow.728077045
Short name	T342
Test name
Test status
Simulation time	119170048416 ps
CPU time	19.2 seconds
Started	Feb 18 02:04:45 PM PST 24
Finished	Feb 18 02:05:07 PM PST 24
Peak memory	198704 kb
Host	smart-df7a5a45-785f-4a3d-b00a-882af6788101
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=728077045 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_overflow.728077045
Directory	/workspace/23.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/23.uart_fifo_reset.213351018
Short name	T171
Test name
Test status
Simulation time	97701989715 ps
CPU time	46.58 seconds
Started	Feb 18 02:04:47 PM PST 24
Finished	Feb 18 02:05:37 PM PST 24
Peak memory	200124 kb
Host	smart-86a28684-8789-4e20-840f-1821a7a5cbf6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=213351018 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_reset.213351018
Directory	/workspace/23.uart_fifo_reset/latest

Test location	/workspace/coverage/default/23.uart_intr.3145667050
Short name	T804
Test name
Test status
Simulation time	669444142195 ps
CPU time	1234.38 seconds
Started	Feb 18 02:04:49 PM PST 24
Finished	Feb 18 02:25:29 PM PST 24
Peak memory	199988 kb
Host	smart-196434ed-7926-4825-99d1-2c5ca28781f1
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145667050 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_intr.3145667050
Directory	/workspace/23.uart_intr/latest

Test location	/workspace/coverage/default/23.uart_long_xfer_wo_dly.2479929684
Short name	T594
Test name
Test status
Simulation time	62542420364 ps
CPU time	277.75 seconds
Started	Feb 18 02:04:47 PM PST 24
Finished	Feb 18 02:09:29 PM PST 24
Peak memory	200032 kb
Host	smart-bab24241-a45d-4091-b06f-7a685d7f4a97
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2479929684 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_long_xfer_wo_dly.2479929684
Directory	/workspace/23.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/23.uart_loopback.902074279
Short name	T626
Test name
Test status
Simulation time	8223238570 ps
CPU time	5.5 seconds
Started	Feb 18 02:04:47 PM PST 24
Finished	Feb 18 02:04:56 PM PST 24
Peak memory	199240 kb
Host	smart-0c5e112b-5df3-4ff8-9494-7a897a4e32e4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=902074279 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_loopback.902074279
Directory	/workspace/23.uart_loopback/latest

Test location	/workspace/coverage/default/23.uart_noise_filter.1417102664
Short name	T524
Test name
Test status
Simulation time	146362960519 ps
CPU time	74.97 seconds
Started	Feb 18 02:04:46 PM PST 24
Finished	Feb 18 02:06:04 PM PST 24
Peak memory	199280 kb
Host	smart-e6defefb-d0ac-4b48-a53c-08961437d7f2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1417102664 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_noise_filter.1417102664
Directory	/workspace/23.uart_noise_filter/latest

Test location	/workspace/coverage/default/23.uart_perf.67281359
Short name	T515
Test name
Test status
Simulation time	12691645224 ps
CPU time	156.75 seconds
Started	Feb 18 02:04:45 PM PST 24
Finished	Feb 18 02:07:25 PM PST 24
Peak memory	200028 kb
Host	smart-a67866fa-2c7c-43f6-97b3-9d9c788c3833
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=67281359 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_perf.67281359
Directory	/workspace/23.uart_perf/latest

Test location	/workspace/coverage/default/23.uart_rx_oversample.321852585
Short name	T478
Test name
Test status
Simulation time	4440840108 ps
CPU time	39.67 seconds
Started	Feb 18 02:04:47 PM PST 24
Finished	Feb 18 02:05:31 PM PST 24
Peak memory	198704 kb
Host	smart-347006d9-f0e8-41fe-a07b-5c6b39667032
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=321852585 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_oversample.321852585
Directory	/workspace/23.uart_rx_oversample/latest

Test location	/workspace/coverage/default/23.uart_rx_parity_err.3198914874
Short name	T252
Test name
Test status
Simulation time	78145750915 ps
CPU time	29.58 seconds
Started	Feb 18 02:04:49 PM PST 24
Finished	Feb 18 02:05:23 PM PST 24
Peak memory	199860 kb
Host	smart-0d74dc98-804d-43d6-8652-a36a0bb6f606
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3198914874 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_parity_err.3198914874
Directory	/workspace/23.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/23.uart_rx_start_bit_filter.1098272951
Short name	T30
Test name
Test status
Simulation time	2652301529 ps
CPU time	5.03 seconds
Started	Feb 18 02:04:47 PM PST 24
Finished	Feb 18 02:04:56 PM PST 24
Peak memory	195512 kb
Host	smart-cd6ea42d-90cd-4ff2-9c31-c65e0205eb4f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1098272951 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_start_bit_filter.1098272951
Directory	/workspace/23.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/23.uart_smoke.2330860390
Short name	T660
Test name
Test status
Simulation time	723852204 ps
CPU time	1.24 seconds
Started	Feb 18 02:04:47 PM PST 24
Finished	Feb 18 02:04:51 PM PST 24
Peak memory	198232 kb
Host	smart-384f91db-fb03-4b84-9c0a-da94ff3a2af4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2330860390 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_smoke.2330860390
Directory	/workspace/23.uart_smoke/latest

Test location	/workspace/coverage/default/23.uart_stress_all.521329256
Short name	T202
Test name
Test status
Simulation time	221428955504 ps
CPU time	334.19 seconds
Started	Feb 18 02:04:50 PM PST 24
Finished	Feb 18 02:10:31 PM PST 24
Peak memory	200064 kb
Host	smart-80392c32-42bd-4b08-b529-a33d941f121f
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521329256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_stress_all.521329256
Directory	/workspace/23.uart_stress_all/latest

Test location	/workspace/coverage/default/23.uart_tx_ovrd.881168651
Short name	T1105
Test name
Test status
Simulation time	1488812806 ps
CPU time	2.77 seconds
Started	Feb 18 02:04:46 PM PST 24
Finished	Feb 18 02:04:52 PM PST 24
Peak memory	198956 kb
Host	smart-28905405-b435-421a-8d8a-d7bee5b51d8b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=881168651 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_ovrd.881168651
Directory	/workspace/23.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/23.uart_tx_rx.427106210
Short name	T44
Test name
Test status
Simulation time	42233238091 ps
CPU time	38.82 seconds
Started	Feb 18 02:04:49 PM PST 24
Finished	Feb 18 02:05:33 PM PST 24
Peak memory	200032 kb
Host	smart-a791772b-1031-4027-85ad-396f657d0268
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=427106210 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_rx.427106210
Directory	/workspace/23.uart_tx_rx/latest

Test location	/workspace/coverage/default/230.uart_fifo_reset.951369877
Short name	T706
Test name
Test status
Simulation time	72414752061 ps
CPU time	10.75 seconds
Started	Feb 18 02:08:20 PM PST 24
Finished	Feb 18 02:08:35 PM PST 24
Peak memory	198812 kb
Host	smart-d8b58890-38a1-4575-b66b-96f6f2051180
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=951369877 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.uart_fifo_reset.951369877
Directory	/workspace/230.uart_fifo_reset/latest

Test location	/workspace/coverage/default/231.uart_fifo_reset.4281409796
Short name	T177
Test name
Test status
Simulation time	192031208479 ps
CPU time	164.7 seconds
Started	Feb 18 02:08:21 PM PST 24
Finished	Feb 18 02:11:09 PM PST 24
Peak memory	200020 kb
Host	smart-f7b1a345-4a17-4220-b5e1-33a4e153a029
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4281409796 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.uart_fifo_reset.4281409796
Directory	/workspace/231.uart_fifo_reset/latest

Test location	/workspace/coverage/default/232.uart_fifo_reset.1775979876
Short name	T1005
Test name
Test status
Simulation time	71605245531 ps
CPU time	58.82 seconds
Started	Feb 18 02:08:19 PM PST 24
Finished	Feb 18 02:09:23 PM PST 24
Peak memory	199864 kb
Host	smart-a1d34cd3-5cd9-417c-8437-775f8bda19ed
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1775979876 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.uart_fifo_reset.1775979876
Directory	/workspace/232.uart_fifo_reset/latest

Test location	/workspace/coverage/default/233.uart_fifo_reset.3511722857
Short name	T249
Test name
Test status
Simulation time	54609628833 ps
CPU time	14.93 seconds
Started	Feb 18 02:08:17 PM PST 24
Finished	Feb 18 02:08:36 PM PST 24
Peak memory	200028 kb
Host	smart-d6e0cec6-64ba-4ad8-b6cb-5e95ea793205
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3511722857 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.uart_fifo_reset.3511722857
Directory	/workspace/233.uart_fifo_reset/latest

Test location	/workspace/coverage/default/234.uart_fifo_reset.1184227654
Short name	T43
Test name
Test status
Simulation time	27946102040 ps
CPU time	47.64 seconds
Started	Feb 18 02:08:18 PM PST 24
Finished	Feb 18 02:09:10 PM PST 24
Peak memory	200148 kb
Host	smart-765e9694-1d7e-4199-9b15-3631595b3892
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1184227654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.uart_fifo_reset.1184227654
Directory	/workspace/234.uart_fifo_reset/latest

Test location	/workspace/coverage/default/236.uart_fifo_reset.2691589461
Short name	T261
Test name
Test status
Simulation time	79903032566 ps
CPU time	140.51 seconds
Started	Feb 18 02:08:19 PM PST 24
Finished	Feb 18 02:10:45 PM PST 24
Peak memory	199648 kb
Host	smart-f81451af-4f50-44c4-90f5-3c8d3dc34388
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2691589461 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.uart_fifo_reset.2691589461
Directory	/workspace/236.uart_fifo_reset/latest

Test location	/workspace/coverage/default/237.uart_fifo_reset.1415979135
Short name	T228
Test name
Test status
Simulation time	18898262800 ps
CPU time	16.01 seconds
Started	Feb 18 02:08:20 PM PST 24
Finished	Feb 18 02:08:40 PM PST 24
Peak memory	199712 kb
Host	smart-3b3d3655-be4c-4784-8d56-66cda879cc82
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1415979135 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.uart_fifo_reset.1415979135
Directory	/workspace/237.uart_fifo_reset/latest

Test location	/workspace/coverage/default/238.uart_fifo_reset.3079637962
Short name	T915
Test name
Test status
Simulation time	43197665453 ps
CPU time	17.46 seconds
Started	Feb 18 02:08:19 PM PST 24
Finished	Feb 18 02:08:41 PM PST 24
Peak memory	200036 kb
Host	smart-a30d3f83-4147-49a3-9f90-49f30b2552ca
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3079637962 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.uart_fifo_reset.3079637962
Directory	/workspace/238.uart_fifo_reset/latest

Test location	/workspace/coverage/default/24.uart_alert_test.2389044353
Short name	T584
Test name
Test status
Simulation time	33755008 ps
CPU time	0.57 seconds
Started	Feb 18 02:04:52 PM PST 24
Finished	Feb 18 02:05:00 PM PST 24
Peak memory	195504 kb
Host	smart-0d333344-3a77-4156-b4f1-4d8d88be7e24
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389044353 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_alert_test.2389044353
Directory	/workspace/24.uart_alert_test/latest

Test location	/workspace/coverage/default/24.uart_fifo_full.85746397
Short name	T369
Test name
Test status
Simulation time	204822351289 ps
CPU time	54.01 seconds
Started	Feb 18 02:05:01 PM PST 24
Finished	Feb 18 02:05:58 PM PST 24
Peak memory	199984 kb
Host	smart-b9808ab4-10a6-4704-9074-f024158d3af7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=85746397 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_full.85746397
Directory	/workspace/24.uart_fifo_full/latest

Test location	/workspace/coverage/default/24.uart_fifo_overflow.2106992060
Short name	T811
Test name
Test status
Simulation time	38281564529 ps
CPU time	23.1 seconds
Started	Feb 18 02:04:54 PM PST 24
Finished	Feb 18 02:05:23 PM PST 24
Peak memory	199504 kb
Host	smart-b741390e-aedf-4228-9b10-c978db24b218
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2106992060 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_overflow.2106992060
Directory	/workspace/24.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/24.uart_intr.2648421684
Short name	T17
Test name
Test status
Simulation time	808488048513 ps
CPU time	1248.66 seconds
Started	Feb 18 02:04:53 PM PST 24
Finished	Feb 18 02:25:49 PM PST 24
Peak memory	199984 kb
Host	smart-76080954-7dab-4a6d-ac14-449c3a7a8d3e
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648421684 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_intr.2648421684
Directory	/workspace/24.uart_intr/latest

Test location	/workspace/coverage/default/24.uart_loopback.866861919
Short name	T469
Test name
Test status
Simulation time	7043649947 ps
CPU time	13.93 seconds
Started	Feb 18 02:04:58 PM PST 24
Finished	Feb 18 02:05:16 PM PST 24
Peak memory	199220 kb
Host	smart-8790135d-c381-4244-bb26-3440be35c6ad
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=866861919 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_loopback.866861919
Directory	/workspace/24.uart_loopback/latest

Test location	/workspace/coverage/default/24.uart_noise_filter.3040544175
Short name	T972
Test name
Test status
Simulation time	142425196078 ps
CPU time	90.33 seconds
Started	Feb 18 02:04:54 PM PST 24
Finished	Feb 18 02:06:30 PM PST 24
Peak memory	208428 kb
Host	smart-9f913d0a-f2dc-4628-a98a-224aac5a78f5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3040544175 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_noise_filter.3040544175
Directory	/workspace/24.uart_noise_filter/latest

Test location	/workspace/coverage/default/24.uart_perf.1210012405
Short name	T479
Test name
Test status
Simulation time	12317007781 ps
CPU time	682.45 seconds
Started	Feb 18 02:04:56 PM PST 24
Finished	Feb 18 02:16:24 PM PST 24
Peak memory	199956 kb
Host	smart-646c689d-d139-4ed3-9797-3315846e63a7
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1210012405 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_perf.1210012405
Directory	/workspace/24.uart_perf/latest

Test location	/workspace/coverage/default/24.uart_rx_oversample.3498722746
Short name	T669
Test name
Test status
Simulation time	567068957 ps
CPU time	6.11 seconds
Started	Feb 18 02:04:54 PM PST 24
Finished	Feb 18 02:05:06 PM PST 24
Peak memory	198116 kb
Host	smart-2f848b8c-4602-4960-864d-c3ea0a7e7799
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3498722746 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_oversample.3498722746
Directory	/workspace/24.uart_rx_oversample/latest

Test location	/workspace/coverage/default/24.uart_rx_parity_err.3828086315
Short name	T993
Test name
Test status
Simulation time	23050323507 ps
CPU time	36.29 seconds
Started	Feb 18 02:04:55 PM PST 24
Finished	Feb 18 02:05:37 PM PST 24
Peak memory	198868 kb
Host	smart-03bfe32d-fec7-418c-90f0-74e71254a93a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3828086315 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_parity_err.3828086315
Directory	/workspace/24.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/24.uart_rx_start_bit_filter.1643379098
Short name	T738
Test name
Test status
Simulation time	6479921848 ps
CPU time	1.44 seconds
Started	Feb 18 02:05:01 PM PST 24
Finished	Feb 18 02:05:06 PM PST 24
Peak memory	195864 kb
Host	smart-77040086-3d53-4657-8746-6ee3505ce9b1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1643379098 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_start_bit_filter.1643379098
Directory	/workspace/24.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/24.uart_smoke.4096539448
Short name	T401
Test name
Test status
Simulation time	120614585 ps
CPU time	0.77 seconds
Started	Feb 18 02:04:47 PM PST 24
Finished	Feb 18 02:04:51 PM PST 24
Peak memory	196532 kb
Host	smart-9b2eeb97-9357-4522-929f-0b1382e92311
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4096539448 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_smoke.4096539448
Directory	/workspace/24.uart_smoke/latest

Test location	/workspace/coverage/default/24.uart_stress_all_with_rand_reset.4124100340
Short name	T864
Test name
Test status
Simulation time	37301947999 ps
CPU time	217.02 seconds
Started	Feb 18 02:04:58 PM PST 24
Finished	Feb 18 02:08:39 PM PST 24
Peak memory	215752 kb
Host	smart-607008da-2d37-4e5a-b35c-d5683636c110
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124100340 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 24.uart_stress_all_with_rand_reset.4124100340
Directory	/workspace/24.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/24.uart_tx_ovrd.1931604313
Short name	T89
Test name
Test status
Simulation time	8040916180 ps
CPU time	11.76 seconds
Started	Feb 18 02:04:56 PM PST 24
Finished	Feb 18 02:05:13 PM PST 24
Peak memory	199508 kb
Host	smart-0258638a-ed52-44c1-912b-881716bd0f44
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1931604313 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_ovrd.1931604313
Directory	/workspace/24.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/24.uart_tx_rx.1553846960
Short name	T404
Test name
Test status
Simulation time	54134815323 ps
CPU time	21.36 seconds
Started	Feb 18 02:04:48 PM PST 24
Finished	Feb 18 02:05:14 PM PST 24
Peak memory	200096 kb
Host	smart-3cb584bd-74e1-4d58-a3be-04c91f7fd638
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1553846960 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_rx.1553846960
Directory	/workspace/24.uart_tx_rx/latest

Test location	/workspace/coverage/default/240.uart_fifo_reset.1969659714
Short name	T209
Test name
Test status
Simulation time	39136496311 ps
CPU time	33.06 seconds
Started	Feb 18 02:08:20 PM PST 24
Finished	Feb 18 02:08:57 PM PST 24
Peak memory	200036 kb
Host	smart-20e2a0b6-0475-4701-bde4-f8258ea4344a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1969659714 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.uart_fifo_reset.1969659714
Directory	/workspace/240.uart_fifo_reset/latest

Test location	/workspace/coverage/default/241.uart_fifo_reset.2892338017
Short name	T1086
Test name
Test status
Simulation time	162034361426 ps
CPU time	14.28 seconds
Started	Feb 18 02:08:29 PM PST 24
Finished	Feb 18 02:08:46 PM PST 24
Peak memory	199984 kb
Host	smart-84714aea-09c2-4867-b0dc-594933e9e9fc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2892338017 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.uart_fifo_reset.2892338017
Directory	/workspace/241.uart_fifo_reset/latest

Test location	/workspace/coverage/default/242.uart_fifo_reset.2623483163
Short name	T290
Test name
Test status
Simulation time	168201722811 ps
CPU time	30.12 seconds
Started	Feb 18 02:08:17 PM PST 24
Finished	Feb 18 02:08:50 PM PST 24
Peak memory	198264 kb
Host	smart-b1c1e867-f056-46d8-8f5d-4dd272043f2b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2623483163 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.uart_fifo_reset.2623483163
Directory	/workspace/242.uart_fifo_reset/latest

Test location	/workspace/coverage/default/243.uart_fifo_reset.89763696
Short name	T224
Test name
Test status
Simulation time	112315528307 ps
CPU time	62.08 seconds
Started	Feb 18 02:08:18 PM PST 24
Finished	Feb 18 02:09:24 PM PST 24
Peak memory	200048 kb
Host	smart-6b36e6b3-6111-4072-98e7-c9b82e3d79ab
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=89763696 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.uart_fifo_reset.89763696
Directory	/workspace/243.uart_fifo_reset/latest

Test location	/workspace/coverage/default/244.uart_fifo_reset.3754035637
Short name	T698
Test name
Test status
Simulation time	164937288298 ps
CPU time	72.11 seconds
Started	Feb 18 02:08:19 PM PST 24
Finished	Feb 18 02:09:36 PM PST 24
Peak memory	200000 kb
Host	smart-2ff2a27c-875a-400a-aef7-08c8a9f4f771
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3754035637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.uart_fifo_reset.3754035637
Directory	/workspace/244.uart_fifo_reset/latest

Test location	/workspace/coverage/default/246.uart_fifo_reset.540347683
Short name	T1035
Test name
Test status
Simulation time	117997942876 ps
CPU time	190.35 seconds
Started	Feb 18 02:08:23 PM PST 24
Finished	Feb 18 02:11:36 PM PST 24
Peak memory	200076 kb
Host	smart-e8e0d981-906b-4687-bbe4-3ac1fa89c971
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=540347683 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.uart_fifo_reset.540347683
Directory	/workspace/246.uart_fifo_reset/latest

Test location	/workspace/coverage/default/247.uart_fifo_reset.3987550586
Short name	T1020
Test name
Test status
Simulation time	18946078551 ps
CPU time	36.03 seconds
Started	Feb 18 02:08:23 PM PST 24
Finished	Feb 18 02:09:02 PM PST 24
Peak memory	200024 kb
Host	smart-efffa93a-0075-4279-ab91-3b73c59d5361
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3987550586 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.uart_fifo_reset.3987550586
Directory	/workspace/247.uart_fifo_reset/latest

Test location	/workspace/coverage/default/248.uart_fifo_reset.123704799
Short name	T1118
Test name
Test status
Simulation time	95215707537 ps
CPU time	144.37 seconds
Started	Feb 18 02:08:23 PM PST 24
Finished	Feb 18 02:10:51 PM PST 24
Peak memory	200020 kb
Host	smart-9430b123-a98d-42db-bbe3-c5a86d221f1d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=123704799 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.uart_fifo_reset.123704799
Directory	/workspace/248.uart_fifo_reset/latest

Test location	/workspace/coverage/default/249.uart_fifo_reset.51931800
Short name	T943
Test name
Test status
Simulation time	201842831078 ps
CPU time	61.03 seconds
Started	Feb 18 02:08:19 PM PST 24
Finished	Feb 18 02:09:25 PM PST 24
Peak memory	200116 kb
Host	smart-8621c0b1-32aa-4709-932b-1ad62d46722c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=51931800 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.uart_fifo_reset.51931800
Directory	/workspace/249.uart_fifo_reset/latest

Test location	/workspace/coverage/default/25.uart_alert_test.1584155145
Short name	T643
Test name
Test status
Simulation time	31973177 ps
CPU time	0.56 seconds
Started	Feb 18 02:05:00 PM PST 24
Finished	Feb 18 02:05:04 PM PST 24
Peak memory	195524 kb
Host	smart-f05621d8-3355-4205-85a6-e8688200527d
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584155145 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_alert_test.1584155145
Directory	/workspace/25.uart_alert_test/latest

Test location	/workspace/coverage/default/25.uart_fifo_full.1682380522
Short name	T675
Test name
Test status
Simulation time	136961316730 ps
CPU time	66.09 seconds
Started	Feb 18 02:05:00 PM PST 24
Finished	Feb 18 02:06:09 PM PST 24
Peak memory	200020 kb
Host	smart-e72d6cfb-ea1c-44db-b5ec-bbb6d0a1f029
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1682380522 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_full.1682380522
Directory	/workspace/25.uart_fifo_full/latest

Test location	/workspace/coverage/default/25.uart_fifo_overflow.1645834842
Short name	T418
Test name
Test status
Simulation time	93550848023 ps
CPU time	139.31 seconds
Started	Feb 18 02:04:55 PM PST 24
Finished	Feb 18 02:07:20 PM PST 24
Peak memory	198852 kb
Host	smart-f9579e72-d328-4372-a2fa-a2fb0a4b49a6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1645834842 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_overflow.1645834842
Directory	/workspace/25.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/25.uart_fifo_reset.425106286
Short name	T1120
Test name
Test status
Simulation time	29071604366 ps
CPU time	72.66 seconds
Started	Feb 18 02:04:55 PM PST 24
Finished	Feb 18 02:06:13 PM PST 24
Peak memory	200020 kb
Host	smart-e5101fdf-100b-4e7d-9fd5-011bfa013198
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=425106286 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_reset.425106286
Directory	/workspace/25.uart_fifo_reset/latest

Test location	/workspace/coverage/default/25.uart_intr.1301940689
Short name	T931
Test name
Test status
Simulation time	242893035710 ps
CPU time	93.98 seconds
Started	Feb 18 02:05:03 PM PST 24
Finished	Feb 18 02:06:41 PM PST 24
Peak memory	199896 kb
Host	smart-7f442e72-2ed3-4ad2-ac2c-e26959c3fe11
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301940689 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_intr.1301940689
Directory	/workspace/25.uart_intr/latest

Test location	/workspace/coverage/default/25.uart_long_xfer_wo_dly.1383968456
Short name	T1084
Test name
Test status
Simulation time	182229676248 ps
CPU time	278.5 seconds
Started	Feb 18 02:05:01 PM PST 24
Finished	Feb 18 02:09:43 PM PST 24
Peak memory	200016 kb
Host	smart-83297c29-57d8-4b5c-9819-1accda874747
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1383968456 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_long_xfer_wo_dly.1383968456
Directory	/workspace/25.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/25.uart_loopback.2357711210
Short name	T601
Test name
Test status
Simulation time	2974894742 ps
CPU time	3.24 seconds
Started	Feb 18 02:05:00 PM PST 24
Finished	Feb 18 02:05:06 PM PST 24
Peak memory	195984 kb
Host	smart-93c54b53-b92e-4dc2-8520-3959a6fc3212
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2357711210 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_loopback.2357711210
Directory	/workspace/25.uart_loopback/latest

Test location	/workspace/coverage/default/25.uart_noise_filter.3492198264
Short name	T1013
Test name
Test status
Simulation time	20656047681 ps
CPU time	8.79 seconds
Started	Feb 18 02:04:52 PM PST 24
Finished	Feb 18 02:05:08 PM PST 24
Peak memory	193676 kb
Host	smart-4d246a54-943b-449c-a3b7-f0b92af1912b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3492198264 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_noise_filter.3492198264
Directory	/workspace/25.uart_noise_filter/latest

Test location	/workspace/coverage/default/25.uart_perf.110792996
Short name	T950
Test name
Test status
Simulation time	30107686697 ps
CPU time	400.41 seconds
Started	Feb 18 02:04:59 PM PST 24
Finished	Feb 18 02:11:43 PM PST 24
Peak memory	200100 kb
Host	smart-ea0a41b9-0334-413e-aa7d-09b0943a6334
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=110792996 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_perf.110792996
Directory	/workspace/25.uart_perf/latest

Test location	/workspace/coverage/default/25.uart_rx_oversample.939950445
Short name	T716
Test name
Test status
Simulation time	1593156019 ps
CPU time	8.73 seconds
Started	Feb 18 02:04:54 PM PST 24
Finished	Feb 18 02:05:09 PM PST 24
Peak memory	198144 kb
Host	smart-fb75589f-f851-4e77-8d47-ad24d0b0107a
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=939950445 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_oversample.939950445
Directory	/workspace/25.uart_rx_oversample/latest

Test location	/workspace/coverage/default/25.uart_rx_parity_err.445116968
Short name	T1034
Test name
Test status
Simulation time	60628834398 ps
CPU time	100.36 seconds
Started	Feb 18 02:04:55 PM PST 24
Finished	Feb 18 02:06:41 PM PST 24
Peak memory	198488 kb
Host	smart-ab089a1a-c3f8-4976-9dc8-c920eaabb8b9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=445116968 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_parity_err.445116968
Directory	/workspace/25.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/25.uart_rx_start_bit_filter.3670961291
Short name	T717
Test name
Test status
Simulation time	87145326119 ps
CPU time	127.32 seconds
Started	Feb 18 02:04:51 PM PST 24
Finished	Feb 18 02:07:04 PM PST 24
Peak memory	195780 kb
Host	smart-7e7120d0-79a3-4722-a344-6e93af73aa94
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3670961291 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_start_bit_filter.3670961291
Directory	/workspace/25.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/25.uart_smoke.2687326092
Short name	T705
Test name
Test status
Simulation time	472215546 ps
CPU time	1.64 seconds
Started	Feb 18 02:05:00 PM PST 24
Finished	Feb 18 02:05:05 PM PST 24
Peak memory	199868 kb
Host	smart-87d98449-f419-450e-9269-a6a4009a463b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2687326092 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_smoke.2687326092
Directory	/workspace/25.uart_smoke/latest

Test location	/workspace/coverage/default/25.uart_stress_all.3950964019
Short name	T1100
Test name
Test status
Simulation time	141831994515 ps
CPU time	190.45 seconds
Started	Feb 18 02:05:00 PM PST 24
Finished	Feb 18 02:08:14 PM PST 24
Peak memory	200024 kb
Host	smart-6ea2cb0b-2d5f-4cf5-a033-5e66ca1f46fe
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950964019 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_stress_all.3950964019
Directory	/workspace/25.uart_stress_all/latest

Test location	/workspace/coverage/default/25.uart_stress_all_with_rand_reset.1881023627
Short name	T676
Test name
Test status
Simulation time	64009972779 ps
CPU time	619.89 seconds
Started	Feb 18 02:05:01 PM PST 24
Finished	Feb 18 02:15:24 PM PST 24
Peak memory	229052 kb
Host	smart-618a9712-24b1-42f3-b6e7-19c10d01eab6
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881023627 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 25.uart_stress_all_with_rand_reset.1881023627
Directory	/workspace/25.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/25.uart_tx_ovrd.3061665325
Short name	T752
Test name
Test status
Simulation time	1318409720 ps
CPU time	2.09 seconds
Started	Feb 18 02:05:01 PM PST 24
Finished	Feb 18 02:05:06 PM PST 24
Peak memory	198128 kb
Host	smart-0dc40339-9ae9-4963-84d2-4f184d8be9b3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3061665325 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_ovrd.3061665325
Directory	/workspace/25.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/25.uart_tx_rx.4026300774
Short name	T719
Test name
Test status
Simulation time	63419011377 ps
CPU time	25.73 seconds
Started	Feb 18 02:04:52 PM PST 24
Finished	Feb 18 02:05:25 PM PST 24
Peak memory	200040 kb
Host	smart-c6c8bb06-7963-4fe6-b261-636cda3fa35c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4026300774 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_rx.4026300774
Directory	/workspace/25.uart_tx_rx/latest

Test location	/workspace/coverage/default/252.uart_fifo_reset.1058573599
Short name	T297
Test name
Test status
Simulation time	139756103396 ps
CPU time	30.67 seconds
Started	Feb 18 02:08:32 PM PST 24
Finished	Feb 18 02:09:09 PM PST 24
Peak memory	199780 kb
Host	smart-ac9213b2-fb3b-4a97-8a62-140a498a1d09
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1058573599 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.uart_fifo_reset.1058573599
Directory	/workspace/252.uart_fifo_reset/latest

Test location	/workspace/coverage/default/253.uart_fifo_reset.1943681202
Short name	T296
Test name
Test status
Simulation time	68960888197 ps
CPU time	57.26 seconds
Started	Feb 18 02:08:33 PM PST 24
Finished	Feb 18 02:09:38 PM PST 24
Peak memory	200124 kb
Host	smart-ec422ca7-6b87-47cf-b7df-05a36d2b3d49
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1943681202 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.uart_fifo_reset.1943681202
Directory	/workspace/253.uart_fifo_reset/latest

Test location	/workspace/coverage/default/254.uart_fifo_reset.2348802959
Short name	T302
Test name
Test status
Simulation time	84728228210 ps
CPU time	141.04 seconds
Started	Feb 18 02:08:32 PM PST 24
Finished	Feb 18 02:10:59 PM PST 24
Peak memory	199564 kb
Host	smart-7f08ff7a-c9c5-4d49-812f-a5b9784e98ac
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2348802959 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.uart_fifo_reset.2348802959
Directory	/workspace/254.uart_fifo_reset/latest

Test location	/workspace/coverage/default/255.uart_fifo_reset.3248660195
Short name	T46
Test name
Test status
Simulation time	103520139657 ps
CPU time	169.11 seconds
Started	Feb 18 02:08:32 PM PST 24
Finished	Feb 18 02:11:24 PM PST 24
Peak memory	199728 kb
Host	smart-0e95118b-22d5-45e0-bb06-bd2f1a328423
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3248660195 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.uart_fifo_reset.3248660195
Directory	/workspace/255.uart_fifo_reset/latest

Test location	/workspace/coverage/default/257.uart_fifo_reset.1823657010
Short name	T199
Test name
Test status
Simulation time	7321124326 ps
CPU time	12.83 seconds
Started	Feb 18 02:08:31 PM PST 24
Finished	Feb 18 02:08:47 PM PST 24
Peak memory	199388 kb
Host	smart-d5e78afd-6492-4c55-a7c2-1debfce7737d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1823657010 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.uart_fifo_reset.1823657010
Directory	/workspace/257.uart_fifo_reset/latest

Test location	/workspace/coverage/default/258.uart_fifo_reset.424467579
Short name	T331
Test name
Test status
Simulation time	117872862886 ps
CPU time	45.02 seconds
Started	Feb 18 02:08:33 PM PST 24
Finished	Feb 18 02:09:24 PM PST 24
Peak memory	200064 kb
Host	smart-a3f52a33-8dd2-4d10-ace6-d02aabe31b5d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=424467579 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.uart_fifo_reset.424467579
Directory	/workspace/258.uart_fifo_reset/latest

Test location	/workspace/coverage/default/259.uart_fifo_reset.3199957777
Short name	T720
Test name
Test status
Simulation time	8433953234 ps
CPU time	4.37 seconds
Started	Feb 18 02:08:31 PM PST 24
Finished	Feb 18 02:08:38 PM PST 24
Peak memory	199412 kb
Host	smart-ffad8b34-53b9-4a50-956b-bc2fc964a28d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3199957777 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.uart_fifo_reset.3199957777
Directory	/workspace/259.uart_fifo_reset/latest

Test location	/workspace/coverage/default/26.uart_alert_test.586710029
Short name	T914
Test name
Test status
Simulation time	12491541 ps
CPU time	0.61 seconds
Started	Feb 18 02:05:03 PM PST 24
Finished	Feb 18 02:05:06 PM PST 24
Peak memory	195500 kb
Host	smart-4c3bec39-a6d5-4c28-94b2-49d5893a9cdb
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586710029 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_alert_test.586710029
Directory	/workspace/26.uart_alert_test/latest

Test location	/workspace/coverage/default/26.uart_fifo_full.1148979429
Short name	T1027
Test name
Test status
Simulation time	120699926101 ps
CPU time	163.74 seconds
Started	Feb 18 02:05:03 PM PST 24
Finished	Feb 18 02:07:50 PM PST 24
Peak memory	200024 kb
Host	smart-19ef204a-f19d-4a21-b78a-d9d7bd485f89
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1148979429 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_full.1148979429
Directory	/workspace/26.uart_fifo_full/latest

Test location	/workspace/coverage/default/26.uart_fifo_overflow.1583260032
Short name	T1025
Test name
Test status
Simulation time	44726214012 ps
CPU time	6.14 seconds
Started	Feb 18 02:05:03 PM PST 24
Finished	Feb 18 02:05:12 PM PST 24
Peak memory	200024 kb
Host	smart-feb51af3-debd-48e9-917a-fd43ef7543d8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1583260032 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_overflow.1583260032
Directory	/workspace/26.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/26.uart_fifo_reset.4283845641
Short name	T1071
Test name
Test status
Simulation time	63566996795 ps
CPU time	20.85 seconds
Started	Feb 18 02:05:00 PM PST 24
Finished	Feb 18 02:05:24 PM PST 24
Peak memory	200060 kb
Host	smart-d309cbb3-b885-490b-953c-1adaa2651785
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4283845641 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_reset.4283845641
Directory	/workspace/26.uart_fifo_reset/latest

Test location	/workspace/coverage/default/26.uart_intr.2451011045
Short name	T768
Test name
Test status
Simulation time	115628276017 ps
CPU time	112.47 seconds
Started	Feb 18 02:05:03 PM PST 24
Finished	Feb 18 02:06:58 PM PST 24
Peak memory	200012 kb
Host	smart-0943a187-ec8a-4460-92e0-fa16ff96107c
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451011045 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_intr.2451011045
Directory	/workspace/26.uart_intr/latest

Test location	/workspace/coverage/default/26.uart_long_xfer_wo_dly.570501774
Short name	T819
Test name
Test status
Simulation time	150964839220 ps
CPU time	334.41 seconds
Started	Feb 18 02:04:58 PM PST 24
Finished	Feb 18 02:10:37 PM PST 24
Peak memory	200104 kb
Host	smart-6682353b-868b-4ea9-bb0c-d8f401fde09f
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=570501774 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_long_xfer_wo_dly.570501774
Directory	/workspace/26.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/26.uart_loopback.3117906316
Short name	T484
Test name
Test status
Simulation time	8876962139 ps
CPU time	20.23 seconds
Started	Feb 18 02:05:02 PM PST 24
Finished	Feb 18 02:05:26 PM PST 24
Peak memory	199260 kb
Host	smart-39121d06-69cf-4fab-a0ea-9169daba6982
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3117906316 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_loopback.3117906316
Directory	/workspace/26.uart_loopback/latest

Test location	/workspace/coverage/default/26.uart_noise_filter.3513880581
Short name	T823
Test name
Test status
Simulation time	95643075762 ps
CPU time	42.83 seconds
Started	Feb 18 02:04:56 PM PST 24
Finished	Feb 18 02:05:44 PM PST 24
Peak memory	198284 kb
Host	smart-02a195f3-b8b7-461c-91b7-404ba3781b9e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3513880581 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_noise_filter.3513880581
Directory	/workspace/26.uart_noise_filter/latest

Test location	/workspace/coverage/default/26.uart_rx_oversample.1689970590
Short name	T933
Test name
Test status
Simulation time	2673873272 ps
CPU time	3.68 seconds
Started	Feb 18 02:05:02 PM PST 24
Finished	Feb 18 02:05:09 PM PST 24
Peak memory	198432 kb
Host	smart-c8c44032-389b-4006-a2f8-9c825c90e6eb
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1689970590 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_oversample.1689970590
Directory	/workspace/26.uart_rx_oversample/latest

Test location	/workspace/coverage/default/26.uart_rx_parity_err.3118241832
Short name	T360
Test name
Test status
Simulation time	14780671445 ps
CPU time	23.49 seconds
Started	Feb 18 02:05:05 PM PST 24
Finished	Feb 18 02:05:33 PM PST 24
Peak memory	199988 kb
Host	smart-2b7d57e1-c61a-4567-ad5c-b7983aa5fa5b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3118241832 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_parity_err.3118241832
Directory	/workspace/26.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/26.uart_rx_start_bit_filter.2302585511
Short name	T889
Test name
Test status
Simulation time	2085683949 ps
CPU time	4 seconds
Started	Feb 18 02:05:03 PM PST 24
Finished	Feb 18 02:05:10 PM PST 24
Peak memory	195444 kb
Host	smart-1e18258f-01c0-44f7-9c5d-c281753cab69
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2302585511 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_start_bit_filter.2302585511
Directory	/workspace/26.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/26.uart_smoke.3414360023
Short name	T744
Test name
Test status
Simulation time	670678875 ps
CPU time	2.31 seconds
Started	Feb 18 02:05:03 PM PST 24
Finished	Feb 18 02:05:08 PM PST 24
Peak memory	198256 kb
Host	smart-f5c3523a-3eb7-46b8-bd2f-ac914d427876
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3414360023 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_smoke.3414360023
Directory	/workspace/26.uart_smoke/latest

Test location	/workspace/coverage/default/26.uart_stress_all_with_rand_reset.66384650
Short name	T98
Test name
Test status
Simulation time	321776548557 ps
CPU time	832.15 seconds
Started	Feb 18 02:04:59 PM PST 24
Finished	Feb 18 02:18:55 PM PST 24
Peak memory	233176 kb
Host	smart-82641601-7d98-4c6a-b6ef-0196cb2a24f5
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66384650 -assert nopostpro c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 26.uart_stress_all_with_rand_reset.66384650
Directory	/workspace/26.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/26.uart_tx_ovrd.1642291450
Short name	T645
Test name
Test status
Simulation time	723536215 ps
CPU time	2.37 seconds
Started	Feb 18 02:05:02 PM PST 24
Finished	Feb 18 02:05:08 PM PST 24
Peak memory	198956 kb
Host	smart-4db3904f-a47b-4fc0-8e73-49d3a116fdc3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1642291450 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_ovrd.1642291450
Directory	/workspace/26.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/26.uart_tx_rx.162030889
Short name	T160
Test name
Test status
Simulation time	131211482578 ps
CPU time	71.08 seconds
Started	Feb 18 02:05:01 PM PST 24
Finished	Feb 18 02:06:15 PM PST 24
Peak memory	200116 kb
Host	smart-9234acc4-1dc2-4b4d-8936-6dbb87e1729b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=162030889 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_rx.162030889
Directory	/workspace/26.uart_tx_rx/latest

Test location	/workspace/coverage/default/260.uart_fifo_reset.1869122184
Short name	T959
Test name
Test status
Simulation time	40171247473 ps
CPU time	14.96 seconds
Started	Feb 18 02:08:32 PM PST 24
Finished	Feb 18 02:08:52 PM PST 24
Peak memory	200036 kb
Host	smart-998f2e12-dfb0-4995-a62e-d9e14d6c8302
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1869122184 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.uart_fifo_reset.1869122184
Directory	/workspace/260.uart_fifo_reset/latest

Test location	/workspace/coverage/default/261.uart_fifo_reset.2405887446
Short name	T147
Test name
Test status
Simulation time	49859210769 ps
CPU time	17.95 seconds
Started	Feb 18 02:08:46 PM PST 24
Finished	Feb 18 02:09:10 PM PST 24
Peak memory	199836 kb
Host	smart-f9dc485a-6ee5-481c-b59f-c6cd5f6d2a73
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2405887446 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.uart_fifo_reset.2405887446
Directory	/workspace/261.uart_fifo_reset/latest

Test location	/workspace/coverage/default/262.uart_fifo_reset.2631450968
Short name	T1017
Test name
Test status
Simulation time	113463632388 ps
CPU time	54.24 seconds
Started	Feb 18 02:08:31 PM PST 24
Finished	Feb 18 02:09:28 PM PST 24
Peak memory	200108 kb
Host	smart-c0fd2fa5-f219-4f83-9172-4cbf44c56d50
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2631450968 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.uart_fifo_reset.2631450968
Directory	/workspace/262.uart_fifo_reset/latest

Test location	/workspace/coverage/default/266.uart_fifo_reset.1805398338
Short name	T998
Test name
Test status
Simulation time	51961790136 ps
CPU time	84.51 seconds
Started	Feb 18 02:08:32 PM PST 24
Finished	Feb 18 02:10:00 PM PST 24
Peak memory	200052 kb
Host	smart-6b85d51e-5aa6-4d5e-8320-b291a17079a2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1805398338 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.uart_fifo_reset.1805398338
Directory	/workspace/266.uart_fifo_reset/latest

Test location	/workspace/coverage/default/267.uart_fifo_reset.2472905380
Short name	T954
Test name
Test status
Simulation time	22102628715 ps
CPU time	33.93 seconds
Started	Feb 18 02:08:33 PM PST 24
Finished	Feb 18 02:09:14 PM PST 24
Peak memory	199652 kb
Host	smart-33ce82ff-0ec9-42a8-b79b-8fb768724860
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2472905380 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.uart_fifo_reset.2472905380
Directory	/workspace/267.uart_fifo_reset/latest

Test location	/workspace/coverage/default/27.uart_alert_test.3694151713
Short name	T640
Test name
Test status
Simulation time	25462348 ps
CPU time	0.58 seconds
Started	Feb 18 02:05:08 PM PST 24
Finished	Feb 18 02:05:13 PM PST 24
Peak memory	195492 kb
Host	smart-5d6554bf-5225-4a4f-908b-cd6cd00b68ee
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694151713 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_alert_test.3694151713
Directory	/workspace/27.uart_alert_test/latest

Test location	/workspace/coverage/default/27.uart_fifo_full.2597727240
Short name	T1104
Test name
Test status
Simulation time	27592684609 ps
CPU time	37.31 seconds
Started	Feb 18 02:05:00 PM PST 24
Finished	Feb 18 02:05:41 PM PST 24
Peak memory	199976 kb
Host	smart-c38eb5cf-4e8b-4c88-b00e-660b753f3c28
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2597727240 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_full.2597727240
Directory	/workspace/27.uart_fifo_full/latest

Test location	/workspace/coverage/default/27.uart_fifo_overflow.1550837411
Short name	T512
Test name
Test status
Simulation time	48635613872 ps
CPU time	74.47 seconds
Started	Feb 18 02:04:59 PM PST 24
Finished	Feb 18 02:06:17 PM PST 24
Peak memory	199468 kb
Host	smart-759af3d6-6b11-47eb-ba57-9122c12e10f1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1550837411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_overflow.1550837411
Directory	/workspace/27.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/27.uart_fifo_reset.2293813967
Short name	T184
Test name
Test status
Simulation time	19388061247 ps
CPU time	15.19 seconds
Started	Feb 18 02:05:03 PM PST 24
Finished	Feb 18 02:05:21 PM PST 24
Peak memory	199676 kb
Host	smart-b17cc1ae-29e9-4e63-8b69-66dccd7dafeb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2293813967 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_reset.2293813967
Directory	/workspace/27.uart_fifo_reset/latest

Test location	/workspace/coverage/default/27.uart_intr.3589087750
Short name	T968
Test name
Test status
Simulation time	66500398566 ps
CPU time	26.97 seconds
Started	Feb 18 02:05:04 PM PST 24
Finished	Feb 18 02:05:34 PM PST 24
Peak memory	199964 kb
Host	smart-61bb930a-dbce-4d74-a8ae-0fe81538a785
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589087750 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_intr.3589087750
Directory	/workspace/27.uart_intr/latest

Test location	/workspace/coverage/default/27.uart_long_xfer_wo_dly.1048300512
Short name	T801
Test name
Test status
Simulation time	82053034569 ps
CPU time	580.5 seconds
Started	Feb 18 02:05:10 PM PST 24
Finished	Feb 18 02:14:54 PM PST 24
Peak memory	200032 kb
Host	smart-b0628c16-ca73-4c07-8da0-cc6a0d9300fd
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1048300512 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_long_xfer_wo_dly.1048300512
Directory	/workspace/27.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/27.uart_loopback.4159971588
Short name	T572
Test name
Test status
Simulation time	63765980 ps
CPU time	0.62 seconds
Started	Feb 18 02:05:10 PM PST 24
Finished	Feb 18 02:05:14 PM PST 24
Peak memory	195428 kb
Host	smart-f3ee712e-577f-484e-8c5b-fffcae695f32
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4159971588 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_loopback.4159971588
Directory	/workspace/27.uart_loopback/latest

Test location	/workspace/coverage/default/27.uart_noise_filter.852095406
Short name	T748
Test name
Test status
Simulation time	11759101581 ps
CPU time	22.41 seconds
Started	Feb 18 02:05:06 PM PST 24
Finished	Feb 18 02:05:32 PM PST 24
Peak memory	198600 kb
Host	smart-27c9134f-f0e6-4514-9748-c1ac5118a0a6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=852095406 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_noise_filter.852095406
Directory	/workspace/27.uart_noise_filter/latest

Test location	/workspace/coverage/default/27.uart_perf.3347921601
Short name	T178
Test name
Test status
Simulation time	29827931530 ps
CPU time	538.03 seconds
Started	Feb 18 02:05:04 PM PST 24
Finished	Feb 18 02:14:05 PM PST 24
Peak memory	200068 kb
Host	smart-2bff813d-c435-49fd-8d71-f841e0130439
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3347921601 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_perf.3347921601
Directory	/workspace/27.uart_perf/latest

Test location	/workspace/coverage/default/27.uart_rx_oversample.1859351194
Short name	T678
Test name
Test status
Simulation time	4195362347 ps
CPU time	10.54 seconds
Started	Feb 18 02:04:59 PM PST 24
Finished	Feb 18 02:05:13 PM PST 24
Peak memory	197908 kb
Host	smart-2391b13d-b836-4c2a-9cc3-f4192f14b96f
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1859351194 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_oversample.1859351194
Directory	/workspace/27.uart_rx_oversample/latest

Test location	/workspace/coverage/default/27.uart_rx_parity_err.2736324156
Short name	T746
Test name
Test status
Simulation time	79740722359 ps
CPU time	136.16 seconds
Started	Feb 18 02:05:11 PM PST 24
Finished	Feb 18 02:07:30 PM PST 24
Peak memory	200044 kb
Host	smart-e3e79846-71bd-4340-a536-5b9d35bad0df
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2736324156 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_parity_err.2736324156
Directory	/workspace/27.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/27.uart_rx_start_bit_filter.1345890283
Short name	T870
Test name
Test status
Simulation time	4257260695 ps
CPU time	2.8 seconds
Started	Feb 18 02:05:08 PM PST 24
Finished	Feb 18 02:05:15 PM PST 24
Peak memory	195700 kb
Host	smart-8426205a-270a-4f87-bdfc-5f1c9168c33d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1345890283 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_start_bit_filter.1345890283
Directory	/workspace/27.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/27.uart_smoke.1333777908
Short name	T821
Test name
Test status
Simulation time	6234077858 ps
CPU time	23.74 seconds
Started	Feb 18 02:05:02 PM PST 24
Finished	Feb 18 02:05:28 PM PST 24
Peak memory	199580 kb
Host	smart-c9a5af48-4c6d-4134-8ff2-74a902b65075
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1333777908 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_smoke.1333777908
Directory	/workspace/27.uart_smoke/latest

Test location	/workspace/coverage/default/27.uart_stress_all.177154580
Short name	T838
Test name
Test status
Simulation time	174033076294 ps
CPU time	1086.64 seconds
Started	Feb 18 02:05:08 PM PST 24
Finished	Feb 18 02:23:19 PM PST 24
Peak memory	200068 kb
Host	smart-858a24cc-088e-435f-b738-f25af90749d6
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177154580 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_stress_all.177154580
Directory	/workspace/27.uart_stress_all/latest

Test location	/workspace/coverage/default/27.uart_tx_ovrd.3393205771
Short name	T1047
Test name
Test status
Simulation time	1261287168 ps
CPU time	7.62 seconds
Started	Feb 18 02:05:08 PM PST 24
Finished	Feb 18 02:05:20 PM PST 24
Peak memory	198992 kb
Host	smart-bd2c7d8f-005d-4536-ab50-dc61138938e1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3393205771 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_ovrd.3393205771
Directory	/workspace/27.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/27.uart_tx_rx.1506713850
Short name	T692
Test name
Test status
Simulation time	31161611995 ps
CPU time	50.76 seconds
Started	Feb 18 02:05:01 PM PST 24
Finished	Feb 18 02:05:55 PM PST 24
Peak memory	200028 kb
Host	smart-f3bafb12-34bb-4e85-8f4b-8efe6386fc5b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1506713850 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_rx.1506713850
Directory	/workspace/27.uart_tx_rx/latest

Test location	/workspace/coverage/default/270.uart_fifo_reset.2542650884
Short name	T154
Test name
Test status
Simulation time	37899461584 ps
CPU time	49.99 seconds
Started	Feb 18 02:08:32 PM PST 24
Finished	Feb 18 02:09:26 PM PST 24
Peak memory	200020 kb
Host	smart-910f99ae-15eb-432b-b7c7-3582930e7989
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2542650884 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.uart_fifo_reset.2542650884
Directory	/workspace/270.uart_fifo_reset/latest

Test location	/workspace/coverage/default/271.uart_fifo_reset.743459055
Short name	T112
Test name
Test status
Simulation time	56674292564 ps
CPU time	24.83 seconds
Started	Feb 18 02:08:46 PM PST 24
Finished	Feb 18 02:09:17 PM PST 24
Peak memory	199924 kb
Host	smart-14cfc459-f3d0-4912-bb71-3463dc13c435
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=743459055 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.uart_fifo_reset.743459055
Directory	/workspace/271.uart_fifo_reset/latest

Test location	/workspace/coverage/default/272.uart_fifo_reset.1068209990
Short name	T1096
Test name
Test status
Simulation time	160096862703 ps
CPU time	51.68 seconds
Started	Feb 18 02:08:32 PM PST 24
Finished	Feb 18 02:09:28 PM PST 24
Peak memory	199464 kb
Host	smart-d095f649-6356-4b07-8775-08292a5cf424
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1068209990 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.uart_fifo_reset.1068209990
Directory	/workspace/272.uart_fifo_reset/latest

Test location	/workspace/coverage/default/273.uart_fifo_reset.151528821
Short name	T310
Test name
Test status
Simulation time	46669765267 ps
CPU time	62.89 seconds
Started	Feb 18 02:08:32 PM PST 24
Finished	Feb 18 02:09:39 PM PST 24
Peak memory	199884 kb
Host	smart-7e300676-c57d-4e2d-940c-943e0d4cbea1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=151528821 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.uart_fifo_reset.151528821
Directory	/workspace/273.uart_fifo_reset/latest

Test location	/workspace/coverage/default/274.uart_fifo_reset.3485951026
Short name	T900
Test name
Test status
Simulation time	38812270947 ps
CPU time	103.96 seconds
Started	Feb 18 02:08:33 PM PST 24
Finished	Feb 18 02:10:24 PM PST 24
Peak memory	200036 kb
Host	smart-bee4aec3-4536-462b-86a5-89ef3be5c399
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3485951026 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.uart_fifo_reset.3485951026
Directory	/workspace/274.uart_fifo_reset/latest

Test location	/workspace/coverage/default/275.uart_fifo_reset.2400221238
Short name	T350
Test name
Test status
Simulation time	38824184559 ps
CPU time	29.64 seconds
Started	Feb 18 02:08:32 PM PST 24
Finished	Feb 18 02:09:07 PM PST 24
Peak memory	200024 kb
Host	smart-b752242d-c20f-445d-a358-9fdd3a78342d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2400221238 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.uart_fifo_reset.2400221238
Directory	/workspace/275.uart_fifo_reset/latest

Test location	/workspace/coverage/default/277.uart_fifo_reset.918271897
Short name	T377
Test name
Test status
Simulation time	14636511176 ps
CPU time	23.95 seconds
Started	Feb 18 02:08:32 PM PST 24
Finished	Feb 18 02:08:59 PM PST 24
Peak memory	199916 kb
Host	smart-0453a6bb-1d10-4ec6-ad19-742830ff093e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=918271897 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.uart_fifo_reset.918271897
Directory	/workspace/277.uart_fifo_reset/latest

Test location	/workspace/coverage/default/278.uart_fifo_reset.3038461949
Short name	T167
Test name
Test status
Simulation time	26153218057 ps
CPU time	37.91 seconds
Started	Feb 18 02:08:45 PM PST 24
Finished	Feb 18 02:09:29 PM PST 24
Peak memory	199476 kb
Host	smart-6a2044b1-1215-4ec7-8f62-4fbe5369a334
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3038461949 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.uart_fifo_reset.3038461949
Directory	/workspace/278.uart_fifo_reset/latest

Test location	/workspace/coverage/default/279.uart_fifo_reset.3559234257
Short name	T155
Test name
Test status
Simulation time	59168722763 ps
CPU time	22.37 seconds
Started	Feb 18 02:08:31 PM PST 24
Finished	Feb 18 02:08:56 PM PST 24
Peak memory	199640 kb
Host	smart-3572eded-43f4-42ee-bfb1-7342d845403e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3559234257 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.uart_fifo_reset.3559234257
Directory	/workspace/279.uart_fifo_reset/latest

Test location	/workspace/coverage/default/28.uart_alert_test.91440729
Short name	T682
Test name
Test status
Simulation time	161692296 ps
CPU time	0.55 seconds
Started	Feb 18 02:05:19 PM PST 24
Finished	Feb 18 02:05:22 PM PST 24
Peak memory	195448 kb
Host	smart-d4fbb238-84b6-425a-a66c-870d11b531ce
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91440729 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_alert_test.91440729
Directory	/workspace/28.uart_alert_test/latest

Test location	/workspace/coverage/default/28.uart_fifo_full.2419219582
Short name	T263
Test name
Test status
Simulation time	289504848183 ps
CPU time	438.25 seconds
Started	Feb 18 02:05:11 PM PST 24
Finished	Feb 18 02:12:32 PM PST 24
Peak memory	200084 kb
Host	smart-60644929-8418-414d-9793-1087d5b8edf0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2419219582 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_full.2419219582
Directory	/workspace/28.uart_fifo_full/latest

Test location	/workspace/coverage/default/28.uart_fifo_overflow.3787722583
Short name	T431
Test name
Test status
Simulation time	328834179467 ps
CPU time	263.71 seconds
Started	Feb 18 02:05:05 PM PST 24
Finished	Feb 18 02:09:33 PM PST 24
Peak memory	199916 kb
Host	smart-79774ec6-055c-4d8b-bd43-c3ba15f696e1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3787722583 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_overflow.3787722583
Directory	/workspace/28.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/28.uart_fifo_reset.2719059352
Short name	T48
Test name
Test status
Simulation time	18523844156 ps
CPU time	42.93 seconds
Started	Feb 18 02:05:08 PM PST 24
Finished	Feb 18 02:05:55 PM PST 24
Peak memory	199984 kb
Host	smart-336fd362-ff08-488a-ae64-bb1af144ca2f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2719059352 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_reset.2719059352
Directory	/workspace/28.uart_fifo_reset/latest

Test location	/workspace/coverage/default/28.uart_intr.703039787
Short name	T764
Test name
Test status
Simulation time	265850064123 ps
CPU time	346.41 seconds
Started	Feb 18 02:05:06 PM PST 24
Finished	Feb 18 02:10:57 PM PST 24
Peak memory	197080 kb
Host	smart-0f617b21-4c9d-46dc-8355-e7d62cbc3d2c
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703039787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_intr.703039787
Directory	/workspace/28.uart_intr/latest

Test location	/workspace/coverage/default/28.uart_long_xfer_wo_dly.117843965
Short name	T407
Test name
Test status
Simulation time	81993030751 ps
CPU time	642.78 seconds
Started	Feb 18 02:05:10 PM PST 24
Finished	Feb 18 02:15:56 PM PST 24
Peak memory	200096 kb
Host	smart-06645b1f-ec02-4a78-8b50-3b420bd6ab6a
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=117843965 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_long_xfer_wo_dly.117843965
Directory	/workspace/28.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/28.uart_loopback.2510915531
Short name	T6
Test name
Test status
Simulation time	5000617791 ps
CPU time	9.41 seconds
Started	Feb 18 02:05:06 PM PST 24
Finished	Feb 18 02:05:19 PM PST 24
Peak memory	199152 kb
Host	smart-95aec267-32bd-4914-b3ad-02bdc75bc935
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2510915531 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_loopback.2510915531
Directory	/workspace/28.uart_loopback/latest

Test location	/workspace/coverage/default/28.uart_noise_filter.2532127709
Short name	T133
Test name
Test status
Simulation time	75546962209 ps
CPU time	31.98 seconds
Started	Feb 18 02:05:05 PM PST 24
Finished	Feb 18 02:05:41 PM PST 24
Peak memory	197208 kb
Host	smart-b09c679b-0e95-4a2c-b4c8-e5b4637c0075
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2532127709 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_noise_filter.2532127709
Directory	/workspace/28.uart_noise_filter/latest

Test location	/workspace/coverage/default/28.uart_perf.1492637133
Short name	T402
Test name
Test status
Simulation time	22016122361 ps
CPU time	63.66 seconds
Started	Feb 18 02:05:10 PM PST 24
Finished	Feb 18 02:06:17 PM PST 24
Peak memory	200020 kb
Host	smart-1540bb7d-554e-4025-9c78-370766d7fd35
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1492637133 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_perf.1492637133
Directory	/workspace/28.uart_perf/latest

Test location	/workspace/coverage/default/28.uart_rx_oversample.4128445873
Short name	T483
Test name
Test status
Simulation time	2188477983 ps
CPU time	19.92 seconds
Started	Feb 18 02:05:08 PM PST 24
Finished	Feb 18 02:05:32 PM PST 24
Peak memory	197676 kb
Host	smart-a476e2da-dc82-4ae6-b551-a18e384c4e02
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4128445873 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_oversample.4128445873
Directory	/workspace/28.uart_rx_oversample/latest

Test location	/workspace/coverage/default/28.uart_rx_parity_err.3058682273
Short name	T15
Test name
Test status
Simulation time	58441925563 ps
CPU time	25.91 seconds
Started	Feb 18 02:05:06 PM PST 24
Finished	Feb 18 02:05:36 PM PST 24
Peak memory	199816 kb
Host	smart-001fb8e2-db92-4074-adf6-afd403804c5e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3058682273 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_parity_err.3058682273
Directory	/workspace/28.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/28.uart_rx_start_bit_filter.2707111638
Short name	T456
Test name
Test status
Simulation time	5704532541 ps
CPU time	7.41 seconds
Started	Feb 18 02:05:07 PM PST 24
Finished	Feb 18 02:05:19 PM PST 24
Peak memory	195792 kb
Host	smart-aa4bfa1c-0765-49b5-b24b-3d626a82326f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2707111638 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_start_bit_filter.2707111638
Directory	/workspace/28.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/28.uart_smoke.2167272254
Short name	T867
Test name
Test status
Simulation time	902289422 ps
CPU time	3.07 seconds
Started	Feb 18 02:05:07 PM PST 24
Finished	Feb 18 02:05:14 PM PST 24
Peak memory	199944 kb
Host	smart-efff51f9-ffdd-4acb-b42a-2d297fe815fc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2167272254 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_smoke.2167272254
Directory	/workspace/28.uart_smoke/latest

Test location	/workspace/coverage/default/28.uart_stress_all.589201589
Short name	T232
Test name
Test status
Simulation time	398062234358 ps
CPU time	162.97 seconds
Started	Feb 18 02:05:08 PM PST 24
Finished	Feb 18 02:07:55 PM PST 24
Peak memory	200284 kb
Host	smart-51ddcfb9-1d78-4326-b7f1-a605f11f0c73
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589201589 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_stress_all.589201589
Directory	/workspace/28.uart_stress_all/latest

Test location	/workspace/coverage/default/28.uart_stress_all_with_rand_reset.558773160
Short name	T20
Test name
Test status
Simulation time	156053895139 ps
CPU time	294.03 seconds
Started	Feb 18 02:05:09 PM PST 24
Finished	Feb 18 02:10:07 PM PST 24
Peak memory	216104 kb
Host	smart-48485252-2216-4042-ac2e-ef1cf93abf56
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558773160 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 28.uart_stress_all_with_rand_reset.558773160
Directory	/workspace/28.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/28.uart_tx_ovrd.3328231860
Short name	T707
Test name
Test status
Simulation time	6923524998 ps
CPU time	16.59 seconds
Started	Feb 18 02:05:08 PM PST 24
Finished	Feb 18 02:05:29 PM PST 24
Peak memory	198920 kb
Host	smart-c6179e98-015f-40d7-9033-d81917a197b9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3328231860 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_ovrd.3328231860
Directory	/workspace/28.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/28.uart_tx_rx.4186235629
Short name	T815
Test name
Test status
Simulation time	13418802530 ps
CPU time	9.71 seconds
Started	Feb 18 02:05:11 PM PST 24
Finished	Feb 18 02:05:23 PM PST 24
Peak memory	198408 kb
Host	smart-94526ad2-2388-4b2e-b2e9-16d00d925d8d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4186235629 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_rx.4186235629
Directory	/workspace/28.uart_tx_rx/latest

Test location	/workspace/coverage/default/281.uart_fifo_reset.2185330229
Short name	T256
Test name
Test status
Simulation time	122018037951 ps
CPU time	180.81 seconds
Started	Feb 18 02:08:36 PM PST 24
Finished	Feb 18 02:11:45 PM PST 24
Peak memory	199580 kb
Host	smart-30720174-3f57-4e9e-8705-17fc584f2dff
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2185330229 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.uart_fifo_reset.2185330229
Directory	/workspace/281.uart_fifo_reset/latest

Test location	/workspace/coverage/default/282.uart_fifo_reset.3976243666
Short name	T212
Test name
Test status
Simulation time	271657489320 ps
CPU time	28.18 seconds
Started	Feb 18 02:08:32 PM PST 24
Finished	Feb 18 02:09:04 PM PST 24
Peak memory	200044 kb
Host	smart-4e096c9d-ba6e-40fa-845a-2ba5a85f0e9b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3976243666 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.uart_fifo_reset.3976243666
Directory	/workspace/282.uart_fifo_reset/latest

Test location	/workspace/coverage/default/283.uart_fifo_reset.4146409043
Short name	T571
Test name
Test status
Simulation time	21674530166 ps
CPU time	30.13 seconds
Started	Feb 18 02:08:46 PM PST 24
Finished	Feb 18 02:09:22 PM PST 24
Peak memory	199912 kb
Host	smart-1f67627f-8730-41d0-8af0-10ea4d222b19
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4146409043 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.uart_fifo_reset.4146409043
Directory	/workspace/283.uart_fifo_reset/latest

Test location	/workspace/coverage/default/284.uart_fifo_reset.3326549609
Short name	T928
Test name
Test status
Simulation time	67536290060 ps
CPU time	62.99 seconds
Started	Feb 18 02:08:32 PM PST 24
Finished	Feb 18 02:09:39 PM PST 24
Peak memory	200012 kb
Host	smart-b0aa3c31-cdb2-4ebe-9293-72ed66e5cc0b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3326549609 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.uart_fifo_reset.3326549609
Directory	/workspace/284.uart_fifo_reset/latest

Test location	/workspace/coverage/default/285.uart_fifo_reset.1408211603
Short name	T279
Test name
Test status
Simulation time	126732027622 ps
CPU time	55.58 seconds
Started	Feb 18 02:08:35 PM PST 24
Finished	Feb 18 02:09:39 PM PST 24
Peak memory	200012 kb
Host	smart-9a1ff1ed-0e40-4724-aec7-46ce3564a7cc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1408211603 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.uart_fifo_reset.1408211603
Directory	/workspace/285.uart_fifo_reset/latest

Test location	/workspace/coverage/default/287.uart_fifo_reset.3400435824
Short name	T534
Test name
Test status
Simulation time	103881006001 ps
CPU time	36.78 seconds
Started	Feb 18 02:08:35 PM PST 24
Finished	Feb 18 02:09:20 PM PST 24
Peak memory	199068 kb
Host	smart-3471a822-5a37-4741-a143-23f6bdcf49bf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3400435824 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.uart_fifo_reset.3400435824
Directory	/workspace/287.uart_fifo_reset/latest

Test location	/workspace/coverage/default/288.uart_fifo_reset.2854630198
Short name	T116
Test name
Test status
Simulation time	14023424123 ps
CPU time	13.4 seconds
Started	Feb 18 02:08:34 PM PST 24
Finished	Feb 18 02:08:56 PM PST 24
Peak memory	199844 kb
Host	smart-d97b41df-bf69-4ed4-a23e-332b8486e795
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2854630198 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.uart_fifo_reset.2854630198
Directory	/workspace/288.uart_fifo_reset/latest

Test location	/workspace/coverage/default/289.uart_fifo_reset.2841024560
Short name	T179
Test name
Test status
Simulation time	115772771220 ps
CPU time	54.6 seconds
Started	Feb 18 02:08:34 PM PST 24
Finished	Feb 18 02:09:37 PM PST 24
Peak memory	198384 kb
Host	smart-9b0acf9c-644c-4174-ae9b-1f64aa8dc95f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2841024560 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.uart_fifo_reset.2841024560
Directory	/workspace/289.uart_fifo_reset/latest

Test location	/workspace/coverage/default/29.uart_alert_test.3579777946
Short name	T438
Test name
Test status
Simulation time	106871119 ps
CPU time	0.56 seconds
Started	Feb 18 02:05:17 PM PST 24
Finished	Feb 18 02:05:20 PM PST 24
Peak memory	195412 kb
Host	smart-f208dc76-f4af-459e-890f-8d3cd0f08766
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579777946 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_alert_test.3579777946
Directory	/workspace/29.uart_alert_test/latest

Test location	/workspace/coverage/default/29.uart_fifo_full.2302984046
Short name	T1065
Test name
Test status
Simulation time	174950949001 ps
CPU time	327.35 seconds
Started	Feb 18 02:05:20 PM PST 24
Finished	Feb 18 02:10:51 PM PST 24
Peak memory	200008 kb
Host	smart-603e3468-2ba0-43c1-958d-c710d9e8f1f9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2302984046 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_full.2302984046
Directory	/workspace/29.uart_fifo_full/latest

Test location	/workspace/coverage/default/29.uart_fifo_overflow.660671519
Short name	T345
Test name
Test status
Simulation time	77315852784 ps
CPU time	30.76 seconds
Started	Feb 18 02:05:13 PM PST 24
Finished	Feb 18 02:05:46 PM PST 24
Peak memory	199244 kb
Host	smart-ad119e31-2637-48f5-b504-4d3babcf6ac4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=660671519 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_overflow.660671519
Directory	/workspace/29.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/29.uart_intr.1216227729
Short name	T965
Test name
Test status
Simulation time	664211633070 ps
CPU time	1305.11 seconds
Started	Feb 18 02:05:12 PM PST 24
Finished	Feb 18 02:27:00 PM PST 24
Peak memory	199304 kb
Host	smart-37e6d7d4-0ec7-4108-a02d-d1a657e36832
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216227729 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_intr.1216227729
Directory	/workspace/29.uart_intr/latest

Test location	/workspace/coverage/default/29.uart_long_xfer_wo_dly.2439273753
Short name	T94
Test name
Test status
Simulation time	97116000130 ps
CPU time	106.97 seconds
Started	Feb 18 02:05:17 PM PST 24
Finished	Feb 18 02:07:06 PM PST 24
Peak memory	199940 kb
Host	smart-d2f964a8-a559-4be1-9beb-29b9830ab730
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2439273753 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_long_xfer_wo_dly.2439273753
Directory	/workspace/29.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/29.uart_loopback.3803066927
Short name	T787
Test name
Test status
Simulation time	503099262 ps
CPU time	1.52 seconds
Started	Feb 18 02:05:24 PM PST 24
Finished	Feb 18 02:05:28 PM PST 24
Peak memory	196656 kb
Host	smart-53d3ed8d-a66b-4469-8873-43700e532b2b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3803066927 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_loopback.3803066927
Directory	/workspace/29.uart_loopback/latest

Test location	/workspace/coverage/default/29.uart_noise_filter.2896415089
Short name	T844
Test name
Test status
Simulation time	196637101408 ps
CPU time	160.27 seconds
Started	Feb 18 02:05:16 PM PST 24
Finished	Feb 18 02:07:58 PM PST 24
Peak memory	200040 kb
Host	smart-3d4e65c1-caef-411d-931b-3d40264feebb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2896415089 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_noise_filter.2896415089
Directory	/workspace/29.uart_noise_filter/latest

Test location	/workspace/coverage/default/29.uart_perf.1657895815
Short name	T186
Test name
Test status
Simulation time	6418320524 ps
CPU time	300.11 seconds
Started	Feb 18 02:05:15 PM PST 24
Finished	Feb 18 02:10:17 PM PST 24
Peak memory	200004 kb
Host	smart-e9c2dbcd-1dd5-4ed1-8b2b-76a4c5692730
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1657895815 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_perf.1657895815
Directory	/workspace/29.uart_perf/latest

Test location	/workspace/coverage/default/29.uart_rx_oversample.126253488
Short name	T1082
Test name
Test status
Simulation time	4830020343 ps
CPU time	15.11 seconds
Started	Feb 18 02:05:17 PM PST 24
Finished	Feb 18 02:05:35 PM PST 24
Peak memory	198796 kb
Host	smart-8d5097bb-b8f4-426b-a549-74ddf15e4982
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=126253488 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_oversample.126253488
Directory	/workspace/29.uart_rx_oversample/latest

Test location	/workspace/coverage/default/29.uart_rx_parity_err.2114013702
Short name	T802
Test name
Test status
Simulation time	44464187654 ps
CPU time	10.92 seconds
Started	Feb 18 02:05:16 PM PST 24
Finished	Feb 18 02:05:29 PM PST 24
Peak memory	199240 kb
Host	smart-50fa3b70-0066-49e6-8b85-658545703554
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2114013702 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_parity_err.2114013702
Directory	/workspace/29.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/29.uart_rx_start_bit_filter.3929527068
Short name	T849
Test name
Test status
Simulation time	2966759697 ps
CPU time	1.18 seconds
Started	Feb 18 02:05:18 PM PST 24
Finished	Feb 18 02:05:22 PM PST 24
Peak memory	195504 kb
Host	smart-455b33a5-2750-4d18-9f95-3754cba6c9d1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3929527068 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_start_bit_filter.3929527068
Directory	/workspace/29.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/29.uart_smoke.1609803186
Short name	T737
Test name
Test status
Simulation time	324606389 ps
CPU time	1.19 seconds
Started	Feb 18 02:05:24 PM PST 24
Finished	Feb 18 02:05:28 PM PST 24
Peak memory	198092 kb
Host	smart-6fc5d0f2-8224-4f7c-a230-4dc17680d9be
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1609803186 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_smoke.1609803186
Directory	/workspace/29.uart_smoke/latest

Test location	/workspace/coverage/default/29.uart_stress_all.3437394395
Short name	T191
Test name
Test status
Simulation time	127643501961 ps
CPU time	53.75 seconds
Started	Feb 18 02:05:19 PM PST 24
Finished	Feb 18 02:06:15 PM PST 24
Peak memory	200040 kb
Host	smart-a0004a55-261c-4bca-963b-c47c4bab1fe7
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437394395 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_stress_all.3437394395
Directory	/workspace/29.uart_stress_all/latest

Test location	/workspace/coverage/default/29.uart_stress_all_with_rand_reset.3612578951
Short name	T736
Test name
Test status
Simulation time	95618818002 ps
CPU time	513.19 seconds
Started	Feb 18 02:05:18 PM PST 24
Finished	Feb 18 02:13:54 PM PST 24
Peak memory	216816 kb
Host	smart-07f3c0e0-c93d-4d6b-b705-13d2523343ee
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612578951 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 29.uart_stress_all_with_rand_reset.3612578951
Directory	/workspace/29.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/29.uart_tx_ovrd.3839204791
Short name	T510
Test name
Test status
Simulation time	813814506 ps
CPU time	1.35 seconds
Started	Feb 18 02:05:19 PM PST 24
Finished	Feb 18 02:05:23 PM PST 24
Peak memory	198220 kb
Host	smart-68cb04cf-1a68-4958-a6f1-3bcbe9032680
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3839204791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_ovrd.3839204791
Directory	/workspace/29.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/29.uart_tx_rx.844072396
Short name	T979
Test name
Test status
Simulation time	115970405377 ps
CPU time	50.29 seconds
Started	Feb 18 02:05:18 PM PST 24
Finished	Feb 18 02:06:10 PM PST 24
Peak memory	200068 kb
Host	smart-b193dffd-5017-47c1-8639-64f1dfec5303
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=844072396 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_rx.844072396
Directory	/workspace/29.uart_tx_rx/latest

Test location	/workspace/coverage/default/290.uart_fifo_reset.304871817
Short name	T1022
Test name
Test status
Simulation time	25544373998 ps
CPU time	41.01 seconds
Started	Feb 18 02:08:38 PM PST 24
Finished	Feb 18 02:09:26 PM PST 24
Peak memory	199924 kb
Host	smart-1595f767-1bcc-4e28-a644-51fd4ea70908
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=304871817 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.uart_fifo_reset.304871817
Directory	/workspace/290.uart_fifo_reset/latest

Test location	/workspace/coverage/default/291.uart_fifo_reset.712224434
Short name	T882
Test name
Test status
Simulation time	4269225392 ps
CPU time	10.61 seconds
Started	Feb 18 02:08:34 PM PST 24
Finished	Feb 18 02:08:53 PM PST 24
Peak memory	200056 kb
Host	smart-45393a0a-088f-4961-9f66-28069a370127
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=712224434 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.uart_fifo_reset.712224434
Directory	/workspace/291.uart_fifo_reset/latest

Test location	/workspace/coverage/default/292.uart_fifo_reset.3157351837
Short name	T641
Test name
Test status
Simulation time	86368788132 ps
CPU time	140.46 seconds
Started	Feb 18 02:08:34 PM PST 24
Finished	Feb 18 02:11:03 PM PST 24
Peak memory	200024 kb
Host	smart-0634f848-b5a0-472a-96bd-9e42f49433e8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3157351837 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.uart_fifo_reset.3157351837
Directory	/workspace/292.uart_fifo_reset/latest

Test location	/workspace/coverage/default/293.uart_fifo_reset.622413781
Short name	T254
Test name
Test status
Simulation time	80640189896 ps
CPU time	118.85 seconds
Started	Feb 18 02:08:33 PM PST 24
Finished	Feb 18 02:10:40 PM PST 24
Peak memory	200024 kb
Host	smart-0345292a-87f9-404c-ad84-f3907cd654cb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=622413781 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.uart_fifo_reset.622413781
Directory	/workspace/293.uart_fifo_reset/latest

Test location	/workspace/coverage/default/294.uart_fifo_reset.135074133
Short name	T790
Test name
Test status
Simulation time	30162447354 ps
CPU time	14.23 seconds
Started	Feb 18 02:08:32 PM PST 24
Finished	Feb 18 02:08:51 PM PST 24
Peak memory	200056 kb
Host	smart-57aec794-29eb-4bbb-9884-87c24064b0ab
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=135074133 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.uart_fifo_reset.135074133
Directory	/workspace/294.uart_fifo_reset/latest

Test location	/workspace/coverage/default/295.uart_fifo_reset.4091355834
Short name	T311
Test name
Test status
Simulation time	77327550887 ps
CPU time	33.4 seconds
Started	Feb 18 02:08:34 PM PST 24
Finished	Feb 18 02:09:16 PM PST 24
Peak memory	199860 kb
Host	smart-f870d5ce-2cf9-4d56-b3f7-096b447383b1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4091355834 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.uart_fifo_reset.4091355834
Directory	/workspace/295.uart_fifo_reset/latest

Test location	/workspace/coverage/default/296.uart_fifo_reset.92390126
Short name	T318
Test name
Test status
Simulation time	134484706244 ps
CPU time	34.24 seconds
Started	Feb 18 02:08:46 PM PST 24
Finished	Feb 18 02:09:26 PM PST 24
Peak memory	199944 kb
Host	smart-7601d8a5-5440-4ca4-9fe0-8b14d4f8786a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=92390126 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.uart_fifo_reset.92390126
Directory	/workspace/296.uart_fifo_reset/latest

Test location	/workspace/coverage/default/297.uart_fifo_reset.3158020656
Short name	T124
Test name
Test status
Simulation time	34935413632 ps
CPU time	51.2 seconds
Started	Feb 18 02:08:33 PM PST 24
Finished	Feb 18 02:09:30 PM PST 24
Peak memory	200012 kb
Host	smart-1228e223-41d3-4ce8-9ade-ff370d6c72e5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3158020656 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.uart_fifo_reset.3158020656
Directory	/workspace/297.uart_fifo_reset/latest

Test location	/workspace/coverage/default/298.uart_fifo_reset.3401286882
Short name	T865
Test name
Test status
Simulation time	42915374006 ps
CPU time	16.33 seconds
Started	Feb 18 02:08:36 PM PST 24
Finished	Feb 18 02:09:01 PM PST 24
Peak memory	200040 kb
Host	smart-3799c9f0-3405-4f2e-aa89-55d7cd9337b4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3401286882 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.uart_fifo_reset.3401286882
Directory	/workspace/298.uart_fifo_reset/latest

Test location	/workspace/coverage/default/299.uart_fifo_reset.4231033043
Short name	T500
Test name
Test status
Simulation time	94224622287 ps
CPU time	31.54 seconds
Started	Feb 18 02:08:34 PM PST 24
Finished	Feb 18 02:09:14 PM PST 24
Peak memory	199936 kb
Host	smart-0e08b23c-1337-4f76-b09b-1c2ce94aab70
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4231033043 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.uart_fifo_reset.4231033043
Directory	/workspace/299.uart_fifo_reset/latest

Test location	/workspace/coverage/default/3.uart_alert_test.3099702772
Short name	T5
Test name
Test status
Simulation time	18737095 ps
CPU time	0.56 seconds
Started	Feb 18 02:03:34 PM PST 24
Finished	Feb 18 02:03:44 PM PST 24
Peak memory	195424 kb
Host	smart-e5a6fba2-3b53-404a-9560-c3ac00598b26
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099702772 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_alert_test.3099702772
Directory	/workspace/3.uart_alert_test/latest

Test location	/workspace/coverage/default/3.uart_fifo_full.4237200636
Short name	T608
Test name
Test status
Simulation time	155453730646 ps
CPU time	20.79 seconds
Started	Feb 18 02:03:41 PM PST 24
Finished	Feb 18 02:04:16 PM PST 24
Peak memory	199992 kb
Host	smart-4804be46-a597-4193-b012-20f1b3a87bd4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4237200636 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_full.4237200636
Directory	/workspace/3.uart_fifo_full/latest

Test location	/workspace/coverage/default/3.uart_fifo_reset.1607101748
Short name	T327
Test name
Test status
Simulation time	9285576657 ps
CPU time	9.09 seconds
Started	Feb 18 02:03:38 PM PST 24
Finished	Feb 18 02:04:00 PM PST 24
Peak memory	199568 kb
Host	smart-4643e908-baff-47e6-9187-b47a904cb141
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1607101748 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_reset.1607101748
Directory	/workspace/3.uart_fifo_reset/latest

Test location	/workspace/coverage/default/3.uart_intr.1546032748
Short name	T966
Test name
Test status
Simulation time	194454357721 ps
CPU time	324.04 seconds
Started	Feb 18 02:03:39 PM PST 24
Finished	Feb 18 02:09:16 PM PST 24
Peak memory	200032 kb
Host	smart-58ddcf84-48c2-4f57-8aec-1d7ba91f40af
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546032748 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_intr.1546032748
Directory	/workspace/3.uart_intr/latest

Test location	/workspace/coverage/default/3.uart_long_xfer_wo_dly.3565457096
Short name	T1048
Test name
Test status
Simulation time	76165013614 ps
CPU time	117.2 seconds
Started	Feb 18 02:03:39 PM PST 24
Finished	Feb 18 02:05:49 PM PST 24
Peak memory	200044 kb
Host	smart-76c8453f-1161-47ad-afb8-d683a5e9c45f
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3565457096 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_long_xfer_wo_dly.3565457096
Directory	/workspace/3.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/3.uart_loopback.145355355
Short name	T450
Test name
Test status
Simulation time	1024699219 ps
CPU time	1.29 seconds
Started	Feb 18 02:03:38 PM PST 24
Finished	Feb 18 02:03:52 PM PST 24
Peak memory	195416 kb
Host	smart-f476c333-b8eb-42eb-83d3-36b152191ff4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=145355355 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_loopback.145355355
Directory	/workspace/3.uart_loopback/latest

Test location	/workspace/coverage/default/3.uart_noise_filter.4030393826
Short name	T987
Test name
Test status
Simulation time	55824180435 ps
CPU time	111.4 seconds
Started	Feb 18 02:03:38 PM PST 24
Finished	Feb 18 02:05:42 PM PST 24
Peak memory	199612 kb
Host	smart-0284efe5-c455-45c1-a806-330cf414ee86
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4030393826 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_noise_filter.4030393826
Directory	/workspace/3.uart_noise_filter/latest

Test location	/workspace/coverage/default/3.uart_perf.2987328534
Short name	T843
Test name
Test status
Simulation time	15173005116 ps
CPU time	200.73 seconds
Started	Feb 18 02:03:39 PM PST 24
Finished	Feb 18 02:07:12 PM PST 24
Peak memory	199960 kb
Host	smart-3b07bb0c-1f1b-45e8-bfac-2abbe9e9086d
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2987328534 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_perf.2987328534
Directory	/workspace/3.uart_perf/latest

Test location	/workspace/coverage/default/3.uart_rx_oversample.486291628
Short name	T1102
Test name
Test status
Simulation time	1344100522 ps
CPU time	7.28 seconds
Started	Feb 18 02:03:40 PM PST 24
Finished	Feb 18 02:03:59 PM PST 24
Peak memory	198112 kb
Host	smart-4021f386-acf5-46e6-abc8-3ab7717146ee
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=486291628 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_oversample.486291628
Directory	/workspace/3.uart_rx_oversample/latest

Test location	/workspace/coverage/default/3.uart_rx_start_bit_filter.275551455
Short name	T1092
Test name
Test status
Simulation time	3547599427 ps
CPU time	2.14 seconds
Started	Feb 18 02:03:38 PM PST 24
Finished	Feb 18 02:03:53 PM PST 24
Peak memory	195420 kb
Host	smart-cfe22a33-1b4d-46d6-bf99-5016c2988d41
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=275551455 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_start_bit_filter.275551455
Directory	/workspace/3.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/3.uart_sec_cm.23779434
Short name	T35
Test name
Test status
Simulation time	40989623 ps
CPU time	0.75 seconds
Started	Feb 18 02:03:42 PM PST 24
Finished	Feb 18 02:03:58 PM PST 24
Peak memory	216840 kb
Host	smart-b1b0def9-db30-498c-bad5-8d1339a392b4
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23779434 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_sec_cm.23779434
Directory	/workspace/3.uart_sec_cm/latest

Test location	/workspace/coverage/default/3.uart_smoke.2447800507
Short name	T940
Test name
Test status
Simulation time	5893218372 ps
CPU time	24.19 seconds
Started	Feb 18 02:03:30 PM PST 24
Finished	Feb 18 02:03:55 PM PST 24
Peak memory	199336 kb
Host	smart-9c44e300-0835-485c-a1f9-63741c89660a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2447800507 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_smoke.2447800507
Directory	/workspace/3.uart_smoke/latest

Test location	/workspace/coverage/default/3.uart_stress_all.1934178485
Short name	T694
Test name
Test status
Simulation time	120569537428 ps
CPU time	85.37 seconds
Started	Feb 18 02:03:33 PM PST 24
Finished	Feb 18 02:05:07 PM PST 24
Peak memory	200136 kb
Host	smart-35f36d55-75e6-4fb5-a941-12cf757445c8
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934178485 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_stress_all.1934178485
Directory	/workspace/3.uart_stress_all/latest

Test location	/workspace/coverage/default/3.uart_stress_all_with_rand_reset.3023797095
Short name	T56
Test name
Test status
Simulation time	50045490630 ps
CPU time	498.75 seconds
Started	Feb 18 02:03:36 PM PST 24
Finished	Feb 18 02:12:09 PM PST 24
Peak memory	208392 kb
Host	smart-182078d9-8bd2-47ec-83a4-21192aee0369
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023797095 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 3.uart_stress_all_with_rand_reset.3023797095
Directory	/workspace/3.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/3.uart_tx_ovrd.1707938014
Short name	T1057
Test name
Test status
Simulation time	7124634495 ps
CPU time	8.61 seconds
Started	Feb 18 02:03:37 PM PST 24
Finished	Feb 18 02:04:00 PM PST 24
Peak memory	199588 kb
Host	smart-d1521a03-0ea4-45f5-98bf-8ae5d93d34c6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1707938014 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_ovrd.1707938014
Directory	/workspace/3.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/3.uart_tx_rx.368188671
Short name	T442
Test name
Test status
Simulation time	8238613886 ps
CPU time	4.11 seconds
Started	Feb 18 02:03:33 PM PST 24
Finished	Feb 18 02:03:45 PM PST 24
Peak memory	196084 kb
Host	smart-4de91903-62fe-4a7e-b859-038f233fced4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=368188671 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_rx.368188671
Directory	/workspace/3.uart_tx_rx/latest

Test location	/workspace/coverage/default/30.uart_alert_test.463082041
Short name	T777
Test name
Test status
Simulation time	38733955 ps
CPU time	0.52 seconds
Started	Feb 18 02:05:21 PM PST 24
Finished	Feb 18 02:05:25 PM PST 24
Peak memory	194576 kb
Host	smart-b5edc7b7-a7fa-4530-b40b-b5818f2595d6
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463082041 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_alert_test.463082041
Directory	/workspace/30.uart_alert_test/latest

Test location	/workspace/coverage/default/30.uart_fifo_full.4068910284
Short name	T501
Test name
Test status
Simulation time	20743331632 ps
CPU time	36.28 seconds
Started	Feb 18 02:05:17 PM PST 24
Finished	Feb 18 02:05:56 PM PST 24
Peak memory	200084 kb
Host	smart-50d6fc83-ac78-452f-a92d-b2820f586465
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4068910284 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_full.4068910284
Directory	/workspace/30.uart_fifo_full/latest

Test location	/workspace/coverage/default/30.uart_fifo_overflow.786595524
Short name	T918
Test name
Test status
Simulation time	54958304646 ps
CPU time	94.1 seconds
Started	Feb 18 02:05:20 PM PST 24
Finished	Feb 18 02:06:57 PM PST 24
Peak memory	199148 kb
Host	smart-3207e2ea-fc39-48ed-a31c-e019b24ef22d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=786595524 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_overflow.786595524
Directory	/workspace/30.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/30.uart_fifo_reset.2389728653
Short name	T646
Test name
Test status
Simulation time	179712983711 ps
CPU time	24.48 seconds
Started	Feb 18 02:05:20 PM PST 24
Finished	Feb 18 02:05:48 PM PST 24
Peak memory	198020 kb
Host	smart-755f55f7-19ee-43b7-9d6f-58e7cce5a37e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2389728653 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_reset.2389728653
Directory	/workspace/30.uart_fifo_reset/latest

Test location	/workspace/coverage/default/30.uart_intr.2720939644
Short name	T556
Test name
Test status
Simulation time	113450978172 ps
CPU time	26.63 seconds
Started	Feb 18 02:05:19 PM PST 24
Finished	Feb 18 02:05:48 PM PST 24
Peak memory	200048 kb
Host	smart-eda9774f-26a2-4a1b-b675-2ad257a1181b
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720939644 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_intr.2720939644
Directory	/workspace/30.uart_intr/latest

Test location	/workspace/coverage/default/30.uart_long_xfer_wo_dly.3426966638
Short name	T522
Test name
Test status
Simulation time	131352914816 ps
CPU time	201.76 seconds
Started	Feb 18 02:05:23 PM PST 24
Finished	Feb 18 02:08:48 PM PST 24
Peak memory	200084 kb
Host	smart-41f77850-d16f-4945-9ef1-3c8c056d916e
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3426966638 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_long_xfer_wo_dly.3426966638
Directory	/workspace/30.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/30.uart_loopback.2057991969
Short name	T25
Test name
Test status
Simulation time	4523066631 ps
CPU time	8.72 seconds
Started	Feb 18 02:05:27 PM PST 24
Finished	Feb 18 02:05:46 PM PST 24
Peak memory	199880 kb
Host	smart-1e928f24-4a5a-4b86-83b7-6eacc81ca500
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2057991969 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_loopback.2057991969
Directory	/workspace/30.uart_loopback/latest

Test location	/workspace/coverage/default/30.uart_noise_filter.3813338944
Short name	T853
Test name
Test status
Simulation time	176356196253 ps
CPU time	375.7 seconds
Started	Feb 18 02:05:23 PM PST 24
Finished	Feb 18 02:11:42 PM PST 24
Peak memory	208096 kb
Host	smart-5ceb695e-f892-489e-9dc9-2bfe2884ffed
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3813338944 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_noise_filter.3813338944
Directory	/workspace/30.uart_noise_filter/latest

Test location	/workspace/coverage/default/30.uart_perf.4085506342
Short name	T1002
Test name
Test status
Simulation time	5919132794 ps
CPU time	335.05 seconds
Started	Feb 18 02:05:23 PM PST 24
Finished	Feb 18 02:11:02 PM PST 24
Peak memory	200040 kb
Host	smart-a447258d-8dce-460e-ad76-17bc464fdb0a
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4085506342 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_perf.4085506342
Directory	/workspace/30.uart_perf/latest

Test location	/workspace/coverage/default/30.uart_rx_oversample.841611181
Short name	T630
Test name
Test status
Simulation time	949063777 ps
CPU time	3.83 seconds
Started	Feb 18 02:05:17 PM PST 24
Finished	Feb 18 02:05:24 PM PST 24
Peak memory	198048 kb
Host	smart-9cc2bfd6-7cec-4418-9ef5-d048f744632c
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=841611181 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_oversample.841611181
Directory	/workspace/30.uart_rx_oversample/latest

Test location	/workspace/coverage/default/30.uart_rx_parity_err.3429715732
Short name	T424
Test name
Test status
Simulation time	16096020607 ps
CPU time	24.62 seconds
Started	Feb 18 02:05:20 PM PST 24
Finished	Feb 18 02:05:49 PM PST 24
Peak memory	200032 kb
Host	smart-6dfc2ccb-6d10-4cf0-964d-d11ccda72863
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3429715732 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_parity_err.3429715732
Directory	/workspace/30.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/30.uart_rx_start_bit_filter.4187740135
Short name	T634
Test name
Test status
Simulation time	39388746565 ps
CPU time	33.35 seconds
Started	Feb 18 02:05:21 PM PST 24
Finished	Feb 18 02:05:58 PM PST 24
Peak memory	195572 kb
Host	smart-fd959c2b-6e71-46d2-ae4b-2184a07596f5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4187740135 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_start_bit_filter.4187740135
Directory	/workspace/30.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/30.uart_smoke.3894457200
Short name	T549
Test name
Test status
Simulation time	6068696807 ps
CPU time	7.77 seconds
Started	Feb 18 02:05:19 PM PST 24
Finished	Feb 18 02:05:30 PM PST 24
Peak memory	199320 kb
Host	smart-d75d9400-7c20-414f-af7d-e98243f32c57
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3894457200 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_smoke.3894457200
Directory	/workspace/30.uart_smoke/latest

Test location	/workspace/coverage/default/30.uart_stress_all.3194800421
Short name	T432
Test name
Test status
Simulation time	1494321433927 ps
CPU time	1398.05 seconds
Started	Feb 18 02:05:21 PM PST 24
Finished	Feb 18 02:28:43 PM PST 24
Peak memory	200124 kb
Host	smart-ffa48441-b7a0-4b09-b23b-bac9a9ca1a9c
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194800421 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_stress_all.3194800421
Directory	/workspace/30.uart_stress_all/latest

Test location	/workspace/coverage/default/30.uart_stress_all_with_rand_reset.3022895756
Short name	T429
Test name
Test status
Simulation time	130252906155 ps
CPU time	409.24 seconds
Started	Feb 18 02:05:16 PM PST 24
Finished	Feb 18 02:12:07 PM PST 24
Peak memory	216700 kb
Host	smart-a0d35036-48f4-4c4c-9db1-63188d3afe3e
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022895756 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 30.uart_stress_all_with_rand_reset.3022895756
Directory	/workspace/30.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/30.uart_tx_ovrd.1145023211
Short name	T728
Test name
Test status
Simulation time	1563324521 ps
CPU time	1.48 seconds
Started	Feb 18 02:05:27 PM PST 24
Finished	Feb 18 02:05:39 PM PST 24
Peak memory	198252 kb
Host	smart-7a19dc23-7bcd-43f0-a2ef-d7e56394fd15
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1145023211 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_ovrd.1145023211
Directory	/workspace/30.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/30.uart_tx_rx.3962630582
Short name	T123
Test name
Test status
Simulation time	70022849365 ps
CPU time	82.62 seconds
Started	Feb 18 02:05:20 PM PST 24
Finished	Feb 18 02:06:46 PM PST 24
Peak memory	199808 kb
Host	smart-c51b2102-ebbb-4c44-8789-7312c2131bf7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3962630582 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_rx.3962630582
Directory	/workspace/30.uart_tx_rx/latest

Test location	/workspace/coverage/default/31.uart_alert_test.1884039201
Short name	T638
Test name
Test status
Simulation time	66433985 ps
CPU time	0.59 seconds
Started	Feb 18 02:05:25 PM PST 24
Finished	Feb 18 02:05:32 PM PST 24
Peak memory	195516 kb
Host	smart-1ef8d374-58b1-493f-ac99-13184138b75f
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884039201 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_alert_test.1884039201
Directory	/workspace/31.uart_alert_test/latest

Test location	/workspace/coverage/default/31.uart_fifo_full.3697647139
Short name	T376
Test name
Test status
Simulation time	143282031414 ps
CPU time	62.28 seconds
Started	Feb 18 02:05:27 PM PST 24
Finished	Feb 18 02:06:39 PM PST 24
Peak memory	199996 kb
Host	smart-60597187-fa58-4803-9c4c-b74187c0a660
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3697647139 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_full.3697647139
Directory	/workspace/31.uart_fifo_full/latest

Test location	/workspace/coverage/default/31.uart_fifo_reset.1686182174
Short name	T211
Test name
Test status
Simulation time	20535776881 ps
CPU time	35.76 seconds
Started	Feb 18 02:05:23 PM PST 24
Finished	Feb 18 02:06:02 PM PST 24
Peak memory	200132 kb
Host	smart-d8da488b-9584-4cb9-844d-3212e925e365
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1686182174 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_reset.1686182174
Directory	/workspace/31.uart_fifo_reset/latest

Test location	/workspace/coverage/default/31.uart_intr.3045422721
Short name	T756
Test name
Test status
Simulation time	318234572422 ps
CPU time	337.57 seconds
Started	Feb 18 02:05:24 PM PST 24
Finished	Feb 18 02:11:04 PM PST 24
Peak memory	199488 kb
Host	smart-4c2c24da-fb8b-4487-9554-9314bdc19935
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045422721 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_intr.3045422721
Directory	/workspace/31.uart_intr/latest

Test location	/workspace/coverage/default/31.uart_long_xfer_wo_dly.2790309198
Short name	T414
Test name
Test status
Simulation time	63658884078 ps
CPU time	306.65 seconds
Started	Feb 18 02:05:24 PM PST 24
Finished	Feb 18 02:10:34 PM PST 24
Peak memory	199984 kb
Host	smart-1f4549f7-21b8-41ef-8fed-b704b32bf399
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2790309198 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_long_xfer_wo_dly.2790309198
Directory	/workspace/31.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/31.uart_noise_filter.3222947560
Short name	T935
Test name
Test status
Simulation time	411911684063 ps
CPU time	87.23 seconds
Started	Feb 18 02:05:22 PM PST 24
Finished	Feb 18 02:06:53 PM PST 24
Peak memory	208376 kb
Host	smart-0f8e7274-cca5-43de-8970-b6c18b540f9b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3222947560 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_noise_filter.3222947560
Directory	/workspace/31.uart_noise_filter/latest

Test location	/workspace/coverage/default/31.uart_perf.2947209284
Short name	T994
Test name
Test status
Simulation time	18246957631 ps
CPU time	436.55 seconds
Started	Feb 18 02:05:20 PM PST 24
Finished	Feb 18 02:12:39 PM PST 24
Peak memory	200020 kb
Host	smart-8a1581e4-e0e3-4d96-ba04-55f27c01c25c
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2947209284 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_perf.2947209284
Directory	/workspace/31.uart_perf/latest

Test location	/workspace/coverage/default/31.uart_rx_parity_err.1486374471
Short name	T12
Test name
Test status
Simulation time	74753143188 ps
CPU time	103.22 seconds
Started	Feb 18 02:05:22 PM PST 24
Finished	Feb 18 02:07:09 PM PST 24
Peak memory	199272 kb
Host	smart-dcd63d6e-d36d-490b-95b9-56a7d8e703ea
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1486374471 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_parity_err.1486374471
Directory	/workspace/31.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/31.uart_rx_start_bit_filter.4222096649
Short name	T841
Test name
Test status
Simulation time	667886381 ps
CPU time	1.23 seconds
Started	Feb 18 02:05:22 PM PST 24
Finished	Feb 18 02:05:27 PM PST 24
Peak memory	195416 kb
Host	smart-688b6c44-4230-4648-94f1-316374079c74
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4222096649 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_start_bit_filter.4222096649
Directory	/workspace/31.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/31.uart_smoke.63434508
Short name	T740
Test name
Test status
Simulation time	551641639 ps
CPU time	2.32 seconds
Started	Feb 18 02:05:23 PM PST 24
Finished	Feb 18 02:05:29 PM PST 24
Peak memory	197956 kb
Host	smart-65583274-a180-4611-b78d-6032c9f199ac
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=63434508 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_smoke.63434508
Directory	/workspace/31.uart_smoke/latest

Test location	/workspace/coverage/default/31.uart_stress_all.2210103732
Short name	T827
Test name
Test status
Simulation time	562928185947 ps
CPU time	930.11 seconds
Started	Feb 18 02:05:26 PM PST 24
Finished	Feb 18 02:21:05 PM PST 24
Peak memory	199976 kb
Host	smart-d1ca442a-579f-41f8-a69f-2549ab07fb6b
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210103732 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_stress_all.2210103732
Directory	/workspace/31.uart_stress_all/latest

Test location	/workspace/coverage/default/31.uart_tx_ovrd.3173167737
Short name	T916
Test name
Test status
Simulation time	856585959 ps
CPU time	2.73 seconds
Started	Feb 18 02:05:27 PM PST 24
Finished	Feb 18 02:05:39 PM PST 24
Peak memory	198468 kb
Host	smart-356feb44-7286-4f1f-b4b4-5156527f568a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3173167737 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_ovrd.3173167737
Directory	/workspace/31.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/31.uart_tx_rx.71943712
Short name	T1107
Test name
Test status
Simulation time	150377595268 ps
CPU time	63 seconds
Started	Feb 18 02:05:18 PM PST 24
Finished	Feb 18 02:06:24 PM PST 24
Peak memory	200048 kb
Host	smart-9df8e2a0-0591-4418-b77e-158ec56f14d7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=71943712 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_rx.71943712
Directory	/workspace/31.uart_tx_rx/latest

Test location	/workspace/coverage/default/32.uart_alert_test.3218240353
Short name	T449
Test name
Test status
Simulation time	28290461 ps
CPU time	0.57 seconds
Started	Feb 18 02:05:25 PM PST 24
Finished	Feb 18 02:05:31 PM PST 24
Peak memory	195496 kb
Host	smart-265ea24f-63b6-4d4c-9a0d-6b0bd3ecc4c3
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218240353 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_alert_test.3218240353
Directory	/workspace/32.uart_alert_test/latest

Test location	/workspace/coverage/default/32.uart_fifo_full.3376941267
Short name	T779
Test name
Test status
Simulation time	23912118306 ps
CPU time	49.92 seconds
Started	Feb 18 02:05:26 PM PST 24
Finished	Feb 18 02:06:25 PM PST 24
Peak memory	200012 kb
Host	smart-1e16a984-b666-4cee-b219-1d305c8c2db5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3376941267 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_full.3376941267
Directory	/workspace/32.uart_fifo_full/latest

Test location	/workspace/coverage/default/32.uart_fifo_overflow.4177164068
Short name	T1073
Test name
Test status
Simulation time	13752795237 ps
CPU time	6.25 seconds
Started	Feb 18 02:05:30 PM PST 24
Finished	Feb 18 02:05:48 PM PST 24
Peak memory	198340 kb
Host	smart-f51e2045-2b02-4ce9-b55d-3fdc278e1a1e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4177164068 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_overflow.4177164068
Directory	/workspace/32.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/32.uart_fifo_reset.3131541272
Short name	T121
Test name
Test status
Simulation time	29214484135 ps
CPU time	21.88 seconds
Started	Feb 18 02:05:30 PM PST 24
Finished	Feb 18 02:06:04 PM PST 24
Peak memory	200004 kb
Host	smart-6bf7f142-c939-4ec1-a2b4-5668a84ae2b1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3131541272 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_reset.3131541272
Directory	/workspace/32.uart_fifo_reset/latest

Test location	/workspace/coverage/default/32.uart_intr.3945703215
Short name	T944
Test name
Test status
Simulation time	780958326967 ps
CPU time	1164.76 seconds
Started	Feb 18 02:05:25 PM PST 24
Finished	Feb 18 02:24:55 PM PST 24
Peak memory	199716 kb
Host	smart-fcb2387d-41af-4da5-a137-0626cde05972
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945703215 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_intr.3945703215
Directory	/workspace/32.uart_intr/latest

Test location	/workspace/coverage/default/32.uart_long_xfer_wo_dly.822258639
Short name	T1119
Test name
Test status
Simulation time	168564705642 ps
CPU time	1141.45 seconds
Started	Feb 18 02:05:26 PM PST 24
Finished	Feb 18 02:24:37 PM PST 24
Peak memory	200052 kb
Host	smart-d394b009-2638-4661-b582-00ce83807957
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=822258639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_long_xfer_wo_dly.822258639
Directory	/workspace/32.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/32.uart_loopback.326057145
Short name	T977
Test name
Test status
Simulation time	9499251776 ps
CPU time	19.27 seconds
Started	Feb 18 02:05:28 PM PST 24
Finished	Feb 18 02:05:59 PM PST 24
Peak memory	199952 kb
Host	smart-f4f74766-17f5-4328-b151-beb1f3a0e07d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=326057145 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_loopback.326057145
Directory	/workspace/32.uart_loopback/latest

Test location	/workspace/coverage/default/32.uart_perf.3956342302
Short name	T207
Test name
Test status
Simulation time	15100820409 ps
CPU time	177.71 seconds
Started	Feb 18 02:05:25 PM PST 24
Finished	Feb 18 02:08:26 PM PST 24
Peak memory	200004 kb
Host	smart-85bd0390-95cd-49b6-a87a-63b87d90b93b
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3956342302 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_perf.3956342302
Directory	/workspace/32.uart_perf/latest

Test location	/workspace/coverage/default/32.uart_rx_oversample.4114351928
Short name	T1030
Test name
Test status
Simulation time	577100031 ps
CPU time	1.1 seconds
Started	Feb 18 02:05:25 PM PST 24
Finished	Feb 18 02:05:33 PM PST 24
Peak memory	197884 kb
Host	smart-81b5c551-4dfe-45da-a8a4-189352183804
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4114351928 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_oversample.4114351928
Directory	/workspace/32.uart_rx_oversample/latest

Test location	/workspace/coverage/default/32.uart_rx_start_bit_filter.3481866179
Short name	T482
Test name
Test status
Simulation time	3145527167 ps
CPU time	5.62 seconds
Started	Feb 18 02:05:26 PM PST 24
Finished	Feb 18 02:05:39 PM PST 24
Peak memory	195868 kb
Host	smart-64311442-78e9-49dc-a098-b0fffd2c4013
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3481866179 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_start_bit_filter.3481866179
Directory	/workspace/32.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/32.uart_smoke.2717907765
Short name	T398
Test name
Test status
Simulation time	5262234561 ps
CPU time	13.76 seconds
Started	Feb 18 02:05:25 PM PST 24
Finished	Feb 18 02:05:44 PM PST 24
Peak memory	199440 kb
Host	smart-b2decd69-8ad9-4dd9-a3b4-af40ca5c019d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2717907765 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_smoke.2717907765
Directory	/workspace/32.uart_smoke/latest

Test location	/workspace/coverage/default/32.uart_stress_all.1624379477
Short name	T349
Test name
Test status
Simulation time	328230980892 ps
CPU time	149.76 seconds
Started	Feb 18 02:05:26 PM PST 24
Finished	Feb 18 02:08:06 PM PST 24
Peak memory	200052 kb
Host	smart-ac0f3951-dbb0-4e6b-9cef-ca951bddc8ff
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624379477 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_stress_all.1624379477
Directory	/workspace/32.uart_stress_all/latest

Test location	/workspace/coverage/default/32.uart_tx_ovrd.384350649
Short name	T830
Test name
Test status
Simulation time	1173630396 ps
CPU time	2.03 seconds
Started	Feb 18 02:05:25 PM PST 24
Finished	Feb 18 02:05:31 PM PST 24
Peak memory	198224 kb
Host	smart-43bfc3d0-6079-4f27-85e4-25dd496ee83f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=384350649 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_ovrd.384350649
Directory	/workspace/32.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/32.uart_tx_rx.3801896470
Short name	T775
Test name
Test status
Simulation time	60050998942 ps
CPU time	27.51 seconds
Started	Feb 18 02:05:26 PM PST 24
Finished	Feb 18 02:06:03 PM PST 24
Peak memory	199964 kb
Host	smart-5ae1487d-4ba5-4cbc-afe3-eec04f27de53
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3801896470 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_rx.3801896470
Directory	/workspace/32.uart_tx_rx/latest

Test location	/workspace/coverage/default/33.uart_alert_test.887792505
Short name	T866
Test name
Test status
Simulation time	15498054 ps
CPU time	0.56 seconds
Started	Feb 18 02:05:37 PM PST 24
Finished	Feb 18 02:05:48 PM PST 24
Peak memory	195524 kb
Host	smart-655a0b73-bf40-4468-afec-4525d8fdbde9
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887792505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_alert_test.887792505
Directory	/workspace/33.uart_alert_test/latest

Test location	/workspace/coverage/default/33.uart_fifo_full.3714386614
Short name	T514
Test name
Test status
Simulation time	196319060533 ps
CPU time	325.28 seconds
Started	Feb 18 02:05:26 PM PST 24
Finished	Feb 18 02:11:01 PM PST 24
Peak memory	200004 kb
Host	smart-32976bbe-254f-46d8-834c-ef2ab30c211e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3714386614 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_full.3714386614
Directory	/workspace/33.uart_fifo_full/latest

Test location	/workspace/coverage/default/33.uart_fifo_overflow.4242990210
Short name	T378
Test name
Test status
Simulation time	68235422355 ps
CPU time	12.53 seconds
Started	Feb 18 02:05:27 PM PST 24
Finished	Feb 18 02:05:51 PM PST 24
Peak memory	199968 kb
Host	smart-905be676-f5bf-4583-a19f-95fc48c2e93a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4242990210 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_overflow.4242990210
Directory	/workspace/33.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/33.uart_fifo_reset.4141418234
Short name	T188
Test name
Test status
Simulation time	56931082221 ps
CPU time	91.5 seconds
Started	Feb 18 02:05:37 PM PST 24
Finished	Feb 18 02:07:18 PM PST 24
Peak memory	199228 kb
Host	smart-87910411-0717-4ac4-82eb-fb09bfa4e881
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4141418234 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_reset.4141418234
Directory	/workspace/33.uart_fifo_reset/latest

Test location	/workspace/coverage/default/33.uart_intr.1739977933
Short name	T574
Test name
Test status
Simulation time	1193778452916 ps
CPU time	418.91 seconds
Started	Feb 18 02:05:35 PM PST 24
Finished	Feb 18 02:12:44 PM PST 24
Peak memory	200024 kb
Host	smart-3fc16cc4-75a5-46df-8939-1b2c25a8c95e
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739977933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_intr.1739977933
Directory	/workspace/33.uart_intr/latest

Test location	/workspace/coverage/default/33.uart_long_xfer_wo_dly.2611970992
Short name	T755
Test name
Test status
Simulation time	102194826288 ps
CPU time	596.11 seconds
Started	Feb 18 02:05:41 PM PST 24
Finished	Feb 18 02:15:47 PM PST 24
Peak memory	199708 kb
Host	smart-ea76160d-d24d-4e10-9f0f-5a6f8a4dd3c6
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2611970992 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_long_xfer_wo_dly.2611970992
Directory	/workspace/33.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/33.uart_loopback.1605385538
Short name	T991
Test name
Test status
Simulation time	1504275461 ps
CPU time	5.06 seconds
Started	Feb 18 02:05:41 PM PST 24
Finished	Feb 18 02:05:56 PM PST 24
Peak memory	196580 kb
Host	smart-221f95ce-d155-4f6d-8de8-efcdb5e55690
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1605385538 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_loopback.1605385538
Directory	/workspace/33.uart_loopback/latest

Test location	/workspace/coverage/default/33.uart_noise_filter.4240462547
Short name	T948
Test name
Test status
Simulation time	70811458854 ps
CPU time	121.13 seconds
Started	Feb 18 02:05:35 PM PST 24
Finished	Feb 18 02:07:46 PM PST 24
Peak memory	200304 kb
Host	smart-a6f8ceae-e05d-4ac5-99f0-b49e19ab1901
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4240462547 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_noise_filter.4240462547
Directory	/workspace/33.uart_noise_filter/latest

Test location	/workspace/coverage/default/33.uart_perf.2700811363
Short name	T1018
Test name
Test status
Simulation time	14336226624 ps
CPU time	729.54 seconds
Started	Feb 18 02:05:37 PM PST 24
Finished	Feb 18 02:17:56 PM PST 24
Peak memory	200040 kb
Host	smart-618e213c-0fbb-4895-a568-740b6d52948d
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2700811363 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_perf.2700811363
Directory	/workspace/33.uart_perf/latest

Test location	/workspace/coverage/default/33.uart_rx_oversample.1879375678
Short name	T767
Test name
Test status
Simulation time	5162082380 ps
CPU time	21.04 seconds
Started	Feb 18 02:05:40 PM PST 24
Finished	Feb 18 02:06:11 PM PST 24
Peak memory	198688 kb
Host	smart-3c5f43b6-012c-43df-abb7-aa5af06310ba
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1879375678 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_oversample.1879375678
Directory	/workspace/33.uart_rx_oversample/latest

Test location	/workspace/coverage/default/33.uart_rx_parity_err.843538016
Short name	T570
Test name
Test status
Simulation time	19813675305 ps
CPU time	28.81 seconds
Started	Feb 18 02:05:37 PM PST 24
Finished	Feb 18 02:06:15 PM PST 24
Peak memory	199996 kb
Host	smart-3c75894f-2a55-4607-94c2-ab5b64d9b680
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=843538016 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_parity_err.843538016
Directory	/workspace/33.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/33.uart_rx_start_bit_filter.3413915359
Short name	T855
Test name
Test status
Simulation time	46006324822 ps
CPU time	62.35 seconds
Started	Feb 18 02:05:38 PM PST 24
Finished	Feb 18 02:06:51 PM PST 24
Peak memory	195880 kb
Host	smart-db73cb49-5949-4e9a-9f53-1a3ae9c302ca
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3413915359 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_start_bit_filter.3413915359
Directory	/workspace/33.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/33.uart_smoke.3250988713
Short name	T536
Test name
Test status
Simulation time	149148410 ps
CPU time	0.8 seconds
Started	Feb 18 02:05:25 PM PST 24
Finished	Feb 18 02:05:31 PM PST 24
Peak memory	196716 kb
Host	smart-efdb882f-f288-483e-a114-429745060cf4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3250988713 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_smoke.3250988713
Directory	/workspace/33.uart_smoke/latest

Test location	/workspace/coverage/default/33.uart_stress_all.1143068858
Short name	T906
Test name
Test status
Simulation time	314746596150 ps
CPU time	504.53 seconds
Started	Feb 18 02:05:37 PM PST 24
Finished	Feb 18 02:14:11 PM PST 24
Peak memory	216072 kb
Host	smart-563c828a-3b26-4ac9-89a8-e8569d440035
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143068858 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_stress_all.1143068858
Directory	/workspace/33.uart_stress_all/latest

Test location	/workspace/coverage/default/33.uart_tx_ovrd.4021160814
Short name	T1040
Test name
Test status
Simulation time	738256617 ps
CPU time	2.5 seconds
Started	Feb 18 02:05:38 PM PST 24
Finished	Feb 18 02:05:51 PM PST 24
Peak memory	199000 kb
Host	smart-b35f1af6-1488-4d40-aec9-ebb0bb140fc8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4021160814 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_ovrd.4021160814
Directory	/workspace/33.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/33.uart_tx_rx.754898786
Short name	T1068
Test name
Test status
Simulation time	12896808477 ps
CPU time	10.65 seconds
Started	Feb 18 02:05:27 PM PST 24
Finished	Feb 18 02:05:48 PM PST 24
Peak memory	200012 kb
Host	smart-d1211337-0cc0-416b-ba3d-01c4e99267f7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=754898786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_rx.754898786
Directory	/workspace/33.uart_tx_rx/latest

Test location	/workspace/coverage/default/34.uart_alert_test.1111717271
Short name	T525
Test name
Test status
Simulation time	11273744 ps
CPU time	0.56 seconds
Started	Feb 18 02:05:37 PM PST 24
Finished	Feb 18 02:05:48 PM PST 24
Peak memory	194572 kb
Host	smart-a6e13d02-6535-4eeb-b129-97f9d8767a58
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111717271 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_alert_test.1111717271
Directory	/workspace/34.uart_alert_test/latest

Test location	/workspace/coverage/default/34.uart_fifo_full.3116036844
Short name	T393
Test name
Test status
Simulation time	69651390931 ps
CPU time	29.62 seconds
Started	Feb 18 02:05:41 PM PST 24
Finished	Feb 18 02:06:21 PM PST 24
Peak memory	200048 kb
Host	smart-faf97e18-787c-40cd-9cf1-be1105a01856
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3116036844 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_full.3116036844
Directory	/workspace/34.uart_fifo_full/latest

Test location	/workspace/coverage/default/34.uart_fifo_overflow.2541941812
Short name	T347
Test name
Test status
Simulation time	19385614200 ps
CPU time	28.92 seconds
Started	Feb 18 02:05:38 PM PST 24
Finished	Feb 18 02:06:17 PM PST 24
Peak memory	199340 kb
Host	smart-162e47c7-f3af-4fa2-a116-8fc4ed8eb234
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2541941812 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_overflow.2541941812
Directory	/workspace/34.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/34.uart_fifo_reset.3333916178
Short name	T796
Test name
Test status
Simulation time	19435142497 ps
CPU time	35.47 seconds
Started	Feb 18 02:05:36 PM PST 24
Finished	Feb 18 02:06:21 PM PST 24
Peak memory	199468 kb
Host	smart-a033111a-d235-4f44-8e42-a4eb21fa2c38
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3333916178 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_reset.3333916178
Directory	/workspace/34.uart_fifo_reset/latest

Test location	/workspace/coverage/default/34.uart_intr.456320973
Short name	T560
Test name
Test status
Simulation time	47097535263 ps
CPU time	63.94 seconds
Started	Feb 18 02:05:37 PM PST 24
Finished	Feb 18 02:06:50 PM PST 24
Peak memory	197824 kb
Host	smart-2743965e-08df-4d99-ae8b-547809a93b57
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456320973 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_intr.456320973
Directory	/workspace/34.uart_intr/latest

Test location	/workspace/coverage/default/34.uart_long_xfer_wo_dly.4211343642
Short name	T769
Test name
Test status
Simulation time	117106332009 ps
CPU time	726.96 seconds
Started	Feb 18 02:05:39 PM PST 24
Finished	Feb 18 02:17:55 PM PST 24
Peak memory	199924 kb
Host	smart-e3cb2e7b-cb16-4127-8b89-29922a0e653e
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4211343642 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_long_xfer_wo_dly.4211343642
Directory	/workspace/34.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/34.uart_loopback.3214999247
Short name	T1079
Test name
Test status
Simulation time	4059600821 ps
CPU time	2.57 seconds
Started	Feb 18 02:05:37 PM PST 24
Finished	Feb 18 02:05:50 PM PST 24
Peak memory	195804 kb
Host	smart-10fcfe59-439b-4b1a-9abb-6f661969e5a8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3214999247 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_loopback.3214999247
Directory	/workspace/34.uart_loopback/latest

Test location	/workspace/coverage/default/34.uart_noise_filter.2785328584
Short name	T846
Test name
Test status
Simulation time	116074607573 ps
CPU time	77.37 seconds
Started	Feb 18 02:05:37 PM PST 24
Finished	Feb 18 02:07:04 PM PST 24
Peak memory	199336 kb
Host	smart-eea2618d-29f7-4020-9f02-0545e24dae37
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2785328584 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_noise_filter.2785328584
Directory	/workspace/34.uart_noise_filter/latest

Test location	/workspace/coverage/default/34.uart_perf.2861199338
Short name	T852
Test name
Test status
Simulation time	11412445638 ps
CPU time	609.27 seconds
Started	Feb 18 02:05:38 PM PST 24
Finished	Feb 18 02:15:58 PM PST 24
Peak memory	200076 kb
Host	smart-b90fa1cb-6064-4425-8386-8ecdf92d416b
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2861199338 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_perf.2861199338
Directory	/workspace/34.uart_perf/latest

Test location	/workspace/coverage/default/34.uart_rx_oversample.4062209463
Short name	T540
Test name
Test status
Simulation time	2084231841 ps
CPU time	9.92 seconds
Started	Feb 18 02:05:38 PM PST 24
Finished	Feb 18 02:05:58 PM PST 24
Peak memory	198096 kb
Host	smart-9562dd59-d536-4f2e-91c3-871ea6c1c467
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4062209463 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_oversample.4062209463
Directory	/workspace/34.uart_rx_oversample/latest

Test location	/workspace/coverage/default/34.uart_rx_parity_err.512440536
Short name	T639
Test name
Test status
Simulation time	77151975935 ps
CPU time	24.83 seconds
Started	Feb 18 02:05:35 PM PST 24
Finished	Feb 18 02:06:10 PM PST 24
Peak memory	199268 kb
Host	smart-261c21c0-b611-42dd-a5be-8456220d496e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=512440536 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_parity_err.512440536
Directory	/workspace/34.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/34.uart_rx_start_bit_filter.3465931717
Short name	T604
Test name
Test status
Simulation time	458334616 ps
CPU time	1.42 seconds
Started	Feb 18 02:05:36 PM PST 24
Finished	Feb 18 02:05:47 PM PST 24
Peak memory	195436 kb
Host	smart-425a7ff7-ca51-4df8-bf57-656e3b657169
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3465931717 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_start_bit_filter.3465931717
Directory	/workspace/34.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/34.uart_smoke.2130392361
Short name	T774
Test name
Test status
Simulation time	636486665 ps
CPU time	1.57 seconds
Started	Feb 18 02:05:36 PM PST 24
Finished	Feb 18 02:05:47 PM PST 24
Peak memory	198380 kb
Host	smart-f94a2cc8-15f3-4769-9dc2-d27a60d18fb3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2130392361 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_smoke.2130392361
Directory	/workspace/34.uart_smoke/latest

Test location	/workspace/coverage/default/34.uart_stress_all.242159615
Short name	T103
Test name
Test status
Simulation time	70519452599 ps
CPU time	120.28 seconds
Started	Feb 18 02:05:35 PM PST 24
Finished	Feb 18 02:07:45 PM PST 24
Peak memory	200140 kb
Host	smart-43cb1e62-2e81-42ed-bd29-ba748f65a001
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242159615 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_stress_all.242159615
Directory	/workspace/34.uart_stress_all/latest

Test location	/workspace/coverage/default/34.uart_stress_all_with_rand_reset.3282659954
Short name	T947
Test name
Test status
Simulation time	66189109934 ps
CPU time	515.63 seconds
Started	Feb 18 02:05:41 PM PST 24
Finished	Feb 18 02:14:27 PM PST 24
Peak memory	208556 kb
Host	smart-5c8b1fc9-2095-40e0-ac47-d35bd5d784f7
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282659954 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 34.uart_stress_all_with_rand_reset.3282659954
Directory	/workspace/34.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/34.uart_tx_ovrd.1492157675
Short name	T934
Test name
Test status
Simulation time	2418957058 ps
CPU time	3.21 seconds
Started	Feb 18 02:05:34 PM PST 24
Finished	Feb 18 02:05:48 PM PST 24
Peak memory	198652 kb
Host	smart-ad3f125f-6682-476f-866a-0eac61fed8e3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1492157675 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_ovrd.1492157675
Directory	/workspace/34.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/34.uart_tx_rx.1856098908
Short name	T625
Test name
Test status
Simulation time	6608052161 ps
CPU time	5.23 seconds
Started	Feb 18 02:05:36 PM PST 24
Finished	Feb 18 02:05:51 PM PST 24
Peak memory	196504 kb
Host	smart-d51457e9-ebbc-4cce-907f-27508ed07850
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1856098908 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_rx.1856098908
Directory	/workspace/34.uart_tx_rx/latest

Test location	/workspace/coverage/default/35.uart_alert_test.1114664747
Short name	T985
Test name
Test status
Simulation time	13857974 ps
CPU time	0.62 seconds
Started	Feb 18 02:05:42 PM PST 24
Finished	Feb 18 02:05:53 PM PST 24
Peak memory	194300 kb
Host	smart-8e1391db-8cb2-4408-881c-ab53996afb06
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114664747 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_alert_test.1114664747
Directory	/workspace/35.uart_alert_test/latest

Test location	/workspace/coverage/default/35.uart_fifo_full.26432027
Short name	T278
Test name
Test status
Simulation time	301923798322 ps
CPU time	64.13 seconds
Started	Feb 18 02:05:36 PM PST 24
Finished	Feb 18 02:06:50 PM PST 24
Peak memory	200024 kb
Host	smart-ca9f46ec-29f2-4734-99e4-4ed02e619408
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=26432027 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_full.26432027
Directory	/workspace/35.uart_fifo_full/latest

Test location	/workspace/coverage/default/35.uart_fifo_overflow.1150698470
Short name	T400
Test name
Test status
Simulation time	72701246138 ps
CPU time	12.61 seconds
Started	Feb 18 02:05:37 PM PST 24
Finished	Feb 18 02:05:59 PM PST 24
Peak memory	199104 kb
Host	smart-8c607fdb-f0cf-4feb-a461-bc3e63c2056e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1150698470 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_overflow.1150698470
Directory	/workspace/35.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/35.uart_fifo_reset.1416663173
Short name	T146
Test name
Test status
Simulation time	86146985646 ps
CPU time	138.03 seconds
Started	Feb 18 02:05:39 PM PST 24
Finished	Feb 18 02:08:06 PM PST 24
Peak memory	199780 kb
Host	smart-136bcbe5-cb77-429d-bfc5-803530f08c40
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1416663173 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_reset.1416663173
Directory	/workspace/35.uart_fifo_reset/latest

Test location	/workspace/coverage/default/35.uart_intr.1903470028
Short name	T803
Test name
Test status
Simulation time	334402950119 ps
CPU time	157.03 seconds
Started	Feb 18 02:05:48 PM PST 24
Finished	Feb 18 02:08:33 PM PST 24
Peak memory	199776 kb
Host	smart-f15c00e6-7a2e-4491-952f-4cbe2ad75ff5
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903470028 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_intr.1903470028
Directory	/workspace/35.uart_intr/latest

Test location	/workspace/coverage/default/35.uart_long_xfer_wo_dly.1206583282
Short name	T665
Test name
Test status
Simulation time	160206705463 ps
CPU time	734.47 seconds
Started	Feb 18 02:05:47 PM PST 24
Finished	Feb 18 02:18:10 PM PST 24
Peak memory	199960 kb
Host	smart-c46368cd-7775-49bd-80e4-ada260dd4369
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1206583282 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_long_xfer_wo_dly.1206583282
Directory	/workspace/35.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/35.uart_loopback.506687440
Short name	T988
Test name
Test status
Simulation time	7382130621 ps
CPU time	8.67 seconds
Started	Feb 18 02:05:47 PM PST 24
Finished	Feb 18 02:06:04 PM PST 24
Peak memory	199024 kb
Host	smart-c23f9103-4717-486d-92e1-2b1c51ba1e0f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=506687440 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_loopback.506687440
Directory	/workspace/35.uart_loopback/latest

Test location	/workspace/coverage/default/35.uart_noise_filter.2671910928
Short name	T1070
Test name
Test status
Simulation time	7687526463 ps
CPU time	7.66 seconds
Started	Feb 18 02:05:41 PM PST 24
Finished	Feb 18 02:05:59 PM PST 24
Peak memory	195984 kb
Host	smart-02cef432-8c1a-4919-b5f0-06423c8e9123
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2671910928 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_noise_filter.2671910928
Directory	/workspace/35.uart_noise_filter/latest

Test location	/workspace/coverage/default/35.uart_perf.592609315
Short name	T952
Test name
Test status
Simulation time	16765212675 ps
CPU time	99.72 seconds
Started	Feb 18 02:05:38 PM PST 24
Finished	Feb 18 02:07:28 PM PST 24
Peak memory	199932 kb
Host	smart-24debb02-f10f-4c2b-8519-ddd300313529
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=592609315 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_perf.592609315
Directory	/workspace/35.uart_perf/latest

Test location	/workspace/coverage/default/35.uart_rx_oversample.1670149717
Short name	T474
Test name
Test status
Simulation time	2860293206 ps
CPU time	10.69 seconds
Started	Feb 18 02:05:41 PM PST 24
Finished	Feb 18 02:06:02 PM PST 24
Peak memory	198512 kb
Host	smart-5339e313-cae6-4a8d-ac7a-40c1ce477a38
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1670149717 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_oversample.1670149717
Directory	/workspace/35.uart_rx_oversample/latest

Test location	/workspace/coverage/default/35.uart_rx_parity_err.726824797
Short name	T8
Test name
Test status
Simulation time	77835816120 ps
CPU time	38.87 seconds
Started	Feb 18 02:05:43 PM PST 24
Finished	Feb 18 02:06:31 PM PST 24
Peak memory	200132 kb
Host	smart-11c34560-f717-4b8b-a4dc-33db5525ecb0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=726824797 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_parity_err.726824797
Directory	/workspace/35.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/35.uart_rx_start_bit_filter.1593013831
Short name	T613
Test name
Test status
Simulation time	42749488027 ps
CPU time	28.22 seconds
Started	Feb 18 02:05:42 PM PST 24
Finished	Feb 18 02:06:20 PM PST 24
Peak memory	195532 kb
Host	smart-af503d54-53d8-4bb4-a216-cd51c9b1a7f1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1593013831 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_start_bit_filter.1593013831
Directory	/workspace/35.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/35.uart_smoke.274834563
Short name	T842
Test name
Test status
Simulation time	717507909 ps
CPU time	2.27 seconds
Started	Feb 18 02:05:37 PM PST 24
Finished	Feb 18 02:05:49 PM PST 24
Peak memory	198352 kb
Host	smart-9ef083dc-2985-48c2-89e2-5cfc9f05dbed
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=274834563 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_smoke.274834563
Directory	/workspace/35.uart_smoke/latest

Test location	/workspace/coverage/default/35.uart_stress_all.1971201895
Short name	T362
Test name
Test status
Simulation time	137270735270 ps
CPU time	1258.04 seconds
Started	Feb 18 02:05:45 PM PST 24
Finished	Feb 18 02:26:53 PM PST 24
Peak memory	200032 kb
Host	smart-95d77f5c-250a-43ca-8d40-f1cd8a7c3e33
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971201895 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_stress_all.1971201895
Directory	/workspace/35.uart_stress_all/latest

Test location	/workspace/coverage/default/35.uart_tx_ovrd.1284917882
Short name	T691
Test name
Test status
Simulation time	1447348299 ps
CPU time	1.64 seconds
Started	Feb 18 02:05:47 PM PST 24
Finished	Feb 18 02:05:57 PM PST 24
Peak memory	198896 kb
Host	smart-cf14f56c-13f9-4e39-8529-9b2d44cb55ea
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1284917882 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_ovrd.1284917882
Directory	/workspace/35.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/35.uart_tx_rx.2025785664
Short name	T417
Test name
Test status
Simulation time	30466491563 ps
CPU time	25.39 seconds
Started	Feb 18 02:05:35 PM PST 24
Finished	Feb 18 02:06:11 PM PST 24
Peak memory	197344 kb
Host	smart-b1212613-ecdb-4215-877b-a14a13c1497e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2025785664 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_rx.2025785664
Directory	/workspace/35.uart_tx_rx/latest

Test location	/workspace/coverage/default/36.uart_alert_test.1246603295
Short name	T440
Test name
Test status
Simulation time	35708917 ps
CPU time	0.55 seconds
Started	Feb 18 02:05:48 PM PST 24
Finished	Feb 18 02:05:57 PM PST 24
Peak memory	195504 kb
Host	smart-a614487e-a9aa-4dc3-a3ee-128505576d47
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246603295 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_alert_test.1246603295
Directory	/workspace/36.uart_alert_test/latest

Test location	/workspace/coverage/default/36.uart_fifo_full.1592673194
Short name	T697
Test name
Test status
Simulation time	25361323573 ps
CPU time	37.91 seconds
Started	Feb 18 02:05:38 PM PST 24
Finished	Feb 18 02:06:26 PM PST 24
Peak memory	200008 kb
Host	smart-157db62b-5244-43bd-858b-751540a32a11
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1592673194 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_full.1592673194
Directory	/workspace/36.uart_fifo_full/latest

Test location	/workspace/coverage/default/36.uart_fifo_overflow.4240196257
Short name	T1103
Test name
Test status
Simulation time	75278662321 ps
CPU time	15.5 seconds
Started	Feb 18 02:05:42 PM PST 24
Finished	Feb 18 02:06:08 PM PST 24
Peak memory	199772 kb
Host	smart-911e9873-72de-4b65-8ea5-64d35f970231
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4240196257 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_overflow.4240196257
Directory	/workspace/36.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/36.uart_intr.1303803856
Short name	T808
Test name
Test status
Simulation time	23236296936 ps
CPU time	29.57 seconds
Started	Feb 18 02:05:44 PM PST 24
Finished	Feb 18 02:06:23 PM PST 24
Peak memory	196400 kb
Host	smart-6875522d-e226-4a48-88ea-cb4f4d582ab5
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303803856 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_intr.1303803856
Directory	/workspace/36.uart_intr/latest

Test location	/workspace/coverage/default/36.uart_long_xfer_wo_dly.438784348
Short name	T1101
Test name
Test status
Simulation time	137392137290 ps
CPU time	525.51 seconds
Started	Feb 18 02:05:42 PM PST 24
Finished	Feb 18 02:14:37 PM PST 24
Peak memory	200044 kb
Host	smart-5c3e0a49-ab70-4496-a3a5-a5b5419ecc33
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=438784348 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_long_xfer_wo_dly.438784348
Directory	/workspace/36.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/36.uart_loopback.4046041800
Short name	T1052
Test name
Test status
Simulation time	8480986985 ps
CPU time	9.92 seconds
Started	Feb 18 02:05:44 PM PST 24
Finished	Feb 18 02:06:04 PM PST 24
Peak memory	198704 kb
Host	smart-4193101d-6e41-4d06-8d92-d4daad748ee1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4046041800 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_loopback.4046041800
Directory	/workspace/36.uart_loopback/latest

Test location	/workspace/coverage/default/36.uart_noise_filter.2571006752
Short name	T433
Test name
Test status
Simulation time	59027993722 ps
CPU time	44.73 seconds
Started	Feb 18 02:05:40 PM PST 24
Finished	Feb 18 02:06:36 PM PST 24
Peak memory	198176 kb
Host	smart-2a1a6717-4d44-482b-af55-f478c22adce1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2571006752 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_noise_filter.2571006752
Directory	/workspace/36.uart_noise_filter/latest

Test location	/workspace/coverage/default/36.uart_perf.93134848
Short name	T989
Test name
Test status
Simulation time	3238173946 ps
CPU time	46.35 seconds
Started	Feb 18 02:05:38 PM PST 24
Finished	Feb 18 02:06:35 PM PST 24
Peak memory	200096 kb
Host	smart-e9782fe1-6555-4eff-9772-a874fa90988d
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=93134848 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_perf.93134848
Directory	/workspace/36.uart_perf/latest

Test location	/workspace/coverage/default/36.uart_rx_oversample.997452135
Short name	T711
Test name
Test status
Simulation time	4494754609 ps
CPU time	41.26 seconds
Started	Feb 18 02:05:42 PM PST 24
Finished	Feb 18 02:06:33 PM PST 24
Peak memory	198500 kb
Host	smart-6148d461-50a7-4f06-9f61-4d9e726c9634
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=997452135 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_oversample.997452135
Directory	/workspace/36.uart_rx_oversample/latest

Test location	/workspace/coverage/default/36.uart_rx_parity_err.1025807704
Short name	T323
Test name
Test status
Simulation time	126972955482 ps
CPU time	156.12 seconds
Started	Feb 18 02:05:48 PM PST 24
Finished	Feb 18 02:08:32 PM PST 24
Peak memory	199640 kb
Host	smart-3dc266cd-872b-4f77-af93-65e181942fc2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1025807704 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_parity_err.1025807704
Directory	/workspace/36.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/36.uart_rx_start_bit_filter.2576158620
Short name	T871
Test name
Test status
Simulation time	33303887430 ps
CPU time	3.71 seconds
Started	Feb 18 02:05:45 PM PST 24
Finished	Feb 18 02:05:58 PM PST 24
Peak memory	195792 kb
Host	smart-f096dc15-39f7-4afd-91f4-df603df456e6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2576158620 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_start_bit_filter.2576158620
Directory	/workspace/36.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/36.uart_smoke.1656179291
Short name	T421
Test name
Test status
Simulation time	5643515856 ps
CPU time	21.29 seconds
Started	Feb 18 02:05:44 PM PST 24
Finished	Feb 18 02:06:16 PM PST 24
Peak memory	198760 kb
Host	smart-68ce58f7-59bf-48a7-97cf-79cd137dab26
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1656179291 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_smoke.1656179291
Directory	/workspace/36.uart_smoke/latest

Test location	/workspace/coverage/default/36.uart_stress_all.2833021291
Short name	T995
Test name
Test status
Simulation time	2448613278790 ps
CPU time	1716.01 seconds
Started	Feb 18 02:05:47 PM PST 24
Finished	Feb 18 02:34:32 PM PST 24
Peak memory	200040 kb
Host	smart-22e2693a-cc9b-45ea-9ad2-42ed84e1416f
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833021291 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_stress_all.2833021291
Directory	/workspace/36.uart_stress_all/latest

Test location	/workspace/coverage/default/36.uart_tx_ovrd.1079045680
Short name	T1064
Test name
Test status
Simulation time	1613918986 ps
CPU time	1.75 seconds
Started	Feb 18 02:05:44 PM PST 24
Finished	Feb 18 02:05:56 PM PST 24
Peak memory	198048 kb
Host	smart-b87c9f8e-1a40-4045-82ba-1d0af12c167d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1079045680 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_ovrd.1079045680
Directory	/workspace/36.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/36.uart_tx_rx.584805431
Short name	T593
Test name
Test status
Simulation time	38610509463 ps
CPU time	29.26 seconds
Started	Feb 18 02:05:41 PM PST 24
Finished	Feb 18 02:06:21 PM PST 24
Peak memory	200092 kb
Host	smart-3d6d3e94-1ab7-45da-912b-5b371e65c327
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=584805431 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_rx.584805431
Directory	/workspace/36.uart_tx_rx/latest

Test location	/workspace/coverage/default/37.uart_alert_test.2234423886
Short name	T887
Test name
Test status
Simulation time	12352604 ps
CPU time	0.59 seconds
Started	Feb 18 02:05:50 PM PST 24
Finished	Feb 18 02:05:58 PM PST 24
Peak memory	194492 kb
Host	smart-22092ac1-77de-423e-9340-3cc42f8e4d8a
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234423886 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_alert_test.2234423886
Directory	/workspace/37.uart_alert_test/latest

Test location	/workspace/coverage/default/37.uart_fifo_overflow.3223568587
Short name	T348
Test name
Test status
Simulation time	90297562954 ps
CPU time	39.46 seconds
Started	Feb 18 02:05:51 PM PST 24
Finished	Feb 18 02:06:37 PM PST 24
Peak memory	200044 kb
Host	smart-a06dfa22-ed38-46e5-95e5-8f11d5e378c7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3223568587 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_overflow.3223568587
Directory	/workspace/37.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/37.uart_intr.4292356392
Short name	T854
Test name
Test status
Simulation time	1604516105725 ps
CPU time	632.68 seconds
Started	Feb 18 02:05:53 PM PST 24
Finished	Feb 18 02:16:33 PM PST 24
Peak memory	199380 kb
Host	smart-01338fd6-2eab-4ae4-a0f7-c2bfdb5f55c7
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292356392 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_intr.4292356392
Directory	/workspace/37.uart_intr/latest

Test location	/workspace/coverage/default/37.uart_long_xfer_wo_dly.1584894616
Short name	T509
Test name
Test status
Simulation time	226459860938 ps
CPU time	203.16 seconds
Started	Feb 18 02:05:56 PM PST 24
Finished	Feb 18 02:09:26 PM PST 24
Peak memory	200040 kb
Host	smart-30c80064-866d-4fd9-adc2-62e2d6511661
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1584894616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_long_xfer_wo_dly.1584894616
Directory	/workspace/37.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/37.uart_loopback.12102731
Short name	T773
Test name
Test status
Simulation time	110086304 ps
CPU time	0.85 seconds
Started	Feb 18 02:06:01 PM PST 24
Finished	Feb 18 02:06:06 PM PST 24
Peak memory	196780 kb
Host	smart-ab3b61de-986c-4e38-821a-eb55ba0b0fa3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=12102731 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_loopback.12102731
Directory	/workspace/37.uart_loopback/latest

Test location	/workspace/coverage/default/37.uart_noise_filter.4119092550
Short name	T1011
Test name
Test status
Simulation time	189999441521 ps
CPU time	27.96 seconds
Started	Feb 18 02:05:53 PM PST 24
Finished	Feb 18 02:06:28 PM PST 24
Peak memory	199456 kb
Host	smart-63311b41-b729-428f-a34b-ac4e9aac2844
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4119092550 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_noise_filter.4119092550
Directory	/workspace/37.uart_noise_filter/latest

Test location	/workspace/coverage/default/37.uart_perf.1024248042
Short name	T872
Test name
Test status
Simulation time	18586837148 ps
CPU time	254.05 seconds
Started	Feb 18 02:05:48 PM PST 24
Finished	Feb 18 02:10:10 PM PST 24
Peak memory	200004 kb
Host	smart-6925f4c4-37f2-4706-8731-9584b272ebf6
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1024248042 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_perf.1024248042
Directory	/workspace/37.uart_perf/latest

Test location	/workspace/coverage/default/37.uart_rx_oversample.3436599005
Short name	T1015
Test name
Test status
Simulation time	2396001021 ps
CPU time	21.93 seconds
Started	Feb 18 02:05:53 PM PST 24
Finished	Feb 18 02:06:22 PM PST 24
Peak memory	198420 kb
Host	smart-faaa8b6b-4e95-4c6e-8faa-2692c0f4aaf7
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3436599005 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_oversample.3436599005
Directory	/workspace/37.uart_rx_oversample/latest

Test location	/workspace/coverage/default/37.uart_rx_parity_err.168118587
Short name	T338
Test name
Test status
Simulation time	61489501676 ps
CPU time	27.57 seconds
Started	Feb 18 02:05:46 PM PST 24
Finished	Feb 18 02:06:23 PM PST 24
Peak memory	200104 kb
Host	smart-d7333951-633d-471b-aa7e-b3d81d619d01
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=168118587 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_parity_err.168118587
Directory	/workspace/37.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/37.uart_rx_start_bit_filter.3615710563
Short name	T732
Test name
Test status
Simulation time	4066878050 ps
CPU time	1.25 seconds
Started	Feb 18 02:05:49 PM PST 24
Finished	Feb 18 02:05:58 PM PST 24
Peak memory	195776 kb
Host	smart-7769e5db-2a5d-46f1-8c50-6d15625116b2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3615710563 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_start_bit_filter.3615710563
Directory	/workspace/37.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/37.uart_smoke.2433245494
Short name	T399
Test name
Test status
Simulation time	802753482 ps
CPU time	3.89 seconds
Started	Feb 18 02:05:54 PM PST 24
Finished	Feb 18 02:06:04 PM PST 24
Peak memory	198032 kb
Host	smart-40832d43-6648-4cce-9fb1-a1d256c258bb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2433245494 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_smoke.2433245494
Directory	/workspace/37.uart_smoke/latest

Test location	/workspace/coverage/default/37.uart_tx_ovrd.1623599684
Short name	T420
Test name
Test status
Simulation time	2530769538 ps
CPU time	2.17 seconds
Started	Feb 18 02:05:51 PM PST 24
Finished	Feb 18 02:06:00 PM PST 24
Peak memory	198572 kb
Host	smart-83224e7b-83c4-4412-86dc-7c8124ca5c18
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1623599684 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_ovrd.1623599684
Directory	/workspace/37.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/37.uart_tx_rx.3277238600
Short name	T677
Test name
Test status
Simulation time	16298152796 ps
CPU time	13.3 seconds
Started	Feb 18 02:05:49 PM PST 24
Finished	Feb 18 02:06:11 PM PST 24
Peak memory	197304 kb
Host	smart-c89e71d1-b5a2-4873-b23e-7bfe824ff29d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3277238600 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_rx.3277238600
Directory	/workspace/37.uart_tx_rx/latest

Test location	/workspace/coverage/default/38.uart_alert_test.2010072734
Short name	T812
Test name
Test status
Simulation time	36279647 ps
CPU time	0.58 seconds
Started	Feb 18 02:06:00 PM PST 24
Finished	Feb 18 02:06:06 PM PST 24
Peak memory	194576 kb
Host	smart-1a656bdd-8a10-476b-8d3b-d7d866103464
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010072734 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_alert_test.2010072734
Directory	/workspace/38.uart_alert_test/latest

Test location	/workspace/coverage/default/38.uart_fifo_full.4179372857
Short name	T663
Test name
Test status
Simulation time	57604680438 ps
CPU time	89.49 seconds
Started	Feb 18 02:05:57 PM PST 24
Finished	Feb 18 02:07:32 PM PST 24
Peak memory	200032 kb
Host	smart-3cdf12ad-9b15-4eab-9be5-febd168de8c3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4179372857 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_full.4179372857
Directory	/workspace/38.uart_fifo_full/latest

Test location	/workspace/coverage/default/38.uart_fifo_overflow.3475922358
Short name	T770
Test name
Test status
Simulation time	71783726375 ps
CPU time	36.36 seconds
Started	Feb 18 02:05:57 PM PST 24
Finished	Feb 18 02:06:39 PM PST 24
Peak memory	199060 kb
Host	smart-1b6d2e6b-e5dd-4a71-94f6-694b5eeb8969
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3475922358 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_overflow.3475922358
Directory	/workspace/38.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/38.uart_intr.463226775
Short name	T714
Test name
Test status
Simulation time	525672463268 ps
CPU time	187.2 seconds
Started	Feb 18 02:05:53 PM PST 24
Finished	Feb 18 02:09:07 PM PST 24
Peak memory	198328 kb
Host	smart-f0bf15d7-3ed9-4e2f-b97e-1a98fda65b6a
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463226775 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_intr.463226775
Directory	/workspace/38.uart_intr/latest

Test location	/workspace/coverage/default/38.uart_long_xfer_wo_dly.1125289527
Short name	T662
Test name
Test status
Simulation time	60021283707 ps
CPU time	61.46 seconds
Started	Feb 18 02:05:54 PM PST 24
Finished	Feb 18 02:07:02 PM PST 24
Peak memory	200112 kb
Host	smart-af0e6e02-07d0-4bfa-a045-09a8a8b29ea6
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1125289527 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_long_xfer_wo_dly.1125289527
Directory	/workspace/38.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/38.uart_noise_filter.3841233960
Short name	T615
Test name
Test status
Simulation time	15187400976 ps
CPU time	28.24 seconds
Started	Feb 18 02:05:55 PM PST 24
Finished	Feb 18 02:06:29 PM PST 24
Peak memory	197812 kb
Host	smart-13fe603f-b14c-4321-a885-e93e36e8b21c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3841233960 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_noise_filter.3841233960
Directory	/workspace/38.uart_noise_filter/latest

Test location	/workspace/coverage/default/38.uart_perf.3903630615
Short name	T753
Test name
Test status
Simulation time	20559034423 ps
CPU time	545.75 seconds
Started	Feb 18 02:05:55 PM PST 24
Finished	Feb 18 02:15:07 PM PST 24
Peak memory	199968 kb
Host	smart-b544e515-6110-435c-aa80-6da343baad20
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3903630615 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_perf.3903630615
Directory	/workspace/38.uart_perf/latest

Test location	/workspace/coverage/default/38.uart_rx_parity_err.2758443312
Short name	T375
Test name
Test status
Simulation time	67788619691 ps
CPU time	27.8 seconds
Started	Feb 18 02:05:52 PM PST 24
Finished	Feb 18 02:06:27 PM PST 24
Peak memory	199444 kb
Host	smart-38c4f26b-f8b7-4b47-a871-d4176d52440c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2758443312 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_parity_err.2758443312
Directory	/workspace/38.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/38.uart_rx_start_bit_filter.2164829828
Short name	T1080
Test name
Test status
Simulation time	49479015744 ps
CPU time	20.32 seconds
Started	Feb 18 02:05:53 PM PST 24
Finished	Feb 18 02:06:20 PM PST 24
Peak memory	195484 kb
Host	smart-1cce1686-e7fd-45c8-887e-0d2c608ea5b5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2164829828 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_start_bit_filter.2164829828
Directory	/workspace/38.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/38.uart_smoke.4288397012
Short name	T1049
Test name
Test status
Simulation time	296172992 ps
CPU time	1.25 seconds
Started	Feb 18 02:05:53 PM PST 24
Finished	Feb 18 02:06:01 PM PST 24
Peak memory	197872 kb
Host	smart-8e4cf9ab-0a2c-49bc-832b-fdc5c3ec06db
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4288397012 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_smoke.4288397012
Directory	/workspace/38.uart_smoke/latest

Test location	/workspace/coverage/default/38.uart_stress_all_with_rand_reset.3205773791
Short name	T589
Test name
Test status
Simulation time	28029269641 ps
CPU time	363.55 seconds
Started	Feb 18 02:05:57 PM PST 24
Finished	Feb 18 02:12:06 PM PST 24
Peak memory	212704 kb
Host	smart-34202d3c-fc3f-4fec-a992-6b041879b4b4
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205773791 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 38.uart_stress_all_with_rand_reset.3205773791
Directory	/workspace/38.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/38.uart_tx_ovrd.2557991243
Short name	T566
Test name
Test status
Simulation time	762617786 ps
CPU time	3.04 seconds
Started	Feb 18 02:05:54 PM PST 24
Finished	Feb 18 02:06:03 PM PST 24
Peak memory	198208 kb
Host	smart-612b3b98-cfbd-49a9-86b1-d1af231118b8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2557991243 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_ovrd.2557991243
Directory	/workspace/38.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/38.uart_tx_rx.696589463
Short name	T541
Test name
Test status
Simulation time	4707041889 ps
CPU time	5.81 seconds
Started	Feb 18 02:05:51 PM PST 24
Finished	Feb 18 02:06:04 PM PST 24
Peak memory	199196 kb
Host	smart-5d2fa6a5-80ad-4079-8d3d-c0daedf4aa93
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=696589463 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_rx.696589463
Directory	/workspace/38.uart_tx_rx/latest

Test location	/workspace/coverage/default/39.uart_alert_test.3613212586
Short name	T31
Test name
Test status
Simulation time	49179624 ps
CPU time	0.55 seconds
Started	Feb 18 02:06:04 PM PST 24
Finished	Feb 18 02:06:07 PM PST 24
Peak memory	195444 kb
Host	smart-fc6f61cb-f19b-4264-b823-4c22e7b47e24
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613212586 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_alert_test.3613212586
Directory	/workspace/39.uart_alert_test/latest

Test location	/workspace/coverage/default/39.uart_fifo_full.3940428417
Short name	T465
Test name
Test status
Simulation time	88429380939 ps
CPU time	39.45 seconds
Started	Feb 18 02:06:01 PM PST 24
Finished	Feb 18 02:06:45 PM PST 24
Peak memory	200052 kb
Host	smart-a8a566a6-3ae3-4f27-85b9-ccf70c9339e0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3940428417 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_full.3940428417
Directory	/workspace/39.uart_fifo_full/latest

Test location	/workspace/coverage/default/39.uart_fifo_overflow.3651121342
Short name	T530
Test name
Test status
Simulation time	28218953680 ps
CPU time	48.25 seconds
Started	Feb 18 02:05:57 PM PST 24
Finished	Feb 18 02:06:51 PM PST 24
Peak memory	199252 kb
Host	smart-e9e2cb9d-930b-4738-bfa4-bf9368169dd1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3651121342 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_overflow.3651121342
Directory	/workspace/39.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/39.uart_fifo_reset.3986076658
Short name	T339
Test name
Test status
Simulation time	20782082391 ps
CPU time	36.53 seconds
Started	Feb 18 02:05:56 PM PST 24
Finished	Feb 18 02:06:38 PM PST 24
Peak memory	200112 kb
Host	smart-a8a251ad-9cbd-445c-be37-d8879eceb12c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3986076658 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_reset.3986076658
Directory	/workspace/39.uart_fifo_reset/latest

Test location	/workspace/coverage/default/39.uart_intr.2011770323
Short name	T883
Test name
Test status
Simulation time	432333836075 ps
CPU time	155.97 seconds
Started	Feb 18 02:05:59 PM PST 24
Finished	Feb 18 02:08:40 PM PST 24
Peak memory	199908 kb
Host	smart-4ed85d8e-fd72-4211-ac16-384715fcff6b
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011770323 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_intr.2011770323
Directory	/workspace/39.uart_intr/latest

Test location	/workspace/coverage/default/39.uart_loopback.980529515
Short name	T443
Test name
Test status
Simulation time	8801122266 ps
CPU time	16.77 seconds
Started	Feb 18 02:06:01 PM PST 24
Finished	Feb 18 02:06:22 PM PST 24
Peak memory	197596 kb
Host	smart-20890ded-aa82-4394-9c5f-bbeac8dd5093
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=980529515 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_loopback.980529515
Directory	/workspace/39.uart_loopback/latest

Test location	/workspace/coverage/default/39.uart_noise_filter.2591766981
Short name	T656
Test name
Test status
Simulation time	78144144913 ps
CPU time	151.87 seconds
Started	Feb 18 02:06:01 PM PST 24
Finished	Feb 18 02:08:37 PM PST 24
Peak memory	200204 kb
Host	smart-22d3578d-264b-46e7-a0d0-cae4cf41bc86
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2591766981 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_noise_filter.2591766981
Directory	/workspace/39.uart_noise_filter/latest

Test location	/workspace/coverage/default/39.uart_perf.1676929246
Short name	T413
Test name
Test status
Simulation time	11605460364 ps
CPU time	191.94 seconds
Started	Feb 18 02:05:55 PM PST 24
Finished	Feb 18 02:09:13 PM PST 24
Peak memory	199968 kb
Host	smart-2872ffe7-9075-4677-baa1-ae7d86403ce0
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1676929246 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_perf.1676929246
Directory	/workspace/39.uart_perf/latest

Test location	/workspace/coverage/default/39.uart_rx_parity_err.3650842859
Short name	T344
Test name
Test status
Simulation time	73175782414 ps
CPU time	13.93 seconds
Started	Feb 18 02:05:55 PM PST 24
Finished	Feb 18 02:06:15 PM PST 24
Peak memory	199032 kb
Host	smart-7f093877-85a3-4311-bf76-8d84c24ab2b2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3650842859 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_parity_err.3650842859
Directory	/workspace/39.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/39.uart_rx_start_bit_filter.2572241029
Short name	T653
Test name
Test status
Simulation time	3681212924 ps
CPU time	2.19 seconds
Started	Feb 18 02:05:59 PM PST 24
Finished	Feb 18 02:06:06 PM PST 24
Peak memory	195788 kb
Host	smart-e86d46e5-ff86-436f-8ec2-fddfae768ca5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2572241029 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_start_bit_filter.2572241029
Directory	/workspace/39.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/39.uart_smoke.3308170721
Short name	T967
Test name
Test status
Simulation time	6290194513 ps
CPU time	18.08 seconds
Started	Feb 18 02:06:00 PM PST 24
Finished	Feb 18 02:06:23 PM PST 24
Peak memory	199484 kb
Host	smart-9c179e6f-5acc-445e-b493-36ca643755a8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3308170721 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_smoke.3308170721
Directory	/workspace/39.uart_smoke/latest

Test location	/workspace/coverage/default/39.uart_stress_all.3683463127
Short name	T982
Test name
Test status
Simulation time	57512092623 ps
CPU time	8.13 seconds
Started	Feb 18 02:06:06 PM PST 24
Finished	Feb 18 02:06:16 PM PST 24
Peak memory	200236 kb
Host	smart-5ea2b9db-d24a-4a2c-91a6-fa7404d5bf60
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683463127 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_stress_all.3683463127
Directory	/workspace/39.uart_stress_all/latest

Test location	/workspace/coverage/default/39.uart_tx_ovrd.3800405720
Short name	T1008
Test name
Test status
Simulation time	656415539 ps
CPU time	1.49 seconds
Started	Feb 18 02:05:54 PM PST 24
Finished	Feb 18 02:06:02 PM PST 24
Peak memory	197948 kb
Host	smart-a7577497-550f-4ca9-b1d3-e3e6c58eca53
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3800405720 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_ovrd.3800405720
Directory	/workspace/39.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/39.uart_tx_rx.915005066
Short name	T888
Test name
Test status
Simulation time	119714546898 ps
CPU time	223.67 seconds
Started	Feb 18 02:05:57 PM PST 24
Finished	Feb 18 02:09:47 PM PST 24
Peak memory	200044 kb
Host	smart-bb26a89d-f0d0-40ef-b056-ec61b2f87c95
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=915005066 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_rx.915005066
Directory	/workspace/39.uart_tx_rx/latest

Test location	/workspace/coverage/default/4.uart_alert_test.314238238
Short name	T451
Test name
Test status
Simulation time	16000856 ps
CPU time	0.57 seconds
Started	Feb 18 02:03:34 PM PST 24
Finished	Feb 18 02:03:44 PM PST 24
Peak memory	195428 kb
Host	smart-65fb2218-3d8b-414d-a58b-d26ab2fad9b3
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314238238 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_alert_test.314238238
Directory	/workspace/4.uart_alert_test/latest

Test location	/workspace/coverage/default/4.uart_fifo_full.2949243244
Short name	T371
Test name
Test status
Simulation time	51731171925 ps
CPU time	28.01 seconds
Started	Feb 18 02:03:40 PM PST 24
Finished	Feb 18 02:04:20 PM PST 24
Peak memory	200016 kb
Host	smart-e149cb00-ca01-4d11-8203-3838e609af09
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2949243244 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_full.2949243244
Directory	/workspace/4.uart_fifo_full/latest

Test location	/workspace/coverage/default/4.uart_fifo_overflow.1625086128
Short name	T781
Test name
Test status
Simulation time	117046558115 ps
CPU time	135.33 seconds
Started	Feb 18 02:03:42 PM PST 24
Finished	Feb 18 02:06:12 PM PST 24
Peak memory	199700 kb
Host	smart-ea83e917-e8cb-457d-b856-6223a4761be1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1625086128 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_overflow.1625086128
Directory	/workspace/4.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/4.uart_fifo_reset.920817955
Short name	T759
Test name
Test status
Simulation time	119015627384 ps
CPU time	47.53 seconds
Started	Feb 18 02:03:36 PM PST 24
Finished	Feb 18 02:04:37 PM PST 24
Peak memory	200072 kb
Host	smart-587bd508-5437-4c50-a915-3e363cd0f646
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=920817955 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_reset.920817955
Directory	/workspace/4.uart_fifo_reset/latest

Test location	/workspace/coverage/default/4.uart_long_xfer_wo_dly.1882380012
Short name	T904
Test name
Test status
Simulation time	209706884711 ps
CPU time	207.93 seconds
Started	Feb 18 02:03:36 PM PST 24
Finished	Feb 18 02:07:16 PM PST 24
Peak memory	200056 kb
Host	smart-3c832bba-d42d-4343-8422-7fbfa9974e90
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1882380012 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_long_xfer_wo_dly.1882380012
Directory	/workspace/4.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/4.uart_loopback.597180914
Short name	T595
Test name
Test status
Simulation time	9030160404 ps
CPU time	10.47 seconds
Started	Feb 18 02:03:41 PM PST 24
Finished	Feb 18 02:04:05 PM PST 24
Peak memory	199740 kb
Host	smart-7a3b13c8-cd9c-4025-ac97-0aa5fabdcdd5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=597180914 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_loopback.597180914
Directory	/workspace/4.uart_loopback/latest

Test location	/workspace/coverage/default/4.uart_noise_filter.1826019916
Short name	T49
Test name
Test status
Simulation time	3621617872 ps
CPU time	3.03 seconds
Started	Feb 18 02:03:37 PM PST 24
Finished	Feb 18 02:03:54 PM PST 24
Peak memory	193704 kb
Host	smart-cc0cabf2-837d-4026-a796-99f4f0525644
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1826019916 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_noise_filter.1826019916
Directory	/workspace/4.uart_noise_filter/latest

Test location	/workspace/coverage/default/4.uart_perf.2459485039
Short name	T623
Test name
Test status
Simulation time	2797322452 ps
CPU time	44.97 seconds
Started	Feb 18 02:03:38 PM PST 24
Finished	Feb 18 02:04:36 PM PST 24
Peak memory	200000 kb
Host	smart-5907128d-9034-4653-a5d5-ce663235d390
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2459485039 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_perf.2459485039
Directory	/workspace/4.uart_perf/latest

Test location	/workspace/coverage/default/4.uart_rx_start_bit_filter.1855897305
Short name	T612
Test name
Test status
Simulation time	4883350334 ps
CPU time	2.65 seconds
Started	Feb 18 02:03:38 PM PST 24
Finished	Feb 18 02:03:54 PM PST 24
Peak memory	195792 kb
Host	smart-c98e6a9c-be21-4771-b17d-24f69d27ef99
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1855897305 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_start_bit_filter.1855897305
Directory	/workspace/4.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/4.uart_sec_cm.1574595954
Short name	T87
Test name
Test status
Simulation time	37772895 ps
CPU time	0.8 seconds
Started	Feb 18 02:03:36 PM PST 24
Finished	Feb 18 02:03:49 PM PST 24
Peak memory	217164 kb
Host	smart-ac18af6b-6f39-42a5-8e33-ed92b2dec199
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574595954 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_sec_cm.1574595954
Directory	/workspace/4.uart_sec_cm/latest

Test location	/workspace/coverage/default/4.uart_smoke.3918791369
Short name	T527
Test name
Test status
Simulation time	5433857256 ps
CPU time	16.86 seconds
Started	Feb 18 02:03:36 PM PST 24
Finished	Feb 18 02:04:05 PM PST 24
Peak memory	199280 kb
Host	smart-d279e1c6-3c43-4cfe-a608-2b710b10ae06
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3918791369 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_smoke.3918791369
Directory	/workspace/4.uart_smoke/latest

Test location	/workspace/coverage/default/4.uart_stress_all.3685832324
Short name	T561
Test name
Test status
Simulation time	476958815737 ps
CPU time	241.61 seconds
Started	Feb 18 02:03:42 PM PST 24
Finished	Feb 18 02:07:57 PM PST 24
Peak memory	200052 kb
Host	smart-d744baa3-5b34-4c18-a7c4-9459cd1eeedf
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685832324 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_stress_all.3685832324
Directory	/workspace/4.uart_stress_all/latest

Test location	/workspace/coverage/default/4.uart_stress_all_with_rand_reset.2905114138
Short name	T553
Test name
Test status
Simulation time	41401720677 ps
CPU time	153 seconds
Started	Feb 18 02:03:42 PM PST 24
Finished	Feb 18 02:06:29 PM PST 24
Peak memory	216728 kb
Host	smart-07c84f91-4449-4b5f-90e8-211ca424c211
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905114138 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 4.uart_stress_all_with_rand_reset.2905114138
Directory	/workspace/4.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/4.uart_tx_ovrd.2033470077
Short name	T873
Test name
Test status
Simulation time	1132304679 ps
CPU time	4.37 seconds
Started	Feb 18 02:03:42 PM PST 24
Finished	Feb 18 02:04:00 PM PST 24
Peak memory	198528 kb
Host	smart-1c0c20ea-f374-4e8b-9399-170da468afd4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2033470077 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_ovrd.2033470077
Directory	/workspace/4.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/4.uart_tx_rx.592704318
Short name	T1099
Test name
Test status
Simulation time	10139793219 ps
CPU time	15.39 seconds
Started	Feb 18 02:03:32 PM PST 24
Finished	Feb 18 02:03:50 PM PST 24
Peak memory	199772 kb
Host	smart-6a840f3c-616f-4280-83e3-346d82454cb2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=592704318 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_rx.592704318
Directory	/workspace/4.uart_tx_rx/latest

Test location	/workspace/coverage/default/40.uart_alert_test.1271992891
Short name	T946
Test name
Test status
Simulation time	34268766 ps
CPU time	0.57 seconds
Started	Feb 18 02:06:13 PM PST 24
Finished	Feb 18 02:06:17 PM PST 24
Peak memory	195516 kb
Host	smart-ad4aa7e4-9cd0-476b-a534-118b91b77ea9
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271992891 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_alert_test.1271992891
Directory	/workspace/40.uart_alert_test/latest

Test location	/workspace/coverage/default/40.uart_fifo_full.3768968788
Short name	T555
Test name
Test status
Simulation time	116808391708 ps
CPU time	51.44 seconds
Started	Feb 18 02:06:02 PM PST 24
Finished	Feb 18 02:06:57 PM PST 24
Peak memory	200060 kb
Host	smart-1dc15214-419b-48d4-a29f-e60ed46714c0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3768968788 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_full.3768968788
Directory	/workspace/40.uart_fifo_full/latest

Test location	/workspace/coverage/default/40.uart_fifo_overflow.3419419242
Short name	T793
Test name
Test status
Simulation time	91685028992 ps
CPU time	36.49 seconds
Started	Feb 18 02:05:59 PM PST 24
Finished	Feb 18 02:06:41 PM PST 24
Peak memory	200024 kb
Host	smart-aaa00abe-11a2-4a27-b2dd-030dba635e53
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3419419242 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_overflow.3419419242
Directory	/workspace/40.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/40.uart_fifo_reset.2016354674
Short name	T939
Test name
Test status
Simulation time	117535089035 ps
CPU time	165.82 seconds
Started	Feb 18 02:06:05 PM PST 24
Finished	Feb 18 02:08:53 PM PST 24
Peak memory	200104 kb
Host	smart-1f292da3-b0f4-486e-9e99-62a4fc6e435b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2016354674 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_reset.2016354674
Directory	/workspace/40.uart_fifo_reset/latest

Test location	/workspace/coverage/default/40.uart_intr.3237119112
Short name	T929
Test name
Test status
Simulation time	288859182741 ps
CPU time	255.31 seconds
Started	Feb 18 02:06:11 PM PST 24
Finished	Feb 18 02:10:30 PM PST 24
Peak memory	199460 kb
Host	smart-956392c3-fdb0-4a93-a00e-89dd3b659742
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237119112 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_intr.3237119112
Directory	/workspace/40.uart_intr/latest

Test location	/workspace/coverage/default/40.uart_long_xfer_wo_dly.392884005
Short name	T794
Test name
Test status
Simulation time	143627512863 ps
CPU time	844.02 seconds
Started	Feb 18 02:06:03 PM PST 24
Finished	Feb 18 02:20:10 PM PST 24
Peak memory	200052 kb
Host	smart-8077ca53-3f01-431b-8fb2-342e484c3a93
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=392884005 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_long_xfer_wo_dly.392884005
Directory	/workspace/40.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/40.uart_loopback.3374024906
Short name	T533
Test name
Test status
Simulation time	1785788099 ps
CPU time	3.47 seconds
Started	Feb 18 02:06:04 PM PST 24
Finished	Feb 18 02:06:10 PM PST 24
Peak memory	198168 kb
Host	smart-9a892cc4-369c-4186-8186-d74c66deb096
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3374024906 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_loopback.3374024906
Directory	/workspace/40.uart_loopback/latest

Test location	/workspace/coverage/default/40.uart_noise_filter.1394128260
Short name	T389
Test name
Test status
Simulation time	89551047318 ps
CPU time	113.52 seconds
Started	Feb 18 02:06:04 PM PST 24
Finished	Feb 18 02:08:00 PM PST 24
Peak memory	208432 kb
Host	smart-5a9e2eae-577e-430c-a224-9dabe1a6cd0a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1394128260 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_noise_filter.1394128260
Directory	/workspace/40.uart_noise_filter/latest

Test location	/workspace/coverage/default/40.uart_perf.2027285354
Short name	T672
Test name
Test status
Simulation time	23094642773 ps
CPU time	543.14 seconds
Started	Feb 18 02:06:04 PM PST 24
Finished	Feb 18 02:15:10 PM PST 24
Peak memory	200016 kb
Host	smart-1db5470c-84b1-43e2-85d2-29b1b6c45281
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2027285354 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_perf.2027285354
Directory	/workspace/40.uart_perf/latest

Test location	/workspace/coverage/default/40.uart_rx_oversample.4205144045
Short name	T22
Test name
Test status
Simulation time	4192063802 ps
CPU time	34.97 seconds
Started	Feb 18 02:06:03 PM PST 24
Finished	Feb 18 02:06:41 PM PST 24
Peak memory	198028 kb
Host	smart-13d81752-c278-429d-a17c-f13a869d706b
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4205144045 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_oversample.4205144045
Directory	/workspace/40.uart_rx_oversample/latest

Test location	/workspace/coverage/default/40.uart_rx_parity_err.4123901713
Short name	T1055
Test name
Test status
Simulation time	358926740592 ps
CPU time	343.07 seconds
Started	Feb 18 02:06:03 PM PST 24
Finished	Feb 18 02:11:49 PM PST 24
Peak memory	199976 kb
Host	smart-57e69998-69ef-43ac-9e7e-dde0f73d09ae
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4123901713 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_parity_err.4123901713
Directory	/workspace/40.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/40.uart_rx_start_bit_filter.4079280729
Short name	T579
Test name
Test status
Simulation time	2827140950 ps
CPU time	2.89 seconds
Started	Feb 18 02:06:06 PM PST 24
Finished	Feb 18 02:06:11 PM PST 24
Peak memory	195492 kb
Host	smart-9cb78586-a48d-4916-a9f5-72df19ff078b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4079280729 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_start_bit_filter.4079280729
Directory	/workspace/40.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/40.uart_smoke.283129825
Short name	T1050
Test name
Test status
Simulation time	682982383 ps
CPU time	1.66 seconds
Started	Feb 18 02:06:06 PM PST 24
Finished	Feb 18 02:06:09 PM PST 24
Peak memory	198420 kb
Host	smart-a5ae982e-25cc-42b7-9518-cd780527fd2f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=283129825 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_smoke.283129825
Directory	/workspace/40.uart_smoke/latest

Test location	/workspace/coverage/default/40.uart_stress_all.1061225739
Short name	T149
Test name
Test status
Simulation time	793786315999 ps
CPU time	68.21 seconds
Started	Feb 18 02:06:04 PM PST 24
Finished	Feb 18 02:07:15 PM PST 24
Peak memory	200236 kb
Host	smart-bc02982e-d8b4-4445-8ef4-1769373c2b79
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061225739 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_stress_all.1061225739
Directory	/workspace/40.uart_stress_all/latest

Test location	/workspace/coverage/default/40.uart_tx_ovrd.2540193730
Short name	T470
Test name
Test status
Simulation time	1012960999 ps
CPU time	3.79 seconds
Started	Feb 18 02:06:02 PM PST 24
Finished	Feb 18 02:06:10 PM PST 24
Peak memory	199152 kb
Host	smart-c5ef332e-1a22-480b-8266-0557d78ef38a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2540193730 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_ovrd.2540193730
Directory	/workspace/40.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/40.uart_tx_rx.2078983275
Short name	T724
Test name
Test status
Simulation time	133804846713 ps
CPU time	220.99 seconds
Started	Feb 18 02:06:11 PM PST 24
Finished	Feb 18 02:09:55 PM PST 24
Peak memory	200048 kb
Host	smart-8a542ac6-ab0b-4d6e-a211-c2e1eccd9c04
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2078983275 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_rx.2078983275
Directory	/workspace/40.uart_tx_rx/latest

Test location	/workspace/coverage/default/41.uart_alert_test.1626123524
Short name	T548
Test name
Test status
Simulation time	11757371 ps
CPU time	0.57 seconds
Started	Feb 18 02:06:14 PM PST 24
Finished	Feb 18 02:06:18 PM PST 24
Peak memory	195424 kb
Host	smart-70487b13-24ed-4739-bd10-753336495b90
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626123524 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_alert_test.1626123524
Directory	/workspace/41.uart_alert_test/latest

Test location	/workspace/coverage/default/41.uart_fifo_full.1373112379
Short name	T499
Test name
Test status
Simulation time	27017290151 ps
CPU time	36.46 seconds
Started	Feb 18 02:06:04 PM PST 24
Finished	Feb 18 02:06:43 PM PST 24
Peak memory	199820 kb
Host	smart-94ddd461-5960-4aba-a8e3-4a7c3223e177
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1373112379 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_full.1373112379
Directory	/workspace/41.uart_fifo_full/latest

Test location	/workspace/coverage/default/41.uart_fifo_overflow.1286439698
Short name	T388
Test name
Test status
Simulation time	123440689203 ps
CPU time	195.13 seconds
Started	Feb 18 02:06:07 PM PST 24
Finished	Feb 18 02:09:24 PM PST 24
Peak memory	200052 kb
Host	smart-3a490a7e-f3b4-49d5-a099-850d103babc6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1286439698 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_overflow.1286439698
Directory	/workspace/41.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/41.uart_fifo_reset.882697049
Short name	T927
Test name
Test status
Simulation time	29255229352 ps
CPU time	8.85 seconds
Started	Feb 18 02:06:05 PM PST 24
Finished	Feb 18 02:06:16 PM PST 24
Peak memory	200124 kb
Host	smart-e86c242f-1bfd-4ea8-ad87-366a3586e17d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=882697049 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_reset.882697049
Directory	/workspace/41.uart_fifo_reset/latest

Test location	/workspace/coverage/default/41.uart_intr.2875553519
Short name	T760
Test name
Test status
Simulation time	72057986929 ps
CPU time	68.98 seconds
Started	Feb 18 02:06:13 PM PST 24
Finished	Feb 18 02:07:25 PM PST 24
Peak memory	199680 kb
Host	smart-9811f3d1-9abf-41ec-95a9-5429a796a02d
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875553519 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_intr.2875553519
Directory	/workspace/41.uart_intr/latest

Test location	/workspace/coverage/default/41.uart_long_xfer_wo_dly.929852462
Short name	T1001
Test name
Test status
Simulation time	76668631739 ps
CPU time	107.96 seconds
Started	Feb 18 02:06:10 PM PST 24
Finished	Feb 18 02:08:00 PM PST 24
Peak memory	200044 kb
Host	smart-1b293c16-7c1c-4973-a8e7-b0e2ccf35742
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=929852462 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_long_xfer_wo_dly.929852462
Directory	/workspace/41.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/41.uart_noise_filter.3917321551
Short name	T519
Test name
Test status
Simulation time	29531942921 ps
CPU time	55.95 seconds
Started	Feb 18 02:06:07 PM PST 24
Finished	Feb 18 02:07:05 PM PST 24
Peak memory	199016 kb
Host	smart-1076bf1c-7082-401a-b1f5-2eafb7ea1599
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3917321551 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_noise_filter.3917321551
Directory	/workspace/41.uart_noise_filter/latest

Test location	/workspace/coverage/default/41.uart_perf.856482184
Short name	T245
Test name
Test status
Simulation time	23844498912 ps
CPU time	97.73 seconds
Started	Feb 18 02:06:10 PM PST 24
Finished	Feb 18 02:07:51 PM PST 24
Peak memory	200080 kb
Host	smart-396a9513-b0d4-4c5d-a808-3fc9b7c70a68
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=856482184 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_perf.856482184
Directory	/workspace/41.uart_perf/latest

Test location	/workspace/coverage/default/41.uart_rx_oversample.1803454924
Short name	T455
Test name
Test status
Simulation time	2576177462 ps
CPU time	15.06 seconds
Started	Feb 18 02:06:07 PM PST 24
Finished	Feb 18 02:06:24 PM PST 24
Peak memory	198408 kb
Host	smart-0bbb95ae-fd78-472d-897a-bf6df8f5f7a8
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1803454924 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_oversample.1803454924
Directory	/workspace/41.uart_rx_oversample/latest

Test location	/workspace/coverage/default/41.uart_rx_parity_err.3138217149
Short name	T137
Test name
Test status
Simulation time	165224521720 ps
CPU time	15.34 seconds
Started	Feb 18 02:06:11 PM PST 24
Finished	Feb 18 02:06:30 PM PST 24
Peak memory	199148 kb
Host	smart-6114e08c-760b-4ade-9ff8-39e649b09b28
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3138217149 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_parity_err.3138217149
Directory	/workspace/41.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/41.uart_rx_start_bit_filter.586074722
Short name	T828
Test name
Test status
Simulation time	537128231 ps
CPU time	1.1 seconds
Started	Feb 18 02:06:11 PM PST 24
Finished	Feb 18 02:06:16 PM PST 24
Peak memory	195404 kb
Host	smart-636adaff-5ca9-4590-a218-682cb9dc4257
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=586074722 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_start_bit_filter.586074722
Directory	/workspace/41.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/41.uart_smoke.3177159802
Short name	T722
Test name
Test status
Simulation time	5365382658 ps
CPU time	6.09 seconds
Started	Feb 18 02:06:02 PM PST 24
Finished	Feb 18 02:06:12 PM PST 24
Peak memory	199660 kb
Host	smart-0a5622ac-60ab-4d96-8afb-4f37b215735d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3177159802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_smoke.3177159802
Directory	/workspace/41.uart_smoke/latest

Test location	/workspace/coverage/default/41.uart_stress_all.2705856116
Short name	T861
Test name
Test status
Simulation time	467846161849 ps
CPU time	238.93 seconds
Started	Feb 18 02:06:09 PM PST 24
Finished	Feb 18 02:10:09 PM PST 24
Peak memory	200104 kb
Host	smart-35c84156-79c6-457b-9c01-da55ac0dd026
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705856116 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_stress_all.2705856116
Directory	/workspace/41.uart_stress_all/latest

Test location	/workspace/coverage/default/41.uart_tx_ovrd.3716421760
Short name	T879
Test name
Test status
Simulation time	699662946 ps
CPU time	2.67 seconds
Started	Feb 18 02:06:05 PM PST 24
Finished	Feb 18 02:06:10 PM PST 24
Peak memory	198580 kb
Host	smart-ea8ac472-e0fa-4a82-9de4-3875d97a3448
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3716421760 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_ovrd.3716421760
Directory	/workspace/41.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/41.uart_tx_rx.1863177277
Short name	T518
Test name
Test status
Simulation time	50709434396 ps
CPU time	57.89 seconds
Started	Feb 18 02:06:11 PM PST 24
Finished	Feb 18 02:07:12 PM PST 24
Peak memory	200044 kb
Host	smart-8a98cddb-9f48-4a33-9c51-a54cc1b6ab20
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1863177277 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_rx.1863177277
Directory	/workspace/41.uart_tx_rx/latest

Test location	/workspace/coverage/default/42.uart_alert_test.3572012092
Short name	T477
Test name
Test status
Simulation time	17179107 ps
CPU time	0.62 seconds
Started	Feb 18 02:06:20 PM PST 24
Finished	Feb 18 02:06:25 PM PST 24
Peak memory	195500 kb
Host	smart-ed470552-319d-44e7-8c38-e21ab25fc1cd
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572012092 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_alert_test.3572012092
Directory	/workspace/42.uart_alert_test/latest

Test location	/workspace/coverage/default/42.uart_fifo_full.1605211737
Short name	T352
Test name
Test status
Simulation time	145001437249 ps
CPU time	83 seconds
Started	Feb 18 02:06:07 PM PST 24
Finished	Feb 18 02:07:32 PM PST 24
Peak memory	200036 kb
Host	smart-c8037e13-2b42-4a3c-82f7-75a5be107078
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1605211737 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_full.1605211737
Directory	/workspace/42.uart_fifo_full/latest

Test location	/workspace/coverage/default/42.uart_fifo_overflow.31029958
Short name	T1060
Test name
Test status
Simulation time	94347525431 ps
CPU time	132.7 seconds
Started	Feb 18 02:06:08 PM PST 24
Finished	Feb 18 02:08:22 PM PST 24
Peak memory	200092 kb
Host	smart-c7462141-ba71-467a-b85e-bd4bfa4b980a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=31029958 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_overflow.31029958
Directory	/workspace/42.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/42.uart_fifo_reset.1516079817
Short name	T1085
Test name
Test status
Simulation time	27752950743 ps
CPU time	50.9 seconds
Started	Feb 18 02:06:12 PM PST 24
Finished	Feb 18 02:07:07 PM PST 24
Peak memory	200052 kb
Host	smart-2d312531-b876-49fd-96bd-d64285ee18c6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1516079817 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_reset.1516079817
Directory	/workspace/42.uart_fifo_reset/latest

Test location	/workspace/coverage/default/42.uart_intr.1450167120
Short name	T1051
Test name
Test status
Simulation time	196654730728 ps
CPU time	77.65 seconds
Started	Feb 18 02:06:12 PM PST 24
Finished	Feb 18 02:07:33 PM PST 24
Peak memory	199976 kb
Host	smart-32330afc-662f-4553-8ffc-53083038f196
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450167120 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_intr.1450167120
Directory	/workspace/42.uart_intr/latest

Test location	/workspace/coverage/default/42.uart_long_xfer_wo_dly.1785623922
Short name	T792
Test name
Test status
Simulation time	81187296111 ps
CPU time	478.84 seconds
Started	Feb 18 02:06:20 PM PST 24
Finished	Feb 18 02:14:23 PM PST 24
Peak memory	200032 kb
Host	smart-90c5faf9-9711-4a18-848e-8f3d94ede76c
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1785623922 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_long_xfer_wo_dly.1785623922
Directory	/workspace/42.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/42.uart_loopback.964421302
Short name	T607
Test name
Test status
Simulation time	9704607545 ps
CPU time	5.81 seconds
Started	Feb 18 02:06:20 PM PST 24
Finished	Feb 18 02:06:30 PM PST 24
Peak memory	199532 kb
Host	smart-2ac949e7-78fd-4502-b5db-255d291ee38a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=964421302 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_loopback.964421302
Directory	/workspace/42.uart_loopback/latest

Test location	/workspace/coverage/default/42.uart_noise_filter.3077864627
Short name	T800
Test name
Test status
Simulation time	107060588263 ps
CPU time	33.94 seconds
Started	Feb 18 02:06:10 PM PST 24
Finished	Feb 18 02:06:47 PM PST 24
Peak memory	208456 kb
Host	smart-a82ad8e3-128c-4aa8-890b-c38b2f9cfbd4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3077864627 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_noise_filter.3077864627
Directory	/workspace/42.uart_noise_filter/latest

Test location	/workspace/coverage/default/42.uart_perf.1355912187
Short name	T614
Test name
Test status
Simulation time	18641257973 ps
CPU time	958.04 seconds
Started	Feb 18 02:06:19 PM PST 24
Finished	Feb 18 02:22:20 PM PST 24
Peak memory	200016 kb
Host	smart-1cf7f60a-f6e7-4f9b-a371-319218f618e1
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1355912187 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_perf.1355912187
Directory	/workspace/42.uart_perf/latest

Test location	/workspace/coverage/default/42.uart_rx_oversample.2957130132
Short name	T545
Test name
Test status
Simulation time	382427948 ps
CPU time	4.75 seconds
Started	Feb 18 02:06:07 PM PST 24
Finished	Feb 18 02:06:13 PM PST 24
Peak memory	198104 kb
Host	smart-71d50909-ee47-4fc4-8c65-dfcb7a9a7ff2
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2957130132 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_oversample.2957130132
Directory	/workspace/42.uart_rx_oversample/latest

Test location	/workspace/coverage/default/42.uart_rx_parity_err.2281832757
Short name	T1117
Test name
Test status
Simulation time	154208877766 ps
CPU time	41.12 seconds
Started	Feb 18 02:06:06 PM PST 24
Finished	Feb 18 02:06:49 PM PST 24
Peak memory	199380 kb
Host	smart-fde42a2c-6d9d-4b18-a9c3-b817bd1aca19
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2281832757 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_parity_err.2281832757
Directory	/workspace/42.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/42.uart_rx_start_bit_filter.2417056844
Short name	T878
Test name
Test status
Simulation time	6030036591 ps
CPU time	2.8 seconds
Started	Feb 18 02:06:08 PM PST 24
Finished	Feb 18 02:06:12 PM PST 24
Peak memory	195780 kb
Host	smart-c42877aa-22ff-4d87-8dd9-3fcbfdb4b9ab
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2417056844 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_start_bit_filter.2417056844
Directory	/workspace/42.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/42.uart_smoke.3215097206
Short name	T924
Test name
Test status
Simulation time	743214551 ps
CPU time	1.41 seconds
Started	Feb 18 02:06:11 PM PST 24
Finished	Feb 18 02:06:16 PM PST 24
Peak memory	198388 kb
Host	smart-f420e79e-f5f9-46cc-bff1-6449cbd09d2c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3215097206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_smoke.3215097206
Directory	/workspace/42.uart_smoke/latest

Test location	/workspace/coverage/default/42.uart_tx_ovrd.3585969211
Short name	T100
Test name
Test status
Simulation time	8597501486 ps
CPU time	9.12 seconds
Started	Feb 18 02:06:21 PM PST 24
Finished	Feb 18 02:06:35 PM PST 24
Peak memory	199716 kb
Host	smart-19c94048-348e-4b48-b1f1-00480bfb52d3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3585969211 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_ovrd.3585969211
Directory	/workspace/42.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/42.uart_tx_rx.771992307
Short name	T700
Test name
Test status
Simulation time	84088342314 ps
CPU time	17.44 seconds
Started	Feb 18 02:06:10 PM PST 24
Finished	Feb 18 02:06:31 PM PST 24
Peak memory	199976 kb
Host	smart-0dfbeb38-b88d-43a6-85cd-d924f58f6565
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=771992307 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_rx.771992307
Directory	/workspace/42.uart_tx_rx/latest

Test location	/workspace/coverage/default/43.uart_alert_test.660470947
Short name	T513
Test name
Test status
Simulation time	30595671 ps
CPU time	0.56 seconds
Started	Feb 18 02:06:19 PM PST 24
Finished	Feb 18 02:06:24 PM PST 24
Peak memory	195508 kb
Host	smart-53ee60f2-4c43-47a9-affe-d83476b95e5f
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660470947 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_alert_test.660470947
Directory	/workspace/43.uart_alert_test/latest

Test location	/workspace/coverage/default/43.uart_fifo_full.1905796017
Short name	T1042
Test name
Test status
Simulation time	56204392513 ps
CPU time	13.66 seconds
Started	Feb 18 02:06:19 PM PST 24
Finished	Feb 18 02:06:37 PM PST 24
Peak memory	200084 kb
Host	smart-e1f6e2f6-f575-4779-8073-ab10a23f7696
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1905796017 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_full.1905796017
Directory	/workspace/43.uart_fifo_full/latest

Test location	/workspace/coverage/default/43.uart_fifo_overflow.2280484696
Short name	T353
Test name
Test status
Simulation time	215978718675 ps
CPU time	35.7 seconds
Started	Feb 18 02:06:19 PM PST 24
Finished	Feb 18 02:06:58 PM PST 24
Peak memory	199400 kb
Host	smart-06c3b74e-fa70-4627-9d4b-1d3292889042
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2280484696 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_overflow.2280484696
Directory	/workspace/43.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/43.uart_fifo_reset.3119290738
Short name	T273
Test name
Test status
Simulation time	75000847241 ps
CPU time	35.05 seconds
Started	Feb 18 02:06:19 PM PST 24
Finished	Feb 18 02:06:58 PM PST 24
Peak memory	199944 kb
Host	smart-362e1236-bded-457a-8225-76da2dd544c0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3119290738 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_reset.3119290738
Directory	/workspace/43.uart_fifo_reset/latest

Test location	/workspace/coverage/default/43.uart_intr.1874079545
Short name	T430
Test name
Test status
Simulation time	182229575094 ps
CPU time	68.44 seconds
Started	Feb 18 02:06:19 PM PST 24
Finished	Feb 18 02:07:31 PM PST 24
Peak memory	199812 kb
Host	smart-670e7353-c69f-430b-ad58-71e38c92a7af
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874079545 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_intr.1874079545
Directory	/workspace/43.uart_intr/latest

Test location	/workspace/coverage/default/43.uart_long_xfer_wo_dly.3531110474
Short name	T1009
Test name
Test status
Simulation time	55204317561 ps
CPU time	73.54 seconds
Started	Feb 18 02:06:19 PM PST 24
Finished	Feb 18 02:07:36 PM PST 24
Peak memory	200072 kb
Host	smart-664ea464-a6b8-40c7-b2df-b9610cb48956
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3531110474 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_long_xfer_wo_dly.3531110474
Directory	/workspace/43.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/43.uart_noise_filter.3404424652
Short name	T546
Test name
Test status
Simulation time	174845727224 ps
CPU time	144.53 seconds
Started	Feb 18 02:06:19 PM PST 24
Finished	Feb 18 02:08:48 PM PST 24
Peak memory	208276 kb
Host	smart-062d3d8d-71c3-4e16-90f5-c689e2478b2c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3404424652 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_noise_filter.3404424652
Directory	/workspace/43.uart_noise_filter/latest

Test location	/workspace/coverage/default/43.uart_perf.479713006
Short name	T1062
Test name
Test status
Simulation time	6056966624 ps
CPU time	89.61 seconds
Started	Feb 18 02:06:19 PM PST 24
Finished	Feb 18 02:07:52 PM PST 24
Peak memory	199924 kb
Host	smart-535b5f94-42e3-4b0a-94a8-633853e81126
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=479713006 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_perf.479713006
Directory	/workspace/43.uart_perf/latest

Test location	/workspace/coverage/default/43.uart_rx_oversample.3953603896
Short name	T925
Test name
Test status
Simulation time	2854129146 ps
CPU time	10.34 seconds
Started	Feb 18 02:06:22 PM PST 24
Finished	Feb 18 02:06:37 PM PST 24
Peak memory	198036 kb
Host	smart-d1ffd245-8a63-4ffd-b8af-c9eb72abf03c
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3953603896 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_oversample.3953603896
Directory	/workspace/43.uart_rx_oversample/latest

Test location	/workspace/coverage/default/43.uart_rx_parity_err.1642488398
Short name	T312
Test name
Test status
Simulation time	127565142516 ps
CPU time	35.82 seconds
Started	Feb 18 02:06:18 PM PST 24
Finished	Feb 18 02:06:57 PM PST 24
Peak memory	199756 kb
Host	smart-800f3d8f-e9c2-4a4a-8c7c-c51412f8950f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1642488398 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_parity_err.1642488398
Directory	/workspace/43.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/43.uart_rx_start_bit_filter.1438145061
Short name	T405
Test name
Test status
Simulation time	6002018200 ps
CPU time	2.94 seconds
Started	Feb 18 02:06:26 PM PST 24
Finished	Feb 18 02:06:32 PM PST 24
Peak memory	195752 kb
Host	smart-6b6f7c53-bee2-43f7-a350-7b11fe308d0e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1438145061 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_start_bit_filter.1438145061
Directory	/workspace/43.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/43.uart_smoke.1873300946
Short name	T816
Test name
Test status
Simulation time	258306866 ps
CPU time	1.66 seconds
Started	Feb 18 02:06:26 PM PST 24
Finished	Feb 18 02:06:30 PM PST 24
Peak memory	198408 kb
Host	smart-923c52b5-6642-4be9-8cd1-5074e8b534b8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1873300946 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_smoke.1873300946
Directory	/workspace/43.uart_smoke/latest

Test location	/workspace/coverage/default/43.uart_tx_ovrd.732206085
Short name	T419
Test name
Test status
Simulation time	6707788106 ps
CPU time	20.94 seconds
Started	Feb 18 02:06:21 PM PST 24
Finished	Feb 18 02:06:46 PM PST 24
Peak memory	199684 kb
Host	smart-f593f7d6-92dc-450e-afbc-88cfb2cafca2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=732206085 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_ovrd.732206085
Directory	/workspace/43.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/43.uart_tx_rx.2754009329
Short name	T997
Test name
Test status
Simulation time	70838866713 ps
CPU time	184.24 seconds
Started	Feb 18 02:06:19 PM PST 24
Finished	Feb 18 02:09:26 PM PST 24
Peak memory	200060 kb
Host	smart-074b0527-c1e9-4412-94e6-e42e4922d086
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2754009329 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_rx.2754009329
Directory	/workspace/43.uart_tx_rx/latest

Test location	/workspace/coverage/default/44.uart_alert_test.1378965490
Short name	T588
Test name
Test status
Simulation time	14556158 ps
CPU time	0.56 seconds
Started	Feb 18 02:06:26 PM PST 24
Finished	Feb 18 02:06:29 PM PST 24
Peak memory	195524 kb
Host	smart-55e74fa2-ffb5-4e26-ad40-e43dd050ae60
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378965490 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_alert_test.1378965490
Directory	/workspace/44.uart_alert_test/latest

Test location	/workspace/coverage/default/44.uart_fifo_full.2859250422
Short name	T661
Test name
Test status
Simulation time	153470424517 ps
CPU time	89.81 seconds
Started	Feb 18 02:06:27 PM PST 24
Finished	Feb 18 02:08:00 PM PST 24
Peak memory	200004 kb
Host	smart-ca6b14f5-ed93-4b37-8127-2de0d5e3e175
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2859250422 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_full.2859250422
Directory	/workspace/44.uart_fifo_full/latest

Test location	/workspace/coverage/default/44.uart_fifo_overflow.3585883802
Short name	T1058
Test name
Test status
Simulation time	23870478743 ps
CPU time	29.72 seconds
Started	Feb 18 02:06:26 PM PST 24
Finished	Feb 18 02:06:58 PM PST 24
Peak memory	199824 kb
Host	smart-beaa6bea-901d-4f17-bc63-873613392712
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3585883802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_overflow.3585883802
Directory	/workspace/44.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/44.uart_fifo_reset.3550474498
Short name	T313
Test name
Test status
Simulation time	163989405282 ps
CPU time	23.28 seconds
Started	Feb 18 02:06:26 PM PST 24
Finished	Feb 18 02:06:52 PM PST 24
Peak memory	199596 kb
Host	smart-7b5add28-5ec2-491c-8513-66d7dfcab4c5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3550474498 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_reset.3550474498
Directory	/workspace/44.uart_fifo_reset/latest

Test location	/workspace/coverage/default/44.uart_intr.3607850602
Short name	T598
Test name
Test status
Simulation time	33652201279 ps
CPU time	16.25 seconds
Started	Feb 18 02:06:25 PM PST 24
Finished	Feb 18 02:06:45 PM PST 24
Peak memory	200020 kb
Host	smart-df24b8e2-461c-4b64-8e35-c2232f86ff72
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607850602 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_intr.3607850602
Directory	/workspace/44.uart_intr/latest

Test location	/workspace/coverage/default/44.uart_long_xfer_wo_dly.2413413529
Short name	T702
Test name
Test status
Simulation time	66528834835 ps
CPU time	157.56 seconds
Started	Feb 18 02:06:30 PM PST 24
Finished	Feb 18 02:09:11 PM PST 24
Peak memory	200008 kb
Host	smart-6d8be012-cd70-4772-b655-89a375ed150d
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2413413529 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_long_xfer_wo_dly.2413413529
Directory	/workspace/44.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/44.uart_noise_filter.2257865581
Short name	T897
Test name
Test status
Simulation time	63851680507 ps
CPU time	134.07 seconds
Started	Feb 18 02:06:24 PM PST 24
Finished	Feb 18 02:08:42 PM PST 24
Peak memory	198364 kb
Host	smart-b284b3f9-0b5f-4b91-b6c1-07c1edfab088
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2257865581 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_noise_filter.2257865581
Directory	/workspace/44.uart_noise_filter/latest

Test location	/workspace/coverage/default/44.uart_perf.2743562162
Short name	T837
Test name
Test status
Simulation time	8086843632 ps
CPU time	107.79 seconds
Started	Feb 18 02:06:22 PM PST 24
Finished	Feb 18 02:08:14 PM PST 24
Peak memory	199984 kb
Host	smart-f68fa1fc-1510-499c-b527-8b8cb54480b7
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2743562162 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_perf.2743562162
Directory	/workspace/44.uart_perf/latest

Test location	/workspace/coverage/default/44.uart_rx_oversample.1274466146
Short name	T805
Test name
Test status
Simulation time	3712998952 ps
CPU time	7.59 seconds
Started	Feb 18 02:06:27 PM PST 24
Finished	Feb 18 02:06:37 PM PST 24
Peak memory	198436 kb
Host	smart-d3886b83-157c-4fc7-9d5c-614bdfed3920
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1274466146 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_oversample.1274466146
Directory	/workspace/44.uart_rx_oversample/latest

Test location	/workspace/coverage/default/44.uart_rx_parity_err.2732299712
Short name	T508
Test name
Test status
Simulation time	12816939830 ps
CPU time	11.91 seconds
Started	Feb 18 02:06:24 PM PST 24
Finished	Feb 18 02:06:39 PM PST 24
Peak memory	199168 kb
Host	smart-7bc08f89-591f-4348-b02f-86a71bafa5cb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2732299712 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_parity_err.2732299712
Directory	/workspace/44.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/44.uart_rx_start_bit_filter.669004826
Short name	T712
Test name
Test status
Simulation time	6375457544 ps
CPU time	2.67 seconds
Started	Feb 18 02:06:26 PM PST 24
Finished	Feb 18 02:06:32 PM PST 24
Peak memory	195788 kb
Host	smart-7294ca66-c953-406f-8768-794eb6f8da50
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=669004826 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_start_bit_filter.669004826
Directory	/workspace/44.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/44.uart_smoke.2175515642
Short name	T461
Test name
Test status
Simulation time	543575014 ps
CPU time	1.63 seconds
Started	Feb 18 02:06:21 PM PST 24
Finished	Feb 18 02:06:27 PM PST 24
Peak memory	199804 kb
Host	smart-e11ec94c-0199-42d0-8768-42a593501e27
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2175515642 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_smoke.2175515642
Directory	/workspace/44.uart_smoke/latest

Test location	/workspace/coverage/default/44.uart_tx_ovrd.4241896308
Short name	T729
Test name
Test status
Simulation time	6312920698 ps
CPU time	14.56 seconds
Started	Feb 18 02:06:23 PM PST 24
Finished	Feb 18 02:06:41 PM PST 24
Peak memory	199584 kb
Host	smart-8b85a697-bb47-4e43-aa8a-afc89fd9272c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4241896308 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_ovrd.4241896308
Directory	/workspace/44.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/44.uart_tx_rx.1592912828
Short name	T204
Test name
Test status
Simulation time	12349831027 ps
CPU time	19.73 seconds
Started	Feb 18 02:06:29 PM PST 24
Finished	Feb 18 02:06:52 PM PST 24
Peak memory	200016 kb
Host	smart-9af12678-171c-4875-8149-877952a0b62f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1592912828 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_rx.1592912828
Directory	/workspace/44.uart_tx_rx/latest

Test location	/workspace/coverage/default/45.uart_alert_test.578874444
Short name	T629
Test name
Test status
Simulation time	28633710 ps
CPU time	0.57 seconds
Started	Feb 18 02:06:33 PM PST 24
Finished	Feb 18 02:06:38 PM PST 24
Peak memory	195512 kb
Host	smart-b09a1502-69fd-49ef-897b-e35b2b089899
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578874444 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_alert_test.578874444
Directory	/workspace/45.uart_alert_test/latest

Test location	/workspace/coverage/default/45.uart_fifo_full.2785092177
Short name	T181
Test name
Test status
Simulation time	145976652234 ps
CPU time	175.42 seconds
Started	Feb 18 02:06:32 PM PST 24
Finished	Feb 18 02:09:32 PM PST 24
Peak memory	200016 kb
Host	smart-7ec91fad-4132-440c-8e9e-9b1033132518
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2785092177 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_full.2785092177
Directory	/workspace/45.uart_fifo_full/latest

Test location	/workspace/coverage/default/45.uart_fifo_overflow.2389403559
Short name	T333
Test name
Test status
Simulation time	134111050337 ps
CPU time	239.65 seconds
Started	Feb 18 02:06:30 PM PST 24
Finished	Feb 18 02:10:33 PM PST 24
Peak memory	200028 kb
Host	smart-c82fcfad-5696-41a5-b558-e0e54a5fcd5a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2389403559 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_overflow.2389403559
Directory	/workspace/45.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/45.uart_fifo_reset.2007293794
Short name	T264
Test name
Test status
Simulation time	123511474934 ps
CPU time	49.11 seconds
Started	Feb 18 02:06:32 PM PST 24
Finished	Feb 18 02:07:26 PM PST 24
Peak memory	198596 kb
Host	smart-b10cbb45-c268-4870-83fc-dd73bffdaa58
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2007293794 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_reset.2007293794
Directory	/workspace/45.uart_fifo_reset/latest

Test location	/workspace/coverage/default/45.uart_long_xfer_wo_dly.4277029501
Short name	T504
Test name
Test status
Simulation time	136984412687 ps
CPU time	305.83 seconds
Started	Feb 18 02:06:31 PM PST 24
Finished	Feb 18 02:11:41 PM PST 24
Peak memory	200112 kb
Host	smart-bb3cd9d4-af3f-4ce9-81fc-e029c203655b
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4277029501 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_long_xfer_wo_dly.4277029501
Directory	/workspace/45.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/45.uart_loopback.2595402746
Short name	T1033
Test name
Test status
Simulation time	8204073272 ps
CPU time	3.6 seconds
Started	Feb 18 02:06:32 PM PST 24
Finished	Feb 18 02:06:39 PM PST 24
Peak memory	198944 kb
Host	smart-8e08b696-e319-45d0-a5c6-1b1f5170bb50
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2595402746 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_loopback.2595402746
Directory	/workspace/45.uart_loopback/latest

Test location	/workspace/coverage/default/45.uart_noise_filter.268174565
Short name	T403
Test name
Test status
Simulation time	40976051474 ps
CPU time	18.26 seconds
Started	Feb 18 02:06:30 PM PST 24
Finished	Feb 18 02:06:51 PM PST 24
Peak memory	199208 kb
Host	smart-d9b9c3c5-a8e7-4de2-9f1c-e6917f3c6f46
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=268174565 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_noise_filter.268174565
Directory	/workspace/45.uart_noise_filter/latest

Test location	/workspace/coverage/default/45.uart_perf.401547141
Short name	T537
Test name
Test status
Simulation time	22588515511 ps
CPU time	140.92 seconds
Started	Feb 18 02:06:31 PM PST 24
Finished	Feb 18 02:08:55 PM PST 24
Peak memory	199964 kb
Host	smart-d8c2c84b-e8a5-4e0c-b50e-1efa585c6229
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=401547141 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_perf.401547141
Directory	/workspace/45.uart_perf/latest

Test location	/workspace/coverage/default/45.uart_rx_parity_err.1135506702
Short name	T986
Test name
Test status
Simulation time	12212286507 ps
CPU time	19.04 seconds
Started	Feb 18 02:06:32 PM PST 24
Finished	Feb 18 02:06:55 PM PST 24
Peak memory	198928 kb
Host	smart-309fd1e7-1e2f-4529-b5c3-578bc4910f34
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1135506702 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_parity_err.1135506702
Directory	/workspace/45.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/45.uart_rx_start_bit_filter.1735140915
Short name	T856
Test name
Test status
Simulation time	7007406543 ps
CPU time	2.19 seconds
Started	Feb 18 02:06:32 PM PST 24
Finished	Feb 18 02:06:38 PM PST 24
Peak memory	195688 kb
Host	smart-bc4f04b9-0147-409d-85fb-65f5c7856fec
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1735140915 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_start_bit_filter.1735140915
Directory	/workspace/45.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/45.uart_smoke.120540573
Short name	T1114
Test name
Test status
Simulation time	675527810 ps
CPU time	2.73 seconds
Started	Feb 18 02:06:26 PM PST 24
Finished	Feb 18 02:06:32 PM PST 24
Peak memory	198412 kb
Host	smart-18d0288d-6a14-4a12-9e42-8869b85eb99d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=120540573 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_smoke.120540573
Directory	/workspace/45.uart_smoke/latest

Test location	/workspace/coverage/default/45.uart_stress_all.2887784976
Short name	T763
Test name
Test status
Simulation time	169020564544 ps
CPU time	1153.45 seconds
Started	Feb 18 02:06:32 PM PST 24
Finished	Feb 18 02:25:50 PM PST 24
Peak memory	199932 kb
Host	smart-9844e3dc-635e-4f8e-9b16-018d67e97ac6
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887784976 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_stress_all.2887784976
Directory	/workspace/45.uart_stress_all/latest

Test location	/workspace/coverage/default/45.uart_stress_all_with_rand_reset.1035440318
Short name	T328
Test name
Test status
Simulation time	93846024952 ps
CPU time	342.02 seconds
Started	Feb 18 02:06:33 PM PST 24
Finished	Feb 18 02:12:19 PM PST 24
Peak memory	208944 kb
Host	smart-65f32d0a-260e-42e9-addb-922d6c3afa10
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035440318 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 45.uart_stress_all_with_rand_reset.1035440318
Directory	/workspace/45.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/45.uart_tx_ovrd.1728688577
Short name	T496
Test name
Test status
Simulation time	1117818338 ps
CPU time	3.94 seconds
Started	Feb 18 02:06:33 PM PST 24
Finished	Feb 18 02:06:41 PM PST 24
Peak memory	198104 kb
Host	smart-d1bcdc5e-c026-40ff-a2ff-ad06b8cf8850
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1728688577 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_ovrd.1728688577
Directory	/workspace/45.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/45.uart_tx_rx.4031718901
Short name	T826
Test name
Test status
Simulation time	159596732408 ps
CPU time	172.99 seconds
Started	Feb 18 02:06:33 PM PST 24
Finished	Feb 18 02:09:30 PM PST 24
Peak memory	200036 kb
Host	smart-3d5dbf8a-8f0d-42d2-8b6c-26dfe498acee
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4031718901 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_rx.4031718901
Directory	/workspace/45.uart_tx_rx/latest

Test location	/workspace/coverage/default/46.uart_alert_test.853628717
Short name	T670
Test name
Test status
Simulation time	130464362 ps
CPU time	0.56 seconds
Started	Feb 18 02:06:43 PM PST 24
Finished	Feb 18 02:06:46 PM PST 24
Peak memory	195492 kb
Host	smart-0780d741-be7e-45fc-bca4-b94c5f4b5489
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853628717 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_alert_test.853628717
Directory	/workspace/46.uart_alert_test/latest

Test location	/workspace/coverage/default/46.uart_fifo_full.1640006618
Short name	T1113
Test name
Test status
Simulation time	49734824343 ps
CPU time	72.11 seconds
Started	Feb 18 02:06:33 PM PST 24
Finished	Feb 18 02:07:50 PM PST 24
Peak memory	199988 kb
Host	smart-6906470a-4dff-4532-b7e3-899de94bcb1b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1640006618 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_full.1640006618
Directory	/workspace/46.uart_fifo_full/latest

Test location	/workspace/coverage/default/46.uart_fifo_overflow.1694914799
Short name	T358
Test name
Test status
Simulation time	113195811006 ps
CPU time	46.42 seconds
Started	Feb 18 02:06:29 PM PST 24
Finished	Feb 18 02:07:18 PM PST 24
Peak memory	200048 kb
Host	smart-ac6868c6-fdab-4afe-a1ed-064e94331591
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1694914799 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_overflow.1694914799
Directory	/workspace/46.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/46.uart_fifo_reset.642578434
Short name	T161
Test name
Test status
Simulation time	112521645001 ps
CPU time	13.3 seconds
Started	Feb 18 02:06:33 PM PST 24
Finished	Feb 18 02:06:50 PM PST 24
Peak memory	200040 kb
Host	smart-c41a4dff-baf8-42ce-81cd-d4c2d2b24a4e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=642578434 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_reset.642578434
Directory	/workspace/46.uart_fifo_reset/latest

Test location	/workspace/coverage/default/46.uart_intr.1910614027
Short name	T1063
Test name
Test status
Simulation time	95751758372 ps
CPU time	61.66 seconds
Started	Feb 18 02:06:29 PM PST 24
Finished	Feb 18 02:07:35 PM PST 24
Peak memory	198196 kb
Host	smart-22b3c627-880c-4ad3-a7ed-0d3cb252fe62
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910614027 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_intr.1910614027
Directory	/workspace/46.uart_intr/latest

Test location	/workspace/coverage/default/46.uart_long_xfer_wo_dly.3523839164
Short name	T506
Test name
Test status
Simulation time	39595356472 ps
CPU time	365.26 seconds
Started	Feb 18 02:06:33 PM PST 24
Finished	Feb 18 02:12:42 PM PST 24
Peak memory	200096 kb
Host	smart-524864c2-2b50-4f77-a7c9-e4d129bf3f34
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3523839164 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_long_xfer_wo_dly.3523839164
Directory	/workspace/46.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/46.uart_loopback.2335929884
Short name	T538
Test name
Test status
Simulation time	9031944597 ps
CPU time	11.06 seconds
Started	Feb 18 02:06:33 PM PST 24
Finished	Feb 18 02:06:48 PM PST 24
Peak memory	199272 kb
Host	smart-09905b94-487a-46ce-83ad-14b856557f92
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2335929884 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_loopback.2335929884
Directory	/workspace/46.uart_loopback/latest

Test location	/workspace/coverage/default/46.uart_noise_filter.1787412539
Short name	T50
Test name
Test status
Simulation time	17428253975 ps
CPU time	28.02 seconds
Started	Feb 18 02:06:32 PM PST 24
Finished	Feb 18 02:07:04 PM PST 24
Peak memory	198120 kb
Host	smart-49b93152-11e5-4593-94b6-b02eaafd3bac
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1787412539 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_noise_filter.1787412539
Directory	/workspace/46.uart_noise_filter/latest

Test location	/workspace/coverage/default/46.uart_perf.2750602302
Short name	T734
Test name
Test status
Simulation time	8046261759 ps
CPU time	107.95 seconds
Started	Feb 18 02:06:33 PM PST 24
Finished	Feb 18 02:08:25 PM PST 24
Peak memory	200016 kb
Host	smart-94f1be94-ef66-4724-a254-3a1e77c0c8f0
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2750602302 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_perf.2750602302
Directory	/workspace/46.uart_perf/latest

Test location	/workspace/coverage/default/46.uart_rx_oversample.478941714
Short name	T971
Test name
Test status
Simulation time	3378082229 ps
CPU time	9.08 seconds
Started	Feb 18 02:06:31 PM PST 24
Finished	Feb 18 02:06:44 PM PST 24
Peak memory	198792 kb
Host	smart-79881b28-754a-44ce-be5b-cc5e9cacc6d3
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=478941714 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_oversample.478941714
Directory	/workspace/46.uart_rx_oversample/latest

Test location	/workspace/coverage/default/46.uart_rx_parity_err.1477264632
Short name	T495
Test name
Test status
Simulation time	128651244656 ps
CPU time	105.81 seconds
Started	Feb 18 02:06:31 PM PST 24
Finished	Feb 18 02:08:20 PM PST 24
Peak memory	200068 kb
Host	smart-63e316f2-ecb3-40ea-a3eb-18411d574c52
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1477264632 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_parity_err.1477264632
Directory	/workspace/46.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/46.uart_rx_start_bit_filter.4022582680
Short name	T460
Test name
Test status
Simulation time	5778339541 ps
CPU time	3.11 seconds
Started	Feb 18 02:06:33 PM PST 24
Finished	Feb 18 02:06:40 PM PST 24
Peak memory	195856 kb
Host	smart-0e015d9c-e460-49b9-9a5f-21c76c6cff39
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4022582680 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_start_bit_filter.4022582680
Directory	/workspace/46.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/46.uart_smoke.3021898698
Short name	T903
Test name
Test status
Simulation time	800555841 ps
CPU time	2.8 seconds
Started	Feb 18 02:06:32 PM PST 24
Finished	Feb 18 02:06:40 PM PST 24
Peak memory	198900 kb
Host	smart-30fd3a6c-f3f6-4c16-b33f-0082e973eef2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3021898698 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_smoke.3021898698
Directory	/workspace/46.uart_smoke/latest

Test location	/workspace/coverage/default/46.uart_stress_all.2427626493
Short name	T905
Test name
Test status
Simulation time	155222333438 ps
CPU time	130.46 seconds
Started	Feb 18 02:06:32 PM PST 24
Finished	Feb 18 02:08:47 PM PST 24
Peak memory	200028 kb
Host	smart-f63c2f0a-83a2-4452-b951-b6c450b1a8a7
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427626493 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_stress_all.2427626493
Directory	/workspace/46.uart_stress_all/latest

Test location	/workspace/coverage/default/46.uart_stress_all_with_rand_reset.3750662513
Short name	T731
Test name
Test status
Simulation time	20641078662 ps
CPU time	216.36 seconds
Started	Feb 18 02:06:31 PM PST 24
Finished	Feb 18 02:10:11 PM PST 24
Peak memory	216720 kb
Host	smart-b6a58d80-c69e-4695-94e0-3f5530c704a8
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750662513 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 46.uart_stress_all_with_rand_reset.3750662513
Directory	/workspace/46.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/46.uart_tx_ovrd.879773888
Short name	T502
Test name
Test status
Simulation time	947628040 ps
CPU time	2.34 seconds
Started	Feb 18 02:06:30 PM PST 24
Finished	Feb 18 02:06:35 PM PST 24
Peak memory	198416 kb
Host	smart-24aff2da-bd4e-4f96-b76e-2039f8147a58
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=879773888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_ovrd.879773888
Directory	/workspace/46.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/46.uart_tx_rx.3053387992
Short name	T10
Test name
Test status
Simulation time	151896957038 ps
CPU time	61.93 seconds
Started	Feb 18 02:06:34 PM PST 24
Finished	Feb 18 02:07:40 PM PST 24
Peak memory	200052 kb
Host	smart-150808e8-a04e-4005-97a7-99157c95ce23
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3053387992 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_rx.3053387992
Directory	/workspace/46.uart_tx_rx/latest

Test location	/workspace/coverage/default/47.uart_alert_test.3326291509
Short name	T93
Test name
Test status
Simulation time	17618254 ps
CPU time	0.54 seconds
Started	Feb 18 02:06:41 PM PST 24
Finished	Feb 18 02:06:44 PM PST 24
Peak memory	194556 kb
Host	smart-62a0ffed-686f-4ff7-ac35-9a0f84ea857e
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326291509 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_alert_test.3326291509
Directory	/workspace/47.uart_alert_test/latest

Test location	/workspace/coverage/default/47.uart_fifo_full.2668372639
Short name	T332
Test name
Test status
Simulation time	40121391854 ps
CPU time	17 seconds
Started	Feb 18 02:06:43 PM PST 24
Finished	Feb 18 02:07:02 PM PST 24
Peak memory	199904 kb
Host	smart-a4821f92-71cb-4427-a8d0-d15b6e845eb2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2668372639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_full.2668372639
Directory	/workspace/47.uart_fifo_full/latest

Test location	/workspace/coverage/default/47.uart_fifo_overflow.593544488
Short name	T690
Test name
Test status
Simulation time	227565242947 ps
CPU time	36.81 seconds
Started	Feb 18 02:06:41 PM PST 24
Finished	Feb 18 02:07:20 PM PST 24
Peak memory	200048 kb
Host	smart-67c5ad85-ce20-4715-a361-9e75c9d9a090
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=593544488 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_overflow.593544488
Directory	/workspace/47.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/47.uart_loopback.1257439240
Short name	T791
Test name
Test status
Simulation time	8487591502 ps
CPU time	6.28 seconds
Started	Feb 18 02:06:41 PM PST 24
Finished	Feb 18 02:06:49 PM PST 24
Peak memory	199260 kb
Host	smart-73d4778a-39ba-4744-b0c4-60e6672e6af6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1257439240 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_loopback.1257439240
Directory	/workspace/47.uart_loopback/latest

Test location	/workspace/coverage/default/47.uart_noise_filter.991716705
Short name	T505
Test name
Test status
Simulation time	143412578914 ps
CPU time	203.43 seconds
Started	Feb 18 02:06:43 PM PST 24
Finished	Feb 18 02:10:09 PM PST 24
Peak memory	207888 kb
Host	smart-63a5fa08-0911-4215-8a55-7d617dcfe256
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=991716705 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_noise_filter.991716705
Directory	/workspace/47.uart_noise_filter/latest

Test location	/workspace/coverage/default/47.uart_perf.2030324229
Short name	T520
Test name
Test status
Simulation time	21385417183 ps
CPU time	1127.59 seconds
Started	Feb 18 02:06:41 PM PST 24
Finished	Feb 18 02:25:30 PM PST 24
Peak memory	200092 kb
Host	smart-8b5cda18-737e-4e7c-a9d0-2226c413fce5
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2030324229 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_perf.2030324229
Directory	/workspace/47.uart_perf/latest

Test location	/workspace/coverage/default/47.uart_rx_oversample.2838385152
Short name	T21
Test name
Test status
Simulation time	1856108866 ps
CPU time	5.35 seconds
Started	Feb 18 02:06:40 PM PST 24
Finished	Feb 18 02:06:48 PM PST 24
Peak memory	198152 kb
Host	smart-e3d35d38-4ddd-4dc7-965a-c018cab4d57d
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2838385152 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_oversample.2838385152
Directory	/workspace/47.uart_rx_oversample/latest

Test location	/workspace/coverage/default/47.uart_rx_parity_err.3409077708
Short name	T90
Test name
Test status
Simulation time	29395081580 ps
CPU time	45.65 seconds
Started	Feb 18 02:06:43 PM PST 24
Finished	Feb 18 02:07:31 PM PST 24
Peak memory	199564 kb
Host	smart-fa5e14d1-3a87-4b0e-b858-d6ad936fa1e9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3409077708 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_parity_err.3409077708
Directory	/workspace/47.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/47.uart_rx_start_bit_filter.2816587107
Short name	T807
Test name
Test status
Simulation time	5779237324 ps
CPU time	5.53 seconds
Started	Feb 18 02:06:43 PM PST 24
Finished	Feb 18 02:06:51 PM PST 24
Peak memory	195768 kb
Host	smart-dd265caf-3a34-4503-8c02-39e503952cf7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2816587107 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_start_bit_filter.2816587107
Directory	/workspace/47.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/47.uart_smoke.1218615349
Short name	T485
Test name
Test status
Simulation time	6051902408 ps
CPU time	11.47 seconds
Started	Feb 18 02:06:40 PM PST 24
Finished	Feb 18 02:06:54 PM PST 24
Peak memory	198868 kb
Host	smart-f3720bdc-647f-42b9-b1fa-51a6aff72d51
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1218615349 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_smoke.1218615349
Directory	/workspace/47.uart_smoke/latest

Test location	/workspace/coverage/default/47.uart_stress_all.3417106647
Short name	T751
Test name
Test status
Simulation time	249346448222 ps
CPU time	147.8 seconds
Started	Feb 18 02:06:42 PM PST 24
Finished	Feb 18 02:09:12 PM PST 24
Peak memory	200100 kb
Host	smart-99001504-4dc0-4f3c-b364-5ec3128e3ace
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417106647 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_stress_all.3417106647
Directory	/workspace/47.uart_stress_all/latest

Test location	/workspace/coverage/default/47.uart_stress_all_with_rand_reset.2040309680
Short name	T831
Test name
Test status
Simulation time	133394548204 ps
CPU time	575.47 seconds
Started	Feb 18 02:06:43 PM PST 24
Finished	Feb 18 02:16:20 PM PST 24
Peak memory	211320 kb
Host	smart-6ef62481-c5b6-495a-a334-a0e989909559
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040309680 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 47.uart_stress_all_with_rand_reset.2040309680
Directory	/workspace/47.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/47.uart_tx_ovrd.1081203358
Short name	T951
Test name
Test status
Simulation time	8110441623 ps
CPU time	9.82 seconds
Started	Feb 18 02:06:42 PM PST 24
Finished	Feb 18 02:06:54 PM PST 24
Peak memory	200128 kb
Host	smart-ed3cf57e-d19b-491f-b932-a936a3e816d7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1081203358 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_ovrd.1081203358
Directory	/workspace/47.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/47.uart_tx_rx.280491844
Short name	T606
Test name
Test status
Simulation time	56926920699 ps
CPU time	38.39 seconds
Started	Feb 18 02:06:42 PM PST 24
Finished	Feb 18 02:07:22 PM PST 24
Peak memory	200056 kb
Host	smart-40940988-8ead-436d-a065-7319248513ef
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=280491844 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_rx.280491844
Directory	/workspace/47.uart_tx_rx/latest

Test location	/workspace/coverage/default/48.uart_alert_test.261982303
Short name	T472
Test name
Test status
Simulation time	36177046 ps
CPU time	0.59 seconds
Started	Feb 18 02:06:46 PM PST 24
Finished	Feb 18 02:06:48 PM PST 24
Peak memory	194476 kb
Host	smart-9511bf84-fb48-43e8-bf1e-bce4fe798375
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261982303 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_alert_test.261982303
Directory	/workspace/48.uart_alert_test/latest

Test location	/workspace/coverage/default/48.uart_fifo_full.3826093741
Short name	T895
Test name
Test status
Simulation time	157259893976 ps
CPU time	45.47 seconds
Started	Feb 18 02:06:44 PM PST 24
Finished	Feb 18 02:07:31 PM PST 24
Peak memory	200112 kb
Host	smart-bfed5c2e-769b-4824-a2ac-544b1de88794
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3826093741 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_full.3826093741
Directory	/workspace/48.uart_fifo_full/latest

Test location	/workspace/coverage/default/48.uart_fifo_overflow.108591664
Short name	T688
Test name
Test status
Simulation time	71973653737 ps
CPU time	60.17 seconds
Started	Feb 18 02:06:40 PM PST 24
Finished	Feb 18 02:07:43 PM PST 24
Peak memory	199708 kb
Host	smart-f736d794-8190-4037-83c3-6fbad85e857c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=108591664 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_overflow.108591664
Directory	/workspace/48.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/48.uart_fifo_reset.1574488931
Short name	T190
Test name
Test status
Simulation time	33729510885 ps
CPU time	11.02 seconds
Started	Feb 18 02:06:43 PM PST 24
Finished	Feb 18 02:06:56 PM PST 24
Peak memory	199928 kb
Host	smart-fb140938-863e-42d3-8f20-453770c22fbb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1574488931 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_reset.1574488931
Directory	/workspace/48.uart_fifo_reset/latest

Test location	/workspace/coverage/default/48.uart_intr.2978909812
Short name	T696
Test name
Test status
Simulation time	399650415231 ps
CPU time	637.42 seconds
Started	Feb 18 02:06:42 PM PST 24
Finished	Feb 18 02:17:21 PM PST 24
Peak memory	200004 kb
Host	smart-61c4a263-7ba8-485c-8cbe-54e1b65e6e46
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978909812 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_intr.2978909812
Directory	/workspace/48.uart_intr/latest

Test location	/workspace/coverage/default/48.uart_long_xfer_wo_dly.3515420244
Short name	T54
Test name
Test status
Simulation time	148138447967 ps
CPU time	160.04 seconds
Started	Feb 18 02:06:54 PM PST 24
Finished	Feb 18 02:09:38 PM PST 24
Peak memory	200108 kb
Host	smart-1b894aae-fe56-453d-a4c1-79f99033da0e
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3515420244 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_long_xfer_wo_dly.3515420244
Directory	/workspace/48.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/48.uart_loopback.718083033
Short name	T578
Test name
Test status
Simulation time	7679442049 ps
CPU time	15.3 seconds
Started	Feb 18 02:07:07 PM PST 24
Finished	Feb 18 02:07:24 PM PST 24
Peak memory	198776 kb
Host	smart-22e95b69-99c5-4b91-9f20-44e1f27b29f4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=718083033 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_loopback.718083033
Directory	/workspace/48.uart_loopback/latest

Test location	/workspace/coverage/default/48.uart_noise_filter.1147801346
Short name	T750
Test name
Test status
Simulation time	57525284106 ps
CPU time	103.49 seconds
Started	Feb 18 02:06:47 PM PST 24
Finished	Feb 18 02:08:32 PM PST 24
Peak memory	199560 kb
Host	smart-a534e262-0fa9-4678-be20-08553abf6f40
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1147801346 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_noise_filter.1147801346
Directory	/workspace/48.uart_noise_filter/latest

Test location	/workspace/coverage/default/48.uart_perf.1649241427
Short name	T550
Test name
Test status
Simulation time	25534650405 ps
CPU time	76.63 seconds
Started	Feb 18 02:06:46 PM PST 24
Finished	Feb 18 02:08:04 PM PST 24
Peak memory	200032 kb
Host	smart-01edfa7b-c791-4512-8e73-ea4c6eb5cbfe
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1649241427 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_perf.1649241427
Directory	/workspace/48.uart_perf/latest

Test location	/workspace/coverage/default/48.uart_rx_parity_err.3843706893
Short name	T655
Test name
Test status
Simulation time	32983427479 ps
CPU time	14.75 seconds
Started	Feb 18 02:06:53 PM PST 24
Finished	Feb 18 02:07:12 PM PST 24
Peak memory	199196 kb
Host	smart-e468e3c2-6c4b-4a2f-88fc-3364368f465f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3843706893 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_parity_err.3843706893
Directory	/workspace/48.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/48.uart_rx_start_bit_filter.307221696
Short name	T762
Test name
Test status
Simulation time	4366909218 ps
CPU time	4.21 seconds
Started	Feb 18 02:06:43 PM PST 24
Finished	Feb 18 02:06:49 PM PST 24
Peak memory	195796 kb
Host	smart-8175367b-d6b9-4297-bfe3-caeee8d5a8d9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=307221696 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_start_bit_filter.307221696
Directory	/workspace/48.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/48.uart_smoke.2690546551
Short name	T425
Test name
Test status
Simulation time	853021440 ps
CPU time	2.69 seconds
Started	Feb 18 02:06:42 PM PST 24
Finished	Feb 18 02:06:47 PM PST 24
Peak memory	199388 kb
Host	smart-7e76602b-bb2f-403b-975d-0c1f6b115846
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2690546551 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_smoke.2690546551
Directory	/workspace/48.uart_smoke/latest

Test location	/workspace/coverage/default/48.uart_tx_ovrd.2340801345
Short name	T880
Test name
Test status
Simulation time	7213151785 ps
CPU time	7.83 seconds
Started	Feb 18 02:07:00 PM PST 24
Finished	Feb 18 02:07:11 PM PST 24
Peak memory	198924 kb
Host	smart-c2302731-ef05-45ab-97c6-13f24de115b6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2340801345 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_ovrd.2340801345
Directory	/workspace/48.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/48.uart_tx_rx.3396977860
Short name	T122
Test name
Test status
Simulation time	88652360075 ps
CPU time	10.69 seconds
Started	Feb 18 02:06:39 PM PST 24
Finished	Feb 18 02:06:52 PM PST 24
Peak memory	196056 kb
Host	smart-b4d255b5-5d13-4ce2-abb9-acf4fadf8f63
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3396977860 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_rx.3396977860
Directory	/workspace/48.uart_tx_rx/latest

Test location	/workspace/coverage/default/49.uart_alert_test.2426478587
Short name	T590
Test name
Test status
Simulation time	14864849 ps
CPU time	0.56 seconds
Started	Feb 18 02:06:49 PM PST 24
Finished	Feb 18 02:06:52 PM PST 24
Peak memory	195516 kb
Host	smart-5770f30c-9bd2-4c1b-819f-34718f802ced
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426478587 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_alert_test.2426478587
Directory	/workspace/49.uart_alert_test/latest

Test location	/workspace/coverage/default/49.uart_fifo_full.3199465629
Short name	T862
Test name
Test status
Simulation time	48698285616 ps
CPU time	90.82 seconds
Started	Feb 18 02:06:59 PM PST 24
Finished	Feb 18 02:08:34 PM PST 24
Peak memory	200020 kb
Host	smart-53d1bb0a-8f09-48db-98ea-995293643545
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3199465629 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_full.3199465629
Directory	/workspace/49.uart_fifo_full/latest

Test location	/workspace/coverage/default/49.uart_fifo_reset.2779909944
Short name	T1109
Test name
Test status
Simulation time	17313794380 ps
CPU time	13.66 seconds
Started	Feb 18 02:06:54 PM PST 24
Finished	Feb 18 02:07:12 PM PST 24
Peak memory	199740 kb
Host	smart-abbebf5a-1b4a-4c9c-9c6f-cf1e4e03bc0c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2779909944 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_reset.2779909944
Directory	/workspace/49.uart_fifo_reset/latest

Test location	/workspace/coverage/default/49.uart_intr.3452705502
Short name	T908
Test name
Test status
Simulation time	958220495617 ps
CPU time	1601.82 seconds
Started	Feb 18 02:06:54 PM PST 24
Finished	Feb 18 02:33:41 PM PST 24
Peak memory	200088 kb
Host	smart-a10c25cf-d454-42c1-904c-350613755dee
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452705502 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_intr.3452705502
Directory	/workspace/49.uart_intr/latest

Test location	/workspace/coverage/default/49.uart_long_xfer_wo_dly.3924838787
Short name	T725
Test name
Test status
Simulation time	157316323502 ps
CPU time	903.68 seconds
Started	Feb 18 02:06:54 PM PST 24
Finished	Feb 18 02:22:02 PM PST 24
Peak memory	200016 kb
Host	smart-0d6431f4-85b5-44b1-8116-ed6baf9e6487
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3924838787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_long_xfer_wo_dly.3924838787
Directory	/workspace/49.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/49.uart_loopback.1316383040
Short name	T458
Test name
Test status
Simulation time	10511734540 ps
CPU time	26.9 seconds
Started	Feb 18 02:06:58 PM PST 24
Finished	Feb 18 02:07:29 PM PST 24
Peak memory	200044 kb
Host	smart-561a7d1c-700e-4e69-ae32-d4e693917bbd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1316383040 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_loopback.1316383040
Directory	/workspace/49.uart_loopback/latest

Test location	/workspace/coverage/default/49.uart_noise_filter.550627953
Short name	T642
Test name
Test status
Simulation time	167906402170 ps
CPU time	58.01 seconds
Started	Feb 18 02:06:44 PM PST 24
Finished	Feb 18 02:07:43 PM PST 24
Peak memory	200108 kb
Host	smart-59c19c36-5585-4fae-911d-c799bf2832f2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=550627953 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_noise_filter.550627953
Directory	/workspace/49.uart_noise_filter/latest

Test location	/workspace/coverage/default/49.uart_perf.3500157096
Short name	T569
Test name
Test status
Simulation time	7160357162 ps
CPU time	378.1 seconds
Started	Feb 18 02:06:59 PM PST 24
Finished	Feb 18 02:13:21 PM PST 24
Peak memory	199724 kb
Host	smart-e4631886-f330-4e08-8fcc-aadbbac8bac5
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3500157096 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_perf.3500157096
Directory	/workspace/49.uart_perf/latest

Test location	/workspace/coverage/default/49.uart_rx_oversample.3171164922
Short name	T102
Test name
Test status
Simulation time	2421532310 ps
CPU time	19.25 seconds
Started	Feb 18 02:06:53 PM PST 24
Finished	Feb 18 02:07:17 PM PST 24
Peak memory	198692 kb
Host	smart-12bcc9fd-be5c-4b54-9ac7-552f4edf0485
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3171164922 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_oversample.3171164922
Directory	/workspace/49.uart_rx_oversample/latest

Test location	/workspace/coverage/default/49.uart_rx_parity_err.1283566801
Short name	T851
Test name
Test status
Simulation time	165724114599 ps
CPU time	55.06 seconds
Started	Feb 18 02:07:03 PM PST 24
Finished	Feb 18 02:08:01 PM PST 24
Peak memory	200092 kb
Host	smart-b76817dc-146b-4cf6-a2d1-919898c9fee0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1283566801 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_parity_err.1283566801
Directory	/workspace/49.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/49.uart_rx_start_bit_filter.2663176014
Short name	T784
Test name
Test status
Simulation time	44232203132 ps
CPU time	64.83 seconds
Started	Feb 18 02:06:55 PM PST 24
Finished	Feb 18 02:08:05 PM PST 24
Peak memory	195480 kb
Host	smart-288c8807-e89c-4ef5-bc14-90f86875a182
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2663176014 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_start_bit_filter.2663176014
Directory	/workspace/49.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/49.uart_smoke.3600454193
Short name	T493
Test name
Test status
Simulation time	6130002735 ps
CPU time	4.66 seconds
Started	Feb 18 02:06:52 PM PST 24
Finished	Feb 18 02:07:01 PM PST 24
Peak memory	199592 kb
Host	smart-e8a5cca8-f66f-4489-9568-442a5ac298c8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3600454193 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_smoke.3600454193
Directory	/workspace/49.uart_smoke/latest

Test location	/workspace/coverage/default/49.uart_stress_all.3877986793
Short name	T1032
Test name
Test status
Simulation time	100539129544 ps
CPU time	184.53 seconds
Started	Feb 18 02:06:59 PM PST 24
Finished	Feb 18 02:10:08 PM PST 24
Peak memory	200244 kb
Host	smart-a83db547-8317-469a-b17d-6890f5ec981a
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877986793 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_stress_all.3877986793
Directory	/workspace/49.uart_stress_all/latest

Test location	/workspace/coverage/default/49.uart_stress_all_with_rand_reset.4018097766
Short name	T953
Test name
Test status
Simulation time	16330576104 ps
CPU time	189.4 seconds
Started	Feb 18 02:06:55 PM PST 24
Finished	Feb 18 02:10:09 PM PST 24
Peak memory	216096 kb
Host	smart-b22f98a0-8b30-451a-a2cb-15f6565b2d70
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018097766 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 49.uart_stress_all_with_rand_reset.4018097766
Directory	/workspace/49.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/49.uart_tx_ovrd.1022159861
Short name	T901
Test name
Test status
Simulation time	712027237 ps
CPU time	3.52 seconds
Started	Feb 18 02:06:56 PM PST 24
Finished	Feb 18 02:07:04 PM PST 24
Peak memory	198508 kb
Host	smart-fa745503-722a-42ee-8824-1e21c4468c78
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1022159861 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_ovrd.1022159861
Directory	/workspace/49.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/49.uart_tx_rx.1851359319
Short name	T858
Test name
Test status
Simulation time	54923031548 ps
CPU time	97.94 seconds
Started	Feb 18 02:07:01 PM PST 24
Finished	Feb 18 02:08:42 PM PST 24
Peak memory	199972 kb
Host	smart-c2a561f0-9116-4475-a8dc-b274f853358d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1851359319 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_rx.1851359319
Directory	/workspace/49.uart_tx_rx/latest

Test location	/workspace/coverage/default/5.uart_alert_test.1399116247
Short name	T446
Test name
Test status
Simulation time	32297862 ps
CPU time	0.56 seconds
Started	Feb 18 02:03:44 PM PST 24
Finished	Feb 18 02:03:58 PM PST 24
Peak memory	195508 kb
Host	smart-221cb55d-afa3-4800-8c07-9896d9fc9889
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399116247 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_alert_test.1399116247
Directory	/workspace/5.uart_alert_test/latest

Test location	/workspace/coverage/default/5.uart_fifo_full.1398632520
Short name	T907
Test name
Test status
Simulation time	77951209655 ps
CPU time	27.38 seconds
Started	Feb 18 02:03:38 PM PST 24
Finished	Feb 18 02:04:18 PM PST 24
Peak memory	199860 kb
Host	smart-81cf4ce9-e2c9-4189-9432-42bb5a8a99e7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1398632520 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_full.1398632520
Directory	/workspace/5.uart_fifo_full/latest

Test location	/workspace/coverage/default/5.uart_fifo_overflow.3057036254
Short name	T214
Test name
Test status
Simulation time	80096345487 ps
CPU time	20.67 seconds
Started	Feb 18 02:03:48 PM PST 24
Finished	Feb 18 02:04:20 PM PST 24
Peak memory	199252 kb
Host	smart-9f3d025d-1119-4dc6-81b9-027feecaf524
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3057036254 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_overflow.3057036254
Directory	/workspace/5.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/5.uart_fifo_reset.3872175114
Short name	T367
Test name
Test status
Simulation time	59498358219 ps
CPU time	39.09 seconds
Started	Feb 18 02:03:50 PM PST 24
Finished	Feb 18 02:04:39 PM PST 24
Peak memory	200056 kb
Host	smart-dc63552b-7c35-4f83-acce-9c5a9cce63c2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3872175114 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_reset.3872175114
Directory	/workspace/5.uart_fifo_reset/latest

Test location	/workspace/coverage/default/5.uart_intr.2379200965
Short name	T836
Test name
Test status
Simulation time	189405923989 ps
CPU time	247.76 seconds
Started	Feb 18 02:03:56 PM PST 24
Finished	Feb 18 02:08:10 PM PST 24
Peak memory	200036 kb
Host	smart-c649ac5a-c26e-454e-b9fd-ef10abf0b740
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379200965 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_intr.2379200965
Directory	/workspace/5.uart_intr/latest

Test location	/workspace/coverage/default/5.uart_long_xfer_wo_dly.2138386614
Short name	T721
Test name
Test status
Simulation time	85910555967 ps
CPU time	311.42 seconds
Started	Feb 18 02:03:43 PM PST 24
Finished	Feb 18 02:09:08 PM PST 24
Peak memory	200044 kb
Host	smart-3e6dfc6e-d436-4ae0-8269-e965784d11f3
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2138386614 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_long_xfer_wo_dly.2138386614
Directory	/workspace/5.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/5.uart_loopback.3721465010
Short name	T647
Test name
Test status
Simulation time	5487066963 ps
CPU time	3.04 seconds
Started	Feb 18 02:03:49 PM PST 24
Finished	Feb 18 02:04:03 PM PST 24
Peak memory	197840 kb
Host	smart-21be2d1c-4ef3-4bee-824e-149e133ec89b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3721465010 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_loopback.3721465010
Directory	/workspace/5.uart_loopback/latest

Test location	/workspace/coverage/default/5.uart_noise_filter.2667699674
Short name	T863
Test name
Test status
Simulation time	34872244571 ps
CPU time	64.9 seconds
Started	Feb 18 02:03:43 PM PST 24
Finished	Feb 18 02:05:02 PM PST 24
Peak memory	200156 kb
Host	smart-e8640b44-4b79-4d7d-80c3-13a81b0202a7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2667699674 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_noise_filter.2667699674
Directory	/workspace/5.uart_noise_filter/latest

Test location	/workspace/coverage/default/5.uart_perf.1838230892
Short name	T754
Test name
Test status
Simulation time	28069659964 ps
CPU time	378.9 seconds
Started	Feb 18 02:03:47 PM PST 24
Finished	Feb 18 02:10:18 PM PST 24
Peak memory	199980 kb
Host	smart-306857e1-cfdb-4bd0-bb78-1be81c2f9830
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1838230892 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_perf.1838230892
Directory	/workspace/5.uart_perf/latest

Test location	/workspace/coverage/default/5.uart_rx_oversample.1839890221
Short name	T648
Test name
Test status
Simulation time	1289224396 ps
CPU time	1.08 seconds
Started	Feb 18 02:03:44 PM PST 24
Finished	Feb 18 02:03:59 PM PST 24
Peak memory	195460 kb
Host	smart-7a9fa144-db0d-492a-b030-075bf852505b
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1839890221 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_oversample.1839890221
Directory	/workspace/5.uart_rx_oversample/latest

Test location	/workspace/coverage/default/5.uart_rx_parity_err.3463626961
Short name	T139
Test name
Test status
Simulation time	200519458345 ps
CPU time	85.05 seconds
Started	Feb 18 02:03:43 PM PST 24
Finished	Feb 18 02:05:22 PM PST 24
Peak memory	199680 kb
Host	smart-b45fdd59-4eef-489b-865a-0f04cd51b781
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3463626961 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_parity_err.3463626961
Directory	/workspace/5.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/5.uart_rx_start_bit_filter.1249343318
Short name	T1028
Test name
Test status
Simulation time	4519528620 ps
CPU time	4.04 seconds
Started	Feb 18 02:03:46 PM PST 24
Finished	Feb 18 02:04:03 PM PST 24
Peak memory	195632 kb
Host	smart-483ed02e-5812-42d6-ac8d-421575e8b25d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1249343318 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_start_bit_filter.1249343318
Directory	/workspace/5.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/5.uart_smoke.3477086466
Short name	T919
Test name
Test status
Simulation time	5906360037 ps
CPU time	8.41 seconds
Started	Feb 18 02:03:42 PM PST 24
Finished	Feb 18 02:04:05 PM PST 24
Peak memory	199304 kb
Host	smart-82b37de1-4a46-4ddd-a47f-c135a7cadfa4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3477086466 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_smoke.3477086466
Directory	/workspace/5.uart_smoke/latest

Test location	/workspace/coverage/default/5.uart_stress_all.4229151403
Short name	T956
Test name
Test status
Simulation time	99116424005 ps
CPU time	178.01 seconds
Started	Feb 18 02:03:49 PM PST 24
Finished	Feb 18 02:06:58 PM PST 24
Peak memory	199984 kb
Host	smart-7297bf58-f279-4b46-8c97-a8b1dffb55e4
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229151403 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_stress_all.4229151403
Directory	/workspace/5.uart_stress_all/latest

Test location	/workspace/coverage/default/5.uart_stress_all_with_rand_reset.1411825005
Short name	T926
Test name
Test status
Simulation time	248425089183 ps
CPU time	550.22 seconds
Started	Feb 18 02:03:43 PM PST 24
Finished	Feb 18 02:13:07 PM PST 24
Peak memory	212476 kb
Host	smart-15a62748-862c-4572-b362-cfd8ab565b2f
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411825005 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 5.uart_stress_all_with_rand_reset.1411825005
Directory	/workspace/5.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/5.uart_tx_ovrd.910492814
Short name	T1093
Test name
Test status
Simulation time	2334262809 ps
CPU time	3.03 seconds
Started	Feb 18 02:03:48 PM PST 24
Finished	Feb 18 02:04:03 PM PST 24
Peak memory	198768 kb
Host	smart-01d6efbb-e88a-42cd-82ca-95dfd3b35021
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=910492814 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_ovrd.910492814
Directory	/workspace/5.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/5.uart_tx_rx.2255733365
Short name	T1112
Test name
Test status
Simulation time	18676278291 ps
CPU time	16.62 seconds
Started	Feb 18 02:03:42 PM PST 24
Finished	Feb 18 02:04:12 PM PST 24
Peak memory	200116 kb
Host	smart-ca1dabe1-416f-4b72-ac6a-bfefc9557c33
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2255733365 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_rx.2255733365
Directory	/workspace/5.uart_tx_rx/latest

Test location	/workspace/coverage/default/50.uart_fifo_reset.2201655102
Short name	T357
Test name
Test status
Simulation time	314214600969 ps
CPU time	44.66 seconds
Started	Feb 18 02:06:47 PM PST 24
Finished	Feb 18 02:07:34 PM PST 24
Peak memory	200112 kb
Host	smart-f814418c-38b1-41dc-8497-abe92bbd08f9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2201655102 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.uart_fifo_reset.2201655102
Directory	/workspace/50.uart_fifo_reset/latest

Test location	/workspace/coverage/default/52.uart_fifo_reset.4154118911
Short name	T718
Test name
Test status
Simulation time	72300753026 ps
CPU time	59.31 seconds
Started	Feb 18 02:07:01 PM PST 24
Finished	Feb 18 02:08:04 PM PST 24
Peak memory	199956 kb
Host	smart-9152357c-eee7-4f6e-a763-616487c71bde
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4154118911 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.uart_fifo_reset.4154118911
Directory	/workspace/52.uart_fifo_reset/latest

Test location	/workspace/coverage/default/53.uart_fifo_reset.467045370
Short name	T304
Test name
Test status
Simulation time	16039568943 ps
CPU time	24.53 seconds
Started	Feb 18 02:06:58 PM PST 24
Finished	Feb 18 02:07:27 PM PST 24
Peak memory	198780 kb
Host	smart-a70451ec-4e98-433a-9ab5-272c3c90e046
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=467045370 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.uart_fifo_reset.467045370
Directory	/workspace/53.uart_fifo_reset/latest

Test location	/workspace/coverage/default/53.uart_stress_all_with_rand_reset.95718517
Short name	T547
Test name
Test status
Simulation time	222405426158 ps
CPU time	762.68 seconds
Started	Feb 18 02:07:07 PM PST 24
Finished	Feb 18 02:19:52 PM PST 24
Peak memory	216788 kb
Host	smart-a780aa6f-3d99-46e3-b26d-69d22755a661
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95718517 -assert nopostpro c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 53.uart_stress_all_with_rand_reset.95718517
Directory	/workspace/53.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/54.uart_stress_all_with_rand_reset.3548785238
Short name	T99
Test name
Test status
Simulation time	489249870877 ps
CPU time	364.01 seconds
Started	Feb 18 02:06:54 PM PST 24
Finished	Feb 18 02:13:03 PM PST 24
Peak memory	216808 kb
Host	smart-dd22c837-7b01-45df-ac98-091c5e59a58b
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548785238 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 54.uart_stress_all_with_rand_reset.3548785238
Directory	/workspace/54.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/55.uart_fifo_reset.3516271327
Short name	T650
Test name
Test status
Simulation time	100408219076 ps
CPU time	73.71 seconds
Started	Feb 18 02:06:56 PM PST 24
Finished	Feb 18 02:08:15 PM PST 24
Peak memory	200032 kb
Host	smart-22cb010b-bcd3-47cb-bfe3-65a7a171d3e1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3516271327 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.uart_fifo_reset.3516271327
Directory	/workspace/55.uart_fifo_reset/latest

Test location	/workspace/coverage/default/56.uart_fifo_reset.2460449803
Short name	T229
Test name
Test status
Simulation time	32228460877 ps
CPU time	13.41 seconds
Started	Feb 18 02:07:02 PM PST 24
Finished	Feb 18 02:07:19 PM PST 24
Peak memory	198132 kb
Host	smart-56c59d22-026c-4709-8a54-14b2c34f1c95
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2460449803 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.uart_fifo_reset.2460449803
Directory	/workspace/56.uart_fifo_reset/latest

Test location	/workspace/coverage/default/56.uart_stress_all_with_rand_reset.2019376701
Short name	T37
Test name
Test status
Simulation time	34429651686 ps
CPU time	286.24 seconds
Started	Feb 18 02:07:05 PM PST 24
Finished	Feb 18 02:11:53 PM PST 24
Peak memory	212244 kb
Host	smart-fff7e9b2-b070-4db7-a723-b043c878b6e4
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019376701 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 56.uart_stress_all_with_rand_reset.2019376701
Directory	/workspace/56.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/57.uart_fifo_reset.485105935
Short name	T913
Test name
Test status
Simulation time	125530304804 ps
CPU time	211.76 seconds
Started	Feb 18 02:07:01 PM PST 24
Finished	Feb 18 02:10:36 PM PST 24
Peak memory	200108 kb
Host	smart-2b4a7dc8-c8c0-4f27-9cc6-8847f6991520
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=485105935 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.uart_fifo_reset.485105935
Directory	/workspace/57.uart_fifo_reset/latest

Test location	/workspace/coverage/default/57.uart_stress_all_with_rand_reset.793479234
Short name	T894
Test name
Test status
Simulation time	55444094689 ps
CPU time	233.72 seconds
Started	Feb 18 02:06:55 PM PST 24
Finished	Feb 18 02:10:53 PM PST 24
Peak memory	216540 kb
Host	smart-aff9cb6c-f853-4b26-964a-3763e43ac050
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793479234 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 57.uart_stress_all_with_rand_reset.793479234
Directory	/workspace/57.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/58.uart_fifo_reset.1245362408
Short name	T1116
Test name
Test status
Simulation time	182862848624 ps
CPU time	81.1 seconds
Started	Feb 18 02:07:02 PM PST 24
Finished	Feb 18 02:08:26 PM PST 24
Peak memory	199852 kb
Host	smart-136b82a8-3bab-43cc-ac8d-0d207be0cdff
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1245362408 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.uart_fifo_reset.1245362408
Directory	/workspace/58.uart_fifo_reset/latest

Test location	/workspace/coverage/default/58.uart_stress_all_with_rand_reset.3063924077
Short name	T24
Test name
Test status
Simulation time	244148688345 ps
CPU time	690.04 seconds
Started	Feb 18 02:07:03 PM PST 24
Finished	Feb 18 02:18:35 PM PST 24
Peak memory	225012 kb
Host	smart-4aa2cc0d-ae4c-4196-8704-ff88c460bf7b
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063924077 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 58.uart_stress_all_with_rand_reset.3063924077
Directory	/workspace/58.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/59.uart_fifo_reset.2016911092
Short name	T475
Test name
Test status
Simulation time	15250343849 ps
CPU time	33.14 seconds
Started	Feb 18 02:06:54 PM PST 24
Finished	Feb 18 02:07:32 PM PST 24
Peak memory	200112 kb
Host	smart-ffb08b86-4864-423d-8e41-3d6d9ccd9ef1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2016911092 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.uart_fifo_reset.2016911092
Directory	/workspace/59.uart_fifo_reset/latest

Test location	/workspace/coverage/default/59.uart_stress_all_with_rand_reset.4262328142
Short name	T60
Test name
Test status
Simulation time	249800103909 ps
CPU time	496.96 seconds
Started	Feb 18 02:06:55 PM PST 24
Finished	Feb 18 02:15:16 PM PST 24
Peak memory	216884 kb
Host	smart-d51b9f6f-e27b-4d5d-ac42-e991fc435eca
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262328142 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 59.uart_stress_all_with_rand_reset.4262328142
Directory	/workspace/59.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/6.uart_alert_test.4075411590
Short name	T441
Test name
Test status
Simulation time	13724950 ps
CPU time	0.59 seconds
Started	Feb 18 02:03:44 PM PST 24
Finished	Feb 18 02:03:58 PM PST 24
Peak memory	194488 kb
Host	smart-e29f5bb5-4d66-4124-a82f-89e2ad71c45f
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075411590 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_alert_test.4075411590
Directory	/workspace/6.uart_alert_test/latest

Test location	/workspace/coverage/default/6.uart_fifo_full.954022250
Short name	T237
Test name
Test status
Simulation time	46275322943 ps
CPU time	66.77 seconds
Started	Feb 18 02:03:46 PM PST 24
Finished	Feb 18 02:05:06 PM PST 24
Peak memory	200056 kb
Host	smart-d6be39f5-d480-435a-bbc4-6082c819751a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=954022250 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_full.954022250
Directory	/workspace/6.uart_fifo_full/latest

Test location	/workspace/coverage/default/6.uart_fifo_overflow.2432946287
Short name	T356
Test name
Test status
Simulation time	83532457557 ps
CPU time	27.07 seconds
Started	Feb 18 02:03:46 PM PST 24
Finished	Feb 18 02:04:26 PM PST 24
Peak memory	199500 kb
Host	smart-2edf6bbc-2562-4ce3-b11b-dfdc8c255984
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2432946287 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_overflow.2432946287
Directory	/workspace/6.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/6.uart_fifo_reset.4175342576
Short name	T115
Test name
Test status
Simulation time	40037490821 ps
CPU time	28.97 seconds
Started	Feb 18 02:03:44 PM PST 24
Finished	Feb 18 02:04:26 PM PST 24
Peak memory	200036 kb
Host	smart-aff88aab-45ec-43dd-b3ca-055348ff78e8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4175342576 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_reset.4175342576
Directory	/workspace/6.uart_fifo_reset/latest

Test location	/workspace/coverage/default/6.uart_intr.1379823548
Short name	T489
Test name
Test status
Simulation time	633796144 ps
CPU time	1.65 seconds
Started	Feb 18 02:03:48 PM PST 24
Finished	Feb 18 02:04:02 PM PST 24
Peak memory	195184 kb
Host	smart-d6b1dfc0-66d6-472c-858e-395380e72598
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379823548 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_intr.1379823548
Directory	/workspace/6.uart_intr/latest

Test location	/workspace/coverage/default/6.uart_long_xfer_wo_dly.2433134194
Short name	T636
Test name
Test status
Simulation time	39731676669 ps
CPU time	136.69 seconds
Started	Feb 18 02:03:45 PM PST 24
Finished	Feb 18 02:06:15 PM PST 24
Peak memory	200020 kb
Host	smart-7cdef00f-5744-46ae-848c-9d40fd69b65f
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2433134194 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_long_xfer_wo_dly.2433134194
Directory	/workspace/6.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/6.uart_loopback.214884397
Short name	T544
Test name
Test status
Simulation time	6559893788 ps
CPU time	11.59 seconds
Started	Feb 18 02:03:45 PM PST 24
Finished	Feb 18 02:04:10 PM PST 24
Peak memory	198908 kb
Host	smart-4a9e01f1-bfaa-4b68-8eeb-475dbf510157
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=214884397 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_loopback.214884397
Directory	/workspace/6.uart_loopback/latest

Test location	/workspace/coverage/default/6.uart_noise_filter.2641575500
Short name	T857
Test name
Test status
Simulation time	54337271023 ps
CPU time	91.65 seconds
Started	Feb 18 02:03:45 PM PST 24
Finished	Feb 18 02:05:30 PM PST 24
Peak memory	200268 kb
Host	smart-61e53079-2eaa-43c5-a760-f198835e83e3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2641575500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_noise_filter.2641575500
Directory	/workspace/6.uart_noise_filter/latest

Test location	/workspace/coverage/default/6.uart_perf.1567025103
Short name	T1066
Test name
Test status
Simulation time	28070109443 ps
CPU time	372.61 seconds
Started	Feb 18 02:03:49 PM PST 24
Finished	Feb 18 02:10:13 PM PST 24
Peak memory	200100 kb
Host	smart-4ae0578b-f86b-4e28-b46c-74f40dc89b17
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1567025103 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_perf.1567025103
Directory	/workspace/6.uart_perf/latest

Test location	/workspace/coverage/default/6.uart_rx_oversample.1536600823
Short name	T445
Test name
Test status
Simulation time	2649237476 ps
CPU time	4.46 seconds
Started	Feb 18 02:03:47 PM PST 24
Finished	Feb 18 02:04:03 PM PST 24
Peak memory	197888 kb
Host	smart-1cc2d9f7-1f76-469b-9550-550042a85f4a
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1536600823 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_oversample.1536600823
Directory	/workspace/6.uart_rx_oversample/latest

Test location	/workspace/coverage/default/6.uart_rx_parity_err.3761675723
Short name	T833
Test name
Test status
Simulation time	13340745171 ps
CPU time	27.43 seconds
Started	Feb 18 02:03:44 PM PST 24
Finished	Feb 18 02:04:25 PM PST 24
Peak memory	199828 kb
Host	smart-17da2e6d-69d3-4b32-83f6-8e4f70cc858a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3761675723 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_parity_err.3761675723
Directory	/workspace/6.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/6.uart_rx_start_bit_filter.1406820967
Short name	T621
Test name
Test status
Simulation time	1693341989 ps
CPU time	3.3 seconds
Started	Feb 18 02:03:45 PM PST 24
Finished	Feb 18 02:04:02 PM PST 24
Peak memory	195440 kb
Host	smart-6586bf27-dea5-40ee-bd75-678e2c7b7280
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1406820967 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_start_bit_filter.1406820967
Directory	/workspace/6.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/6.uart_smoke.3888897229
Short name	T454
Test name
Test status
Simulation time	320317095 ps
CPU time	0.97 seconds
Started	Feb 18 02:03:49 PM PST 24
Finished	Feb 18 02:04:01 PM PST 24
Peak memory	198100 kb
Host	smart-55287885-613e-45d9-8ce9-c95852339fe5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3888897229 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_smoke.3888897229
Directory	/workspace/6.uart_smoke/latest

Test location	/workspace/coverage/default/6.uart_stress_all.4055010103
Short name	T981
Test name
Test status
Simulation time	571296671120 ps
CPU time	674.88 seconds
Started	Feb 18 02:03:48 PM PST 24
Finished	Feb 18 02:15:15 PM PST 24
Peak memory	200084 kb
Host	smart-d5ba9eb9-5a3a-450c-938b-c6046f004a36
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055010103 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_stress_all.4055010103
Directory	/workspace/6.uart_stress_all/latest

Test location	/workspace/coverage/default/6.uart_stress_all_with_rand_reset.2915734263
Short name	T411
Test name
Test status
Simulation time	42123592599 ps
CPU time	550.22 seconds
Started	Feb 18 02:03:43 PM PST 24
Finished	Feb 18 02:13:07 PM PST 24
Peak memory	224964 kb
Host	smart-a16b935d-a267-4952-ad29-13d4187935a7
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915734263 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 6.uart_stress_all_with_rand_reset.2915734263
Directory	/workspace/6.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/6.uart_tx_ovrd.1418963863
Short name	T610
Test name
Test status
Simulation time	8841229251 ps
CPU time	8.37 seconds
Started	Feb 18 02:03:42 PM PST 24
Finished	Feb 18 02:04:05 PM PST 24
Peak memory	199704 kb
Host	smart-a4a27174-5312-46fc-a9c1-b9c270efe70a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1418963863 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_ovrd.1418963863
Directory	/workspace/6.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/6.uart_tx_rx.4115161734
Short name	T162
Test name
Test status
Simulation time	50327477755 ps
CPU time	18.33 seconds
Started	Feb 18 02:03:56 PM PST 24
Finished	Feb 18 02:04:20 PM PST 24
Peak memory	200040 kb
Host	smart-fbb0d3db-46af-4fc7-be6a-2d75faf3bc53
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4115161734 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_rx.4115161734
Directory	/workspace/6.uart_tx_rx/latest

Test location	/workspace/coverage/default/60.uart_fifo_reset.4044966080
Short name	T287
Test name
Test status
Simulation time	151093366969 ps
CPU time	155.02 seconds
Started	Feb 18 02:06:56 PM PST 24
Finished	Feb 18 02:09:36 PM PST 24
Peak memory	200020 kb
Host	smart-087d779d-736d-47aa-b99a-354a3de23369
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4044966080 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.uart_fifo_reset.4044966080
Directory	/workspace/60.uart_fifo_reset/latest

Test location	/workspace/coverage/default/61.uart_fifo_reset.1201208393
Short name	T189
Test name
Test status
Simulation time	451736563791 ps
CPU time	41.22 seconds
Started	Feb 18 02:06:52 PM PST 24
Finished	Feb 18 02:07:38 PM PST 24
Peak memory	200076 kb
Host	smart-2c2e544a-9a3c-457b-9094-156cb81bee93
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1201208393 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.uart_fifo_reset.1201208393
Directory	/workspace/61.uart_fifo_reset/latest

Test location	/workspace/coverage/default/62.uart_fifo_reset.2454256396
Short name	T616
Test name
Test status
Simulation time	29949711456 ps
CPU time	82.59 seconds
Started	Feb 18 02:07:07 PM PST 24
Finished	Feb 18 02:08:32 PM PST 24
Peak memory	199660 kb
Host	smart-4708bd3d-29e9-4fa4-87fe-4078eb3e6374
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2454256396 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.uart_fifo_reset.2454256396
Directory	/workspace/62.uart_fifo_reset/latest

Test location	/workspace/coverage/default/62.uart_stress_all_with_rand_reset.79442416
Short name	T108
Test name
Test status
Simulation time	38722456923 ps
CPU time	236.89 seconds
Started	Feb 18 02:07:02 PM PST 24
Finished	Feb 18 02:11:02 PM PST 24
Peak memory	216536 kb
Host	smart-2e912615-ad6d-4bbd-abbe-714d712894e8
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79442416 -assert nopostpro c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 62.uart_stress_all_with_rand_reset.79442416
Directory	/workspace/62.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/63.uart_fifo_reset.594827210
Short name	T973
Test name
Test status
Simulation time	31696038782 ps
CPU time	13.64 seconds
Started	Feb 18 02:06:56 PM PST 24
Finished	Feb 18 02:07:14 PM PST 24
Peak memory	199532 kb
Host	smart-5c23c7ba-85f0-45f0-bdfe-5a695a2ef17c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=594827210 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.uart_fifo_reset.594827210
Directory	/workspace/63.uart_fifo_reset/latest

Test location	/workspace/coverage/default/64.uart_fifo_reset.401702109
Short name	T183
Test name
Test status
Simulation time	24385024596 ps
CPU time	40.92 seconds
Started	Feb 18 02:06:53 PM PST 24
Finished	Feb 18 02:07:39 PM PST 24
Peak memory	200012 kb
Host	smart-14e2c9a1-4e69-4e14-b37b-876bb279bb3d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=401702109 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.uart_fifo_reset.401702109
Directory	/workspace/64.uart_fifo_reset/latest

Test location	/workspace/coverage/default/65.uart_fifo_reset.1425075475
Short name	T276
Test name
Test status
Simulation time	9090644294 ps
CPU time	16.68 seconds
Started	Feb 18 02:07:16 PM PST 24
Finished	Feb 18 02:07:33 PM PST 24
Peak memory	200064 kb
Host	smart-8eeae18e-fb39-4fa8-8316-85b5e85ae4e2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1425075475 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.uart_fifo_reset.1425075475
Directory	/workspace/65.uart_fifo_reset/latest

Test location	/workspace/coverage/default/66.uart_fifo_reset.3267577474
Short name	T180
Test name
Test status
Simulation time	49707808606 ps
CPU time	40.12 seconds
Started	Feb 18 02:07:09 PM PST 24
Finished	Feb 18 02:07:51 PM PST 24
Peak memory	199816 kb
Host	smart-77aa3363-6479-4a06-8c3b-45cc2daa4339
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3267577474 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.uart_fifo_reset.3267577474
Directory	/workspace/66.uart_fifo_reset/latest

Test location	/workspace/coverage/default/66.uart_stress_all_with_rand_reset.4212978667
Short name	T494
Test name
Test status
Simulation time	94805483346 ps
CPU time	733.06 seconds
Started	Feb 18 02:07:04 PM PST 24
Finished	Feb 18 02:19:19 PM PST 24
Peak memory	216672 kb
Host	smart-b4bd3e8c-cf0c-4aaa-bbb5-dfca7ec859a1
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212978667 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 66.uart_stress_all_with_rand_reset.4212978667
Directory	/workspace/66.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/67.uart_stress_all_with_rand_reset.602833485
Short name	T173
Test name
Test status
Simulation time	178559880917 ps
CPU time	660.77 seconds
Started	Feb 18 02:07:05 PM PST 24
Finished	Feb 18 02:18:08 PM PST 24
Peak memory	216572 kb
Host	smart-8ad3fe22-fb1e-4660-b3c1-9a042c4af02d
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602833485 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 67.uart_stress_all_with_rand_reset.602833485
Directory	/workspace/67.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/68.uart_fifo_reset.2245824651
Short name	T912
Test name
Test status
Simulation time	96799521058 ps
CPU time	51.61 seconds
Started	Feb 18 02:07:11 PM PST 24
Finished	Feb 18 02:08:04 PM PST 24
Peak memory	200112 kb
Host	smart-503e0e7c-14f5-4f85-b818-c258bc387fcb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2245824651 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.uart_fifo_reset.2245824651
Directory	/workspace/68.uart_fifo_reset/latest

Test location	/workspace/coverage/default/69.uart_fifo_reset.1126037560
Short name	T169
Test name
Test status
Simulation time	3754874367 ps
CPU time	6.6 seconds
Started	Feb 18 02:07:02 PM PST 24
Finished	Feb 18 02:07:11 PM PST 24
Peak memory	199896 kb
Host	smart-3d46e529-3774-4920-9a96-42455c42710a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1126037560 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.uart_fifo_reset.1126037560
Directory	/workspace/69.uart_fifo_reset/latest

Test location	/workspace/coverage/default/69.uart_stress_all_with_rand_reset.2523556415
Short name	T59
Test name
Test status
Simulation time	34388057150 ps
CPU time	350.85 seconds
Started	Feb 18 02:07:11 PM PST 24
Finished	Feb 18 02:13:04 PM PST 24
Peak memory	216464 kb
Host	smart-2dab4640-f931-41df-9004-d45158461748
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523556415 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 69.uart_stress_all_with_rand_reset.2523556415
Directory	/workspace/69.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/7.uart_alert_test.612620318
Short name	T627
Test name
Test status
Simulation time	12118781 ps
CPU time	0.6 seconds
Started	Feb 18 02:03:57 PM PST 24
Finished	Feb 18 02:04:03 PM PST 24
Peak memory	195524 kb
Host	smart-c1463ee8-c0ec-4106-91c0-6ce7b725693c
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612620318 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_alert_test.612620318
Directory	/workspace/7.uart_alert_test/latest

Test location	/workspace/coverage/default/7.uart_fifo_full.908250607
Short name	T507
Test name
Test status
Simulation time	148142291643 ps
CPU time	230.63 seconds
Started	Feb 18 02:03:45 PM PST 24
Finished	Feb 18 02:07:49 PM PST 24
Peak memory	200008 kb
Host	smart-883159ba-2a8d-4c4b-8ce6-24792371b9f6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=908250607 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_full.908250607
Directory	/workspace/7.uart_fifo_full/latest

Test location	/workspace/coverage/default/7.uart_fifo_overflow.2782420659
Short name	T192
Test name
Test status
Simulation time	42042304415 ps
CPU time	37.58 seconds
Started	Feb 18 02:03:50 PM PST 24
Finished	Feb 18 02:04:38 PM PST 24
Peak memory	199872 kb
Host	smart-2148820c-b166-46a0-b330-97672a730f79
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2782420659 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_overflow.2782420659
Directory	/workspace/7.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/7.uart_fifo_reset.4062123293
Short name	T142
Test name
Test status
Simulation time	64418730561 ps
CPU time	11.7 seconds
Started	Feb 18 02:03:44 PM PST 24
Finished	Feb 18 02:04:10 PM PST 24
Peak memory	199184 kb
Host	smart-dcd30233-829b-40fd-97ab-4305bed21698
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4062123293 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_reset.4062123293
Directory	/workspace/7.uart_fifo_reset/latest

Test location	/workspace/coverage/default/7.uart_intr.2844535915
Short name	T685
Test name
Test status
Simulation time	1363453475664 ps
CPU time	1779.12 seconds
Started	Feb 18 02:03:48 PM PST 24
Finished	Feb 18 02:33:39 PM PST 24
Peak memory	199956 kb
Host	smart-e1a15cd5-d6e4-424c-9250-5ec8d57fa75a
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844535915 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_intr.2844535915
Directory	/workspace/7.uart_intr/latest

Test location	/workspace/coverage/default/7.uart_long_xfer_wo_dly.2013835362
Short name	T652
Test name
Test status
Simulation time	25975351072 ps
CPU time	60.63 seconds
Started	Feb 18 02:03:57 PM PST 24
Finished	Feb 18 02:05:03 PM PST 24
Peak memory	200040 kb
Host	smart-a1c822c5-fb56-476e-a73e-e463207d00a8
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2013835362 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_long_xfer_wo_dly.2013835362
Directory	/workspace/7.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/7.uart_loopback.1560337431
Short name	T1069
Test name
Test status
Simulation time	7697535443 ps
CPU time	8.97 seconds
Started	Feb 18 02:04:05 PM PST 24
Finished	Feb 18 02:04:18 PM PST 24
Peak memory	199032 kb
Host	smart-2c7166c4-0904-4b7f-9e6d-d75165681f2d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1560337431 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_loopback.1560337431
Directory	/workspace/7.uart_loopback/latest

Test location	/workspace/coverage/default/7.uart_noise_filter.1892697880
Short name	T673
Test name
Test status
Simulation time	44973137895 ps
CPU time	81.17 seconds
Started	Feb 18 02:03:49 PM PST 24
Finished	Feb 18 02:05:22 PM PST 24
Peak memory	199716 kb
Host	smart-67229d33-73eb-47e4-86e1-447b4d457cb6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1892697880 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_noise_filter.1892697880
Directory	/workspace/7.uart_noise_filter/latest

Test location	/workspace/coverage/default/7.uart_perf.2549109022
Short name	T632
Test name
Test status
Simulation time	20521565745 ps
CPU time	1096.75 seconds
Started	Feb 18 02:03:57 PM PST 24
Finished	Feb 18 02:22:20 PM PST 24
Peak memory	200020 kb
Host	smart-f65349bd-93d6-4558-9af5-ddc5a62a3c6f
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2549109022 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_perf.2549109022
Directory	/workspace/7.uart_perf/latest

Test location	/workspace/coverage/default/7.uart_rx_parity_err.1358692970
Short name	T551
Test name
Test status
Simulation time	144223671069 ps
CPU time	233.65 seconds
Started	Feb 18 02:03:46 PM PST 24
Finished	Feb 18 02:07:52 PM PST 24
Peak memory	199812 kb
Host	smart-e2a762e6-d0c7-4caf-991a-91e78d9c1218
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1358692970 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_parity_err.1358692970
Directory	/workspace/7.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/7.uart_rx_start_bit_filter.4173093662
Short name	T408
Test name
Test status
Simulation time	2440361513 ps
CPU time	3.5 seconds
Started	Feb 18 02:03:50 PM PST 24
Finished	Feb 18 02:04:04 PM PST 24
Peak memory	195516 kb
Host	smart-64ce90d0-8374-493d-a39b-f5986877290c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4173093662 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_start_bit_filter.4173093662
Directory	/workspace/7.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/7.uart_smoke.1332338256
Short name	T1003
Test name
Test status
Simulation time	444711099 ps
CPU time	1.52 seconds
Started	Feb 18 02:03:48 PM PST 24
Finished	Feb 18 02:04:01 PM PST 24
Peak memory	198976 kb
Host	smart-8c64c487-2c77-400a-b53d-98b04d86436a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1332338256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_smoke.1332338256
Directory	/workspace/7.uart_smoke/latest

Test location	/workspace/coverage/default/7.uart_stress_all.3965752033
Short name	T104
Test name
Test status
Simulation time	254967774168 ps
CPU time	266.59 seconds
Started	Feb 18 02:04:06 PM PST 24
Finished	Feb 18 02:08:37 PM PST 24
Peak memory	200044 kb
Host	smart-85fa9b40-02a6-44e3-9c55-09c5ebd48918
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965752033 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_stress_all.3965752033
Directory	/workspace/7.uart_stress_all/latest

Test location	/workspace/coverage/default/7.uart_tx_ovrd.1387295881
Short name	T1072
Test name
Test status
Simulation time	1360650728 ps
CPU time	1.55 seconds
Started	Feb 18 02:03:44 PM PST 24
Finished	Feb 18 02:03:59 PM PST 24
Peak memory	198160 kb
Host	smart-4cee3f65-37aa-4372-bed3-c573cbe4b0a0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1387295881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_ovrd.1387295881
Directory	/workspace/7.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/7.uart_tx_rx.2682110371
Short name	T453
Test name
Test status
Simulation time	2825562396 ps
CPU time	5.29 seconds
Started	Feb 18 02:03:50 PM PST 24
Finished	Feb 18 02:04:05 PM PST 24
Peak memory	196956 kb
Host	smart-aced880c-5794-4f8e-8d3f-34bfdcb786bf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2682110371 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_rx.2682110371
Directory	/workspace/7.uart_tx_rx/latest

Test location	/workspace/coverage/default/70.uart_fifo_reset.1617440058
Short name	T559
Test name
Test status
Simulation time	149058669850 ps
CPU time	38.65 seconds
Started	Feb 18 02:07:11 PM PST 24
Finished	Feb 18 02:07:51 PM PST 24
Peak memory	200036 kb
Host	smart-0173df5c-db91-46ff-a128-fcaafdd7e0a1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1617440058 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.uart_fifo_reset.1617440058
Directory	/workspace/70.uart_fifo_reset/latest

Test location	/workspace/coverage/default/71.uart_fifo_reset.3001892584
Short name	T127
Test name
Test status
Simulation time	25182247331 ps
CPU time	38.33 seconds
Started	Feb 18 02:07:13 PM PST 24
Finished	Feb 18 02:07:53 PM PST 24
Peak memory	200060 kb
Host	smart-febbb075-8461-4dcf-93b9-2ead5d26da51
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3001892584 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.uart_fifo_reset.3001892584
Directory	/workspace/71.uart_fifo_reset/latest

Test location	/workspace/coverage/default/71.uart_stress_all_with_rand_reset.1878000708
Short name	T251
Test name
Test status
Simulation time	208554543942 ps
CPU time	593.52 seconds
Started	Feb 18 02:07:06 PM PST 24
Finished	Feb 18 02:17:01 PM PST 24
Peak memory	224976 kb
Host	smart-4ebab136-79a8-461a-8583-fe94808e5965
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878000708 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 71.uart_stress_all_with_rand_reset.1878000708
Directory	/workspace/71.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/72.uart_fifo_reset.2452249508
Short name	T1106
Test name
Test status
Simulation time	24183860669 ps
CPU time	39.36 seconds
Started	Feb 18 02:07:09 PM PST 24
Finished	Feb 18 02:07:50 PM PST 24
Peak memory	199412 kb
Host	smart-bb85f74a-8521-471c-bde3-27629bcb17a7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2452249508 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.uart_fifo_reset.2452249508
Directory	/workspace/72.uart_fifo_reset/latest

Test location	/workspace/coverage/default/72.uart_stress_all_with_rand_reset.957228140
Short name	T945
Test name
Test status
Simulation time	138967826985 ps
CPU time	461.5 seconds
Started	Feb 18 02:07:03 PM PST 24
Finished	Feb 18 02:14:47 PM PST 24
Peak memory	208440 kb
Host	smart-8fc70005-fa11-4754-8b3b-f748897ad45f
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957228140 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 72.uart_stress_all_with_rand_reset.957228140
Directory	/workspace/72.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/73.uart_fifo_reset.3436141170
Short name	T635
Test name
Test status
Simulation time	48235576779 ps
CPU time	36.58 seconds
Started	Feb 18 02:07:10 PM PST 24
Finished	Feb 18 02:07:48 PM PST 24
Peak memory	199408 kb
Host	smart-76999b12-01f3-4acc-a34b-2c3b5ad45ec2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3436141170 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.uart_fifo_reset.3436141170
Directory	/workspace/73.uart_fifo_reset/latest

Test location	/workspace/coverage/default/73.uart_stress_all_with_rand_reset.2005309831
Short name	T877
Test name
Test status
Simulation time	203641361742 ps
CPU time	872.12 seconds
Started	Feb 18 02:07:03 PM PST 24
Finished	Feb 18 02:21:38 PM PST 24
Peak memory	225044 kb
Host	smart-28cc5afa-8a07-4bb5-897d-484bd0112dc5
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005309831 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 73.uart_stress_all_with_rand_reset.2005309831
Directory	/workspace/73.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/74.uart_fifo_reset.1769699779
Short name	T144
Test name
Test status
Simulation time	29705434653 ps
CPU time	45.7 seconds
Started	Feb 18 02:07:11 PM PST 24
Finished	Feb 18 02:07:59 PM PST 24
Peak memory	200024 kb
Host	smart-78738509-73c3-4dbc-a434-d5d7570fd076
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1769699779 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.uart_fifo_reset.1769699779
Directory	/workspace/74.uart_fifo_reset/latest

Test location	/workspace/coverage/default/74.uart_stress_all_with_rand_reset.3318269638
Short name	T649
Test name
Test status
Simulation time	24767082151 ps
CPU time	281.02 seconds
Started	Feb 18 02:07:11 PM PST 24
Finished	Feb 18 02:11:54 PM PST 24
Peak memory	208408 kb
Host	smart-8e0ffa3b-5b50-4b01-8056-90491360616f
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318269638 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 74.uart_stress_all_with_rand_reset.3318269638
Directory	/workspace/74.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/75.uart_fifo_reset.4189701013
Short name	T109
Test name
Test status
Simulation time	17173252458 ps
CPU time	13.43 seconds
Started	Feb 18 02:07:03 PM PST 24
Finished	Feb 18 02:07:19 PM PST 24
Peak memory	199268 kb
Host	smart-210b9384-cfb9-4dcc-a23b-a5622d7a02e1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4189701013 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.uart_fifo_reset.4189701013
Directory	/workspace/75.uart_fifo_reset/latest

Test location	/workspace/coverage/default/76.uart_fifo_reset.4089468060
Short name	T210
Test name
Test status
Simulation time	88593124487 ps
CPU time	49.42 seconds
Started	Feb 18 02:07:07 PM PST 24
Finished	Feb 18 02:07:59 PM PST 24
Peak memory	199948 kb
Host	smart-b6b34c50-f060-493c-b53b-fba5f478ceeb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4089468060 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.uart_fifo_reset.4089468060
Directory	/workspace/76.uart_fifo_reset/latest

Test location	/workspace/coverage/default/76.uart_stress_all_with_rand_reset.3103994158
Short name	T58
Test name
Test status
Simulation time	103968047186 ps
CPU time	256.03 seconds
Started	Feb 18 02:07:07 PM PST 24
Finished	Feb 18 02:11:25 PM PST 24
Peak memory	213732 kb
Host	smart-47f4263e-69ef-472b-b4cf-b0fcc268d037
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103994158 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 76.uart_stress_all_with_rand_reset.3103994158
Directory	/workspace/76.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/77.uart_fifo_reset.3816586329
Short name	T201
Test name
Test status
Simulation time	86687400529 ps
CPU time	120.56 seconds
Started	Feb 18 02:07:12 PM PST 24
Finished	Feb 18 02:09:14 PM PST 24
Peak memory	199836 kb
Host	smart-bdf06235-9c53-461a-bde4-fda3e6fb6e18
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3816586329 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.uart_fifo_reset.3816586329
Directory	/workspace/77.uart_fifo_reset/latest

Test location	/workspace/coverage/default/77.uart_stress_all_with_rand_reset.1645029200
Short name	T1010
Test name
Test status
Simulation time	54900063173 ps
CPU time	724.84 seconds
Started	Feb 18 02:07:13 PM PST 24
Finished	Feb 18 02:19:20 PM PST 24
Peak memory	224616 kb
Host	smart-733f1ff7-ee3f-434b-b166-26fa7b1e15d4
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645029200 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 77.uart_stress_all_with_rand_reset.1645029200
Directory	/workspace/77.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/78.uart_fifo_reset.2189866681
Short name	T238
Test name
Test status
Simulation time	17522700123 ps
CPU time	15.71 seconds
Started	Feb 18 02:07:11 PM PST 24
Finished	Feb 18 02:07:28 PM PST 24
Peak memory	199516 kb
Host	smart-a731a607-ac66-4845-9ecc-87a6d422119b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2189866681 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.uart_fifo_reset.2189866681
Directory	/workspace/78.uart_fifo_reset/latest

Test location	/workspace/coverage/default/79.uart_stress_all_with_rand_reset.2795083120
Short name	T61
Test name
Test status
Simulation time	26142616443 ps
CPU time	296.16 seconds
Started	Feb 18 02:07:08 PM PST 24
Finished	Feb 18 02:12:06 PM PST 24
Peak memory	216516 kb
Host	smart-079233ef-1190-4c8d-b7ce-d15542e48349
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795083120 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 79.uart_stress_all_with_rand_reset.2795083120
Directory	/workspace/79.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/8.uart_alert_test.2356399599
Short name	T535
Test name
Test status
Simulation time	105567916 ps
CPU time	0.53 seconds
Started	Feb 18 02:03:59 PM PST 24
Finished	Feb 18 02:04:06 PM PST 24
Peak memory	194488 kb
Host	smart-868420e1-5359-4ace-b1e3-0afc6116da59
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356399599 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_alert_test.2356399599
Directory	/workspace/8.uart_alert_test/latest

Test location	/workspace/coverage/default/8.uart_fifo_full.1861428680
Short name	T658
Test name
Test status
Simulation time	33050365111 ps
CPU time	56 seconds
Started	Feb 18 02:03:55 PM PST 24
Finished	Feb 18 02:04:58 PM PST 24
Peak memory	200004 kb
Host	smart-c5a9da26-0c8d-483f-a759-89a81cb5b0a6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1861428680 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_full.1861428680
Directory	/workspace/8.uart_fifo_full/latest

Test location	/workspace/coverage/default/8.uart_fifo_overflow.308024440
Short name	T343
Test name
Test status
Simulation time	74900357268 ps
CPU time	114.02 seconds
Started	Feb 18 02:03:57 PM PST 24
Finished	Feb 18 02:05:57 PM PST 24
Peak memory	200016 kb
Host	smart-e808d488-3ff1-403e-975f-87a1a136a526
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=308024440 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_overflow.308024440
Directory	/workspace/8.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/8.uart_fifo_reset.3177967677
Short name	T902
Test name
Test status
Simulation time	32565091123 ps
CPU time	32.83 seconds
Started	Feb 18 02:04:06 PM PST 24
Finished	Feb 18 02:04:43 PM PST 24
Peak memory	200108 kb
Host	smart-5841276f-544c-4629-8dac-c796264b4a12
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3177967677 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_reset.3177967677
Directory	/workspace/8.uart_fifo_reset/latest

Test location	/workspace/coverage/default/8.uart_intr.2764689908
Short name	T580
Test name
Test status
Simulation time	16480329771 ps
CPU time	36.77 seconds
Started	Feb 18 02:03:59 PM PST 24
Finished	Feb 18 02:04:42 PM PST 24
Peak memory	199432 kb
Host	smart-49361d43-3fe9-4aa3-a5c7-ceaa282e5fdf
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764689908 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_intr.2764689908
Directory	/workspace/8.uart_intr/latest

Test location	/workspace/coverage/default/8.uart_long_xfer_wo_dly.2829910407
Short name	T818
Test name
Test status
Simulation time	113692753343 ps
CPU time	330.2 seconds
Started	Feb 18 02:03:58 PM PST 24
Finished	Feb 18 02:09:34 PM PST 24
Peak memory	200028 kb
Host	smart-836f8776-2292-470d-8730-98fc400b72ff
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2829910407 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_long_xfer_wo_dly.2829910407
Directory	/workspace/8.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/8.uart_loopback.3788015816
Short name	T892
Test name
Test status
Simulation time	5121546608 ps
CPU time	10.71 seconds
Started	Feb 18 02:03:57 PM PST 24
Finished	Feb 18 02:04:13 PM PST 24
Peak memory	198176 kb
Host	smart-1e8332d6-b570-4281-b0fa-aaff8f2846ce
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3788015816 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_loopback.3788015816
Directory	/workspace/8.uart_loopback/latest

Test location	/workspace/coverage/default/8.uart_noise_filter.2698905979
Short name	T391
Test name
Test status
Simulation time	169647629602 ps
CPU time	303.78 seconds
Started	Feb 18 02:03:54 PM PST 24
Finished	Feb 18 02:09:05 PM PST 24
Peak memory	200056 kb
Host	smart-1a740d9a-3296-48a0-aa73-d8ee7e07a412
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2698905979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_noise_filter.2698905979
Directory	/workspace/8.uart_noise_filter/latest

Test location	/workspace/coverage/default/8.uart_perf.2231400507
Short name	T476
Test name
Test status
Simulation time	10972805853 ps
CPU time	613.71 seconds
Started	Feb 18 02:04:03 PM PST 24
Finished	Feb 18 02:14:22 PM PST 24
Peak memory	200052 kb
Host	smart-8990eb37-5677-4f6f-982d-b4c73ec1d565
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2231400507 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_perf.2231400507
Directory	/workspace/8.uart_perf/latest

Test location	/workspace/coverage/default/8.uart_rx_parity_err.1822694197
Short name	T467
Test name
Test status
Simulation time	38075422676 ps
CPU time	26.85 seconds
Started	Feb 18 02:03:55 PM PST 24
Finished	Feb 18 02:04:28 PM PST 24
Peak memory	199680 kb
Host	smart-e024ac89-0cf2-4c6c-bde5-7b3078525d57
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1822694197 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_parity_err.1822694197
Directory	/workspace/8.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/8.uart_rx_start_bit_filter.3337407935
Short name	T1110
Test name
Test status
Simulation time	1918568862 ps
CPU time	1.81 seconds
Started	Feb 18 02:03:59 PM PST 24
Finished	Feb 18 02:04:07 PM PST 24
Peak memory	195428 kb
Host	smart-21c2eba3-9218-42b2-9078-2c41cbf04248
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3337407935 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_start_bit_filter.3337407935
Directory	/workspace/8.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/8.uart_smoke.3829735408
Short name	T814
Test name
Test status
Simulation time	482021865 ps
CPU time	1.28 seconds
Started	Feb 18 02:03:58 PM PST 24
Finished	Feb 18 02:04:06 PM PST 24
Peak memory	198360 kb
Host	smart-a5344b6b-aa15-4aa8-a39a-828125643798
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3829735408 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_smoke.3829735408
Directory	/workspace/8.uart_smoke/latest

Test location	/workspace/coverage/default/8.uart_stress_all.3843641559
Short name	T437
Test name
Test status
Simulation time	140135504013 ps
CPU time	471.42 seconds
Started	Feb 18 02:03:59 PM PST 24
Finished	Feb 18 02:11:57 PM PST 24
Peak memory	200216 kb
Host	smart-335460ea-9c09-4bb0-89f3-1badd3f368db
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843641559 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_stress_all.3843641559
Directory	/workspace/8.uart_stress_all/latest

Test location	/workspace/coverage/default/8.uart_stress_all_with_rand_reset.3257445435
Short name	T57
Test name
Test status
Simulation time	92148539261 ps
CPU time	492.36 seconds
Started	Feb 18 02:03:58 PM PST 24
Finished	Feb 18 02:12:16 PM PST 24
Peak memory	216760 kb
Host	smart-7cd4ee30-b6b4-4362-a12d-dff71d4d848a
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257445435 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 8.uart_stress_all_with_rand_reset.3257445435
Directory	/workspace/8.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/8.uart_tx_ovrd.3219216135
Short name	T684
Test name
Test status
Simulation time	770693737 ps
CPU time	2.19 seconds
Started	Feb 18 02:03:55 PM PST 24
Finished	Feb 18 02:04:04 PM PST 24
Peak memory	199096 kb
Host	smart-53a16c37-c5f3-4115-8a62-a81cc961ce44
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3219216135 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_ovrd.3219216135
Directory	/workspace/8.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/8.uart_tx_rx.2090177505
Short name	T1039
Test name
Test status
Simulation time	52398154371 ps
CPU time	105.02 seconds
Started	Feb 18 02:03:56 PM PST 24
Finished	Feb 18 02:05:47 PM PST 24
Peak memory	200052 kb
Host	smart-3d75813a-5dbe-4023-a07e-ad269af71e1b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2090177505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_rx.2090177505
Directory	/workspace/8.uart_tx_rx/latest

Test location	/workspace/coverage/default/81.uart_fifo_reset.3638049634
Short name	T268
Test name
Test status
Simulation time	102668705152 ps
CPU time	25.15 seconds
Started	Feb 18 02:07:15 PM PST 24
Finished	Feb 18 02:07:41 PM PST 24
Peak memory	199984 kb
Host	smart-36c4cdc3-b31c-4cef-bf7f-748179e78c95
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3638049634 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.uart_fifo_reset.3638049634
Directory	/workspace/81.uart_fifo_reset/latest

Test location	/workspace/coverage/default/81.uart_stress_all_with_rand_reset.420965563
Short name	T39
Test name
Test status
Simulation time	18303106484 ps
CPU time	196.31 seconds
Started	Feb 18 02:07:08 PM PST 24
Finished	Feb 18 02:10:26 PM PST 24
Peak memory	215700 kb
Host	smart-cf35fe42-b663-4eed-a1b0-5ac5e71a9ee3
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420965563 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 81.uart_stress_all_with_rand_reset.420965563
Directory	/workspace/81.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/82.uart_fifo_reset.2606402567
Short name	T194
Test name
Test status
Simulation time	71857872047 ps
CPU time	105.54 seconds
Started	Feb 18 02:07:06 PM PST 24
Finished	Feb 18 02:08:53 PM PST 24
Peak memory	200044 kb
Host	smart-24597747-a30f-4710-a63f-0763ab9c2fa3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2606402567 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.uart_fifo_reset.2606402567
Directory	/workspace/82.uart_fifo_reset/latest

Test location	/workspace/coverage/default/82.uart_stress_all_with_rand_reset.33083843
Short name	T218
Test name
Test status
Simulation time	140666140256 ps
CPU time	966.89 seconds
Started	Feb 18 02:07:07 PM PST 24
Finished	Feb 18 02:23:15 PM PST 24
Peak memory	211728 kb
Host	smart-42d53c23-2fe3-4093-991a-7ec9300290b5
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33083843 -assert nopostpro c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 82.uart_stress_all_with_rand_reset.33083843
Directory	/workspace/82.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/83.uart_fifo_reset.2095527426
Short name	T182
Test name
Test status
Simulation time	200901437545 ps
CPU time	25.18 seconds
Started	Feb 18 02:07:08 PM PST 24
Finished	Feb 18 02:07:34 PM PST 24
Peak memory	199944 kb
Host	smart-6e9e9e6e-e690-4788-9df8-422d202c691b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2095527426 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.uart_fifo_reset.2095527426
Directory	/workspace/83.uart_fifo_reset/latest

Test location	/workspace/coverage/default/84.uart_fifo_reset.2598517654
Short name	T117
Test name
Test status
Simulation time	17006458633 ps
CPU time	28.04 seconds
Started	Feb 18 02:07:21 PM PST 24
Finished	Feb 18 02:07:52 PM PST 24
Peak memory	200016 kb
Host	smart-12f07844-d08d-4c2f-9ff7-cb68a99b3aac
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2598517654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.uart_fifo_reset.2598517654
Directory	/workspace/84.uart_fifo_reset/latest

Test location	/workspace/coverage/default/85.uart_fifo_reset.1729055455
Short name	T157
Test name
Test status
Simulation time	8442227798 ps
CPU time	8.48 seconds
Started	Feb 18 02:07:15 PM PST 24
Finished	Feb 18 02:07:25 PM PST 24
Peak memory	197396 kb
Host	smart-137e190f-ddbf-4e48-bc02-5aae34177aa3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1729055455 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.uart_fifo_reset.1729055455
Directory	/workspace/85.uart_fifo_reset/latest

Test location	/workspace/coverage/default/86.uart_fifo_reset.1537522838
Short name	T151
Test name
Test status
Simulation time	61776440311 ps
CPU time	44.03 seconds
Started	Feb 18 02:07:15 PM PST 24
Finished	Feb 18 02:08:00 PM PST 24
Peak memory	200036 kb
Host	smart-512e4368-931a-436d-a364-406ec06fb196
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1537522838 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.uart_fifo_reset.1537522838
Directory	/workspace/86.uart_fifo_reset/latest

Test location	/workspace/coverage/default/87.uart_fifo_reset.2708318920
Short name	T4
Test name
Test status
Simulation time	65977793893 ps
CPU time	19 seconds
Started	Feb 18 02:07:15 PM PST 24
Finished	Feb 18 02:07:35 PM PST 24
Peak memory	200040 kb
Host	smart-eeeecd3b-b1af-4250-972f-703b8cc8361c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2708318920 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.uart_fifo_reset.2708318920
Directory	/workspace/87.uart_fifo_reset/latest

Test location	/workspace/coverage/default/88.uart_fifo_reset.2955070595
Short name	T234
Test name
Test status
Simulation time	23078281333 ps
CPU time	34.19 seconds
Started	Feb 18 02:07:12 PM PST 24
Finished	Feb 18 02:07:48 PM PST 24
Peak memory	199324 kb
Host	smart-42336f2b-6471-4b78-832c-03e2f1e4040a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2955070595 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.uart_fifo_reset.2955070595
Directory	/workspace/88.uart_fifo_reset/latest

Test location	/workspace/coverage/default/89.uart_fifo_reset.2303896829
Short name	T113
Test name
Test status
Simulation time	130768223806 ps
CPU time	209.21 seconds
Started	Feb 18 02:07:24 PM PST 24
Finished	Feb 18 02:10:56 PM PST 24
Peak memory	200028 kb
Host	smart-1a39b294-7ce9-4b2a-9614-2721c14fc75e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2303896829 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.uart_fifo_reset.2303896829
Directory	/workspace/89.uart_fifo_reset/latest

Test location	/workspace/coverage/default/89.uart_stress_all_with_rand_reset.797704713
Short name	T216
Test name
Test status
Simulation time	72475752863 ps
CPU time	209.77 seconds
Started	Feb 18 02:07:19 PM PST 24
Finished	Feb 18 02:10:50 PM PST 24
Peak memory	216532 kb
Host	smart-6f18daa2-19f3-4804-8b3e-79cf81d9fb59
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797704713 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 89.uart_stress_all_with_rand_reset.797704713
Directory	/workspace/89.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/9.uart_alert_test.513355351
Short name	T795
Test name
Test status
Simulation time	13431705 ps
CPU time	0.61 seconds
Started	Feb 18 02:03:57 PM PST 24
Finished	Feb 18 02:04:03 PM PST 24
Peak memory	195500 kb
Host	smart-1b233503-d5d9-4d2f-add9-320442a79563
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513355351 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_alert_test.513355351
Directory	/workspace/9.uart_alert_test/latest

Test location	/workspace/coverage/default/9.uart_fifo_full.352964204
Short name	T480
Test name
Test status
Simulation time	10240553303 ps
CPU time	9.19 seconds
Started	Feb 18 02:03:55 PM PST 24
Finished	Feb 18 02:04:11 PM PST 24
Peak memory	199992 kb
Host	smart-81a380f8-100f-4fe9-8cff-4a6005a7c3a6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=352964204 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_full.352964204
Directory	/workspace/9.uart_fifo_full/latest

Test location	/workspace/coverage/default/9.uart_fifo_overflow.3005720951
Short name	T217
Test name
Test status
Simulation time	128539328469 ps
CPU time	50.09 seconds
Started	Feb 18 02:03:58 PM PST 24
Finished	Feb 18 02:04:54 PM PST 24
Peak memory	199860 kb
Host	smart-03489bb0-1e1a-4bee-a0e9-937ff9c75772
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3005720951 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_overflow.3005720951
Directory	/workspace/9.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/9.uart_fifo_reset.546312262
Short name	T274
Test name
Test status
Simulation time	106461023255 ps
CPU time	118.71 seconds
Started	Feb 18 02:03:59 PM PST 24
Finished	Feb 18 02:06:04 PM PST 24
Peak memory	200036 kb
Host	smart-3625faf2-cc8f-4f9c-b080-f95c8a208590
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=546312262 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_reset.546312262
Directory	/workspace/9.uart_fifo_reset/latest

Test location	/workspace/coverage/default/9.uart_intr.2405371528
Short name	T526
Test name
Test status
Simulation time	802748429003 ps
CPU time	680.61 seconds
Started	Feb 18 02:04:03 PM PST 24
Finished	Feb 18 02:15:29 PM PST 24
Peak memory	199968 kb
Host	smart-366e7441-ab1d-4d1d-b9cf-db9affbad38e
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405371528 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_intr.2405371528
Directory	/workspace/9.uart_intr/latest

Test location	/workspace/coverage/default/9.uart_long_xfer_wo_dly.3556466873
Short name	T528
Test name
Test status
Simulation time	182927922448 ps
CPU time	349.99 seconds
Started	Feb 18 02:04:02 PM PST 24
Finished	Feb 18 02:09:58 PM PST 24
Peak memory	199988 kb
Host	smart-31dbcbfb-7017-42d6-b42a-c1b66cf1aaf9
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3556466873 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_long_xfer_wo_dly.3556466873
Directory	/workspace/9.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/9.uart_loopback.2984609679
Short name	T659
Test name
Test status
Simulation time	4368683165 ps
CPU time	9.73 seconds
Started	Feb 18 02:04:01 PM PST 24
Finished	Feb 18 02:04:16 PM PST 24
Peak memory	199956 kb
Host	smart-a23fcd6e-440f-450f-b762-b9a1c29cc5c3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2984609679 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_loopback.2984609679
Directory	/workspace/9.uart_loopback/latest

Test location	/workspace/coverage/default/9.uart_noise_filter.996203209
Short name	T1121
Test name
Test status
Simulation time	16852504785 ps
CPU time	28.62 seconds
Started	Feb 18 02:03:54 PM PST 24
Finished	Feb 18 02:04:30 PM PST 24
Peak memory	196996 kb
Host	smart-d17a9def-e020-440c-afb1-a408977032bc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=996203209 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_noise_filter.996203209
Directory	/workspace/9.uart_noise_filter/latest

Test location	/workspace/coverage/default/9.uart_perf.3894136769
Short name	T597
Test name
Test status
Simulation time	26898523998 ps
CPU time	331.54 seconds
Started	Feb 18 02:03:59 PM PST 24
Finished	Feb 18 02:09:37 PM PST 24
Peak memory	200016 kb
Host	smart-5ab4c486-6eae-416b-af8a-e734dcde9cab
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3894136769 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_perf.3894136769
Directory	/workspace/9.uart_perf/latest

Test location	/workspace/coverage/default/9.uart_rx_start_bit_filter.1433193895
Short name	T1021
Test name
Test status
Simulation time	6275994340 ps
CPU time	5.5 seconds
Started	Feb 18 02:03:59 PM PST 24
Finished	Feb 18 02:04:10 PM PST 24
Peak memory	195228 kb
Host	smart-9da84d50-652f-45df-9398-a83954de4750
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1433193895 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_start_bit_filter.1433193895
Directory	/workspace/9.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/9.uart_smoke.187028519
Short name	T917
Test name
Test status
Simulation time	267359811 ps
CPU time	1.84 seconds
Started	Feb 18 02:03:55 PM PST 24
Finished	Feb 18 02:04:04 PM PST 24
Peak memory	198352 kb
Host	smart-dd8501b1-9b4c-4f29-8dee-5fd4a6ab11bc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=187028519 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_smoke.187028519
Directory	/workspace/9.uart_smoke/latest

Test location	/workspace/coverage/default/9.uart_stress_all.3651657747
Short name	T709
Test name
Test status
Simulation time	1252072813915 ps
CPU time	655.48 seconds
Started	Feb 18 02:03:56 PM PST 24
Finished	Feb 18 02:14:58 PM PST 24
Peak memory	200064 kb
Host	smart-58f00f57-e047-4184-9937-6c84e2e9abf1
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651657747 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_stress_all.3651657747
Directory	/workspace/9.uart_stress_all/latest

Test location	/workspace/coverage/default/9.uart_stress_all_with_rand_reset.2794525413
Short name	T62
Test name
Test status
Simulation time	177015215465 ps
CPU time	540.72 seconds
Started	Feb 18 02:04:00 PM PST 24
Finished	Feb 18 02:13:07 PM PST 24
Peak memory	216616 kb
Host	smart-6b553e6f-0f9c-40ea-81a4-0d312303a475
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794525413 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 9.uart_stress_all_with_rand_reset.2794525413
Directory	/workspace/9.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/9.uart_tx_ovrd.2995457463
Short name	T27
Test name
Test status
Simulation time	2718497376 ps
CPU time	2.32 seconds
Started	Feb 18 02:03:58 PM PST 24
Finished	Feb 18 02:04:07 PM PST 24
Peak memory	198416 kb
Host	smart-68109b88-857d-4806-a473-26a91b13023e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2995457463 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_ovrd.2995457463
Directory	/workspace/9.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/9.uart_tx_rx.2099970941
Short name	T798
Test name
Test status
Simulation time	28678288698 ps
CPU time	47.88 seconds
Started	Feb 18 02:03:58 PM PST 24
Finished	Feb 18 02:04:52 PM PST 24
Peak memory	200128 kb
Host	smart-4921592d-5d8a-4a5d-b583-824698128e46
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2099970941 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_rx.2099970941
Directory	/workspace/9.uart_tx_rx/latest

Test location	/workspace/coverage/default/90.uart_fifo_reset.1229227226
Short name	T771
Test name
Test status
Simulation time	117231143210 ps
CPU time	91.33 seconds
Started	Feb 18 02:07:12 PM PST 24
Finished	Feb 18 02:08:45 PM PST 24
Peak memory	200112 kb
Host	smart-95a78ef5-f22a-4f99-9704-a0daa647d802
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1229227226 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.uart_fifo_reset.1229227226
Directory	/workspace/90.uart_fifo_reset/latest

Test location	/workspace/coverage/default/92.uart_fifo_reset.204098731
Short name	T241
Test name
Test status
Simulation time	22224929322 ps
CPU time	41.85 seconds
Started	Feb 18 02:07:17 PM PST 24
Finished	Feb 18 02:08:01 PM PST 24
Peak memory	199992 kb
Host	smart-760edd05-6ea6-414b-869d-f2e99ca989e4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=204098731 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.uart_fifo_reset.204098731
Directory	/workspace/92.uart_fifo_reset/latest

Test location	/workspace/coverage/default/92.uart_stress_all_with_rand_reset.3327997169
Short name	T1097
Test name
Test status
Simulation time	113209652876 ps
CPU time	330.35 seconds
Started	Feb 18 02:07:17 PM PST 24
Finished	Feb 18 02:12:49 PM PST 24
Peak memory	208372 kb
Host	smart-2e83b65e-b606-4c5c-ad00-2942837252f2
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327997169 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 92.uart_stress_all_with_rand_reset.3327997169
Directory	/workspace/92.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/93.uart_fifo_reset.4078617326
Short name	T1043
Test name
Test status
Simulation time	32916239461 ps
CPU time	38.39 seconds
Started	Feb 18 02:07:26 PM PST 24
Finished	Feb 18 02:08:06 PM PST 24
Peak memory	200016 kb
Host	smart-876ff2a8-affd-4f54-a880-c0a9c4147cbf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4078617326 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.uart_fifo_reset.4078617326
Directory	/workspace/93.uart_fifo_reset/latest

Test location	/workspace/coverage/default/94.uart_fifo_reset.2968818045
Short name	T294
Test name
Test status
Simulation time	81568191501 ps
CPU time	35.37 seconds
Started	Feb 18 02:07:21 PM PST 24
Finished	Feb 18 02:08:00 PM PST 24
Peak memory	200120 kb
Host	smart-a17aac7d-621b-44ad-806a-e5a36ca86073
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2968818045 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.uart_fifo_reset.2968818045
Directory	/workspace/94.uart_fifo_reset/latest

Test location	/workspace/coverage/default/94.uart_stress_all_with_rand_reset.2459936804
Short name	T832
Test name
Test status
Simulation time	290240229941 ps
CPU time	399.95 seconds
Started	Feb 18 02:07:20 PM PST 24
Finished	Feb 18 02:14:03 PM PST 24
Peak memory	216708 kb
Host	smart-ea709a9a-7dfd-41cc-9a76-17cca9e09356
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459936804 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 94.uart_stress_all_with_rand_reset.2459936804
Directory	/workspace/94.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/95.uart_fifo_reset.29909844
Short name	T850
Test name
Test status
Simulation time	13062998472 ps
CPU time	16.7 seconds
Started	Feb 18 02:07:17 PM PST 24
Finished	Feb 18 02:07:35 PM PST 24
Peak memory	200064 kb
Host	smart-7cd67c25-5e56-420e-b7c6-0e1bfefeb5ab
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=29909844 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.uart_fifo_reset.29909844
Directory	/workspace/95.uart_fifo_reset/latest

Test location	/workspace/coverage/default/95.uart_stress_all_with_rand_reset.3968747718
Short name	T97
Test name
Test status
Simulation time	54432675505 ps
CPU time	564.8 seconds
Started	Feb 18 02:07:21 PM PST 24
Finished	Feb 18 02:16:49 PM PST 24
Peak memory	216604 kb
Host	smart-9267a043-ee1f-4f90-b43f-365ce1d4bc85
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968747718 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 95.uart_stress_all_with_rand_reset.3968747718
Directory	/workspace/95.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/96.uart_fifo_reset.1986241982
Short name	T265
Test name
Test status
Simulation time	61729430676 ps
CPU time	27.61 seconds
Started	Feb 18 02:07:22 PM PST 24
Finished	Feb 18 02:07:53 PM PST 24
Peak memory	200100 kb
Host	smart-64e92d15-6935-4ce7-ad27-cc1d9853952d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1986241982 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.uart_fifo_reset.1986241982
Directory	/workspace/96.uart_fifo_reset/latest

Test location	/workspace/coverage/default/97.uart_fifo_reset.3898349553
Short name	T497
Test name
Test status
Simulation time	173262002954 ps
CPU time	20.82 seconds
Started	Feb 18 02:07:19 PM PST 24
Finished	Feb 18 02:07:42 PM PST 24
Peak memory	199904 kb
Host	smart-565227d7-1a50-47a9-b44b-acc8564e0c99
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3898349553 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.uart_fifo_reset.3898349553
Directory	/workspace/97.uart_fifo_reset/latest

Test location	/workspace/coverage/default/97.uart_stress_all_with_rand_reset.3849998062
Short name	T40
Test name
Test status
Simulation time	46262371492 ps
CPU time	540.76 seconds
Started	Feb 18 02:07:24 PM PST 24
Finished	Feb 18 02:16:27 PM PST 24
Peak memory	224968 kb
Host	smart-f657bc90-44b3-4917-8cf0-a3fc467c8785
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849998062 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 97.uart_stress_all_with_rand_reset.3849998062
Directory	/workspace/97.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/98.uart_fifo_reset.1143208953
Short name	T909
Test name
Test status
Simulation time	6298429143 ps
CPU time	10.37 seconds
Started	Feb 18 02:07:24 PM PST 24
Finished	Feb 18 02:07:37 PM PST 24
Peak memory	198032 kb
Host	smart-0b33afec-948d-4e8c-8024-c9b59fa1d491
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1143208953 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.uart_fifo_reset.1143208953
Directory	/workspace/98.uart_fifo_reset/latest

Test location	/workspace/coverage/default/99.uart_fifo_reset.3014033544
Short name	T923
Test name
Test status
Simulation time	143707761598 ps
CPU time	104.45 seconds
Started	Feb 18 02:07:25 PM PST 24
Finished	Feb 18 02:09:11 PM PST 24
Peak memory	200008 kb
Host	smart-01f64938-5602-45b0-a3ba-7f4a8e893159
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3014033544 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.uart_fifo_reset.3014033544
Directory	/workspace/99.uart_fifo_reset/latest

Test location	/workspace/coverage/default/99.uart_stress_all_with_rand_reset.3945181013
Short name	T435
Test name
Test status
Simulation time	7827223332 ps
CPU time	92 seconds
Started	Feb 18 02:07:20 PM PST 24
Finished	Feb 18 02:08:56 PM PST 24
Peak memory	200160 kb
Host	smart-b940e7f2-7894-4e9d-9130-98af241008ae
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945181013 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 99.uart_stress_all_with_rand_reset.3945181013
Directory	/workspace/99.uart_stress_all_with_rand_reset/latest

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