Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	67648336	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

25829213

1

T1

257

T2

218

T3

15

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	88850609	1			T1	669900		T2	1654		T3	1
values[0x0]	2197329	1			T1	177		T2	162		T3	11
values[0x1]	2429611	1			T1	164		T2	137		T3	10

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	47763609	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

45713940

1

T1

223520

T2

734

T3

16

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	387700	1			T1	2608		T2	5		T4	1619
valid_sources[0x01]	333835	1			T1	2567		T2	13		T4	1497
valid_sources[0x02]	497507	1			T1	2528		T4	1481		T5	18
valid_sources[0x03]	328377	1			T1	2631		T2	2		T4	1489
valid_sources[0x04]	352337	1			T1	2615		T4	1458		T5	18
valid_sources[0x05]	365620	1			T1	2543		T4	1626		T5	8
valid_sources[0x06]	331934	1			T1	2590		T2	5		T4	1536
valid_sources[0x07]	336953	1			T1	2602		T2	29		T3	1
valid_sources[0x08]	374488	1			T1	2548		T4	1438		T5	5
valid_sources[0x09]	380431	1			T1	2685		T4	1430		T5	5
valid_sources[0x0a]	335069	1			T1	2608		T4	1389		T5	11
valid_sources[0x0b]	357872	1			T1	2533		T2	5		T3	1
valid_sources[0x0c]	396190	1			T1	2663		T4	1627		T6	3
valid_sources[0x0d]	331072	1			T1	2582		T4	1555		T5	11
valid_sources[0x0e]	430160	1			T1	2554		T4	1580		T5	10
valid_sources[0x0f]	374861	1			T1	2501		T2	4		T4	1578
valid_sources[0x10]	339225	1			T1	2510		T4	1536		T5	7
valid_sources[0x11]	338703	1			T1	2714		T2	8		T4	1589
valid_sources[0x12]	342775	1			T1	2674		T2	11		T4	1642
valid_sources[0x13]	362764	1			T1	2740		T2	1		T4	1573
valid_sources[0x14]	361547	1			T1	2598		T2	36		T4	1510
valid_sources[0x15]	366798	1			T1	2598		T2	11		T4	1569
valid_sources[0x16]	333740	1			T1	2661		T2	1		T4	1483
valid_sources[0x17]	332819	1			T1	2664		T2	1		T4	1558
valid_sources[0x18]	454680	1			T1	2663		T4	1552		T5	5
valid_sources[0x19]	383709	1			T1	2612		T2	32		T4	1585
valid_sources[0x1a]	386387	1			T1	2574		T2	8		T4	1402
valid_sources[0x1b]	355313	1			T1	2579		T2	10		T4	1474
valid_sources[0x1c]	426756	1			T1	2545		T2	3		T4	1577
valid_sources[0x1d]	331671	1			T1	2604		T2	3		T4	1516
valid_sources[0x1e]	360680	1			T1	2598		T2	1		T4	1424
valid_sources[0x1f]	355598	1			T1	2518		T2	3		T4	1609
valid_sources[0x20]	356147	1			T1	2665		T2	1		T4	1457
valid_sources[0x21]	352633	1			T1	2717		T2	34		T4	1598
valid_sources[0x22]	391204	1			T1	2605		T4	1592		T5	19
valid_sources[0x23]	338837	1			T1	2611		T2	4		T4	1485
valid_sources[0x24]	348170	1			T1	2508		T3	1		T4	1489
valid_sources[0x25]	350341	1			T1	2603		T4	1442		T5	10
valid_sources[0x26]	364394	1			T1	2678		T2	25		T4	1520
valid_sources[0x27]	332262	1			T1	2533		T4	1515		T5	8
valid_sources[0x28]	380320	1			T1	2618		T4	1579		T5	10
valid_sources[0x29]	327640	1			T1	2538		T4	1510		T5	14
valid_sources[0x2a]	332284	1			T1	2657		T2	39		T4	1564
valid_sources[0x2b]	376202	1			T1	2632		T2	6		T4	1579
valid_sources[0x2c]	337937	1			T1	2610		T2	8		T4	1648
valid_sources[0x2d]	375644	1			T1	2629		T2	11		T4	1531
valid_sources[0x2e]	438955	1			T1	2667		T2	11		T3	1
valid_sources[0x2f]	355470	1			T1	2668		T4	1529		T5	14
valid_sources[0x30]	367951	1			T1	2544		T2	6		T4	1557
valid_sources[0x31]	339070	1			T1	2667		T4	1384		T5	26
valid_sources[0x32]	354094	1			T1	2583		T2	7		T4	1504
valid_sources[0x33]	345206	1			T1	2594		T2	11		T4	1505
valid_sources[0x34]	333243	1			T1	2685		T2	16		T4	1642
valid_sources[0x35]	375393	1			T1	2634		T2	4		T4	1456
valid_sources[0x36]	351478	1			T1	2623		T2	6		T4	1494
valid_sources[0x37]	366068	1			T1	2651		T2	28		T4	1560
valid_sources[0x38]	426190	1			T1	2709		T2	11		T4	1636
valid_sources[0x39]	405021	1			T1	2651		T2	4		T4	1456
valid_sources[0x3a]	363589	1			T1	2706		T2	1		T4	1512
valid_sources[0x3b]	347565	1			T1	2653		T4	1490		T5	16
valid_sources[0x3c]	424047	1			T1	2616		T2	10		T4	1398
valid_sources[0x3d]	369062	1			T1	2586		T2	2		T4	1515
valid_sources[0x3e]	362487	1			T1	2666		T2	8		T4	1527
valid_sources[0x3f]	318043	1			T1	2651		T2	11		T4	1320
valid_sources[0x40]	406636	1			T1	2603		T2	2		T4	1524
valid_sources[0x41]	350142	1			T1	2636		T2	2		T4	1594
valid_sources[0x42]	335895	1			T1	2625		T4	1506		T5	13
valid_sources[0x43]	374081	1			T1	2627		T2	3		T4	1472
valid_sources[0x44]	367660	1			T1	2609		T4	1432		T5	24
valid_sources[0x45]	449281	1			T1	2604		T2	24		T4	1532
valid_sources[0x46]	385305	1			T1	2612		T2	4		T4	1500
valid_sources[0x47]	1714843	1			T1	2622		T4	1464		T5	8
valid_sources[0x48]	370587	1			T1	2632		T4	1440		T5	12
valid_sources[0x49]	336774	1			T1	2662		T2	1		T4	1571
valid_sources[0x4a]	325930	1			T1	2498		T2	22		T4	1412
valid_sources[0x4b]	358912	1			T1	2560		T2	27		T4	1552
valid_sources[0x4c]	339830	1			T1	2588		T4	1667		T5	8
valid_sources[0x4d]	367889	1			T1	2686		T2	14		T4	1523
valid_sources[0x4e]	382945	1			T1	2550		T2	8		T3	3
valid_sources[0x4f]	393698	1			T1	2669		T4	1490		T5	7
valid_sources[0x50]	331361	1			T1	2618		T2	35		T4	1585
valid_sources[0x51]	408806	1			T1	2620		T2	24		T4	1548
valid_sources[0x52]	348067	1			T1	2655		T2	18		T4	1475
valid_sources[0x53]	360579	1			T1	2663		T2	21		T3	1
valid_sources[0x54]	334101	1			T1	2679		T2	14		T4	1439
valid_sources[0x55]	326653	1			T1	2621		T2	21		T4	1611
valid_sources[0x56]	373312	1			T1	2606		T2	38		T4	1622
valid_sources[0x57]	321989	1			T1	2645		T2	3		T4	1511
valid_sources[0x58]	359114	1			T1	2645		T4	1650		T5	13
valid_sources[0x59]	370555	1			T1	2669		T4	1475		T5	3
valid_sources[0x5a]	366216	1			T1	2612		T2	8		T4	1584
valid_sources[0x5b]	344133	1			T1	2653		T2	4		T4	1613
valid_sources[0x5c]	345430	1			T1	2513		T2	8		T4	1517
valid_sources[0x5d]	342249	1			T1	2647		T4	1529		T5	6
valid_sources[0x5e]	369745	1			T1	2648		T4	1526		T5	11
valid_sources[0x5f]	327724	1			T1	2590		T2	13		T4	1644
valid_sources[0x60]	378694	1			T1	2578		T2	20		T4	1521
valid_sources[0x61]	370047	1			T1	2663		T2	5		T4	1591
valid_sources[0x62]	436123	1			T1	2597		T2	18		T4	1450
valid_sources[0x63]	330739	1			T1	2712		T2	8		T4	1468
valid_sources[0x64]	342364	1			T1	2681		T2	6		T4	1477
valid_sources[0x65]	368220	1			T1	2734		T4	1427		T5	6
valid_sources[0x66]	333818	1			T1	2591		T4	1496		T5	10
valid_sources[0x67]	345525	1			T1	2677		T2	12		T4	1459
valid_sources[0x68]	334430	1			T1	2557		T4	1503		T5	12
valid_sources[0x69]	377208	1			T1	2633		T2	5		T3	1
valid_sources[0x6a]	335246	1			T1	2644		T2	4		T3	1
valid_sources[0x6b]	348950	1			T1	2580		T2	24		T4	1489
valid_sources[0x6c]	360031	1			T1	2610		T2	5		T4	1604
valid_sources[0x6d]	349413	1			T1	2642		T2	19		T4	1434
valid_sources[0x6e]	340536	1			T1	2675		T2	11		T3	1
valid_sources[0x6f]	361744	1			T1	2572		T2	7		T4	1499
valid_sources[0x70]	341191	1			T1	2623		T2	9		T4	1503
valid_sources[0x71]	350652	1			T1	2557		T4	1578		T5	15
valid_sources[0x72]	391907	1			T1	2485		T2	15		T4	1449
valid_sources[0x73]	383527	1			T1	2637		T2	1		T4	1505
valid_sources[0x74]	384950	1			T1	2535		T4	1466		T5	11
valid_sources[0x75]	330594	1			T1	2628		T4	1614		T5	13
valid_sources[0x76]	328848	1			T1	2623		T2	1		T4	1363
valid_sources[0x77]	392008	1			T1	2549		T2	3		T4	1516
valid_sources[0x78]	336393	1			T1	2591		T2	21		T3	1
valid_sources[0x79]	483244	1			T1	2528		T2	3		T4	1450
valid_sources[0x7a]	338567	1			T1	2645		T4	1474		T5	10
valid_sources[0x7b]	355208	1			T1	2725		T2	23		T4	1479
valid_sources[0x7c]	335345	1			T1	2532		T2	5		T4	1491
valid_sources[0x7d]	355613	1			T1	2569		T2	7		T4	1481
valid_sources[0x7e]	340675	1			T1	2701		T4	1435		T5	5
valid_sources[0x7f]	345429	1			T1	2660		T4	1504		T5	8
valid_sources[0x80]	380677	1			T1	2588		T2	9		T4	1605

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

21956938

1

T1

176

T2

119

T3

1

values[0x0]

all_enables

biggest_size

1963533

1

T1

59

T2

68

T3

7

values[0x1]

all_enables

biggest_size

1908742

1

T1

22

T2

31

T3

7