Unified Coverage Report :: Module :: uart_csr_assert_fpv

Module : uart_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_uart_csr_assert_0/uart_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.uart_csr_assert	100.00						100.00

---

Module Instance : tb.dut.uart_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : uart_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	6192850	0	0
ctrl_rd_A	2147483647	121622	0	0
intr_enable_rd_A	2147483647	108390	0	0
ovrd_rd_A	2147483647	119954	0	0
timeout_ctrl_rd_A	2147483647	119315	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	6192850	0	0
T11	173755	0	0	0
T12	448103	0	0	0
T17	425304	0	0	0
T18	309917	0	0	0
T19	356806	0	0	0
T24	210800	48186	0	0
T25	0	148251	0	0
T26	0	174562	0	0
T34	222641	0	0	0
T35	0	103077	0	0
T36	0	157342	0	0
T37	0	123911	0	0
T38	0	86508	0	0
T39	0	141928	0	0
T40	0	160471	0	0
T41	0	224708	0	0
T42	55140	0	0	0
T43	237965	0	0	0
T44	170883	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	121622	0	0
T11	173755	0	0	0
T12	448103	0	0	0
T17	425304	0	0	0
T18	309917	0	0	0
T19	356806	0	0	0
T24	210800	5489	0	0
T34	222641	0	0	0
T35	0	5543	0	0
T38	0	4641	0	0
T40	0	17781	0	0
T42	55140	0	0	0
T43	237965	0	0	0
T44	170883	0	0	0
T49	0	6709	0	0
T108	0	21050	0	0
T109	0	8094	0	0
T110	0	5094	0	0
T111	0	16225	0	0
T112	0	1863	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	108390	0	0
T11	173755	0	0	0
T12	448103	0	0	0
T17	425304	0	0	0
T18	309917	0	0	0
T19	356806	0	0	0
T24	210800	4978	0	0
T34	222641	0	0	0
T35	0	4748	0	0
T38	0	4029	0	0
T40	0	15308	0	0
T42	55140	0	0	0
T43	237965	0	0	0
T44	170883	0	0	0
T49	0	6258	0	0
T108	0	19462	0	0
T109	0	7029	0	0
T110	0	4728	0	0
T113	0	35	0	0
T114	0	9	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	119954	0	0
T11	173755	0	0	0
T12	448103	0	0	0
T17	425304	0	0	0
T18	309917	0	0	0
T19	356806	0	0	0
T24	210800	5809	0	0
T34	222641	0	0	0
T35	0	5401	0	0
T38	0	4474	0	0
T40	0	17999	0	0
T42	55140	0	0	0
T43	237965	0	0	0
T44	170883	0	0	0
T49	0	7093	0	0
T108	0	21980	0	0
T109	0	8262	0	0
T110	0	5063	0	0
T111	0	15376	0	0
T112	0	1765	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	119315	0	0
T11	173755	0	0	0
T12	448103	0	0	0
T17	425304	0	0	0
T18	309917	0	0	0
T19	356806	0	0	0
T24	210800	5375	0	0
T34	222641	0	0	0
T35	0	5300	0	0
T38	0	4567	0	0
T40	0	17465	0	0
T42	55140	0	0	0
T43	237965	0	0	0
T44	170883	0	0	0
T49	0	7047	0	0
T108	0	21361	0	0
T109	0	8483	0	0
T110	0	5151	0	0
T111	0	15833	0	0
T112	0	1640	0	0