Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	71890891	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

24108889

1

T1

14

T2

274

T3

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	91533848	1			T1	9471		T2	1035		T3	1
values[0x0]	2120852	1			T1	5		T2	189		T3	1
values[0x1]	2345080	1			T1	8		T2	204		T4	215

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	50348548	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

45651232

1

T1

3234

T2

560

T3

1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	334785	1			T1	12		T2	5		T4	79
valid_sources[0x01]	352713	1			T1	26		T2	8		T4	71
valid_sources[0x02]	350239	1			T1	50		T2	16		T4	77
valid_sources[0x03]	353236	1			T1	31		T4	84		T5	11
valid_sources[0x04]	363188	1			T1	37		T4	71		T5	17
valid_sources[0x05]	353128	1			T1	22		T4	87		T5	18
valid_sources[0x06]	343969	1			T1	1		T2	8		T4	90
valid_sources[0x07]	357157	1			T1	49		T2	5		T4	79
valid_sources[0x08]	331291	1			T1	59		T4	86		T5	9
valid_sources[0x09]	350224	1			T1	16		T2	14		T4	73
valid_sources[0x0a]	373357	1			T1	36		T4	90		T5	21
valid_sources[0x0b]	344232	1			T1	38		T2	26		T4	68
valid_sources[0x0c]	338632	1			T1	34		T2	7		T4	81
valid_sources[0x0d]	368037	1			T1	49		T2	14		T4	88
valid_sources[0x0e]	346500	1			T1	31		T2	3		T4	77
valid_sources[0x0f]	363500	1			T1	22		T4	83		T5	12
valid_sources[0x10]	434038	1			T1	12		T2	7		T4	70
valid_sources[0x11]	449521	1			T1	75		T4	75		T5	14
valid_sources[0x12]	345836	1			T1	39		T4	116		T5	16
valid_sources[0x13]	350005	1			T1	33		T2	1		T4	89
valid_sources[0x14]	618318	1			T1	14		T4	95		T5	9
valid_sources[0x15]	357867	1			T1	36		T4	83		T5	10
valid_sources[0x16]	366737	1			T1	61		T2	9		T4	82
valid_sources[0x17]	340194	1			T1	26		T2	3		T4	93
valid_sources[0x18]	413502	1			T1	31		T2	18		T4	78
valid_sources[0x19]	358284	1			T1	62		T2	2		T4	62
valid_sources[0x1a]	333425	1			T1	45		T2	5		T4	76
valid_sources[0x1b]	356876	1			T1	6		T4	81		T5	8
valid_sources[0x1c]	343060	1			T1	57		T2	25		T4	73
valid_sources[0x1d]	376010	1			T1	49		T4	85		T5	11
valid_sources[0x1e]	350282	1			T1	45		T2	18		T4	82
valid_sources[0x1f]	394173	1			T1	40		T4	88		T5	14
valid_sources[0x20]	347403	1			T2	6		T4	82		T5	13
valid_sources[0x21]	362345	1			T1	30		T4	84		T5	14
valid_sources[0x22]	412045	1			T1	28		T2	6		T4	78
valid_sources[0x23]	374256	1			T1	23		T4	80		T5	20
valid_sources[0x24]	337792	1			T1	28		T2	11		T4	85
valid_sources[0x25]	358921	1			T1	72		T4	75		T5	12
valid_sources[0x26]	357990	1			T1	83		T4	87		T5	5
valid_sources[0x27]	476141	1			T1	17		T2	8		T4	71
valid_sources[0x28]	365737	1			T1	57		T2	28		T4	79
valid_sources[0x29]	354467	1			T1	26		T2	6		T4	77
valid_sources[0x2a]	354253	1			T1	18		T4	98		T5	11
valid_sources[0x2b]	333399	1			T1	37		T4	86		T5	9
valid_sources[0x2c]	358919	1			T1	38		T2	30		T4	100
valid_sources[0x2d]	352859	1			T1	33		T2	4		T4	80
valid_sources[0x2e]	365592	1			T1	20		T2	1		T4	81
valid_sources[0x2f]	372033	1			T1	7		T2	6		T4	76
valid_sources[0x30]	358834	1			T1	38		T2	3		T4	69
valid_sources[0x31]	368676	1			T1	33		T2	2		T4	94
valid_sources[0x32]	371542	1			T1	5		T2	1		T4	85
valid_sources[0x33]	362102	1			T1	51		T2	5		T4	97
valid_sources[0x34]	436656	1			T1	60		T2	19		T4	81
valid_sources[0x35]	396820	1			T1	62		T2	26		T4	84
valid_sources[0x36]	436349	1			T1	85		T2	2		T4	67
valid_sources[0x37]	397422	1			T1	67		T4	72		T5	8
valid_sources[0x38]	360991	1			T1	41		T2	5		T4	77
valid_sources[0x39]	372285	1			T1	35		T4	71		T5	12
valid_sources[0x3a]	377696	1			T1	39		T4	79		T5	10
valid_sources[0x3b]	474372	1			T1	64		T2	1		T4	88
valid_sources[0x3c]	361577	1			T1	50		T4	78		T5	8
valid_sources[0x3d]	361998	1			T1	31		T2	22		T4	60
valid_sources[0x3e]	446463	1			T1	10		T4	87		T5	12
valid_sources[0x3f]	449799	1			T1	20		T4	97		T5	11
valid_sources[0x40]	435424	1			T1	28		T2	6		T4	82
valid_sources[0x41]	348573	1			T1	13		T4	88		T5	15
valid_sources[0x42]	354523	1			T1	17		T2	9		T4	78
valid_sources[0x43]	375939	1			T1	43		T4	79		T5	9
valid_sources[0x44]	354703	1			T1	56		T4	70		T5	6
valid_sources[0x45]	371596	1			T1	33		T2	14		T4	84
valid_sources[0x46]	354284	1			T1	43		T4	73		T5	9
valid_sources[0x47]	345516	1			T1	56		T2	2		T4	86
valid_sources[0x48]	380846	1			T1	43		T2	12		T4	73
valid_sources[0x49]	442604	1			T1	38		T2	17		T4	106
valid_sources[0x4a]	402753	1			T1	30		T2	21		T4	88
valid_sources[0x4b]	345456	1			T1	12		T4	101		T5	7
valid_sources[0x4c]	354153	1			T1	69		T2	8		T4	104
valid_sources[0x4d]	364912	1			T1	13		T4	81		T5	17
valid_sources[0x4e]	335072	1			T1	27		T4	75		T5	18
valid_sources[0x4f]	367884	1			T1	45		T4	76		T5	14
valid_sources[0x50]	1387942	1			T1	60		T2	2		T4	79
valid_sources[0x51]	354998	1			T1	42		T2	10		T4	88
valid_sources[0x52]	396697	1			T1	12		T4	81		T5	18
valid_sources[0x53]	338789	1			T1	25		T2	18		T4	93
valid_sources[0x54]	392019	1			T1	15		T2	2		T4	83
valid_sources[0x55]	352915	1			T1	16		T4	84		T5	11
valid_sources[0x56]	364039	1			T1	24		T2	1		T4	89
valid_sources[0x57]	370571	1			T1	47		T2	1		T4	94
valid_sources[0x58]	350415	1			T1	55		T2	4		T4	79
valid_sources[0x59]	345139	1			T1	34		T2	19		T4	80
valid_sources[0x5a]	368965	1			T1	22		T4	83		T5	16
valid_sources[0x5b]	357668	1			T1	40		T2	28		T4	74
valid_sources[0x5c]	385434	1			T1	57		T2	7		T4	85
valid_sources[0x5d]	356652	1			T1	29		T4	71		T5	14
valid_sources[0x5e]	395888	1			T1	53		T4	83		T5	11
valid_sources[0x5f]	358286	1			T1	51		T4	69		T5	10
valid_sources[0x60]	372628	1			T1	44		T4	83		T5	12
valid_sources[0x61]	365442	1			T1	40		T4	81		T5	12
valid_sources[0x62]	481444	1			T1	9		T4	83		T5	10
valid_sources[0x63]	349009	1			T1	31		T2	20		T4	90
valid_sources[0x64]	337126	1			T1	9		T2	3		T4	74
valid_sources[0x65]	356504	1			T1	58		T2	4		T4	94
valid_sources[0x66]	377740	1			T1	48		T4	87		T5	15
valid_sources[0x67]	364571	1			T1	21		T2	10		T4	73
valid_sources[0x68]	370535	1			T1	14		T2	8		T4	76
valid_sources[0x69]	370917	1			T1	28		T2	9		T4	75
valid_sources[0x6a]	342905	1			T1	6		T4	89		T5	17
valid_sources[0x6b]	366435	1			T1	40		T4	105		T5	12
valid_sources[0x6c]	370367	1			T1	70		T2	6		T4	94
valid_sources[0x6d]	343615	1			T1	35		T2	4		T4	78
valid_sources[0x6e]	370664	1			T1	27		T2	14		T4	80
valid_sources[0x6f]	355003	1			T1	40		T4	81		T5	11
valid_sources[0x70]	349853	1			T1	28		T2	9		T4	91
valid_sources[0x71]	376305	1			T1	20		T4	74		T5	11
valid_sources[0x72]	433425	1			T1	12		T2	17		T4	90
valid_sources[0x73]	397734	1			T1	12		T2	10		T4	97
valid_sources[0x74]	396785	1			T1	54		T2	5		T4	65
valid_sources[0x75]	362880	1			T1	44		T3	1		T4	70
valid_sources[0x76]	335300	1			T1	52		T2	6		T4	75
valid_sources[0x77]	353608	1			T1	35		T2	21		T4	82
valid_sources[0x78]	348974	1			T1	18		T2	3		T4	86
valid_sources[0x79]	324534	1			T1	28		T4	77		T5	9
valid_sources[0x7a]	421687	1			T1	13		T4	98		T5	15
valid_sources[0x7b]	377564	1			T1	22		T2	6		T4	80
valid_sources[0x7c]	349973	1			T1	49		T2	4		T4	73
valid_sources[0x7d]	409012	1			T1	39		T2	1		T4	77
valid_sources[0x7e]	338068	1			T1	8		T2	7		T4	104
valid_sources[0x7f]	367815	1			T1	25		T2	9		T4	68
valid_sources[0x80]	351157	1			T1	24		T4	84		T5	14

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

20354840

1

T1

8

T2

154

T3

1

values[0x0]

all_enables

biggest_size

1901969

1

T1

2

T2

71

T4

66

values[0x1]

all_enables

biggest_size

1852080

1

T1

4

T2

49

T4

52