Unified Coverage Report :: Module :: uart_csr_assert_fpv

Module : uart_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_uart_csr_assert_0/uart_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.uart_csr_assert	100.00						100.00

---

Module Instance : tb.dut.uart_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : uart_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	6030956	0	0
ctrl_rd_A	2147483647	137789	0	0
intr_enable_rd_A	2147483647	121187	0	0
ovrd_rd_A	2147483647	135009	0	0
timeout_ctrl_rd_A	2147483647	136000	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	6030956	0	0
T15	804106	307631	0	0
T19	430318	0	0	0
T25	114970	0	0	0
T29	0	136102	0	0
T30	0	127512	0	0
T36	0	27012	0	0
T37	0	77495	0	0
T38	0	273403	0	0
T39	0	62398	0	0
T40	0	633564	0	0
T41	0	183961	0	0
T42	0	116738	0	0
T43	214785	0	0	0
T44	553270	0	0	0
T45	145815	0	0	0
T46	191355	0	0	0
T47	440929	0	0	0
T48	175115	0	0	0
T49	219170	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	137789	0	0
T39	250979	7488	0	0
T40	198489	0	0	0
T41	0	8026	0	0
T42	0	13024	0	0
T114	0	28404	0	0
T115	0	3476	0	0
T116	0	7950	0	0
T117	0	10455	0	0
T118	0	10723	0	0
T119	0	11343	0	0
T120	0	10611	0	0
T121	147281	0	0	0
T122	522152	0	0	0
T123	185470	0	0	0
T124	776928	0	0	0
T125	428976	0	0	0
T126	196603	0	0	0
T127	705985	0	0	0
T128	410262	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	121187	0	0
T39	250979	6290	0	0
T40	198489	0	0	0
T41	0	7198	0	0
T42	0	11619	0	0
T114	0	24710	0	0
T115	0	3539	0	0
T116	0	6912	0	0
T117	0	8765	0	0
T118	0	9418	0	0
T121	147281	0	0	0
T122	522152	0	0	0
T123	185470	0	0	0
T124	776928	0	0	0
T125	428976	0	0	0
T126	196603	0	0	0
T127	705985	0	0	0
T128	410262	0	0	0
T129	0	23	0	0
T130	0	15	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	135009	0	0
T39	250979	7044	0	0
T40	198489	0	0	0
T41	0	7667	0	0
T42	0	12683	0	0
T114	0	28600	0	0
T115	0	3623	0	0
T116	0	7507	0	0
T117	0	10560	0	0
T118	0	11128	0	0
T119	0	11389	0	0
T120	0	10771	0	0
T121	147281	0	0	0
T122	522152	0	0	0
T123	185470	0	0	0
T124	776928	0	0	0
T125	428976	0	0	0
T126	196603	0	0	0
T127	705985	0	0	0
T128	410262	0	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	136000	0	0
T39	250979	7114	0	0
T40	198489	0	0	0
T41	0	8138	0	0
T42	0	13412	0	0
T114	0	27827	0	0
T115	0	3719	0	0
T116	0	8253	0	0
T117	0	9677	0	0
T118	0	10799	0	0
T119	0	11873	0	0
T120	0	10327	0	0
T121	147281	0	0	0
T122	522152	0	0	0
T123	185470	0	0	0
T124	776928	0	0	0
T125	428976	0	0	0
T126	196603	0	0	0
T127	705985	0	0	0
T128	410262	0	0	0