Unified Coverage Report :: Module :: uart_csr_assert_fpv

Module : uart_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_uart_csr_assert_0/uart_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.uart_csr_assert	100.00						100.00

---

Module Instance : tb.dut.uart_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : uart_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	4240574	0	0
ctrl_rd_A	2147483647	67865	0	0
intr_enable_rd_A	2147483647	59983	0	0
ovrd_rd_A	2147483647	65671	0	0
timeout_ctrl_rd_A	2147483647	66434	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4240574	0	0
T8	610100	247251	0	0
T9	141175	0	0	0
T10	313768	0	0	0
T11	626198	257681	0	0
T18	631501	0	0	0
T20	0	40681	0	0
T21	840	0	0	0
T27	0	106594	0	0
T28	0	184736	0	0
T29	0	307765	0	0
T30	0	186028	0	0
T31	0	110703	0	0
T32	0	301699	0	0
T33	0	99429	0	0
T34	26743	0	0	0
T35	122191	0	0	0
T36	892019	0	0	0
T37	774883	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	67865	0	0
T28	571589	8137	0	0
T52	0	6638	0	0
T53	0	16823	0	0
T70	0	13	0	0
T96	0	2163	0	0
T97	0	9541	0	0
T98	0	5256	0	0
T99	0	11401	0	0
T100	0	4583	0	0
T101	0	29	0	0
T102	693299	0	0	0
T103	120774	0	0	0
T104	222851	0	0	0
T105	965919	0	0	0
T106	311824	0	0	0
T107	40785	0	0	0
T108	173523	0	0	0
T109	380200	0	0	0
T110	517856	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	59983	0	0
T28	571589	7190	0	0
T52	0	5746	0	0
T53	0	15387	0	0
T74	709947	6	0	0
T96	0	1792	0	0
T97	0	8243	0	0
T98	0	4587	0	0
T99	0	9656	0	0
T102	693299	0	0	0
T103	120774	0	0	0
T104	222851	0	0	0
T105	965919	0	0	0
T106	311824	0	0	0
T107	40785	0	0	0
T108	173523	0	0	0
T109	380200	0	0	0
T111	0	6	0	0
T112	0	5	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	65671	0	0
T28	571589	7935	0	0
T52	0	6453	0	0
T53	0	17420	0	0
T70	0	2	0	0
T96	0	1983	0	0
T97	0	9267	0	0
T98	0	4958	0	0
T99	0	11471	0	0
T100	0	4685	0	0
T101	0	15	0	0
T102	693299	0	0	0
T103	120774	0	0	0
T104	222851	0	0	0
T105	965919	0	0	0
T106	311824	0	0	0
T107	40785	0	0	0
T108	173523	0	0	0
T109	380200	0	0	0
T110	517856	0	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	66434	0	0
T28	571589	8046	0	0
T52	0	6495	0	0
T53	0	17835	0	0
T96	0	1922	0	0
T97	0	9354	0	0
T98	0	5094	0	0
T99	0	11267	0	0
T100	0	4956	0	0
T101	0	21	0	0
T102	693299	0	0	0
T103	120774	0	0	0
T104	222851	0	0	0
T105	965919	0	0	0
T106	311824	0	0	0
T107	40785	0	0	0
T108	173523	0	0	0
T109	380200	0	0	0
T110	517856	0	0	0
T113	0	8	0	0