Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	60861588	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

19531272

1

T1

152

T2

26

T3

112

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	76306856	1			T1	189		T2	1807		T3	2813
values[0x0]	1939353	1			T1	64		T2	20		T3	93
values[0x1]	2146651	1			T1	75		T2	12		T3	112

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	42495272	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

37897588

1

T1

178

T2

615

T3

1003

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	303336	1			T2	11		T5	4		T8	73
valid_sources[0x01]	279283	1			T1	1		T2	18		T5	4
valid_sources[0x02]	291482	1			T1	1		T2	7		T5	4
valid_sources[0x03]	294830	1			T1	1		T2	4		T8	76
valid_sources[0x04]	292773	1			T2	11		T5	2		T8	63
valid_sources[0x05]	326276	1			T2	7		T5	5		T8	70
valid_sources[0x06]	284475	1			T1	1		T2	8		T5	2
valid_sources[0x07]	305223	1			T1	3		T2	4		T5	10
valid_sources[0x08]	293983	1			T2	4		T5	8		T6	2
valid_sources[0x09]	300830	1			T1	1		T2	13		T8	58
valid_sources[0x0a]	281418	1			T1	5		T2	3		T5	6
valid_sources[0x0b]	333774	1			T2	7		T8	90		T10	92
valid_sources[0x0c]	284966	1			T1	1		T2	10		T5	3
valid_sources[0x0d]	310727	1			T1	1		T2	4		T5	7
valid_sources[0x0e]	309687	1			T1	1		T2	10		T8	71
valid_sources[0x0f]	278073	1			T1	3		T2	6		T5	4
valid_sources[0x10]	293793	1			T2	5		T5	13		T8	64
valid_sources[0x11]	314497	1			T1	1		T2	10		T8	86
valid_sources[0x12]	278776	1			T2	4		T8	69		T10	227
valid_sources[0x13]	280525	1			T1	2		T2	2		T8	57
valid_sources[0x14]	291434	1			T2	11		T5	3		T8	70
valid_sources[0x15]	278158	1			T2	8		T5	14		T8	87
valid_sources[0x16]	279426	1			T1	5		T2	5		T5	5
valid_sources[0x17]	287585	1			T1	1		T2	5		T8	62
valid_sources[0x18]	314448	1			T2	8		T5	15		T8	66
valid_sources[0x19]	417305	1			T2	5		T5	2		T8	71
valid_sources[0x1a]	318533	1			T1	1		T2	11		T7	876
valid_sources[0x1b]	282886	1			T1	1		T2	8		T5	2
valid_sources[0x1c]	315922	1			T1	10		T2	10		T5	2
valid_sources[0x1d]	315258	1			T1	5		T2	5		T5	25
valid_sources[0x1e]	301514	1			T2	7		T5	6		T8	66
valid_sources[0x1f]	288578	1			T1	1		T2	7		T8	73
valid_sources[0x20]	289407	1			T2	8		T5	31		T8	72
valid_sources[0x21]	337657	1			T1	3		T2	3		T8	65
valid_sources[0x22]	291229	1			T2	11		T8	79		T9	2
valid_sources[0x23]	294713	1			T1	1		T2	2		T5	8
valid_sources[0x24]	307034	1			T1	5		T2	9		T8	49
valid_sources[0x25]	272388	1			T1	1		T2	7		T8	85
valid_sources[0x26]	298376	1			T1	8		T2	6		T5	23
valid_sources[0x27]	294951	1			T1	2		T2	7		T5	8
valid_sources[0x28]	320689	1			T1	1		T2	9		T5	3
valid_sources[0x29]	293612	1			T2	6		T5	19		T8	79
valid_sources[0x2a]	293309	1			T1	3		T2	5		T5	15
valid_sources[0x2b]	342855	1			T1	2		T2	11		T8	71
valid_sources[0x2c]	307213	1			T2	6		T8	69		T9	3
valid_sources[0x2d]	292154	1			T1	3		T2	3		T8	74
valid_sources[0x2e]	282592	1			T2	6		T5	4		T8	72
valid_sources[0x2f]	302849	1			T2	7		T5	10		T8	69
valid_sources[0x30]	331030	1			T1	1		T2	3		T5	6
valid_sources[0x31]	282110	1			T1	3		T2	3		T5	1
valid_sources[0x32]	281687	1			T2	11		T5	7		T8	85
valid_sources[0x33]	283759	1			T2	8		T5	3		T8	67
valid_sources[0x34]	1840744	1			T1	3		T2	14		T5	4
valid_sources[0x35]	287889	1			T1	1		T2	6		T5	1
valid_sources[0x36]	289112	1			T2	2		T8	86		T9	1
valid_sources[0x37]	286463	1			T1	4		T2	10		T5	11
valid_sources[0x38]	307328	1			T2	9		T5	11		T8	79
valid_sources[0x39]	301184	1			T2	4		T5	2		T8	66
valid_sources[0x3a]	293478	1			T2	8		T5	7		T8	58
valid_sources[0x3b]	315325	1			T2	6		T8	73		T9	2
valid_sources[0x3c]	267346	1			T2	4		T5	2		T7	1
valid_sources[0x3d]	308166	1			T2	7		T8	66		T9	2
valid_sources[0x3e]	281078	1			T2	7		T8	65		T9	1
valid_sources[0x3f]	290583	1			T1	2		T2	12		T5	24
valid_sources[0x40]	301618	1			T1	1		T2	5		T5	5
valid_sources[0x41]	291393	1			T1	1		T2	7		T5	10
valid_sources[0x42]	357760	1			T2	6		T5	26		T8	57
valid_sources[0x43]	298682	1			T2	5		T5	4		T8	73
valid_sources[0x44]	317426	1			T1	1		T2	9		T5	7
valid_sources[0x45]	280495	1			T2	9		T8	77		T10	152
valid_sources[0x46]	290012	1			T1	2		T2	9		T5	15
valid_sources[0x47]	288192	1			T1	2		T2	7		T8	62
valid_sources[0x48]	291904	1			T2	6		T5	3		T8	82
valid_sources[0x49]	309873	1			T2	10		T8	67		T9	2
valid_sources[0x4a]	317103	1			T1	5		T2	7		T5	7
valid_sources[0x4b]	315048	1			T2	12		T5	2		T8	78
valid_sources[0x4c]	293552	1			T1	2		T2	10		T5	10
valid_sources[0x4d]	306428	1			T1	1		T2	1		T8	77
valid_sources[0x4e]	273923	1			T1	1		T2	4		T5	4
valid_sources[0x4f]	375263	1			T1	5		T2	9		T5	5
valid_sources[0x50]	291856	1			T1	5		T2	5		T5	4
valid_sources[0x51]	303215	1			T2	5		T5	3		T8	73
valid_sources[0x52]	284161	1			T1	4		T2	2		T5	9
valid_sources[0x53]	427337	1			T2	7		T5	14		T8	94
valid_sources[0x54]	274229	1			T2	6		T5	9		T8	77
valid_sources[0x55]	304424	1			T2	3		T8	68		T9	4
valid_sources[0x56]	295337	1			T1	1		T2	7		T5	3
valid_sources[0x57]	271204	1			T2	10		T5	2		T8	78
valid_sources[0x58]	310076	1			T1	3		T2	13		T5	13
valid_sources[0x59]	296989	1			T2	6		T5	18		T8	81
valid_sources[0x5a]	303857	1			T2	5		T5	46		T8	71
valid_sources[0x5b]	300051	1			T2	5		T5	9		T8	60
valid_sources[0x5c]	1367406	1			T2	4		T5	3		T8	63
valid_sources[0x5d]	278095	1			T2	17		T8	62		T9	1
valid_sources[0x5e]	340524	1			T1	1		T2	11		T5	22
valid_sources[0x5f]	281808	1			T1	2		T2	4		T5	4
valid_sources[0x60]	304363	1			T1	2		T2	12		T5	2
valid_sources[0x61]	296838	1			T1	12		T2	8		T5	2
valid_sources[0x62]	279624	1			T2	11		T5	7		T8	65
valid_sources[0x63]	291070	1			T1	2		T2	6		T8	55
valid_sources[0x64]	278424	1			T2	7		T5	5		T8	57
valid_sources[0x65]	280567	1			T1	2		T2	8		T5	17
valid_sources[0x66]	286674	1			T1	3		T2	7		T5	5
valid_sources[0x67]	287942	1			T2	8		T5	8		T8	60
valid_sources[0x68]	323938	1			T2	4		T5	3		T8	64
valid_sources[0x69]	300945	1			T2	7		T4	513		T5	20
valid_sources[0x6a]	308918	1			T2	7		T5	1		T8	76
valid_sources[0x6b]	309929	1			T1	3		T2	8		T8	59
valid_sources[0x6c]	317997	1			T1	2		T2	10		T5	8
valid_sources[0x6d]	278845	1			T1	1		T2	5		T5	17
valid_sources[0x6e]	304127	1			T2	8		T5	24		T8	65
valid_sources[0x6f]	282309	1			T2	4		T8	63		T9	2
valid_sources[0x70]	300922	1			T1	1		T2	11		T5	18
valid_sources[0x71]	299952	1			T1	2		T2	5		T5	20
valid_sources[0x72]	366371	1			T2	10		T5	1		T8	71
valid_sources[0x73]	291383	1			T2	11		T5	3		T8	79
valid_sources[0x74]	308322	1			T1	6		T2	8		T5	7
valid_sources[0x75]	319984	1			T1	3		T2	10		T5	2
valid_sources[0x76]	321473	1			T1	1		T2	11		T5	24
valid_sources[0x77]	287892	1			T2	6		T5	3		T8	53
valid_sources[0x78]	363432	1			T1	1		T2	8		T5	30
valid_sources[0x79]	308249	1			T1	3		T2	5		T5	1
valid_sources[0x7a]	280576	1			T2	10		T5	2		T8	81
valid_sources[0x7b]	275942	1			T1	2		T2	7		T8	60
valid_sources[0x7c]	287504	1			T1	2		T2	5		T5	8
valid_sources[0x7d]	436042	1			T1	1		T2	7		T8	85
valid_sources[0x7e]	309107	1			T2	10		T5	6		T8	87
valid_sources[0x7f]	291787	1			T1	1		T2	7		T8	70
valid_sources[0x80]	323180	1			T2	9		T8	86		T9	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

16116377

1

T1

109

T2

2

T3

46

values[0x0]

all_enables

biggest_size

1732427

1

T1

27

T2

16

T3

37

values[0x1]

all_enables

biggest_size

1682468

1

T1

16

T2

8

T3

29