Unified Coverage Report :: Module :: uart_csr_assert_fpv

Module : uart_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_uart_csr_assert_0/uart_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.uart_csr_assert	100.00						100.00

---

Module Instance : tb.dut.uart_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : uart_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	5567756	0	0
ctrl_rd_A	2147483647	70308	0	0
intr_enable_rd_A	2147483647	61627	0	0
ovrd_rd_A	2147483647	68614	0	0
timeout_ctrl_rd_A	2147483647	69053	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5567756	0	0
T11	0	154162	0	0
T12	0	226840	0	0
T13	115743	0	0	0
T18	252826	0	0	0
T21	373945	154050	0	0
T23	103973	0	0	0
T24	0	149497	0	0
T25	241866	61748	0	0
T31	0	136746	0	0
T32	0	118212	0	0
T33	0	41918	0	0
T34	0	53593	0	0
T35	0	61253	0	0
T36	176327	0	0	0
T37	278101	0	0	0
T38	46481	0	0	0
T39	100745	0	0	0
T40	189392	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	70308	0	0
T15	155334	0	0	0
T24	0	7804	0	0
T25	241866	7074	0	0
T34	0	6065	0	0
T38	46481	0	0	0
T39	100745	0	0	0
T40	189392	0	0	0
T41	124098	0	0	0
T55	0	660	0	0
T112	0	5949	0	0
T113	0	4517	0	0
T114	0	4629	0	0
T115	0	6535	0	0
T116	0	18782	0	0
T117	0	5051	0	0
T118	114220	0	0	0
T119	40660	0	0	0
T120	321643	0	0	0
T121	817931	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	61627	0	0
T15	155334	0	0	0
T24	0	6823	0	0
T25	241866	5712	0	0
T34	0	5553	0	0
T38	46481	0	0	0
T39	100745	0	0	0
T40	189392	0	0	0
T41	124098	0	0	0
T44	0	50	0	0
T55	0	685	0	0
T112	0	5237	0	0
T118	114220	0	0	0
T119	40660	0	0	0
T120	321643	0	0	0
T121	817931	0	0	0
T122	0	14	0	0
T123	0	54	0	0
T124	0	9	0	0
T125	0	4	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	68614	0	0
T15	155334	0	0	0
T24	0	7723	0	0
T25	241866	6904	0	0
T34	0	6331	0	0
T38	46481	0	0	0
T39	100745	0	0	0
T40	189392	0	0	0
T41	124098	0	0	0
T55	0	804	0	0
T112	0	6021	0	0
T113	0	4391	0	0
T114	0	4451	0	0
T115	0	6382	0	0
T116	0	18914	0	0
T117	0	4700	0	0
T118	114220	0	0	0
T119	40660	0	0	0
T120	321643	0	0	0
T121	817931	0	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	69053	0	0
T15	155334	0	0	0
T24	0	7819	0	0
T25	241866	6856	0	0
T34	0	6048	0	0
T38	46481	0	0	0
T39	100745	0	0	0
T40	189392	0	0	0
T41	124098	0	0	0
T55	0	628	0	0
T112	0	6002	0	0
T113	0	4652	0	0
T114	0	4594	0	0
T115	0	6354	0	0
T116	0	19277	0	0
T117	0	4808	0	0
T118	114220	0	0	0
T119	40660	0	0	0
T120	321643	0	0	0
T121	817931	0	0	0